Verilog generation verification method and device for multi-mode circuit design specification

Abstract

The application provides a Verilog generation verification method and device for a multi-modal circuit design specification, and relates to the technical field of artificial intelligence. The method comprises the following steps: acquiring a circuit code dataset, generating a first group of circuit pictures, using a large language model to perform natural language description, and constructing a multi-modal circuit dataset; a second group of circuit pictures is generated according to Python code, and a multi-modal general dataset is constructed; a multi-modal large language model is fine-tuned and trained; prompt words are customized for different tasks, a plurality of task agents are constructed according to the prompt words and the trained multi-modal large language model; a core interactive agent is designed, and the core interactive agent and the plurality of task agents are used to complete a circuit design, circuit verification and circuit knowledge question and answer task. The application can improve the circuit design verification accuracy and shorten the design verification time.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence and integrated circuit technology, and in particular to a Verilog generation and verification method and device for multi-modal circuit design specifications. BACKGROUND

[0002] Large language models have made significant progress in code generation in programming languages such as C and Python. However, extending them to the field of electronic design automation, especially automatically generating and verifying Verilog hardware description language from natural language specifications, faces many challenges. The main difficulty is that natural language specifications usually only provide functional requirement descriptions, lack strict formal definitions, and cannot accurately express hardware features such as timing, parallelism, and modular design in Verilog, resulting in generated Verilog code often not consistent with the expected hardware behavior. In recent years, the development of multi-modal and multi-agent technologies has provided new opportunities to solve this problem.

[0003] Multi-modal large language models can understand and generate information in a more rich and complex context by processing multiple types of input data simultaneously. In code generation, it can combine the graph structure of code (such as abstract syntax tree, control flow graph, dependency graph, etc.) to represent the complex relationships between program elements, thereby improving the understanding, reasoning, and generation capabilities of code.

[0004] Multi-agent technology overcomes the limitations of a single agent in handling complex reasoning and multi-step decision-making by dividing and collaborating among multiple autonomous agents (usually large language model instances). In the code generation task, each agent takes on the responsibilities of analysis, design, implementation, testing, etc., and through collaboration and information sharing, they collectively solve high-complexity code generation problems. Role division can effectively reduce the cognitive burden of a single model in handling complex logic, and by introducing a test agent and other post-verification methods, the correctness and stability of the final code result can be improved.

[0005] Existing technologies mainly focus on generating circuit code from text modal circuit design specifications, and common techniques include training models using natural language and Verilog code pairs. Existing technologies lack the ability to uniformly model and understand multi-modal design specifications, making it difficult to handle common multi-modal information such as circuit structure diagrams, timing diagrams, state transition diagrams, and flowcharts, resulting in lower functional correctness of code generation. In addition, the automated verification capability is limited, with low test coverage, and cannot effectively guide circuit optimization. In summary, existing Verilog code generation methods still have deficiencies in multi-modal understanding, functional correctness verification, and reasoning capabilities. SUMMARY

[0006] In order to solve the problem that there are various modal information in the existing circuit design specification, how to design a multi-modal multi-agent circuit design verification system, thereby solving the technical problem that the large language model has poor ability to generate Verilog code and cannot simultaneously design and verify, the embodiment of the present application provides a Verilog generation verification method and device for multi-modal circuit design specification. The technical scheme is as follows:

[0007] On the one hand, a Verilog generation verification method for multi-modal circuit design specification is provided, which is realized by a Verilog generation verification device, and the method comprises the following steps:

[0008] S1, obtain a circuit code data set, generate a first group of circuit pictures according to the circuit code data set, use a large language model to describe the circuit code data set in natural language, obtain a natural language description result of the circuit code, and then construct a multi-modal circuit data set; wherein the first group of circuit pictures comprises a circuit structure diagram, a state transition diagram, a timing diagram and a flowchart.

[0009] S2, generate a second group of circuit pictures according to the Python code, use a large language model to describe the Python code in natural language, obtain a natural language description result of the Python code, and then construct a multi-modal general data set.

[0010] S3, fine-tune the multi-modal large language model according to the multi-modal circuit data set and the multi-modal general data set, and obtain a trained multi-modal large language model.

[0011] S4, customize prompt words for different tasks, and construct a plurality of task agents according to the prompt words and the trained multi-modal large language model.

[0012] S5, design a core interactive agent, and complete the circuit design, circuit verification and circuit knowledge question answering tasks according to the core interactive agent and the plurality of task agents.

[0013] Optionally, in S1, the first group of circuit pictures is generated according to the circuit code data set, the circuit code data set is described in natural language by using a large language model, a natural language description result of the circuit code is obtained, and a multi-modal circuit data set is constructed, comprising:

[0014] Each circuit code in the circuit code data set is used to generate a corresponding circuit picture by using a script, and a first group of circuit pictures is obtained; the circuit code data set is described in natural language by using a large language model, and a natural language description result of the circuit code is obtained; and a multi-modal circuit data set is constructed according to the first group of circuit pictures and the natural language description result of the corresponding circuit code.

[0015] Optionally, in S2, the second group of circuit pictures is generated according to the Python code, a large language model is used to describe the Python code in natural language, a natural language description result of the Python code is obtained, and a multi-modal general data set is constructed, including:

[0016] The second group of circuit pictures is generated according to the Python code, a large language model is used to describe the Python code in natural language, a natural language description result of the Python code is obtained, and a multi-modal general data set is constructed according to the second group of circuit pictures and the natural language description result of the corresponding Python code; wherein the second group of circuit pictures includes circuit structure diagrams, state transition diagrams, timing diagrams and flowcharts.

[0017] Optionally, in S2, the second group of circuit pictures is generated according to the Python code, including:

[0018] The circuit structure diagrams, state transition diagrams, timing diagrams and flowcharts are generated by calling the related libraries using the Python code, and the second group of circuit pictures is constructed by randomly generating a plurality of circuit pictures.

[0019] Optionally, S3 further includes:

[0020] A multi-modal design specification understanding evaluation benchmark is designed, and the trained multi-modal large language model is evaluated.

[0021] Optionally, in S4, the prompt words are customized for different tasks, and a plurality of task agents are constructed according to the prompt words and the trained multi-modal large language model, including:

[0022] The prompt words are customized for the circuit design task, the circuit verification task and the circuit knowledge question and answer task, and a plurality of task agents are constructed according to the prompt words and the trained multi-modal large language model for any task.

[0023] Optionally, in S5, the circuit design, circuit verification and circuit knowledge question and answer tasks are completed according to the core interaction agent and the plurality of task agents, including:

[0024] The user input is read by the core interaction agent and the user's task is determined, the user's task is assigned to the plurality of task agents for execution, the outputs of the plurality of task agents are integrated, and the integrated result is returned to the user; wherein the user's task includes circuit design, circuit verification and circuit knowledge question and answer.

[0025] On the other hand, a Verilog generation verification device for multi-modal circuit design specifications is provided, which is applied to a Verilog generation verification method for multi-modal circuit design specifications, and the device includes:

[0026] The multi-modal circuit dataset construction module is configured to obtain a circuit code dataset, generate a first set of circuit pictures based on the circuit code dataset, use a large language model to generate a natural language description of the circuit code dataset, and obtain a natural language description result of the circuit code, and then construct a multi-modal circuit dataset; wherein the first set of circuit pictures includes a circuit structure diagram, a state transition diagram, a timing diagram, and a flowchart.

[0027] The multi-modal general dataset construction module is configured to generate a second set of circuit pictures based on the Python code, use a large language model to generate a natural language description of the Python code, and obtain a natural language description result of the Python code, and then construct a multi-modal general dataset.

[0028] The training module is configured to fine-tune a multi-modal large language model based on the multi-modal circuit dataset and the multi-modal general dataset, and obtain a trained multi-modal large language model.

[0029] The construction module is configured to customize prompt words for different tasks, and construct a plurality of task agents based on the prompt words and the trained multi-modal large language model.

[0030] The output module is configured to design a core interactive agent, and complete a circuit design, a circuit verification, and a circuit knowledge question and answer task based on the core interactive agent and the plurality of task agents.

[0031] Optionally, the multi-modal circuit dataset construction module is further configured to:

[0032] generate a corresponding circuit picture for each circuit code in the circuit code dataset using a script, obtain the first set of circuit pictures, use a large language model to generate a natural language description of the circuit code dataset, and obtain a natural language description result of the circuit code; and construct a multi-modal circuit dataset based on the first set of circuit pictures and the natural language description result of the corresponding circuit code.

[0033] Optionally, the multi-modal general dataset construction module is further configured to:

[0034] generate a second set of circuit pictures based on the Python code, use a large language model to generate a natural language description of the Python code, and obtain a natural language description result of the Python code, and construct a multi-modal general dataset based on the second set of circuit pictures and the natural language description result of the corresponding Python code; wherein the second set of circuit pictures includes a circuit structure diagram, a state transition diagram, a timing diagram, and a flowchart.

[0035] Optionally, the multi-modal general dataset construction module is further configured to:

[0036] The circuit structure diagram, the state transition diagram, the timing diagram and the flowchart are called by using the Python code to generate a related library, and a plurality of circuit pictures are randomly generated to construct a second group of circuit pictures.

[0037] Optionally, the training module is further configured to:

[0038] The multi-modal design specification understanding evaluation benchmark is designed, and the trained multi-modal large language model is evaluated.

[0039] Optionally, the construction module is further configured to:

[0040] The prompt words are customized for the circuit design task, the circuit verification task and the circuit knowledge question and answer task, and the multi-modal large language model is constructed into a plurality of task agents according to the prompt words and the trained multi-modal large language model.

[0041] Optionally, the output module is further configured to:

[0042] The user input is read by the core interaction agent, and the task of the user is determined, the task of the user is assigned to the plurality of task agents for execution, the outputs of the plurality of task agents are integrated, and the integrated result is returned to the user; wherein the task of the user includes circuit design, circuit verification and circuit knowledge question and answer.

[0043] In another aspect, a Verilog generation verification device is provided, comprising a processor, and a memory having computer readable instructions stored thereon, wherein the computer readable instructions, when executed by the processor, implement any one of the above-mentioned methods for Verilog generation verification of multi-modal circuit design specifications.

[0044] In another aspect, a computer readable storage medium is provided, wherein the storage medium stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement any one of the above-mentioned methods for Verilog generation verification of multi-modal circuit design specifications.

[0045] The technical scheme provided by the embodiments of the application has at least the following beneficial effects:

[0046] In the present application, a Verilog code generation and verification method based on a multi-modal multi-agent large language model is proposed, a large-scale open source dataset and a picture dataset are introduced for multi-modal large language model fine-tuning training; prompt words are designed to improve the ability of the multi-modal large model in circuit generation, circuit verification and circuit knowledge question and answer tasks, and multiple agents are constituted; a core interactive agent and a task agent collaborative framework are designed for task allocation and answer integration; the present application can generate and verify circuit according to design specifications containing multiple modalities, and solves the problems of low circuit generation accuracy and low verification efficiency of the existing method. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0048] Figure 1 It is a Verilog generation and verification method process for multi-modal circuit design specification provided by the embodiment of the present application Figure 1 ;

[0049] Figure 2 It is a Verilog generation and verification method process for multi-modal circuit design specification provided by the embodiment of the present application Figure 2 ;

[0050] Figure 3 It is a Verilog generation and verification device block diagram for multi-modal circuit design specification provided by the embodiment of the present application

[0051] Figure 4 It is a structural schematic diagram of a Verilog generation and verification device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the present application will be described below in combination with the drawings.

[0053] In the embodiments of the present application, the words such as "example", "for example" are used to represent as an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present application, the meaning expressed by "and / or" can be both, or can be one of the two.

[0054] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0055] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0056] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0057] This invention provides a Verilog generation and verification method for multimodal circuit design specifications. This method can be implemented using a Verilog generation and verification device, which can be a terminal or a server. Figure 1 , Figure 2 The flowchart shown is a Verilog generation and verification method for multimodal circuit design specifications. The processing flow of this method may include the following steps:

[0058] S1. Obtain the circuit code dataset, generate the first set of circuit images based on the circuit code dataset, use a large language model to perform natural language description on the circuit code dataset, obtain the natural language description results of the circuit code, and then construct a multimodal circuit dataset; wherein, the first set of circuit images includes circuit structure diagram, state transition diagram, timing diagram and flowchart.

[0059] Specifically, for each circuit code in the circuit code dataset, a script is used to generate a corresponding circuit image to obtain the first set of circuit images; a large language model is used to perform natural language description on the circuit code dataset to obtain the natural language description results of the circuit codes; and a multimodal circuit dataset is constructed based on the first set of circuit images and the corresponding natural language description results of the circuit codes.

[0060] In one feasible implementation, a large-scale circuit dataset is collected from an open-source website, and a script is used to generate circuit structure diagrams, state transition diagrams, etc., corresponding to the circuit code. A large language model is then used to describe the aforementioned dataset in natural language, ultimately forming a multimodal circuit dataset.

[0061] S2. Generate a second set of circuit images based on the Python code, use a large language model to perform natural language description on the Python code, obtain the natural language description results of the Python code, and then construct a multimodal general dataset.

[0062] Specifically, the circuit structure diagram, the state transition diagram, the timing diagram and the flowchart are called using Python code to generate a related library, a plurality of circuit pictures are randomly generated to construct a second group of circuit pictures, a large language model is used to describe the Python code in natural language to obtain a natural language description result of the Python code, and a multi-modal general data set is constructed according to the second group of circuit pictures and the natural language description result of the corresponding Python code; wherein the second group of circuit pictures includes the circuit structure diagram, the state transition diagram, the timing diagram and the flowchart.

[0063] In a feasible implementation, the state transition diagram, the timing diagram, the flowchart and the circuit structure diagram are generated using a script, natural language description and data cleaning are performed using a large language model, and finally a multi-modal general data set is formed.

[0064] Specifically, the state transition diagram, the timing diagram, the flowchart and the circuit structure diagram are called using Python to generate a related library, a plurality of pictures are randomly generated, and the Python code used to generate the pictures is converted into natural language expression using a general large language model, so as to obtain a plurality of pictures and their natural language description pairs, which can be used to train a model to improve the ability of the model to interpret picture content.

[0065] S3, fine-tuning and training a multi-modal large language model according to the multi-modal circuit data set and the multi-modal general data set to obtain a trained multi-modal large language model.

[0066] Optionally, S3 further includes:

[0067] A multi-modal design specification understanding evaluation benchmark is designed, including circuit design specifications, circuit related pictures, reference verilog code and verilog test platform. The trained multi-modal large language model is evaluated in terms of syntax correctness and functional correctness.

[0068] S4, customizing prompt words for different tasks, and constructing a plurality of task agents according to the prompt words and the trained multi-modal large language model.

[0069] In a feasible implementation, the task agents are constructed for circuit design, circuit verification, circuit knowledge question and answer and other tasks using custom prompt words, and the tasks and the agents correspond one by one to improve the execution ability of the model for specific tasks.

[0070] S5, designing a core interactive agent, and completing circuit design, circuit verification and circuit knowledge question and answer tasks according to the core interactive agent and the plurality of task agents.

[0071] Specifically, the core interaction agent reads user input and determines the user's task, assigns the user's task to multiple task agents for execution, integrates the outputs of the multiple task agents, and returns the integration result to the user; wherein the user's task includes circuit design, circuit verification and circuit knowledge question answering.

[0072] In an available implementation, a core interaction agent and a task agent collaborative architecture are designed for task allocation and answer integration.

[0073] Specifically, the core interaction agent is responsible for interacting with the user, reading user input and determining user requirements (circuit design, circuit verification or circuit knowledge question answering), then assigning user input to specific agents for task execution, waiting for the task agent to respond, integrating the task agent's output, and returning the final result to the user.

[0074] In the embodiment of the application, a Verilog code generation and verification method based on a multi-modal multi-agent large language model is proposed, which introduces large-scale open source data sets and picture data sets for multi-modal large language model fine-tuning training; prompt words are designed to improve the ability of multi-modal large models in circuit generation, circuit verification and circuit knowledge question answering tasks, and multiple agents are formed; a core interaction agent and a task agent collaborative framework are designed for task allocation and answer integration; the present application can generate and verify circuit with multiple modal design specifications, solving the problem of low circuit generation accuracy and low verification efficiency of existing methods.

[0075] Figure 3 is a Verilog generation and verification device block diagram for a multi-modal circuit design specification according to an exemplary embodiment, which is used for a Verilog generation and verification method for a multi-modal circuit design specification. Referring to Figure 3 The device includes a multi-modal circuit data set construction module 310, a multi-modal general data set construction module 320, a training module 330, a construction module 340 and an output module 350. Wherein:

[0076] The multi-modal circuit data set construction module 310 is used to obtain a circuit code data set, generate a first group of circuit pictures according to the circuit code data set, use a large language model to describe the circuit code data set in natural language, obtain the natural language description result of the circuit code, and further construct a multi-modal circuit data set; wherein the first group of circuit pictures includes circuit structure diagram, state transition diagram, timing diagram and flowchart.

[0077] The multi-modal general data set construction module 320 is configured to generate a second group of circuit pictures according to Python code, perform natural language description on the Python code by using a large language model, obtain a natural language description result of the Python code, and then construct a multi-modal general data set.

[0078] The training module 330 is configured to fine-tune train a multi-modal large language model according to the multi-modal circuit data set and the multi-modal general data set, and obtain a trained multi-modal large language model.

[0079] The construction module 340 is configured to customize prompt words for different tasks, and construct a plurality of task agents according to the prompt words and the trained multi-modal large language model.

[0080] The output module 350 is configured to design a core interactive agent, and complete a circuit design, circuit verification and circuit knowledge question and answer task according to the core interactive agent and the plurality of task agents.

[0081] In the embodiment of the present application, a Verilog code generation and verification method based on a multi-modal multi-agent large language model is provided, the large-scale open source data set and the picture data set are introduced for fine-tuning training of the multi-modal large language model; the prompt words are designed to improve the ability of the multi-modal large model in the circuit generation, circuit verification and circuit knowledge question and answer tasks, and a plurality of agents are constituted; the core interactive agent and the task agent are designed to form a collaborative framework, and the task allocation and answer integration are performed; the present application can generate and verify the circuit according to the design specification containing multiple modalities, and solves the problems of low circuit generation accuracy and low verification efficiency of the existing method.

[0082] Figure 4 is a structural schematic diagram of a Verilog generation and verification device provided by the embodiment of the present application, as Figure 4 shown, the Verilog generation and verification device can include the Verilog generation and verification apparatus for multi-modal circuit design specification shown in the above Figure 3 Optionally, the Verilog generation and verification device 410 can include a first processor 2001.

[0083] Optionally, the Verilog generation and verification device 410 can further include a memory 2002 and a transceiver 2003.

[0084] Among them, the first processor 2001 and the memory 2002 and the transceiver 2003, such as can be connected through the communication bus.

[0085] The following will be Figure 4 specifically introduced to each component of the Verilog generation and verification device 410:

[0086] The first processor 2001, the control center of the Verilog generation and verification device 410, can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0087] Optionally, the first processor 2001 can perform various functions of the Verilog generation and verification device 410 by running or executing software programs stored in the memory 2002 and calling data stored in the memory 2002.

[0088] In a specific implementation, as one example, the first processor 2001 may include one or more CPUs, for example... Figure 4 CPU0 and CPU1 are shown in the diagram.

[0089] In a specific implementation, as one example, the Verilog generation and verification device 410 may also include multiple processors, for example... Figure 4 The first processor 2001 and the second processor 2004 are shown in the diagram. Each of these processors can be a single-core processor or a multi-core processor. Here, a processor can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0090] The memory 2002 is used to store the software program that executes the present invention, and is controlled by the first processor 2001 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.

[0091] Optionally, the memory 2002 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this. The memory 2002 can be integrated with the first processor 2001 or exist independently and be coupled with the first processor 2001 through an interface circuit (not shown in the figure) of the Verilog generation and verification device 410, and the embodiments of the present application do not make specific limitations here. Figure 4

[0092] The transceiver 2003 is configured to communicate with a network device or a terminal device.

[0093] Optionally, the transceiver 2003 can include a receiver and a transmitter (not shown in the figure separately). The receiver is configured to realize the receiving function, and the transmitter is configured to realize the transmitting function. Figure 4

[0094] Optionally, the transceiver 2003 can be integrated with the first processor 2001 or exist independently and be coupled with the first processor 2001 through an interface circuit (not shown in the figure) of the Verilog generation and verification device 410, and the embodiments of the present application do not make specific limitations here. Figure 4 It should be noted that the structure of the Verilog generation and verification device 410 shown in the figure does not constitute a limitation on the router, and the actual knowledge structure identification device can include more or fewer components than those shown in the figure, or combine certain components, or different component arrangements.

[0095] ​ In addition, the technical effects of the Verilog generation and verification device 410 can refer to the technical effects of the Verilog generation and verification method for the multi-modal circuit design specification described in the above method embodiments, which will not be repeated here.

[0096]

[0097] ​​​​It is to be understood that the first processor 2001 in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic components, discrete hardware components, etc. The general-purpose processor can be a microprocessor or can also be any conventional processor.

[0098] It is also to be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memory. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM).

[0099] The above-described embodiments can be implemented in whole or in part by software, hardware (such as a circuit), firmware, or any combination thereof. When implemented in software, the above-described embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are wholly or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center through a wired (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. containing one or more available medium collections. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state disk.

[0100] It should be understood that the term "and / or" herein merely describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after it, but it can also represent an "and / or" relationship, which can be understood according to the context before and after it.

[0101] In the present application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or the like means any combination of the items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0102] It should be understood that in various embodiments of the present application, the size of the sequence number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0103] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the devices, apparatuses and units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0105] In several embodiments provided by the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0106] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0107] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0108] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0109] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A Verilog generation and verification method for multimodal circuit design specifications, characterized in that, The method comprises: S1, acquiring a circuit code data set, generating a first group of circuit pictures according to the circuit code data set, using a large language model to describe the circuit code data set in natural language, obtaining a natural language description result of the circuit code, and then constructing a multi-modal circuit data set; wherein the first group of circuit pictures comprises a circuit structure diagram, a state transition diagram, a timing diagram and a flowchart; S2, generating a second group of circuit pictures according to the Python code, using a large language model to describe the Python code in natural language, obtaining a natural language description result of the Python code, and then constructing a multi-modal general data set; S3, fine-tuning a multi-modal large language model according to the multi-modal circuit data set and the multi-modal general data set, and obtaining a trained multi-modal large language model; S4, customizing prompt words for different tasks, and constructing a plurality of task agents according to the prompt words and the trained multi-modal large language model; S5, designing a core interaction agent, and completing circuit design, circuit verification and circuit knowledge question and answer tasks according to the core interaction agent and the plurality of task agents.

2. The Verilog generation verification method for multi-modal circuit design specification according to claim 1, wherein, In the S1, the first group of circuit pictures is generated according to the circuit code data set, the circuit code data set is described in natural language using a large language model, a natural language description result of the circuit code is obtained, and a multi-modal circuit data set is constructed, comprising: Each circuit code in the circuit code data set is generated using a script to generate a corresponding circuit picture, obtaining a first group of circuit pictures; the circuit code data set is described in natural language using a large language model, obtaining a natural language description result of the circuit code; and a multi-modal circuit data set is constructed according to the first group of circuit pictures and the natural language description result of the corresponding circuit code.

3. The Verilog generation and verification method for multi-modal circuit design specification according to claim 1, wherein, In the S2, the second group of circuit pictures is generated according to the Python code, the Python code is described in natural language using a large language model, a natural language description result of the Python code is obtained, and a multi-modal general data set is constructed, comprising: A second group of circuit pictures is generated according to the Python code, the Python code is described in natural language using a large language model, a natural language description result of the Python code is obtained, and a multi-modal general data set is constructed according to the second group of circuit pictures and the natural language description result of the corresponding Python code; wherein the second group of circuit pictures comprises a circuit structure diagram, a state transition diagram, a timing diagram and a flowchart.

4. The method of claim 1, wherein the method is performed by a computer system. In the S2, the second group of circuit pictures is generated according to the Python code, comprising: A related library is generated by calling a circuit structure diagram, a state transition diagram, a timing diagram and a flowchart using a Python code, and a second group of circuit pictures is constructed by randomly generating a plurality of circuit pictures.

5. The method for Verilog generation verification against multi-modal circuit design specification as claimed in claim 1 wherein, The S3 further comprises: A multi-modal design specification understanding evaluation benchmark is designed, and the trained multi-modal large language model is evaluated.

6. The Verilog generation and verification method for multi-modal circuit design specification according to claim 1, wherein, In the S4, the prompt words are customized for different tasks, and a plurality of task agents are constructed according to the prompt words and the trained multi-modal large language model, comprising: The prompt words are customized for circuit design tasks, circuit verification tasks, and circuit knowledge question and answer tasks, and multiple task agents are constructed according to the prompt words and the trained multi-modal large language model for any task.

7. The Verilog generation and verification method for multi-modal circuit design specification according to claim 1, wherein, The S5 includes completing circuit design, circuit verification, and circuit knowledge question and answer tasks according to the core interaction agent and the multiple task agents. The core interaction agent reads user input and determines the user's task, assigns the user's task to the multiple task agents for execution, integrates the outputs of the multiple task agents, and returns the integration result to the user; wherein the user's task includes circuit design, circuit verification, and circuit knowledge question and answer.

8. A Verilog generation verification apparatus for multi-modal circuit design specification, the Verilog generation verification apparatus for multi-modal circuit design specification is used to implement the Verilog generation verification method for multi-modal circuit design specification as claimed in any one of claims 1-7, characterized in that, The device includes: A multi-modal circuit dataset construction module is configured to obtain a circuit code dataset, generate a first set of circuit pictures based on the circuit code dataset, use a large language model to generate a natural language description of the circuit code dataset, and obtain a natural language description result of the circuit code, and then construct a multi-modal circuit dataset; wherein the first set of circuit pictures includes circuit structure diagrams, state transition diagrams, timing diagrams, and flowcharts; A multi-modal general dataset construction module is configured to generate a second set of circuit pictures based on Python code, use a large language model to generate a natural language description of the Python code, and obtain a natural language description result of the Python code, and then construct a multi-modal general dataset; A training module is configured to fine-tune a multi-modal large language model based on the multi-modal circuit dataset and the multi-modal general dataset, and obtain a trained multi-modal large language model; A construction module is configured to customize prompt words for different tasks, and construct multiple task agents based on the prompt words and the trained multi-modal large language model; An output module is configured to design a core interaction agent, and complete circuit design, circuit verification, and circuit knowledge question and answer tasks according to the core interaction agent and the multiple task agents.

9. A Verilog generation verification apparatus, characterized by comprising: The Verilog generation verification device includes: A processor; A memory having computer readable instructions stored thereon, the computer readable instructions being executed by the processor to implement the method of any one of claims 1 to 7.

10. A computer readable storage medium, characterized in that, The computer readable storage medium stores program code that can be invoked and executed by the processor to implement the method of any one of claims 1 to 7.

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