Display panel and display device

Abstract

The invention provides a display panel and a display device. A first-class shift register group in the gate drive circuit comprises a plurality of cascaded first shift registers and a plurality of first gating units, and first output ends of the first shift registers from the ith stage to the last stage are electrically connected with the first gating units. A first initialization module, a threshold compensation module and a driving module in the pixel driving circuit are connected to a first node, and the first node is located between the driving module and a light-emitting element. The first output ends of at least part of the first shifting registers are electrically connected with the control ends of the threshold compensation modules in the at least one row of pixel driving circuits through the first gating units, and the second output ends of at least part of the first shifting registers are electrically connected with the first initialization modules in the at least one row of pixel driving circuits. According to the embodiment of the invention, the number of the gating units can be reduced while partition refreshing is realized, so that a narrow frame of the display panel can be realized.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Display panels typically include display areas and non-display areas. The display area is equipped with multiple pixel driving circuits and light-emitting elements. The pixel driving circuits are used to drive the light-emitting elements to emit light in order to display images. The non-display area is equipped with gate driving circuits, which are used to provide scanning control signals to the pixel driving circuits so that the light-emitting elements are lit up line by line under the drive of the pixel driving circuits.

[0003] In related technologies, in order to achieve partitioned refresh of the display area, it is necessary to add relevant gating devices to the gate driving circuit, which increases the size of the gate driving circuit and thus makes the bezel of the display panel larger. Summary of the Invention

[0004] The present invention provides a display panel and display device that can reduce the number of gating units while achieving partitioned refresh, thereby facilitating the realization of narrow bezels.

[0005] In a first aspect, the present invention provides a display panel, the display panel comprising:

[0006] Pixel driving circuit and gate driving circuit;

[0007] The gate driving circuit includes a first gate driving module, and the first gate driving module includes a first type of shift register group;

[0008] The first type of shift register group includes multiple cascaded first shift registers and multiple first gating units. The first output terminals of the i-th stage first shift register to the last stage first shift register are all electrically connected to the first gating unit, where i is a positive integer greater than 1.

[0009] The pixel driving circuit includes a first initialization module, a threshold compensation module, a driving module, and a light-emitting element. The first initialization module, the threshold compensation module, and the driving module are connected to a first node, and the first node is located between the driving module and the light-emitting element.

[0010] At least a portion of the first output terminal of the first shift register is electrically connected to the control terminal of the threshold compensation module in at least one row of pixel driving circuit through the first gating unit, and at least a portion of the second output terminal of the first shift register is electrically connected to the first initialization module in at least one row of pixel driving circuit.

[0011] In a second aspect, embodiments of the present invention provide a display device including the display panel described in the first aspect.

[0012] In the display panel provided by the embodiments of the present invention, a first initialization module, a threshold compensation module, and a driving module in the pixel driving circuit are connected to a first node, and the first node is located between the driving module and the light-emitting element. At least a portion of the first output terminals of the first shift registers in the gate driving circuit are electrically connected to the control terminal of the threshold compensation module in at least one row of pixel driving circuits through a first gating unit, and at least a portion of the second output terminals of the first shift registers are electrically connected to the first initialization module in at least one row of pixel driving circuits. Thus, during high refresh, at least a portion of the effective level scan signals output from the first output terminal of the first shift register, after passing through the first gating unit, output an effective level first scan signal to the control terminal of the threshold compensation module. The effective level second scan signal output from the second output terminal is directly transmitted to the control terminal of the first initialization module. When both the threshold compensation module and the first initialization module are on, the corresponding row pixel driving circuit is refreshed. During low refresh, at least a portion of the scan signals output from the first output terminal of the first shift register cannot pass through the disconnected first gating unit, thus outputting an invalid level first scan signal to the control terminal of the threshold compensation module. The second scan signal output from the second output terminal is directly transmitted to the control terminal of the first initialization module. When the threshold compensation module is off, regardless of whether the first initialization module is on or off, the corresponding row pixel driving circuit is not refreshed. Furthermore, by setting the output terminal of the first initialization module to the first node and removing the gating unit of the second scan signal, the number of gating units is reduced. This achieves partitioned refresh while also being advantageous for achieving a narrow bezel on the display panel. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0014] Figure 2 This is a circuit diagram of a gate driving circuit provided in an embodiment of the present invention;

[0015] Figure 3 This is a circuit diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0016] Figure 4 This is a timing diagram of the operation of a display panel provided in an embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0018] Figure 6 This is a timing diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 7This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0020] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0021] Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be fully described below with reference to the accompanying drawings of the embodiments of this invention through specific implementation methods. Obviously, the described embodiments are only some, not all, embodiments of this invention. Various modifications and variations can be made to this invention without departing from the spirit or scope of this invention, which will be obvious to those skilled in the art. Therefore, this invention is intended to cover modifications and variations of this invention that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents.

[0024] Furthermore, the terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "an," "one," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "including" or "comprising" mean that the element or object preceding the word encompasses the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, descriptions of "same" or "equal" involved in the embodiments of this disclosure do not mean that two objects are completely equal in size or shape; they are allowed to be approximately the same or approximately equal within a certain error range. It should be noted that the implementation methods provided in the embodiments of this invention can be combined with each other without contradiction.

[0025] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a circuit diagram of a gate driving circuit provided in an embodiment of the present invention. Figure 3This is a circuit diagram of a pixel driving circuit provided in an embodiment of the present invention. See also... Figures 1-3 The display panel includes a pixel driving circuit 01 and a gate driving circuit 02. The gate driving circuit 02 includes a first gate driving module 20, which includes a first type of shift register group 210. The first type of shift register group 210 includes multiple cascaded first shift registers 211 and multiple first gating units 212. The first output terminals of the i-th stage first shift register to the last stage first shift register are all electrically connected to the first gating unit 212, where i is a positive integer greater than 1. The pixel driving circuit 01 includes a first initialization module 110, a threshold compensation module 120, a driving module 130, and a light-emitting element 140. The first initialization module 110, the threshold compensation module 120, and the driving module 130 are connected to a first node N1, and the first node N1 is located between the driving module 130 and the light-emitting element 140. At least a portion of the first output terminal of the first shift register 211 is electrically connected to the control terminal of the threshold compensation module 120 in at least one row pixel driving circuit 01 through the first gating unit 212, and at least a portion of the second output terminal of the first shift register 211 is electrically connected to the first initialization module 150 in at least one row pixel driving circuit 01.

[0026] Specifically, such as Figure 1 and Figure 2 As shown, the display panel includes a display area AA and a non-display area BB. The non-display area BB surrounds the display area AA. The display area AA includes multiple pixel driving circuits 01 arranged in an array and multiple light-emitting elements 140. The pixel driving circuits 01 are electrically connected to the light-emitting elements 140, and provide various driving signals to the light-emitting elements 140 to make the light-emitting elements 140 emit light to realize the display of the image on the display panel. The non-display area BB surrounds at least a portion of the display area AA. For example, as shown... Figure 1 In the illustrated embodiment, the non-display area BB is the bezel area of ​​the display panel, including the left bezel area, right bezel area, top bezel area, and bottom bezel area. Furthermore, the display panel also includes a gate driving circuit 02 and a driving chip 03 located in the non-display area BB. The gate driving circuit 02 can be located in the left bezel area and / or the right bezel area of ​​the display panel. The gate driving circuit 02 is electrically connected to the pixel driving circuit 01 of each row via scan signal lines 04, and is used to provide scan signals to the pixel driving circuit 01 of each row. (Continue to see...) Figure 1 The driver chip 03 can be located in the lower border area of ​​the non-display area BB. The driver chip 03 is electrically connected to the pixel driving circuit 01 of each column through the data signal line 05, thereby providing data signals to the pixel driving circuit 01 of each column.

[0027] Furthermore, display panels typically require partitioned refresh rates. For example, in the column direction of the pixel driving circuit array 01, the pixel driving circuit 01 is divided into multiple display areas, each including multiple rows of pixel driving circuits 01, and the refresh rates of different display areas are different. In the prior art, to achieve partitioned refresh of the display panel, the gate driving circuit is typically configured to include multiple cascaded first shift registers and multiple cascaded second shift registers. The first shift register provides a first scan signal to the pixel driving circuit of the corresponding row, and the second shift register provides a second scan signal to the pixel driving circuit of the corresponding row. A gating unit is provided at the output of each first shift register and second shift register. When the corresponding display area needs to achieve a high refresh rate, the corresponding gating unit is turned on, so that the first scan signal with an effective level provided by the first shift register and the second scan signal with an effective level provided by the second shift register can be provided to the pixel driving circuit of the corresponding display area. When a low refresh rate (high refresh rate) is required for the corresponding display area, the corresponding gating unit is turned off, preventing the first scan signal provided by the first shift register and the second scan signal provided by the second shift register from being supplied to the pixel driving circuit of the corresponding display area. However, since gating units need to be set at the outputs of both the first and second shift registers, the gating units occupy a large space, resulting in a large bezel area for the display panel, which is not conducive to achieving a narrow bezel for the display panel.

[0028] Therefore, the embodiments of the present invention improve both the pixel driving circuit 01 and the gate driving circuit 02. For example... Figure 2As shown, the pixel driving circuit 01 in this embodiment of the invention includes a first initialization module 110, a threshold compensation module 120, a driving module 130, and a light-emitting element 140. The driving module 130 and the light-emitting element 20 are connected in series between a first power signal terminal PVDD and a second power signal terminal PVEE, forming a first series branch. Under the action of the first power signal terminal PVDD and the second power signal terminal PVEE, the driving module 130 controls the current or voltage flowing through the light-emitting element 140 according to the data signal Vdata input to the driving module 130, thereby controlling the brightness of the light-emitting element 140. The control terminal of the threshold compensation module 120 receives a first scan signal SN1, and its output terminal is electrically connected to the control terminal of the driving module 130. When the first scan signal SN1 is at a valid level, the threshold compensation module 120 performs threshold compensation on the control terminal of the driving module 130 (i.e., it affects the driving current of the driving module 130). In the prior art, the control terminal of the first initialization module 110 receives the second scan signal SN2, and the output terminal of the first initialization module 110 is electrically connected to the control terminal of the driving module 130. When the second scan signal SN2 is at an effective level, the first initialization module 110 initializes the control terminal of the driving module 130 to complete the refresh of the pixel driving circuit 01. In this embodiment of the invention, the position of the first initialization module 110 is changed, and the first initialization module 110 is set at the first node N1 between the driving module 130 and the light-emitting element 140. That is, the first initialization module 150, the threshold compensation module 120 and the driving module 130 are connected to the first node N1, so that when the second scan signal SN2 is at an effective level, the first initialization module 110 will not refresh the pixel driving circuit 01 (without affecting the driving current of the driving module 130).

[0029] Furthermore, this embodiment of the invention also improves the gate driving circuit 02, which includes a first gate driving module 20, and the first gate driving module 20 includes a first type of shift register group 210. The first type of shift register group 210 includes multiple cascaded first shift registers 211 and multiple first gating units 212. The first output terminals of the i-th stage first shift register to the last stage first shift register are all electrically connected to the first gating unit 212. Among them, the first shift registers 211 electrically connected to the first gating unit 212 simultaneously output the first scan signal SN1 and the second scan signal SN2, and the first shift registers 211 without the first gating unit 212 only output the second scan signal SN2. Based on this, at least a portion of the first output terminals of the first shift registers 211 are electrically connected to the control terminal of the threshold compensation module 120 in at least one row pixel driving circuit 01 through the first gating unit 212, and at least a portion of the second output terminals of the first shift registers 211 are electrically connected to the first initialization module 110 in at least one row pixel driving circuit 01. Thus, during high refresh rate, the first gating unit 212 is turned on, and the valid level scan signal can pass through the first gating unit 212, ultimately outputting a valid level first scan signal SN1 to the control terminal of the threshold compensation module 120. Simultaneously, a valid level second scan signal SN2 is directly transmitted to the control terminal of the first initialization module 110. Both the threshold compensation module 120 and the first initialization module 110 are turned on (initializing and threshold compensating the driving module 130) to complete the refresh of the corresponding row pixel driving circuit 01. During low refresh rate, the first gating unit 212 is turned off, and the scan signal output from the second output terminal cannot pass through the first gating unit 212, ultimately outputting an invalid level first scan signal SN1 to the control terminal of the threshold compensation module 120. The second scan signal SN2 is directly transmitted to the control terminal of the first initialization module 110. The first initialization module 110 is either turned on or off. Since the threshold compensation module 120 is not turned on, even if the first initialization module 110 is turned on, it cannot initialize the driving module 130 or perform threshold compensation, thereby achieving low refresh rate for the corresponding row pixel driving circuit 01. The above solution reduces the number of gating units by setting the first initialization module 110 at the first node N1 and removing the gating unit corresponding to the second scan signal SN2, thereby saving the space occupied by the first gate driving module 210. While realizing partitioned refresh, it is also beneficial for realizing a narrow bezel of the display panel.

[0030] It should be noted that, Figure 3 The example described is based solely on the example of the output of the first shift register 211 being electrically connected to a row pixel driving circuit 01, but this is not a limitation. In other embodiments, the output of the first shift register 211 may also be electrically connected to a multi-row pixel driving circuit 01, and those skilled in the art can configure it as needed.

[0031] In summary, in this embodiment of the invention, by setting the first initialization module, threshold compensation module, and driving module in the pixel driving circuit to be connected to the first node, and the first node being located between the driving module and the light-emitting element, and by setting at least a portion of the first output terminals of the first shift register to be electrically connected to the control terminal of the threshold compensation module in at least one row of pixel driving circuits through the first gating unit, and at least a portion of the second output terminals of the first shift register to be electrically connected to the first initialization module in at least one row of pixel driving circuits, the first shift register with the first gating unit outputs a first scan signal and directly outputs a second scan signal through the first gating unit. The first scan signal is output to the threshold compensation module, and the second scan signal is output to the first initialization module. In this way, by removing the gating unit corresponding to the second scan signal, the space occupied by the first gate driving module 210 is saved, and the output terminal of the first initialization module is connected to the first node, which is beneficial for achieving narrow bezels of the display panel while realizing partitioned refresh.

[0032] Optionally, based on the above embodiments, see also... Figure 3 The first output terminal of the first shift register 211 is electrically connected to the control terminal of the threshold compensation module 120 in the row pixel driving circuit 01 through the first gating unit 212, and the second output terminal of the first shift register 211 is electrically connected to the control terminal of the first initialization module 110 in the row pixel driving circuit 01. The first output terminal of the j-th level first shift register is electrically connected to the control terminal of the threshold compensation module 120 in the (j-i+1)-th row pixel driving circuit 01 through the first gating unit 212, and the second output terminal of the j-th level first shift register is electrically connected to the control terminal of the first initialization module 110 in the j-th row pixel driving circuit 01, where j is a positive integer greater than or equal to i.

[0033] For example, such as Figure 2 and Figure 3In the illustrated embodiment, j = 4 and i = 3 is used as an example for explanation. Since the first scan signal SN1 is used to control the conduction of the threshold compensation module 120 to achieve threshold compensation, and the second scan signal SN2 is used to control the conduction of the first initialization module 110 to initialize the driving module 130 (initialization can be achieved when both the threshold compensation module 120 and the first initialization module 110 are conducted), in the same row of pixel driving circuits 01, the initialization timing precedes the threshold compensation timing; that is, the effective level of the second scan signal SN2 needs to be earlier than the effective level of the first scan signal SN1. Therefore, in this embodiment, the first shift register 211 of the pre-i-1 stage does not have a first gating unit 212, and is used to output only the second scan signal SN2. In the cascaded first shift registers 211, the first-stage first shift register 211(1) and the second-stage first shift register 211(2) do not have a first gating unit 212, and both the first-stage first shift register 211(1) and the second-stage first shift register 211(2) only output the second scan signal SN2. The third-stage first shift register 211(3) to the last stage first shift register all have a first gating unit 212 at the first output terminal. The first gating unit 212 is electrically connected to the first output terminal and outputs the first scan signal SN1. The second output terminal directly outputs the second scan signal SN2. Based on this, the first output terminal of the fourth-level first shift register 211(4) outputs the first scan signal SN1 to the control terminal of the threshold compensation module 120 in the second row pixel driving circuit 01 through the first gating unit 212; the second output terminal of the fourth-level first shift register 211(4) outputs the second scan signal SN2 to the control terminal of the first initialization module 110 in the fourth row pixel driving circuit 01; the first output terminal of the fifth-level first shift register 211(5) outputs the first scan signal SN1 to the control terminal of the threshold compensation module 120 in the third row pixel driving circuit 01 through the first gating unit 212; the second output terminal of the fifth-level first shift register 211(5) outputs the second scan signal SN2 to the control terminal of the first initialization module 110 in the fifth row pixel driving circuit 01... In this way, it is ensured that at least some rows of pixel driving circuits 01 can receive the first scan signal SN1 and the second scan signal SN2, thereby ensuring the normal operation of at least some pixel driving circuits 01 while achieving a narrow bezel on the display panel.

[0034] Optionally, based on the above, please refer to [further details]. Figure 2 and Figure 3 The second output terminal of the first shift register 211(1) of the first stage to the second output terminal of the first shift register of the (i-1)th stage are sequentially electrically connected to the control terminal of the first initialization module 110 in the first row pixel driving circuit 01 and the (i-1)th row pixel driving circuit 01.

[0035] For example, such as Figure 2 and Figure 3 In the embodiment shown, taking i=3 as an example, in the two (i-1) level first shift registers 211, the second output terminal of the first level first shift register 211(1) outputs the second scan signal SN2 to the control terminal of the first initialization module 110 in the first row pixel driving circuit 01, and the second output terminal of the second level first shift register 211(1) outputs the second scan signal SN2 to the control terminal of the first initialization module 110 in the second row pixel driving circuit 01. Thus, based on the first output terminal of the j-th level first shift register being electrically connected to the control terminal of the threshold compensation module 120 in the (j-i+1)-th row pixel driving circuit 01 through the first gating unit 212, and the second output terminal of the j-th level first shift register being electrically connected to the control terminal of the first initialization module 110 in the j-th row pixel driving circuit 01, it is ensured that each row pixel driving circuit 01 can receive the first scan signal SN1 and the second scan signal SN2, thereby ensuring the normal operation of the display panel while achieving a narrow bezel.

[0036] Optionally, based on the above embodiments, Figure 4 This is a timing diagram of a display panel provided in an embodiment of the present invention. See also: Figure 3 and Figure 4 The first output of the first shift register 211 outputs a first scan signal SN1 to the control terminal of the threshold compensation module 120 through the first gating unit 212. At least a portion of the second output of the first shift register 211 outputs a second scan signal SN2 to the control terminal of the first initialization module 110. The operation phases of the display panel include a first refresh frame S1 and a second refresh frame S2. In the first refresh frame S1, both the first scan signal SN1 and the second scan signal SN2 have valid levels. In the second refresh frame SN2, the second scan signal SN2 has a valid level, and the first scan signal SN1 has an invalid level.

[0037] For example, such as Figures 2-4In the illustrated embodiment, the first initialization module 110 includes a first transistor M1, the threshold compensation module 120 includes a second transistor M2, and the driving module 130 includes a third transistor M3. The first terminal of the first transistor M1 receives a first reference signal Vref1, the second terminal of the first transistor M1 is electrically connected to a first node N1, and the gate of the first transistor M1 receives a second scan signal SN2. The first terminal of the second transistor M2 is electrically connected to the first node N1, the second terminal of the second transistor M2 is electrically connected to the gate of the third transistor M3, and the gate of the second transistor M2 receives the first scan signal SN1. The operating phases of the display panel include a first refresh frame S1 and a second refresh frame S2. The refresh frequency of the first refresh frame S1 is greater than the refresh frequency of the second refresh frame S2; that is, the first refresh frame S1 is a high refresh rate, and the second refresh frame is a low refresh rate. In the first refresh frame S1, the gate of the third transistor M3 needs to be initialized and data written. Therefore, by setting both the first scan signal SN1 and the second scan signal SN2 to include an active level, both the first transistor M1 and the second transistor M2 are turned on. At this time, the first reference signal Vref can reach the gate of the third transistor M3 through the first transistor M1 and the second transistor M2, thereby initializing the gate of the third transistor M3. In addition, when the second transistor M2 is turned on, a threshold voltage can be provided to the gate of the third transistor M3 for threshold compensation. In the second refresh frame S2, the first gating unit 212 is deactivated, causing the first scan signal SN1 to include an invalid level. The second scan signal SN2 is the scan signal (pulse signal) output from the second output terminal of the first shift register 211, and therefore includes an active level. At this time, the first transistor M1 is turned on, and the second transistor M2 is turned off. Because the second transistor M2 is turned off, even if the first transistor M1 is turned on, the first reference signal Vref cannot be transmitted to the gate of the third transistor M3, meaning that the initialization of the gate of the third transistor M3 and threshold compensation cannot be completed. Thus, by setting both the first scan signal SN1 and the second scan signal SN2 to include active levels in the first refresh frame S1, and the second scan signal SN2 to include an active level in the second refresh frame SN2, while the first scan signal SN1 includes an invalid level, the display panel can achieve zoned refresh.

[0038] It should be noted that the pixel driving circuit 01 may also include a first light-emitting control module 150 and a second light-emitting control module 160. The first light-emitting control module 150 includes a fourth transistor M4, and the second light-emitting control module 160 includes a fifth transistor M5. The first terminal of the fourth transistor M4 is electrically connected to the first power signal terminal PVDD, and the second terminal is electrically connected to the first terminal of the third transistor M3. The control terminal receives the light-emitting control signal EM. The first terminal of the fifth transistor M5 is electrically connected to the first node N1, and the second terminal is electrically connected to the light-emitting element 140. The control terminal receives the light-emitting control terminal EM. When the light-emitting control signal EM is at an effective level, the branches containing the first power signal terminal PVDD and the second power signal terminal PVEE are turned on, thereby controlling the light-emitting time of the light-emitting element 140 through the fourth transistor M4 and the fifth transistor M5.

[0039] Understandably, based on the above, please refer to [further details]. Figure 4 In the first refresh frame S1, the end time of the effective level of the first scan signal SN1 is located between the start and end times of the effective level of the second scan signal SN2. Specifically, since the gate of the third transistor M3 needs to be initialized in the first refresh frame S1, and the first reference signal Vref1 can reach the gate of the third transistor M3 only when the first transistor M1 and the second transistor M3 are simultaneously turned on, by setting the end time of the effective level of the first scan signal SN1 in the first refresh frame S1 to be located between the start and end times of the effective level of the second scan signal SN2, the effective levels of the first scan signal SN1 and the second scan signal SN2 in the first refresh frame S1 at least partially overlap, thereby ensuring the normal operation of the display panel in the first refresh frame S1.

[0040] Optionally, based on the above, please refer to [further details]. Figures 2-4 The pulse width W of the effective level of the first scan signal SN1 satisfies: W>n*(i-1)*H, where n is the number of pixel driving circuit rows connected to the first output terminal of the first shift register 211, and H is the refresh time of a row of pixel driving circuit 01.

[0041] Specifically, such as Figures 2-4As shown, both the first and second outputs of the first shift register 211 output the same scan signal. A first gating unit 212 is set at a portion of the first output of the first shift register 211. After passing through the first gating unit 212, the first output outputs the first scan signal SN1. Since the first gating unit 212 is only used to control whether the scan signal can pass through, the pulse widths of the first scan signal SN1 and the second scan signal SN2 are the same for the pixel driving circuit 01. For the same row of pixel driving circuits 01, in the first refresh frame S1, the first scan signal SN1 is equivalent to the second scan signal SN2 being shifted backward. Based on this, by setting the pulse width W of the effective level of the first scan signal SN1 to satisfy: W > n*(i-1)*H, it is ensured that the pulse widths of the effective levels of the first scan signal SN1 and the second scan signal SN2 are long enough to overlap in the first refresh frame S1, thereby ensuring the normal operation of the display panel in the first refresh frame S1.

[0042] Optional, Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 2 and Figure 5 The first gate driving module 20 further includes a second type of shift register group 220. The second type of shift register group 220 includes multiple cascaded second shift registers 221 and multiple second gating units 222. The first output terminals of each of the second shift registers 221 are electrically connected to the second gating unit 222. The pixel driving circuit 01 also includes a data writing module 170, a second initialization module 180, and a lift-up module 190. The data writing module 170, driving module 130, and lift-up module 190 are connected to the second node N2. The second initialization module 180 is electrically connected to the first electrode of the light-emitting element 140. At least a portion of the first output terminals of the second shift registers 221 are electrically connected to the control terminals of the data writing module 170 in at least one row of the pixel driving circuit 01 through the second gating unit 222. At least a portion of the second output terminals of the second shift registers 221 are electrically connected to the control terminals of the second initialization module 180 and the lift-up module 190 in at least one row of the pixel driving circuit 01.

[0043] Specifically, such as Figure 2As shown, the pixel driving circuit 01 also includes a data writing module 170, a second initialization module 180, and a lift-up module 190. The data writing module 170 includes a sixth transistor M6, the second initialization module 180 includes a seventh transistor M7, and the lift-up module 190 includes an eighth transistor M8. Specifically, the first terminal of the sixth transistor M6 receives the data signal Vdata, its control terminal receives the third scan signal SN3, and its second terminal is electrically connected to the second node N2. The first terminal of the seventh transistor M7 receives the second reference signal Vref2, its second terminal is electrically connected to the first terminal of the light-emitting element 140, and its control terminal receives the fourth scan signal SN4. The first terminal of the eighth transistor M8 receives the first fixed signal DVH, its second terminal is electrically connected to the second node N2, and its gate receives the fourth scan signal SN4. In this embodiment of the invention, the fourth scan signal SN4 is used to control the on and off states of the eighth transistor M8 and the seventh transistor M7. When the eighth transistor M8 is on, it ensures a high potential for the second node N2. When the seventh transistor M7 is on, it initializes the first electrode of the light-emitting element 140. That is, during low refresh, even if the eighth transistor M8 and the seventh transistor M7 are on, it will not affect the gate of the third transistor M3. Therefore, this embodiment of the invention further includes a second type of shift register group 220 in the first gate driving module 20. The second type of shift register group 220 includes multiple cascaded second shift registers 221 and multiple second gating units 222. The first output terminals of the second shift registers 221 are all electrically connected to the second gating units 222.

[0044] Furthermore, at least a portion of the first output terminal of the second shift register 221 is electrically connected to the control terminal of the data writing module 170 in at least one row pixel driving circuit 01 via the second gating unit 222, and at least a portion of the second output terminal of the second shift register 221 is electrically connected to the control terminals of the second initialization module 180 and the lift-up module 190 in at least one row pixel driving circuit 01. Thus, during high refresh, the second gating unit 222 is turned on, and the valid level scan signal can pass through the second gating unit 222, ultimately outputting a valid level third scan signal SN3 to the control terminal of the data writing module 170. At the same time, the valid level fourth scan signal SN4 is directly transmitted to the control terminals of the second initialization module 180 and the lift-up module 190 to complete the refresh of the corresponding row pixel driving circuit 01. During low refresh, the second gating unit 222 is turned off, and the scan signal output from the second output terminal cannot pass through the second gating unit 222. Ultimately, an invalid third scan signal SN3 is output to the control terminal of the data writing module 170, while an effective fourth scan signal SN4 reaches the control terminals of the second initialization module 180 and the lift-up module 190. The second initialization module 180 and the lift-up module 190 are turned on, but this does not affect the gate of the third transistor M3, thus achieving low refresh for the corresponding row pixel driving circuit 01. This scheme, by removing the gating unit corresponding to the fourth scan signal, further reduces the number of gating units, saving space occupied by the first gate driving module 20. While achieving partitioned refresh, it is also beneficial for achieving a narrow bezel on the display panel.

[0045] It should be noted that, Figure 5 The example described is based solely on the example of the output of the second shift register 221 being electrically connected to a row pixel driving circuit 01, but this is not a limitation. In other embodiments, the output of the second shift register 221 may also be electrically connected to a multi-row pixel driving circuit 01, and those skilled in the art can configure it as needed.

[0046] Optionally, based on the above embodiments, see also... Figure 5 The first output terminal of the second shift register 221 is electrically connected to the control terminal of the data writing module 170 in the row pixel driving circuit 01, and the second output terminal of the second shift register 221 is electrically connected to the control terminals of the second initialization module 180 and the lift module 190 in the row pixel driving circuit 01. The first output terminal of the m-th stage second shift register 221 is electrically connected to the control terminal of the data writing module 170 in the m-th row pixel driving circuit 01 via the second gating unit 222, and the second output terminal of the m-th stage second shift register is electrically connected to the control terminals of the second initialization module 180 and the lift module 190 in the (m-1)-th row pixel driving circuit 01, where m is a positive integer greater than 1.

[0047] Specifically, such as Figure 2 and Figure 5 In the illustrated embodiment, m=2 is used as an example. The third scan signal SN3 controls the data writing module 170 to turn on, thus enabling data writing. The fourth scan signal SN4 controls the second initialization module 180 and the lifting module 190 to turn on, respectively initializing the first electrode of the light-emitting element 140 and maintaining the potential of the second node N2. In the same row of pixel driving circuits 01, the timing of data writing precedes the timing of the initialization of the first electrode of the light-emitting element 140; that is, the effective level of the third scan signal SN3 needs to be earlier than the effective level of the fourth scan signal SN4. Therefore, in this embodiment, the third scan signal SN3 is provided to the current row of pixel driving circuits 01 through the first output of the second shift register 221 of the current stage and the second gating unit 222, and the fourth scan signal SN4 is provided to the current row of pixel driving circuits 01 through the second output of the second shift register 221 of the next stage. In the cascaded multiple second shift registers 221, the first-stage second shift register 221 provides a third scan signal to the pixel driving circuit 01 of the first row through the second gating unit 222. The first output of the second-stage second shift register 221 provides a third scan signal to the pixel driving circuit 01 of the second row through the second gating unit 222, and the second output of the second-stage second shift register 221 provides a fourth scan signal to the pixel driving circuit 01 of the first row. Similarly, the first output of the third-stage second shift register 221 provides a third scan signal to the pixel driving circuit 01 of the third row through the second gating unit 222, and the second output of the third-stage second shift register 221 provides a fourth scan signal to the pixel driving circuit 01 of the second row, and so on. This ensures that the pixel driving circuit 01 can receive both the third scan signal SN3 and the fourth scan signal SN4, thereby ensuring the normal operation of the pixel driving circuit 01 while achieving a narrow bezel on the display panel.

[0048] It should be noted that the second type of shift register group 220 also includes a dummy register 223. The dummy register 223 is cascaded with the second shift register 221 and is the last i-th stage of the cascade (the last stage is used as an example in the figure). The output of the dummy register 223 does not have a second gating unit 222 and is used to provide the fourth scan signal SN4 for the pixel driving circuit 01 of the last row.

[0049] Optionally, based on the above embodiments, Figure 6 This is a timing diagram of another display panel provided in an embodiment of the present invention. See also... Figure 2 , Figure 5 and Figure 6The first output of the second shift register 221 outputs a third scan signal SN3 to the control terminal of the data writing module 170 via the second gating unit 222. The second output of the second shift register 221 outputs a fourth scan signal SN4 to the control terminals of the second initialization module 180 and the lift-up module 190. The operation phases of the display panel include a first refresh frame S1 and a second refresh frame S2. In the first refresh frame S1, both the third scan signal SN3 and the fourth scan signal SN4 have valid levels. In the second refresh frame S2, the fourth scan signal SN4 has a valid level, and the third scan signal SN3 has an invalid level.

[0050] Specifically, the refresh frequency of the first refresh frame S1 is greater than that of the second refresh frame S2; that is, the first refresh frame S1 is a high refresh rate, and the second refresh frame is a low refresh rate. In the first refresh frame S1, a data signal needs to be written to the second node N2 via the sixth transistor M6. Therefore, by setting the third scan signal SN3 to include an active level, the sixth transistor M6 is turned on. At this time, the data signal Vdata can reach the second node N2 through the sixth transistor, thereby realizing data writing. In addition, when the fourth scan signal SN4 includes an active level, the seventh transistor M7 can be turned on to initialize the first electrode of the light-emitting element 140 via the second reference signal Vref2. The eighth transistor M8 can also be turned on to raise the potential of the second node N2 via the first fixed signal DVH. In the second refresh frame S2, the second gating unit 222 is turned off, causing the third scan signal SN3 to include an invalid level. The fourth scan signal SN4 is the scan signal (pulse signal) output from the second output terminal of the second shift register 221, and therefore includes an active level, turning on the sixth transistor M6 and turning off the seventh transistor M and the eighth transistor M8. At this time, even if the first electrode of the light-emitting element 140 is initialized and the potential of the second node N2 is raised, it cannot affect the gate potential of the third transistor M3. Thus, by setting both the third scan signal SN3 and the fourth scan signal SN4 to include active levels in the first refresh frame S1, and in the second refresh frame SN2, the fourth scan signal SN4 includes an active level and the third scan signal SN3 includes an invalid level, thereby ensuring that the display panel can achieve zoned refresh.

[0051] Optionally, in yet another embodiment, Figure 7 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 2 and Figure 7The first gate driving module 20 also includes a third type of shift register group 230. The third type of shift register group 230 includes multiple cascaded third shift registers 231 and fourth shift registers 232, which are arranged alternately. The pixel driving circuit 01 also includes a data writing module 170, a second initialization module 180, and a lift-up module 190. The data writing module 170, driving module 130, and lift-up module 190 are connected to the second node N2. The second initialization module 180 is electrically connected to the first electrode of the light-emitting element 140. The output terminal of the third shift register 231 is electrically connected to the control terminal of the data writing module 170 in at least one row of the pixel driving circuit 01, and the output terminal of the fourth shift register 232 is electrically connected to the control terminals of the second initialization module 180 and the lift-up module 190 in at least one row of the pixel driving circuit 01.

[0052] Specifically, in this embodiment of the invention, the fourth scan signal SN4 is used to control the on and off states of the eighth transistor M8 and the seventh transistor M7. When the eighth transistor M8 is on, it ensures a high potential for the second node N2. When the seventh transistor M7 is on, it initializes the first electrode of the light-emitting element 140. That is, during low refresh rate, even if the eighth transistor M8 and the seventh transistor M7 are on, it will not affect the gate of the third transistor M3. Furthermore, the third scan signal SN3 is used to control the on and off states of the sixth transistor M6. When the sixth transistor is on, it writes a data signal to the second node N2. That is, during low refresh rate, even if the sixth transistor M6 is on, it will not affect the gate of the third transistor M3. Therefore, this embodiment of the invention further includes a third type of shift register group 230 in the first gate driving module 20. The third type of shift register group 230 includes multiple cascaded third shift registers 231 and fourth shift registers 232, which are arranged alternately. The third shift register 231 provides a third scan signal SN3 to the current row pixel driving circuit 01, and the fourth shift register 232 provides a fourth scan signal SN4 to the current row pixel driving circuit 01. The output of the third shift register 231 is electrically connected to the control terminal of the data writing module 170 in at least one row pixel driving circuit 01, and the output of the fourth shift register 232 is electrically connected to the control terminals of the second initialization module 180 and the lifting module 190 in at least one row pixel driving circuit 01. By eliminating the gating units corresponding to the fourth scan signal SN4 and the third scan signal SN3, the number of gating units is further reduced, saving space occupied by the first gate driving module 20. This allows for partitioned refresh while also facilitating the implementation of a narrow bezel on the display panel.

[0053] Optionally, based on the above examples, Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. See also... Figure 8 The display panel also includes a display area AA and a non-display area BB, with the non-display area BB surrounding at least a portion of the display area AA. Both the first type of shift register group 210 and the second type of shift register group 220 are located in the non-display area BB and on the same side of the display area AA. See details... Figure 8 The non-display area BB may include a left border area and a right border area. In one embodiment, the first type of shift register group 210 and the second type of shift register group 220 are both located in the left border area. The first shift register group 210 provides a first scan signal and a second scan signal to each row of pixel driving circuits, and the second shift register group 220 provides a second scan signal to each row of pixel driving circuits. That is, the display panel is driven on one side only.

[0054] In yet another implementation, Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention. See also... Figure 9 The display panel also includes a display area AA and a non-display area BB, with the non-display area BB surrounding at least a portion of the display area AA. The display panel also includes a second gate driving circuit 30. Both the first gate driving circuit 20 and the second gate driving circuit 30 are located in the non-display area BB, and are respectively located on different sides of the display area AA. The first gate driving circuit 20 and the second gate driving circuit 30 are used to provide scan signals to different portions of the pixel driving circuit 01 in the same row. Specifically, as shown in Figure 9, the display panel can be dual-sided driven, that is, the first gate driving circuit 20 is set in the left frame area of ​​the display panel and the second gate driving circuit 30 is set in the right frame area of ​​the display panel. The first gate driving circuit 20 is used to provide scan signals to the pixel driving circuits in the left half of the display area AA, and the second gate driving circuit 30 is used to provide scan signals to the pixel driving circuits in the right half of the display area AA, thereby improving the voltage drop of the scan signal during transmission.

[0055] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 10 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 10 As shown, the display device includes the display panel 100 in the above embodiments. This display device includes the display panel 100 of any embodiment of the present invention; therefore, the display device provided by the embodiments of the present invention possesses the corresponding beneficial effects of the display panel 100 provided by the embodiments of the present invention, which will not be elaborated further here. For example, the display device can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device; the embodiments of the present invention do not limit this.

[0056] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Pixel driving circuit and gate driving circuit; The gate driving circuit includes a first gate driving module, and the first gate driving module includes a first type of shift register group; The first type of shift register group includes multiple cascaded first shift registers and multiple first gating units. The first output terminals of the i-th stage first shift register to the last stage first shift register are all electrically connected to the first gating unit, where i is a positive integer greater than 1. The pixel driving circuit includes a first initialization module, a threshold compensation module, a driving module, and a light-emitting element. The first initialization module, the threshold compensation module, and the driving module are connected to a first node, and the first node is located between the driving module and the light-emitting element. At least a portion of the first output terminal of the first shift register is electrically connected to the control terminal of the threshold compensation module in at least one row of pixel driving circuit through the first gating unit, and at least a portion of the second output terminal of the first shift register is electrically connected to the first initialization module in at least one row of pixel driving circuit.

2. The display panel according to claim 1, characterized in that, The first output terminal of the first shift register is electrically connected to the control terminal of the threshold compensation module in the row pixel driving circuit through the first gating unit, and the second output terminal of the first shift register is electrically connected to the control terminal of the first initialization module in the row pixel driving circuit. The first output terminal of the j-th level first shift register is electrically connected to the control terminal of the threshold compensation module in the (j-i+1)-th row pixel driving circuit through the first gating unit, and the second output terminal of the j-th level first shift register is electrically connected to the control terminal of the first initialization module in the j-th row pixel driving circuit, where j is a positive integer greater than or equal to i.

3. The display panel according to claim 2, characterized in that, The first output terminal of the first shift register of the first stage to the second output terminal of the first shift register of the (i-1)th stage are sequentially electrically connected to the control terminal of the first initialization module in the first row pixel driving circuit and the (i-1)th row pixel driving circuit.

4. The display panel according to claim 1, characterized in that, The first output terminal of the first shift register outputs a first scan signal to the control terminal of the threshold compensation module through the first gating unit; At least a portion of the second output terminal of the first shift register outputs a second scan signal to the control terminal of the first initialization module; The working phases of the display panel include the first refresh frame and the second refresh frame; In the first refresh frame, both the first scan signal and the second scan signal include an active level; In the second refresh frame, the second scan signal includes an active level, and the first scan signal includes an inactive level.

5. The display panel according to claim 4, characterized in that, In the first refresh frame, the end time of the effective level of the first scan signal is located between the start time and the end time of the effective level of the second scan signal.

6. The display panel according to claim 5, characterized in that, The pulse width W of the effective level of the first scan signal satisfies: W>n*(i-1)*H, where n is the number of pixel driving circuit rows connected to the first output terminal of the first shift register, and H is the refresh time of a row of pixel driving circuits.

7. The display panel according to claim 1, characterized in that, The first gate drive module also includes a second type of shift register group; The second type of shift register group includes multiple cascaded second shift registers and multiple second gating units, and the first output terminals of the second shift registers are all electrically connected to the second gating units; The pixel driving circuit further includes a data writing module, a second initialization module, and a lifting module. The data writing module, the driving module, and the lifting module are connected to the second node. The second initialization module is electrically connected to the first electrode of the light-emitting element. At least a portion of the first output terminal of the second shift register is electrically connected to the control terminal of the data writing module in at least one row of pixel driving circuit through the second gating unit, and at least a portion of the second output terminal of the second shift register is electrically connected to the control terminal of the second initialization module and the lifting module in at least one row of pixel driving circuit.

8. The display panel according to claim 7, characterized in that, The first output terminal of the second shift register is electrically connected to the control terminal of the data writing module in the row pixel driving circuit, and the second output terminal of the second shift register is electrically connected to the control terminals of the second initialization module and the lifting module in the row pixel driving circuit. The first output terminal of the m-th level second shift register is electrically connected to the control terminal of the data writing module in the m-th row pixel driving circuit through the second gating unit, and the second output terminal of the m-th level second shift register is electrically connected to the control terminals of the second initialization module and the lifting module in the (m-1)-th row pixel driving circuit, where m is a positive integer greater than 1.

9. The display panel according to claim 7, characterized in that, The first output of the second shift register outputs a third scan signal to the control terminal of the data writing module through the second gating unit; The second output terminal of the second shift register outputs a fourth scan signal to the control terminals of the second initialization module and the lifting module; The working phases of the display panel include the first refresh frame and the second refresh frame; In the first refresh frame, both the third scan signal and the fourth scan signal include an active level; In the second refresh frame, the fourth scan signal includes an active level, and the third scan signal includes an inactive level.

10. The display panel according to claim 1, characterized in that, The first gate drive module also includes a third type of shift register group; The third type of shift register group includes multiple cascaded third shift registers and fourth shift registers, which are arranged alternately at intervals; The pixel driving circuit further includes a data writing module, a second initialization module, and a lifting module. The data writing module, the driving module, and the lifting module are connected to the second node. The second initialization module is electrically connected to the first electrode of the light-emitting element. The output of the third shift register is electrically connected to the control terminal of the data writing module in at least one row of pixel driving circuits, and the output of the fourth shift register is electrically connected to the control terminals of the second initialization module and the lifting module in at least one row of pixel driving circuits.

11. The display panel according to claim 7, characterized in that, The display panel further includes a display area and a non-display area, wherein the non-display area is disposed around at least a portion of the display area; Both the first type of shift register group and the second type of shift register group are located in the non-display area and on the same side of the display area.

12. The display panel according to claim 7, characterized in that, The display panel further includes a display area and a non-display area, wherein the non-display area is disposed around at least a portion of the display area; The display panel further includes a second gate driving circuit. Both the first gate driving circuit and the second gate driving circuit are located in the non-display area, and the first gate driving circuit and the second gate driving circuit are located on different sides of the display area. The first gate driving circuit and the second gate driving circuit are used to provide scanning signals to different parts of the same row of pixel driving circuits respectively.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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