Multi-mode dual-band low noise amplifier, chip and device

Abstract

The application discloses a kind of multi-mode dual-frequency low-noise amplifiers, chip and equipment, wherein amplifier adopts three-stage cascade amplifier topological structure design, including: first common-source common-gate amplifier, input adopts broadband input matching, output end adopts inductive switching module as load;Different inductance values are switched by bias voltage control inductive switching module;Second common-source common-gate amplifier, its load adopts reconfigurable dual-frequency load of inductive coupling;The frequency response of reconfigurable dual-frequency load is switched by bias voltage control;Third common-source common-gate amplifier, switch wave trap module is arranged between common-source common-gate amplifier;The working state of switch wave trap module is controlled by bias voltage.This application realizes multi-mode dual-frequency switching by controlling corresponding bias in variable inductance, reconfigurable dual-frequency load and switch inductive capacitance wave trap module, i.e.it realizes the switching between broadband, parallel and reconfigurable dual-frequency.The application can be widely applied in mobile communication technology field.

Description

Technical Field

[0001] This invention relates to the field of mobile communication technology, and in particular to a multi-mode dual-frequency low-noise amplifier, chip, and device. Background Technology

[0002] To reduce the cost of millimeter-wave RF receiver systems and improve their adaptability to different operating scenarios, the design of multi-mode, dual-band RF front-ends and corresponding circuit modules has become a research hotspot. Millimeter-wave low-noise amplifiers are core modules of the RF front-end in 5G communication systems, and are circuit modules with dual-band or multi-band operating requirements.

[0003] Currently, most millimeter-wave multimode dual-frequency low-noise amplifier designs employ a multi-channel design supporting different frequency bands. This is achieved by controlling a branch of the circuit with a switch or using a switching inductor for tuning, enabling individual or simultaneous operation at different frequency bands. In millimeter-wave low-noise amplifier design, capacitors have very limited matching and tuning capabilities, so reconfigurable designs primarily rely on tuning inductors. Switching inductors offer high switching differentials but reduce the inductor's quality factor. In summary, existing millimeter-wave multimode dual-frequency low-noise amplifiers have the following drawbacks: 1) For branch-controlled designs, interference between branches often results in high noise figures and poor matching performance; 2) For low-noise amplifiers tuned with switching inductors, the noise figure is also affected by the low quality factor, and the tuning capability of switching inductors is limited, making it difficult to meet high-frequency differential requirements. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a multimode dual-frequency low-noise amplifier, chip and device.

[0005] The first technical solution adopted in this invention is:

[0006] A multimode dual-frequency low-noise amplifier, employing a three-stage cascaded amplifier topology, includes:

[0007] The first-stage common-source cascode amplifier uses wideband input matching at its input and an inductor switching module as its output load. Different inductance values ​​are switched by the inductor switching module through bias voltage control.

[0008] The second-stage common-source cascode amplifier uses an inductively coupled reconfigurable dual-frequency load as its load; the frequency response switching of the reconfigurable dual-frequency load is controlled by the bias voltage.

[0009] The third stage is a common-source cascode amplifier, and a switched notch filter module is set between the common-source cascode amplifiers; the operating state of the switched notch filter module is controlled by the bias voltage.

[0010] Furthermore, the inductor switching module includes an inductor L p1 Inductor L s1 Transistor M T1 Transistor M T2 Resistance R B and capacitor C p ;

[0011] The inductor L p1 One end is connected to the output of the common-source cascode amplifier, and the other end is connected to the power supply voltage;

[0012] The inductor L s1 With inductor L p1 Mutual coupling, inductance L s1 One end is connected to transistor M T1 The source of the transistor is connected to transistor M at the other end. T1 The drain electrode;

[0013] The transistor M T2 Source-connected transistor M T1 The source and drain are connected through capacitor C. p Connected to inductor L s1 The center tap; the resistor R B One end is connected to transistor M T1 One end is the source, and the other end is grounded;

[0014] The transistor M T1 Gate connection bias voltage V T1 transistor M T2 Gate connection bias voltage V T Transistor M is controlled by bias voltage. T1 and transistor M T2 The conduction status of the inductor L is then adjusted to switch the inductor L. p1 The value of feeling.

[0015] Furthermore, the inductively coupled reconfigurable dual-frequency load includes inductor L1, inductor L2, capacitor C1, capacitor C2, and transistor M. S1 and negative resistance compensation module;

[0016] One end of inductor L1 is connected to the output of the second-stage common-source cascode amplifier, and the other end is connected to one end of inductor L2; the other end of inductor L2 is connected to the power supply voltage; and inductor L1 and inductor L2 are coupled to each other.

[0017] One end of the capacitor C1 is connected to the output of the second-stage common-source cascode amplifier, and the other end is connected to the power supply voltage;

[0018] One end of capacitor C2 is connected to the other end of inductor L1, and the other end is connected to the negative resistance compensation module.

[0019] The transistor M S1 The drain of the capacitor is connected to the other end of C2, the source is grounded, and the gate is connected to the bias voltage V. C .

[0020] Furthermore, the negative resistance compensation module includes capacitors C3, C4, and C5, and transistor M. S2 Transistor M S3 and resistor R5;

[0021] One end of capacitor C3 is connected to the other end of capacitor C2, and the other end is connected to transistor M. S2 The gate;

[0022] The transistor M S2 The drain is connected to the power supply voltage, and the source is connected to transistor M. S3 The drain electrode;

[0023] The transistor M S3 The source is grounded, and the gate is connected to a bias voltage V. S ;

[0024] One end of capacitor C4 is connected to the other end of capacitor C2, and the other end of capacitor C4 is connected to one end of capacitor C5 and transistor M. S3 The drain of capacitor C5; the other end of capacitor C5 is grounded;

[0025] One end of resistor R5 is connected to the power supply voltage, and the other end is connected to transistor M. S2 The gate.

[0026] Furthermore, the third-stage common-source cascode amplifier includes transistor M5 and transistor M6; the gate of transistor M5 is connected to the output of the second-stage common-source cascode amplifier, and its drain is connected to the source of transistor M6, which is grounded; the drain of transistor M6 outputs the amplified signal.

[0027] The switching notch filter module includes an inductor L3, a capacitor C8, and a transistor M7;

[0028] One end of the capacitor C8 is connected to the drain of the transistor M5, and the other end is connected to one end of the drain inductor L3;

[0029] The other end of the inductor L3 is connected to the drain of the transistor M7;

[0030] The gate connection bias voltage V of transistor M7 LC The source electrode is grounded.

[0031] Furthermore, the first-stage common-source cascode amplifier includes transistor M1 and transistor M2; the drain of transistor M1 is connected to the source of transistor M2, and the drain of transistor M2 serves as the output terminal of the first-stage common-source cascode amplifier.

[0032] The input matching network of the first-stage cascode amplifier includes an inductor L. p Inductor L g Inductance Ls;

[0033] The inductor L g One end is connected to the gate of transistor M1, and the other end is used to input the signal to be amplified;

[0034] The inductor L p One end is connected to the inductor L g The other end is connected to the bias voltage V. bias ;

[0035] One end of the inductor Ls is connected to the source of the transistor M, and the other end is grounded; and the inductor Ls p It is coupled with inductor Ls.

[0036] Furthermore, the first-stage common-source cascode amplifier includes transistors M1 and M2, which are used to match and amplify the input AC signal;

[0037] The second-stage common-source cascode amplifier includes transistors M3 and M4, which are used to amplify AC signals;

[0038] The first-stage common-source cascode amplifier includes transistors M5 and M6, which are used to amplify and output AC signals.

[0039] In this configuration, the drain of transistor M1 is connected to the source of transistor M2, and the drain of transistor M2 is connected to the gate of transistor M3 via a DC blocking capacitor C6; the drain of transistor M3 is connected to the source of transistor M4, and the drain of transistor M4 is connected to the gate of transistor M5 via a DC blocking capacitor C7; the drain of transistor M5 is connected to the source of transistor M6. Further,

[0040] Furthermore, the gate of the transistor M2 is connected to the inductor L g1 The gate of transistor M4 is connected to the power supply voltage; the gate of transistor M6 is connected to the power supply voltage.

[0041] The second technical solution adopted in this invention is:

[0042] A chip comprising the multimode dual-frequency low-noise amplifier described above.

[0043] The third technical solution adopted in this invention is:

[0044] An electronic device includes a housing and a peripheral circuit board, the peripheral circuit board including the chip described above.

[0045] The beneficial effects of this invention are as follows: This invention utilizes a three-stage cascaded multimode dual-frequency low-noise amplifier based on a transformer-based tapped variable inductor, an inductively coupled reconfigurable dual-frequency load, and a switched inductor-capacitor notch filter module. By controlling the bias of the corresponding transistors in the variable inductor, the reconfigurable dual-frequency load, and the switched inductor-capacitor notch filter module, multimode dual-frequency switching is achieved, i.e., switching between broadband, parallel, and reconfigurable dual-frequency modes. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a circuit diagram of the millimeter-wave multimode dual-frequency low-noise amplifier in Embodiment 1 of the present invention;

[0048] Figure 2 This is a schematic diagram of the transformer-based tapped variable inductor structure in Embodiment 1 of the present invention;

[0049] Figure 3 This is a simulation result of the S-parameters of the millimeter-wave multimode dual-frequency low-noise amplifier in parallel mode in Embodiment 1 of the present invention;

[0050] Figure 4 This is a simulation result of the noise figure of the millimeter-wave multimode dual-frequency low-noise amplifier in parallel mode in Embodiment 1 of the present invention;

[0051] Figure 5 This is a simulation result of the S-parameters of the broadband mode of the millimeter-wave multimode dual-frequency low-noise amplifier in Embodiment 1 of the present invention;

[0052] Figure 6 This is a simulation result of the noise figure of the broadband mode of the millimeter-wave multimode dual-frequency low-noise amplifier in Embodiment 1 of the present invention;

[0053] Figure 7 This is a simulation result diagram of the S-parameters of the reconfigurable mode low-frequency band and high-frequency band of the millimeter-wave multimode dual-frequency low-noise amplifier in Embodiment 1 of the present invention;

[0054] Figure 8This is a simulation result of the noise figure of the reconfigurable mode low-frequency band and high-frequency band of the millimeter-wave multimode dual-frequency low-noise amplifier in Embodiment 1 of the present invention.

[0055] Figure 9 This is a circuit diagram of the inductor switching module in Embodiment 2 of the present invention;

[0056] Figure 10 This is a circuit diagram of the multimode dual-frequency low-noise amplifier in Embodiment 3 of the present invention;

[0057] Figure 11 This is a circuit diagram of the multimode dual-frequency low-noise amplifier in Embodiment 4 of the present invention;

[0058] Figure 12 This is a circuit diagram of the dual-frequency low-noise amplifier in Embodiment 5 of the present invention. Detailed Implementation

[0059] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0060] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the embodiments of this application. The singular forms "a," "described," and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise expressly limited, terms such as "set," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0061] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0062] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0063] In the description of this application, "and / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship.

[0064] To address the aforementioned technical problems, the present invention employs a three-stage cascaded amplifier topology. The first and second stage loads each include a multi-tap magnetically coupled switchable inductor and a dual-frequency network based on a reconfigurable transformer. The primary coil inductance of the switchable inductor can be tuned by controlling the voltage of the secondary coil switch, while the inductively coupled reconfigurable dual-frequency load, including a high-order LC network based on the transformer, provides different frequency responses for concurrent, reconfigurable, and broadband modes. To reduce losses introduced by the transformer and switch, a negative resistance compensation module is employed.

[0065] Example 1

[0066] See Figure 1 This embodiment provides a millimeter-wave multimode dual-frequency low-noise amplifier, including:

[0067] The first-stage common-source cascode amplifier uses wideband input matching at its input and an inductor switching module as its output load. Different inductance values ​​are switched by the inductor switching module through bias voltage control.

[0068] The second-stage common-source cascode amplifier uses an inductively coupled reconfigurable dual-frequency load as its load; the frequency response switching of the reconfigurable dual-frequency load is controlled by the bias voltage.

[0069] The third stage is a common-source cascode amplifier, and a switched notch filter module is set between the common-source cascode amplifiers; the operating state of the switched notch filter module is controlled by the bias voltage.

[0070] All three stages of the amplifier employ a common-source common-gate (CSG) structure. Specifically, the first-stage CSG amplifier includes transistors M1 and M2, which are used to match and amplify the input AC signal; the second-stage CSG amplifier includes transistors M3 and M4, which are used to amplify the AC signal; and the third-stage CSG amplifier includes transistors M5 and M6, which are used to amplify and output the AC signal.

[0071] In some embodiments, the drain of transistor M1 is connected to the source of transistor M2, and the drain of transistor M2 is connected to the gate of transistor M3 through a DC blocking capacitor C6; the drain of transistor M3 is connected to the source of transistor M4, and the drain of transistor M4 is connected to the gate of transistor M5 through a DC blocking capacitor C7; the drain of transistor M5 is connected to the source of transistor M6.

[0072] As an optional implementation, the gate of the transistor M2 is connected to an inductor L. g1 The gates of transistors M4 and M6 are connected to the power supply voltage. It should be noted that, besides this method, other methods can also be used to DC bias these transistors.

[0073] See Figure 2 In one implementation, the inductor switching module includes an inductor L. p1 Inductor L s1 Transistor M T1 Transistor M T2 Resistance R B and capacitor C p ;

[0074] The inductor L p1 One end is connected to the output of the common-source cascode amplifier, and the other end is connected to the power supply voltage;

[0075] The inductor L s1 With inductor L p1 Mutual coupling, inductance L s1 One end is connected to transistor M T1 The source of the transistor is connected to transistor M at the other end. T1 The drain electrode;

[0076] The transistor M T2 Source-connected transistor M T1 The source and drain are connected through capacitor C. p Connected to inductor L s1 The center tap; the resistor R B One end is connected to transistor M T1 One end is the source, and the other end is grounded;

[0077] The transistor M T1 Gate connection bias voltage V T1 transistor M T2 Gate connection bias voltage V T Transistor M is controlled by bias voltage. T1 and transistor M T2 The conduction status of the inductor L is then adjusted to switch the inductor L. p1The value of feeling.

[0078] By controlling the connection status of the transistor, the conduction state of the second inductor is controlled, thereby switching the inductance value of the first inductor.

[0079] See Figure 1 In one implementation, the inductively coupled reconfigurable dual-frequency load includes inductor L1, inductor L2, capacitor C1, capacitor C2, and transistor M. S1 and negative resistance compensation module;

[0080] One end of inductor L1 is connected to the output of the second-stage common-source cascode amplifier, and the other end is connected to one end of inductor L2; the other end of inductor L2 is connected to the power supply voltage; and inductor L1 and inductor L2 are coupled to each other.

[0081] One end of the capacitor C1 is connected to the output of the second-stage common-source cascode amplifier, and the other end is connected to the power supply voltage;

[0082] One end of capacitor C2 is connected to the other end of inductor L1, and the other end is connected to the negative resistance compensation module.

[0083] The transistor M S1 The drain of the capacitor is connected to the other end of C2, the source is grounded, and the gate is connected to the bias voltage V. C .

[0084] The negative resistance compensation module is used to reduce losses introduced by the transformer and switch. As an optional implementation, the negative resistance compensation module includes capacitors C3, C4, and C5, and transistor M. S2 Transistor M S3 and resistor R5;

[0085] One end of capacitor C3 is connected to the other end of capacitor C2, and the other end is connected to transistor M. S2 The gate;

[0086] The transistor M S2 The drain is connected to the power supply voltage, and the source is connected to transistor M. S3 The drain electrode;

[0087] The transistor M S3 The source is grounded, and the gate is connected to a bias voltage V. S ;

[0088] One end of capacitor C4 is connected to the other end of capacitor C2, and the other end of capacitor C4 is connected to one end of capacitor C5 and transistor M. S3 The drain of capacitor C5; the other end of capacitor C5 is grounded;

[0089] One end of resistor R5 is connected to the power supply voltage, and the other end is connected to transistor M.S2 The gate.

[0090] In this embodiment, inductors L1 and L2 are connected in series and coupled to each other, and are connected in parallel with capacitor C1. Capacitor C2 is connected in parallel to the connection point of inductors L1 and L2 in series, which enables the function of parallel dual-frequency response. Furthermore, compared to traditional dual-frequency systems that require two or even three inductors to achieve parallel dual-frequency response, the structure in this embodiment only requires the area of ​​one inductor on the layout, and can achieve a similar or even better parallel dual-frequency response effect.

[0091] See Figure 1 In one embodiment, the switching notch filter module includes an inductor L3, a capacitor C8, and a transistor M7; the switching notch filter module is connected to the cascade point of the eleventh transistor M5 and the twelfth transistor M6.

[0092] Specifically, one end of capacitor C8 is connected to the drain of transistor M5, and the other end is connected to one end of drain inductor L3; the other end of inductor L3 is connected to the drain of transistor M7; the gate of transistor M7 is connected to bias voltage V. LC The source electrode is grounded.

[0093] See Figure 1 As one implementation method, transistor M T1 Transistor M T2 Transistor M S1 Transistor M S3 Both transistor M7 and transistor M8 have their gates connected to the bias voltage via resistors.

[0094] The circuit structure and working principle of the amplifier described above will be explained in detail below with reference to the accompanying drawings.

[0095] (1) Circuit structure description

[0096] like Figure 1 As shown, in one embodiment, the amplifier's circuit connection structure is as follows:

[0097] In the first stage of the circuit, the common-source cascode stage, the radio frequency signal originates from RF... in The input terminal receives the signal, which then passes through the DC blocking capacitor C. in Then with inductor L p and the inductor L connected in series with the gate of the common-source transistor M1 g Connected, inductor L p The other end provides the gate voltage bias V for transistor M1. bias The source of transistor M1 and inductor L s After connecting, ground the inductor L p With inductor L sThe coupling is k1. The drain of transistor M1 is connected to the source of transistor M2, and the gate of transistor M2 is connected to inductor L. g1 After connection with V dd The power supply is connected. The drain of transistor M2 is connected to the variable inductor L. R One end of the (i.e., inductor switching module) is connected to the variable inductor L. R The other end and V dd Power supply connection. See details. Figure 2 Variable inductor L R The specific structure is: Inductor L p1 and inductor L s1 Coupling, Inductance L s1 Both ends and transistor M T1 Connect, and in transistor M T1 The source of L is grounded through a resistor; s1 Taps and transistor M T2 Drain, capacitor C p Connection, transistor M T2 Source and transistor M T1 Source connection; by controlling the transistor connection, the L s1 The conduction state of the L is then switched. p1 The value of feeling.

[0098] In the second stage of the circuit, the common-source common-gate stage is connected to the first stage through capacitor C6, and transistor M3 is biased by V through gate resistor R1. bias The source of transistor M3 is grounded. The drain of transistor M3 is connected to the source of transistor M4, and the gate of transistor M4 is directly connected to V. dd The power supply is connected. The drain of transistor M4 is connected to the reconfigurable dual-frequency load network. Specifically, the circuit structure of the reconfigurable dual-frequency load network is as follows: inductors L1 and L2 are connected in series, and L1 and L2 are coupled with a coupling coefficient of k2; capacitor C1 is connected in parallel with the series-connected inductors L1 and L2; one end of capacitor C2 is connected to the series connection point of inductors L1 and L2; transistor M4 is connected to the power supply. S1 The drain is connected to the other end of C2, transistor M S1 The source is grounded, and the gate is biased by resistor R4. C Capacitor C4 and capacitor C5 are connected in series at their first terminals, and capacitor C5 is grounded at its second terminal. Capacitor C3's first terminal is connected to capacitor C4, and its second terminal is connected to transistor M. S2 Gate connection; the connection point between capacitor C2 and capacitor C4 and transistor M S The drain connection. Transistor M S2 The gate is connected to resistor R5, and resistor R5 is connected to transistor M. S2 Drain connection and then V dd Power supply connection, transistor M S2The source and transistor M S3 Drain connection; transistor M S3 The source is grounded, and the gate is biased by resistor R5. S transistor M S3 With transistor M S2 Connect the joint to the joint between C2 and C4.

[0099] In the third stage of the circuit, the common-source and common-gate stage is connected to the second stage through capacitor C7, and transistor M5 is biased by V through gate resistor R2. bias The source of transistor M5 is grounded. The drain of transistor M5 is connected to the source of transistor M6 and the first terminal of capacitor C8. The second terminal of capacitor C8 is connected to the first terminal of inductor L3. The second terminal of inductor L3 is connected to the drain of transistor M7, and the source of transistor M7 is grounded. The gate of transistor M6 is connected to V... dd The power supply is connected, and the drain is connected to inductor L4, while a DC blocking capacitor C is connected. out RF output terminal out Connected, the other end of L4 is connected to V dd Power supply connection.

[0100] (2) Explanation of circuit working principle

[0101] The amplifier in this embodiment is a millimeter-wave multimode dual-frequency low-noise amplifier with a focused transformer-coupled tapped variable inductor and inductively coupled reconfigurable dual-frequency load. This low-noise amplifier uses a common-source, common-gate, three-stage cascaded architecture. The first stage employs wideband input matching to achieve good matching across multiple modes. The load uses a variable inductor L... R Tuning is achieved; the second-stage load uses an inductively coupled reconfigurable dual-frequency load, and the third stage serves as a buffer stage, with a switching LC notch filter branch between the stages.

[0102] The switching of this multimode dual-frequency amplifier is controlled by voltage V. T V T1 V C V S and V LC accomplish.

[0103] V T and V T1 Controlling the variable inductor L R The inductance value, V C and V S Controlling the frequency response switching of reconfigurable dual-frequency loads, V LC Controls whether the switch-type LC notch filter branch is working.

[0104] The control voltage settings for the three modes are shown in Table 1:

[0105] Table 1

[0106]

[0107] In parallel dual-frequency mode, V can be adjusted S The size can be adjusted to achieve different stopband rejection ratios.

[0108] (3) Experimental Results

[0109] The amplifier in this embodiment can be used for communication in different scenarios of 5G millimeter-wave 28GHz and 39GHz frequency band wireless devices. The S-parameter simulation results in parallel dual-band mode are as follows: Figure 3 As shown, the 3dB bandwidths in the 28GHz and 39GHz frequency bands are 25-31GHz and 37.5-41.6GHz, respectively; the noise figure simulation results are as follows. Figure 4 As shown, the noise figures within a 3dB bandwidth in the 28GHz and 39GHz frequency bands are 3.1-3.3dB and 3.5-3.9dB, respectively.

[0110] In broadband mode, the S-parameter simulation results are as follows: Figure 5 As shown, the 3dB bandwidth is 24.5-42.9GHz; the noise figure simulation results are as follows. Figure 6 As shown, the noise figures within the 3dB bandwidth are 3.3-4dB.

[0111] The S-parameter simulation results in reconfigurable dual-frequency mode are as follows: Figure 7 As shown, the 3dB bandwidths in the 28GHz and 39GHz frequency bands are 25.6-33.8GHz and 35.3-43.5GHz, respectively; the noise figure simulation results are as follows. Figure 8 As shown, the noise figures within a 3dB bandwidth in the 28GHz and 39GHz frequency bands are 3-3.1dB and 3.5-4dB, respectively. Figure 7 (a) shows the S-parameter simulation results of the reconfigurable mode low-frequency band of the millimeter-wave multimode dual-frequency low-noise amplifier. Figure 7 (b) shows the simulation results of S-parameters for the high-frequency band of the reconfigurable mode; Figure 8 Figure (a) shows the simulation results of the noise figure in the low-frequency band of the reconfigurable mode of the millimeter-wave multimode dual-frequency low-noise amplifier. Figure 8 Figure (b) shows the simulation results of the noise figure in the high-frequency band of the reconfigurable mode.

[0112] In summary, this embodiment proposes an inductively coupled reconfigurable dual-frequency load design technology. Combined with an inductor switching module and a switching LC notch filter, it can achieve switching between three modes: parallel dual-frequency, broadband, and reconfigurable dual-frequency in the millimeter-wave band.

[0113] Example 2

[0114] The amplifier circuit structure in this embodiment is largely the same as that in Embodiment 1 above, with the main difference being the inductor switching module: see [link to embodiment]. Figure 9 In this embodiment, the inductor switching module includes a primary coil Lpri1, a secondary coil Lsec1, a capacitor Cp, and a transistor switch M. T1 Transistor switch M T2 and transistor switch M T3 By adding transistor switch M T3 This allows for a wider range of inductance values ​​to be selected. Therefore, the specific circuit structure can be chosen based on the actual circuit requirements.

[0115] Specifically, transistor switch M T3 The drain is connected to the center tap of the secondary coil Lsec1, and the source is connected to the transistor switch M. T2 The drain and gate are connected to a bias voltage V. T2 .

[0116] Example 3

[0117] The amplifier circuit structure in this embodiment is largely the same as that in Embodiment 1 above, with the main difference being the reconfigurable dual-frequency load: see [link to previous embodiment]. Figure 10 In this embodiment, capacitors C4 and C5 are variable capacitors, and transistor M... s1 It is used only for switching parallel dual-frequency responses with other frequency responses, and does not participate in regulating other frequency responses of reconfigurable loads. Capacitors C4 and C5 are used for regulation. Therefore, the specific circuit structure can be selected based on actual circuit requirements.

[0118] Example 4

[0119] The amplifier circuit structure in this embodiment is largely the same as that in Embodiment 1 above, with the main difference being the reconfigurable module: see [link to embodiment]. Figure 11 In this embodiment, instead of using a negative resistance compensation circuit, a variable capacitor is used for capacitor C2, achieving the same function as in Embodiment 1. Therefore, the specific circuit structure can be chosen based on actual circuit requirements.

[0120] Specifically, one end of capacitor C2 is connected to the connection point of inductors L1 and L2, and the other end is connected to transistor M. s1 The drain of transistor M s1 The source electrode is grounded.

[0121] Example 5

[0122] The amplifier circuit structure in this embodiment is largely the same as that in Embodiment 1 above, with the main difference being in the load sections of the first-stage amplifier and the second-stage amplifier: See [link to embodiment]. Figure 12In this embodiment, both the first-stage amplifier and the second-stage amplifier use transformer-based dual-frequency loads, enabling parallel dual-frequency mode. Therefore, the specific circuit structure can be chosen based on actual circuit requirements.

[0123] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0124] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A multimode dual-frequency low-noise amplifier, characterized in that, The design employs a three-stage cascaded amplifier topology, including: The first-stage common-source cascode amplifier uses wideband input matching at its input and an inductor switching module as its output load. The inductor switching module switches between different inductance values ​​by controlling the bias voltage. The second-stage common-source cascode amplifier uses an inductively coupled reconfigurable dual-frequency load as its load. The third-stage common-source cascode amplifier is equipped with a switched notch filter module between the common-source cascode amplifiers; The inductor switching module includes an inductor L p1 Inductor L s1 Transistor M T1 Transistor M T2 Resistance R B and capacitor C p ; The inductor L p1 One end is connected to the output of the common-source cascode amplifier, and the other end is connected to the power supply voltage; The inductor L s1 With inductor L p1 Mutual coupling, inductance L s1 One end is connected to transistor M T1 The source of the transistor is connected to transistor M at the other end. T1 The drain electrode; The transistor M T2 Source-connected transistor M T1 The source and drain are connected through capacitor C. p Connected to inductor L s1 The center tap; the resistor R B One end is connected to transistor M T1 One end is the source, and the other end is grounded; The transistor M T1 Gate connection bias voltage V T1 transistor M T2 Gate connection bias voltage V T Transistor M is controlled by bias voltage. T1 and transistor M T2 The conduction status of the inductor L is then adjusted to switch the inductor L. p1 The value of feeling.

2. The multimode dual-frequency low-noise amplifier according to claim 1, characterized in that, The inductively coupled reconfigurable dual-frequency load includes inductor L1, inductor L2, capacitor C1, capacitor C2, and transistor M. S1 and negative resistance compensation module; One end of inductor L1 is connected to the output of the second-stage common-source common-gate amplifier, and the other end is connected to one end of inductor L2; the other end of inductor L2 is connected to the power supply voltage; and inductor L1 and inductor L2 are coupled to each other. One end of the capacitor C1 is connected to the output of the second-stage common-source cascode amplifier, and the other end is connected to the power supply voltage; One end of capacitor C2 is connected to the other end of inductor L1, and the other end is connected to the negative resistance compensation module. The transistor M S1 The drain of the capacitor is connected to the other end of C2, the source is grounded, and the gate is connected to the bias voltage V. C .

3. The multimode dual-frequency low-noise amplifier according to claim 2, characterized in that, The negative resistance compensation module includes capacitor C3, capacitor C4, capacitor C5, and transistor M. S2 Transistor M S3 and resistor R5; One end of capacitor C3 is connected to the other end of capacitor C2, and the other end is connected to transistor M. S2 The gate; The transistor M S2 The drain is connected to the power supply voltage, and the source is connected to transistor M. S3 The drain electrode; The transistor M S3 The source is grounded, and the gate is connected to a bias voltage V. S ; One end of capacitor C4 is connected to the other end of capacitor C2, and the other end of capacitor C4 is connected to one end of capacitor C5 and transistor M. S3 The drain of capacitor C5; the other end of capacitor C5 is grounded; One end of resistor R5 is connected to the power supply voltage, and the other end is connected to transistor M. S2 The gate.

4. The multimode dual-frequency low-noise amplifier according to claim 1, characterized in that, The third-stage common-source cascode amplifier includes transistor M5 and transistor M6; the gate of transistor M5 is connected to the output of the second-stage common-source cascode amplifier, and its drain is connected to the source of transistor M6, which is grounded; the drain of transistor M6 outputs the amplified signal. The switching notch filter module includes an inductor L3, a capacitor C8, and a transistor M7; One end of the capacitor C8 is connected to the drain of the transistor M5, and the other end is connected to one end of the drain inductor L3; The other end of the inductor L3 is connected to the drain of the transistor M7; The gate connection bias voltage V of transistor M7 LC The source electrode is grounded.

5. A multimode dual-frequency low-noise amplifier according to claim 1, characterized in that, The first-stage common-source cascode amplifier includes transistor M1 and transistor M2; the drain of transistor M1 is connected to the source of transistor M2, and the drain of transistor M2 serves as the output terminal of the first-stage common-source cascode amplifier. The input matching network of the first-stage cascode amplifier includes an inductor L. p Inductor L g Inductance Ls; The inductor L g One end is connected to the gate of transistor M1, and the other end is used to input the signal to be amplified; The inductor L p One end is connected to the inductor L g The other end is connected to the bias voltage V. bias ; One end of the inductor Ls is connected to the source of the transistor M, and the other end is grounded; and the inductor Ls p It is coupled with inductor Ls.

6. A multimode dual-frequency low-noise amplifier according to claim 1, characterized in that, The first-stage common-source common-gate amplifier includes transistors M1 and M2, which are used to match and amplify the input AC signal; The second-stage common-source cascode amplifier includes transistors M3 and M4, which are used to amplify AC signals; The third-stage common-source common-gate amplifier includes transistors M5 and M6, which are used to amplify and output AC signals. In this configuration, the drain of transistor M1 is connected to the source of transistor M2, and the drain of transistor M2 is connected to the gate of transistor M3 through a DC blocking capacitor C6; the drain of transistor M3 is connected to the source of transistor M4, and the drain of transistor M4 is connected to the gate of transistor M5 through a DC blocking capacitor C7; the drain of transistor M5 is connected to the source of transistor M6.

7. A multimode dual-frequency low-noise amplifier according to claim 6, characterized in that, The gate of transistor M2 is connected to inductor L g1 The gate of transistor M4 is connected to the power supply voltage; the gate of transistor M6 is connected to the power supply voltage.

8. A chip, characterized in that, Includes a multimode dual-frequency low-noise amplifier as described in any one of claims 1-7.

9. An electronic device, characterized in that, It includes a housing and a peripheral circuit board, the peripheral circuit board including the chip as described in claim 8.

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