Buffer and integrated circuit

Abstract

The invention relates to a buffer and an integrated circuit. The buffer includes: an operational amplifier; the first end of the voltage-voltage feedback network is coupled to the positive phase / negative phase input end of the operational amplifier; the first end of the isolation resistor is coupled to the output end of the buffer; the first group of switches and the second group of switches are controlled to be closed when the first capacitive load is driven, the second group of switches are disconnected when the second capacitive load is driven, and the first group of switches are disconnected and the second group of switches are closed when the second capacitive load is driven; in the first load, the output end of the operational amplifier is coupled to the output end of the buffer through at least one switch in the first group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the buffer through at least one switch in the first group of switches. In the second load, the output end of the operational amplifier is coupled to the second end of the isolation resistor through at least one switch in the second group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the operational amplifier through at least one switch in the second group of switches.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and in particular to a buffer and an integrated circuit. Background Technology

[0002] Currently, voltage-voltage feedback operational amplifiers (hereinafter referred to as "op-amps") can be used as buffers to improve the driving capability of circuits. These buffers feature high input impedance and low output impedance, but may introduce stability issues when driving capacitive loads.

[0003] Therefore, a buffer that can stably drive capacitive loads is needed. Summary of the Invention

[0004] One technical problem this disclosure aims to solve is to provide a buffer and integrated circuit that can stably drive capacitive loads.

[0005] According to a first aspect of this disclosure, a buffer is provided, comprising: an operational amplifier having a non-inverting or negative-inverting input terminal receiving an output from a preceding circuit; a voltage-voltage feedback network for the operational amplifier, a first terminal of which is coupled to the non-inverting or negative-inverting input terminal of the operational amplifier; an isolation resistor having a first terminal coupled to the output terminal of the buffer; and a first set of switches and a second set of switches, controlled such that when the buffer drives a first capacitive load, the first set of switches closes and the second set of switches opens, and when the buffer drives a second capacitive load, the first set of switches opens and the second set of switches closes, such that when the buffer drives the first capacitive load, the operational amplifier... The output terminal of the device is coupled to the output terminal of the buffer via at least one switch in the first group of switches. The second terminal of the voltage-voltage feedback network is coupled to the output terminal of the buffer via at least one switch in the first group of switches, or the second terminal of the voltage-voltage feedback network is directly coupled to the second terminal of the isolation resistor so that the isolation resistor is used as the feedback resistor of the operational amplifier. When the buffer drives the second capacitive load, the output terminal of the operational amplifier is coupled to the second terminal of the isolation resistor via at least one switch in the second group of switches, and the second terminal of the voltage-voltage feedback network is coupled to the output terminal of the operational amplifier via at least one switch in the second group of switches.

[0006] Optionally, the first set of switches includes a first switch and a second switch, and the second set of switches includes a third switch and a fourth switch, wherein the first switch is coupled between the output terminal of the operational amplifier and the output terminal of the buffer, the second switch is coupled between the second terminal of the voltage-voltage feedback network and the output terminal of the buffer, the third switch is coupled between the output terminal of the operational amplifier and the second terminal of the isolation resistor, and the fourth switch is coupled between the second terminal of the voltage-voltage feedback network and the output terminal of the operational amplifier.

[0007] Optionally, the output stage of the operational amplifier includes a first PMOS transistor and a first NMOS transistor, wherein the drains of the first PMOS transistor and the first NMOS transistor are used as the output terminals of the operational amplifier; the first set of switches includes a fifth switch, a sixth switch, and a seventh switch, and the second set of switches includes an eighth switch, a ninth switch, and a tenth switch, wherein the fifth switch is coupled between the drain of the first PMOS transistor and the output terminal of the buffer, the sixth switch is coupled between the drain of the first NMOS transistor and the output terminal of the buffer, the seventh switch is coupled between the second terminal of the voltage-voltage feedback network and the output terminal of the buffer, the eighth switch is coupled between the drain of the first PMOS transistor and the second terminal of the voltage-voltage feedback network, the ninth switch is coupled between the drain of the first NMOS transistor and the second terminal of the voltage-voltage feedback network, and the tenth switch is coupled between the second terminal of the voltage-voltage feedback network and the second terminal of the isolation resistor.

[0008] Optionally, the buffer further includes a first Miller compensation capacitor, a second Miller compensation capacitor, a third Miller compensation capacitor, and a fourth Miller compensation capacitor; the first group of switches further includes an eleventh switch and a twelfth switch; the second group of switches further includes a thirteenth switch and a fourteenth switch; wherein the eleventh switch and the first Miller compensation capacitor are connected in series between the gate of the first PMOS transistor and the output terminal of the buffer, the twelfth switch and the second Miller compensation capacitor are connected in series between the gate of the first NMOS transistor and the output terminal of the buffer, the thirteenth switch and the third Miller compensation capacitor are connected in series between the gate of the first PMOS transistor and the second terminal of the voltage-voltage feedback network, and the fourteenth switch and the fourth Miller compensation capacitor are connected in series between the gate of the first NMOS transistor and the second terminal of the voltage-voltage feedback network.

[0009] Optionally, the non-inverting input of the operational amplifier receives a fixed voltage; the inverting input of the operational amplifier receives the output of the preamplifier circuit and is coupled to a first terminal of the voltage-voltage feedback network; the voltage-voltage feedback network includes a first feedback resistor coupled between its first and second terminals.

[0010] Optionally, the resistance value of the first feedback resistor is equal to the resistance value of the output resistor of the preceding circuit.

[0011] Optionally, the non-inverting input of the operational amplifier receives the output of the preamplifier circuit; the inverting input of the operational amplifier is coupled to the first terminal of the voltage-voltage feedback network; the voltage-voltage feedback network includes a wire or a second feedback resistor coupled between its first and second terminals.

[0012] Optionally, if the voltage-voltage feedback network includes the second feedback resistor, the voltage-voltage feedback network further includes a third feedback resistor coupled between its first terminal and ground.

[0013] Optionally, the output stage of the operational amplifier includes a first PMOS transistor and a first NMOS transistor, wherein the drains of the first PMOS transistor and the first NMOS transistor are used as the output terminals of the operational amplifier; the first set of switches includes a fifteenth switch and a sixteenth switch, and the second set of switches includes a seventeenth switch and an eighteenth switch, wherein the second terminal of the voltage-voltage feedback network is directly coupled to the second terminal of the isolation resistor, the fifteenth switch is coupled between the drain of the first PMOS transistor and the output terminal of the buffer, the sixteenth switch is coupled between the drain of the first NMOS transistor and the output terminal of the buffer, the seventeenth switch is coupled between the drain of the first PMOS transistor and the second terminal of the voltage-voltage feedback network, and the eighteenth switch is coupled between the drain of the first NMOS transistor and the second terminal of the voltage-voltage feedback network.

[0014] Optionally, the pre-amplifier circuit is a resistive DAC; the resistance value of the first feedback resistor is equal to the resistance value of the output resistor of the resistive DAC; the value of the fixed voltage is equal to half the value of the maximum output voltage of the resistive DAC; and the output voltage of the resistive DAC is an analog voltage obtained by inverting and quantizing the input digital code value.

[0015] Optionally, the first switch, the second switch, the third switch, and the fourth switch are all CMOS transmission gates.

[0016] Optionally, the fifth and eighth switches are both PMOS switches; the sixth and ninth switches are both NMOS switches; and the seventh and tenth switches are both CMOS transmission gates.

[0017] Optionally, the eleventh and thirteenth switches are both PMOS switches; the twelfth and fourteenth switches are both NMOS switches.

[0018] Optionally, the fifteenth and seventeenth switches are both PMOS switches; the sixteenth and eighteenth switches are both NMOS switches.

[0019] Optionally, the capacitance value of the second capacitive load is greater than the capacitance value of the first capacitive load.

[0020] Therefore, this disclosure can selectively configure different negative feedback loops by controlling the on / off state of two sets of switches when the buffer drives different capacitive loads, and reduce the influence of the introduced switches on the negative feedback loop by optimizing the arrangement of these two sets of switches, thereby ensuring that the buffer can stably drive various capacitive loads.

[0021] Another aspect of the present invention provides an integrated circuit that includes a buffer according to any of the solutions in the first aspect of the present invention. That is, all components included in the buffers of the aforementioned solutions are integrated into the same IC chip.

[0022] Optionally, the integrated circuit further includes a preamplifier circuit whose output is coupled to the buffer, wherein the preamplifier circuit is a circuit module that can be equivalent to a voltage source with an output resistor.

[0023] Optionally, the first set of switches and the second set of switches are controlled by signals from outside the integrated circuit.

[0024] Optionally, the first set of switches and the second set of switches are controlled by configuring register bits inside the integrated circuit.

[0025] Therefore, this disclosure can conveniently control the switching of the internal buffer of the integrated circuit according to the size of the capacitive load driven by the application, through external signals or register configuration, and select the negative feedback loop with / without isolation resistor, thereby obtaining a stable negative feedback loop. Moreover, it has a wide range of applications, is easy to use, and has low cost. Attached Figure Description

[0026] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0027] Figure 1A and Figure 1B Schematic diagrams of buffers according to some embodiments of the present disclosure are shown.

[0028] Figures 2A to 2C Schematic block diagrams of buffers according to some embodiments of the present disclosure are shown respectively. Figure 2D A schematic diagram illustrating the implementation principle of a portion of a buffer according to some embodiments of the present disclosure is shown, and Figures 2E to 2G Schematic block diagrams of buffers according to some embodiments of the present disclosure are shown.

[0029] Figures 3A to 3C Schematic diagrams of the composition of buffers including specific switch arrangements according to some embodiments of the present disclosure are shown.

[0030] Figures 4 to 10 Schematic diagrams of specific circuit constructions of buffers according to some embodiments of the present disclosure are shown. Detailed Implementation

[0031] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0032] Figure 1A and Figure 1B Schematic diagrams of buffers according to some embodiments of this disclosure are shown, with one specific implementation of a non-inverting input buffer employing a voltage-voltage feedback mechanism as an example to illustrate the driving of different capacitive loads CLP and CLN. It should be understood that... Figure 1A and Figure 1B The types of buffers and their connection methods described herein are merely exemplary and not limiting; this disclosure can employ any suitable buffer structure implemented using an operational amplifier with voltage-voltage feedback.

[0033] like Figure 1A and Figure 1BAs shown, the buffer includes an operational amplifier (op-amp) and its feedback resistor R1. The input voltage Vi of the op-amp is coupled to the non-inverting input terminal of the op-amp via resistor R2, and the feedback resistor R1 is coupled between the inverting input terminal and the output terminal of the op-amp. Thus, the op-amp constitutes a unity-gain buffer with a follower structure, and its stability is affected by the capacitance value of the driven capacitive load.

[0034] like Figure 1A As shown, the output Vo of the buffer can directly drive a small load capacitor CLP, such as a small capacitive load with a capacitance value in the pF range (e.g., tens of pF, below 100 pF, or below hundreds of pF). When driving a small capacitive load, Miller compensation within the op-amp, such as the Miller compensation capacitor inside the op-amp (not shown in the figure), can typically push the output pole outside the unity-gain bandwidth of the loop, stabilizing the negative feedback loop and providing ample gain and phase margins. In other words, when driving a small capacitive load, the output of the op-amp can be used as the output of the buffer, directly coupled to the load, thus ensuring the stability of the buffer's operation.

[0035] However, when the capacitance of the driven capacitive load increases to the nF or uF level, the zero-pole distribution in the negative feedback loop changes, causing the output poles to fall near or within the loop's unity-gain bandwidth, making the negative feedback loop unstable. Therefore, as... Figure 1B As shown, when the buffer drives a large load capacitor CLN (a large capacitive load, such as a load with a capacitance value in the nF or uF range), a large isolation resistor RN can be used to ensure that the zero-pole distribution in the negative feedback loop is not changed, and the loop remains stable. However, when driving a small capacitive load, it is desirable for the output impedance of the buffer to approach 0, so it is undesirable for the isolation resistor RN to appear between the output of the op-amp and the load capacitor.

[0036] Therefore, in order to ensure that the buffer can stably drive various capacitive loads, different negative feedback loops need to be configured according to the capacitance value of the capacitive load.

[0037] Therefore, this disclosure proposes a novel buffer structure that can selectively configure different negative feedback loops by controlling the on / off states of two sets of switches, and reduces the impact of the introduced switches on the negative feedback loops by optimizing the arrangement of these two sets of switches, thereby ensuring that the buffer can stably drive various capacitive loads. Furthermore, in some embodiments, all components of the buffer (including operational amplifiers, feedback networks, isolation resistors, and switches, etc.) can be integrated into a single integrated circuit. Depending on the size of the capacitive load being driven, the on / off states of the switches within the buffer can be conveniently controlled via external signal control or register configuration of the integrated circuit, selecting the negative feedback loop with / without the isolation resistor, thus obtaining a stable negative feedback loop. This design is widely applicable, easy to use, and low in cost.

[0038] In some embodiments, this disclosure provides a buffer comprising:

[0039] An operational amplifier whose positive or negative input terminal receives the output of the preceding circuit.

[0040] The voltage-voltage feedback network for the operational amplifier has its first terminal coupled to either the positive or negative input terminal of the operational amplifier.

[0041] An isolation resistor, the first end of which is coupled to the output of the buffer; and

[0042] The first set of switches and the second set of switches are controlled such that when the buffer drives a first capacitive load, the first set of switches closes and the second set of switches opens, and when the buffer drives a second capacitive load, the first set of switches opens and the second set of switches closes, such that:

[0043] When the buffer drives the first capacitive load, the output of the operational amplifier is coupled to the output of the buffer via at least one switch in the first set of switches, and the second end of the voltage-voltage feedback network is coupled to the output of the buffer via at least one switch in the first set of switches, or the second end of the voltage-voltage feedback network is directly coupled to the second end of the isolation resistor so that the isolation resistor is used as the feedback resistor of the operational amplifier.

[0044] When the buffer drives the second capacitive load, the output of the operational amplifier is coupled to the second terminal of the isolation resistor via at least one of the switches in the second group of switches, and the second terminal of the voltage-voltage feedback network is coupled to the output of the operational amplifier via at least one of the switches in the second group of switches.

[0045] This disclosure does not limit the coupling method of the operational amplifier and its voltage-voltage feedback network; for example, the operational amplifier may receive the output of the preceding circuit at its non-inverting input or negative input, and correspondingly couple the first end of the voltage-voltage feedback network to the non-inverting input or negative input of the operational amplifier, thereby forming a corresponding non-inverting input buffer or inverting input buffer.

[0046] Furthermore, this disclosure does not limit the specific implementation of the voltage-voltage feedback network, as long as it can be coupled between the input and output terminals of the operational amplifier to form corresponding negative feedback. In the scheme of this disclosure, the first and second terminals of the voltage-voltage feedback network are only used to distinguish their coupling positions and do not have any other limiting function. The first terminal is directly coupled to a certain input terminal of the operational amplifier, while the second terminal is coupled to the output terminal of the operational amplifier through a switch.

[0047] Furthermore, the buffers disclosed herein have wide applications and can be connected after various circuits to improve their driving capability. That is, this disclosure does not limit the specific structure or function of the pre-amplifier circuit; for example, as will be detailed in the following figures, the pre-amplifier circuit can be any circuit module that can be equivalent to a voltage source with an output resistor. The following examples will use a DAC (Digital to Analog Converter) as an example of a pre-amplifier circuit (i.e., using the buffers of this disclosure to improve the DAC's driving capability), but it should be understood that this disclosure is not limited thereto. In some examples, the DAC can be various types of resistive DACs, for example, DACs employing T-type or inverted-T-type resistor networks.

[0048] In addition, in the scheme disclosed herein, the first and second ends of the isolation resistor are only used to distinguish their coupling positions and do not have any other limiting function. The first end is directly coupled to the output end of the buffer, while the second end can be coupled to the output end of the operational amplifier through a switch or directly coupled to the second end of the voltage-voltage feedback network.

[0049] Furthermore, this disclosure does not limit the specific implementation of the first and second sets of switches, as long as they can be controlled to alternately open and close (i.e., when one set of switches is closed, the other set of switches is open, and vice versa), and implement the two different coupling methods (i.e., two different negative feedback loops) specified in the aforementioned scheme under two different conditions. For example, as will be detailed later with reference to the accompanying drawings, which set of the two sets of switches can be closed according to the driven load, so that there is or is no isolation resistor in the negative feedback loop of the buffer, and the second end of the voltage-voltage feedback network can be coupled to the output of the buffer instead of the output of the operational amplifier via the switch without the need for an isolation resistor, thereby avoiding the existence of resistance between the output of the operational amplifier and the output of the buffer, that is, avoiding introducing or increasing the output impedance of the buffer, because the output impedance of the buffer should be zero under ideal conditions.

[0050] The following is combined with Figures 2A to 2G The schematic block diagram is used to discuss some buffer structures according to the scheme of this disclosure. It should be understood that, although in Figures 2A to 2G The same reference numerals are used to represent the same parts in all figures, but this does not mean that these parts have the same structural or device parameters in the examples of each figure. Rather, the same or different structural or device parameters may be used depending on the actual situation of each example.

[0051] Figure 2A The buffer shown is a negative input buffer, in which the non-inverting input of op-amp 210 receives a fixed voltage VCM, and the inverting input of op-amp 210 receives the output of the preamp circuit 240 (equivalent to the voltage source VI + output resistor RS shown in the dashed box in the figure) and is coupled to the first terminal of the voltage-voltage feedback network 220. The first terminal of the isolation resistor RN is coupled to the output terminal VO_BUF of the buffer. The output terminal Vo_op of op-amp 210 can be coupled to the second terminal of the isolation resistor RN or the output terminal VO_BUF of the buffer via at least one of the two sets of switches 230. The second terminal of the voltage-voltage feedback network 220 can be coupled to the output terminal Vo_op of op-amp 210 or the output terminal VO_BUF of the buffer via at least one of the two sets of switches 230. Thus, the negative feedback loop can be selectively configured with or without an isolation resistor to adapt to different load conditions. In addition, the second end of the voltage-voltage feedback network can be coupled to the output of the buffer instead of the output of the operational amplifier via a switch without the isolation resistor in the negative feedback loop. This avoids the resistance between the output of the operational amplifier and the output of the buffer, that is, it avoids introducing or increasing the output impedance of the buffer, since the output impedance of the buffer should be zero under ideal conditions.

[0052] In addition, compared to the positive input buffer described later, the negative input buffer has another advantage: the input voltage received by the op-amp's input pair is always a fixed voltage VCM or a feedback voltage that varies around it. This avoids the need to use an op-amp with rail-to-rail input (which may require more complex input pairs, such as PMOS and NMOS input pairs, and the offset of PMOS and NMOS input pairs is often inconsistent, resulting in a larger offset error).

[0053] As stated above, this disclosure does not limit the specific implementation of the voltage-voltage feedback network 220 and the two sets of switches 230, therefore... Figure 2A and subsequent Figures 2B-2G Both are represented by a block diagram.

[0054] Figure 2B The buffer shown is a non-inverting input buffer, which is related to... Figure 2A The main difference lies in that the output of the preamplifier circuit 240 is coupled to the non-inverting input of the op-amp 210 instead of its inverting input. The first terminal of the voltage-voltage feedback network 220 is still coupled to the inverting input of the op-amp 210. The remaining coupling methods and switching operation are the same as described above. Figure 2A The same applies, so I won't repeat it here.

[0055] Figure 2C The buffer shown is also a non-inverting input buffer, which is similar to... Figure 2B The main difference lies in the fact that the second terminal of the voltage-voltage feedback network 220 is directly coupled to the isolation resistor R. N The second terminal, and so that in the case where no isolation resistor is needed in the negative feedback loop, i.e., when the output terminal Vo_op of op-amp 210 is coupled to the output terminal VO_BUF of the buffer via at least one switch, the isolation resistor RN is used as the feedback resistor of op-amp 210. That is to say, Figure 2C The isolation resistor R in N Both sets of switches 230 can be connected in the application circuit of the buffer when they are closed respectively (R) N When used as an isolation resistor, it is not in the negative feedback loop, but when the buffer drives a large capacitive load, R... N R is used as an isolation resistor to improve stability, while in cases where the buffer drives a small capacitive load... N It becomes the feedback resistor for the operational amplifier 210. The remaining coupling methods and switching operation are the same as described above. Figure 2B The same applies, so I won't repeat it here.

[0056] Furthermore, to further optimize the switch arrangement and reduce the impact of the introduced switches on the negative feedback loop, in some embodiments, at least some of the aforementioned two sets of switches can be combined with the last stage of the operational amplifier (i.e., the output stage), for example, as shown below. Figure 2D to Figure 2G As shown, among which Figure 2D Its principle is briefly illustrated.

[0057] like Figure 2D As shown in the upper part, the output terminal Vo_op of op-amp 210 is typically drawn from the connection between the drains of the PMOS transistor (identified by MP1) and the NMOS transistor (identified by MN1) in its output stage. That is, the drains of both PMOS transistor MP1 and NMOS transistor MN1 can be considered as the output terminal of op-amp 210. As previously mentioned, in the scheme of this disclosure, the output terminal Vo_op of op-amp 210 can be coupled to two different nodes (e.g., ...) via two different switches (identified by S1 and S2). Figure 2D (as shown in the first and second nodes), thereby configuring different negative feedback loops.

[0058] It should be understood that, as mentioned above, the scheme disclosed herein can employ various suitable operational amplifier structures, voltage-voltage feedback network structures, and two-set switch structures, etc., therefore, in Figure 2D In the text, apart from the components that explain the principle, the rest are represented by ellipses.

[0059] Additionally, it should be understood that the output stage of an op-amp refers to the stage within the op-amp that involves output, typically the last driving and amplifying stage. If the op-amp itself has only one stage, then the output stage is the op-amp itself. Depending on the structure of the output stage, the sources of PMOS transistor MP1 and NMOS transistor MN1 may be connected to the power supply voltage and ground, respectively, or they may be connected to other PMOS and NMOS transistors; therefore, ellipses are used in the diagram. Furthermore, "node one" and "node two" in the diagram are simply used to refer to two different nodes, which can be the nodes discussed earlier as needed. Figures 2A to 2C The endpoints of various components or a certain intermediate node, etc.

[0060] In some embodiments, it can be changed Figure 2D The arrangement of the switches shown at the top is incorporated into the output stage of the operational amplifier 210, for example... Figure 2D The lower part is shown.

[0061] like Figure 2DAs shown in the lower part, two series switches S11 and S12 can be inserted between the drain of PMOS transistor MP1 and the drain of NMOS transistor MN1 in the output stage of op-amp 210, and the connection between these two series switches S11 and S12 is directly coupled to the first node; similarly, another switch branch, namely two more series switches S21 and S22, can be inserted in parallel with the two series switches S11 and S12 between the drain of PMOS transistor MP1 and the drain of NMOS transistor MN1, and the connection between these two series switches S21 and S22 is directly coupled to the second node.

[0062] When switches S11 and S12 are closed and switches S21 and S22 are open, the output terminal of op-amp 210 can be regarded as the connection point between switches S11 and S12, which is directly coupled to the first node. When switches S11 and S12 are open and switches S21 and S22 are closed, the output terminal of op-amp 210 can be regarded as the connection point between switches S21 and S22, which is directly coupled to the second node.

[0063] Compared to Figure 2D The switch arrangement shown at the top, Figure 2D The switch arrangement shown at the bottom can be viewed as integrating the switches into the op-amp output stage, allowing the op-amp output to be directly coupled to different nodes, thus reducing the impact of switches placed after the op-amp output. Additionally, in some cases, Figure 2D The switches S1 and S2 shown at the top are typically implemented using CMOS transmission gates, while Figure 2D The switches S11 and S21 shown at the bottom are typically implemented by PMOS transistors, while switches S12 and S22 are typically implemented by NMOS transistors. Compared to switches S1 and S2, switches S11, S12, S21 and S22 are easier to manufacture with low internal resistance and small area.

[0064] Therefore, it can be Figures 2A to 2C The buffers are respectively transformed into Figures 2E to 2G The buffer shown is illustrated in this diagram. For ease of description, the switch inserted between the drains of PMOS transistor MP1 and NMOS transistor MN1 is considered part of two sets of switches 230, not part of operational amplifier 210. The drains of PMOS transistor MP1 and NMOS transistor MN1 are considered as the output terminals Vo_op1 / Vo_op2 of the operational amplifier. The remaining coupling methods and switch operation are the same as described above. Figures 2A to 2C The same applies, so I won't repeat it here.

[0065] The following is combined with Figures 3A to 3C Let us discuss some specific examples of the arrangement of two sets of switches in a buffer according to some embodiments of this disclosure. It should be understood that, although in Figures 3A to 3C The same reference numerals are used to denote the same components in the figures, but this does not mean that these components have the same structural or device parameters in the examples of each figure. Rather, the same or different structural or device parameters may be used depending on the actual situation of each example. In addition, although only a specific arrangement example of two sets of switches for selectively configuring two different loops is given in the figures of this disclosure, it should be understood that this disclosure is not limited to this, but can be applied to more sets of switches to selectively configure more different loops. The specific implementation method can be easily obtained from the teachings of this disclosure.

[0066] Figure 3A The buffer structure corresponds to the aforementioned Figure 2A The structure shown differs only in that it provides a specific arrangement example of two sets of switches, but it should be understood that... Figure 3A The switch arrangement shown is not only applicable to Figure 2A The buffer structure shown is applicable to various other suitable buffer structures, such as... Figure 2B The structure shown, etc.

[0067] like Figure 3A As shown, the first set of switches in the two sets of switches 330 includes a first switch SP2 and a second switch SP1, and the second set of switches includes a third switch SN2 and a fourth switch SN1. Switch SP2 is coupled between the output of operational amplifier 310 and the output of buffer VO_BUF; switch SP1 is coupled between the second terminal of voltage-voltage feedback network 320 and the output of buffer VO_BUF; switch SN2 is coupled between the output of operational amplifier 310 and the second terminal of isolation resistor RN; and switch SN1 is coupled between the second terminal of voltage-voltage feedback network 320 and the output of operational amplifier 310. In some examples, switches SP1, SP2, SN1, and SN2 are all CMOS transmission gate switches.

[0068] When driving the first capacitive load (e.g., a small capacitive load), the first set of switches SP1 and SP2 are closed, and the second set of switches SN1 and SN2 are open. The output of operational amplifier 310 reaches the output terminal VO_BUF of the buffer via switch SP2, and is then fed back to the inverting input terminal via switch SP1 and the voltage-voltage feedback network 320. When driving the second capacitive load (e.g., a large capacitive load), the first set of switches SP1 and SP2 are open, and the second set of switches SN1 and SN2 are closed. The output of operational amplifier 310 is negatively fed back to the inverting input terminal via switch SN1 and the voltage-voltage feedback network 320, and reaches the output terminal VO_BUF of the buffer via switch SN2 and the isolation resistor RN. In this case, the resistor RN acts as an isolation resistor. Thus, the two sets of switches can be used to configure the two negative feedback loops of the buffer, and the corresponding negative feedback loop can be selected to operate by controlling one set of switches to close while the other switches are open.

[0069] Furthermore, it should be understood that each switch has on-resistance (also known as the internal resistance of the switch) when it is turned on. In some cases, the internal resistance of the switch may affect the output of the buffer. Therefore, the switch arrangement in this disclosure aims to minimize the impact of the internal resistance of the switches. Figure 3A As shown, when driving the first capacitive load, the drive current of the buffer is usually large, that is, the current flowing through the closed switch SP2 is large. The internal resistance of SP2 may cause a large voltage drop across SP2, such as a voltage drop on the order of 0.1V or 1V. This results in the op-amp not having the driving capability, and ultimately the voltage at VO_BUF is also incorrect (it cannot be driven). Therefore, to avoid the final output voltage of the buffer (i.e., the voltage at the output terminal VO_BUF) being inaccurate, Figure 3A The second terminal of the voltage-voltage feedback network 320 is coupled to the output terminal VO_BUF of the buffer via switch SP1, instead of being coupled to the output terminal of the operational amplifier 310. In this case, the internal resistance of the closed switch SP1 constitutes the feedback resistor. For commonly used voltage-voltage feedback networks 320, as detailed later, the internal resistance of switch SP1 is typically set to be small, negligible compared to the feedback network resistance, or its effect on the voltage fed back to the operational amplifier input is negligible. Therefore, the final output voltage of the buffer can be fed back to the operational amplifier input with approximately accuracy, ensuring that the voltage at the buffer output terminal VO_BUF is essentially accurate. Furthermore, when driving the second capacitive load, the internal resistance of the closed switch SN2 can act as isolation along with the isolation resistor RN. Similarly, the internal resistance of the closed switch SN1 also constitutes the feedback resistor, which is set to be negligible compared to the feedback network resistance; therefore, its effect on the final output voltage of the buffer is also negligible.

[0070] Figure 3B The buffer structure corresponds to the aforementioned Figure 2EThe structure shown differs only in that it provides a specific arrangement example of two sets of switches, but it should be understood that... Figure 3B The switch arrangement shown is not only applicable to Figure 2E The buffer structure shown is applicable to various other suitable buffer structures, such as... Figure 2F The structure shown, etc.

[0071] like Figure 3B As shown, the first set of switches in the two sets of switches 330 includes the fifth switch SP3, the sixth switch SP4, and the seventh switch SP5, and the second set of switches includes the eighth switch SN3, the ninth switch SN4, and the tenth switch SN5. Switch SP3 is coupled between the drain of PMOS transistor MP1 and the output terminal VO_BUF of the buffer; switch SP4 is coupled between the drain of NMOS transistor MN1 and the output terminal VO_BUF of the buffer; switch SP5 is coupled between the second terminal of the voltage-voltage feedback network 320 and the output terminal VO_BUF of the buffer; switch SN3 is coupled between the drain of PMOS transistor MP1 and the second terminal of the voltage-voltage feedback network 320; switch SN4 is coupled between the drain of NMOS transistor MN1 and the second terminal of the voltage-voltage feedback network 320; and switch SN5 is coupled between the second terminal of the voltage-voltage feedback network 320 and the second terminal of the isolation resistor RN. In some examples, switches SP3 and SN3 are both PMOS switches, switches SP4 and SN4 are both NMOS switches, and switches SP5 and SN5 are both CMOS transmission gate switches. For example, PMOS switches and NMOS switches can be implemented using a single PMOS transistor and a single NMOS transistor, respectively.

[0072] When driving a small capacitive load, the first set of switches SP3, SP4, and SP5 are closed, and the second set of switches SN3, SN4, and SN5 are open. Transistors MP1 and MN1 in the output stage of op-amp 310 are connected via switches SP3 and SP4, causing the op-amp's output to reach the output terminal VO_BUF of the buffer, and then fed back to the inverting input terminal via switch SP5 and the voltage-voltage feedback network 320. When driving a large capacitive load, the first set of switches SP3, SP4, and SP5 are open, and the second set of switches SN3, SN4, and SN5 are closed. Transistors MP1 and MN1 in the output stage of op-amp 310 are connected via switches SN3 and SN4, causing the op-amp's output to be negatively fed back to the inverting input terminal via the voltage-voltage feedback network 320, and simultaneously reaching the output terminal VO_BUF of the buffer via switch SN5 and the isolation resistor RN. In this case, resistor RN acts as an isolation resistor. Thus, the two sets of switches can be used to configure the two negative feedback loops of the buffer, and by controlling one set of switches to close while the other switches are open, the corresponding negative feedback loop can be selected to operate.

[0073] With the previous Figure 3A akin, Figure 3B The switch arrangement shown also minimizes the adverse effects of switch internal resistance on the buffer's output voltage. Furthermore, as mentioned earlier, compared to... Figure 3A The switch in the middle, Figure 3B The switch can have lower internal resistance and smaller area, which is beneficial to the implementation of the buffer of this disclosure.

[0074] Figure 3C The buffer structure corresponds to the aforementioned Figure 2G The structure shown differs only in that it provides a specific arrangement example of two sets of switches, but it should be understood that... Figure 3C The switch arrangement shown is not only applicable to Figure 2G The buffer structure shown is applicable to various other suitable buffer structures.

[0075] like Figure 3C As shown, the second terminal of the voltage-voltage feedback network 320 is directly coupled to the second terminal of the isolation resistor RN. Additionally, the first set of switches in the two sets of switches 330 includes the fifteenth switch SP6 and the sixteenth switch SP7, and the second set includes the seventeenth switch SN6 and the eighteenth switch SN7. Switch SP6 is coupled between the drain of the PMOS transistor MP1 and the output terminal VO_BUF of the buffer; switch SP7 is coupled between the drain of the NMOS transistor MN1 and the output terminal VO_BUF of the buffer; switch SN6 is coupled between the drain of the PMOS transistor MP1 and the second terminal of the voltage-voltage feedback network 320; and switch SN7 is coupled between the drain of the NMOS transistor MN1 and the second terminal of the voltage-voltage feedback network 320. In some examples, switches SP6 and SN6 are both PMOS switches, and switches SP7 and SN7 are both NMOS switches.

[0076] When driving a small capacitive load, the first set of switches SP6 and SP7 are closed, and the second set of switches SN6 and SN7 are open. Transistors MP1 and MN1 in the output stage of op-amp 310 are connected via switches SP6 and SP7, causing the op-amp output to reach the output terminal VO_BUF of the buffer. The output is then fed back to the inverting input terminal via the isolation resistor RN and the voltage-voltage feedback network 320. In this case, resistor RN does not function as an isolation resistor but instead becomes a feedback resistor in the feedback branch. When driving a large capacitive load, the first set of switches SP6 and SP7 are open, and the second set of switches SN6 and SN7 are closed. Transistors MP1 and MN1 in the output stage of op-amp 310 are connected via switches SN6 and SN7, causing the op-amp output to be negatively fed back to the inverting input terminal via the voltage-voltage feedback network 320. Simultaneously, the output reaches the output terminal VO_BUF of the buffer via the isolation resistor RN. In this case, resistor RN acts as an isolation resistor. Thus, the two sets of switches can be used to configure two negative feedback loops of the buffer, and by controlling one set of switches to close while the others are open, the corresponding negative feedback loop can be selected to operate. It should be understood that in some cases, such as when the voltage-voltage feedback network 320, which will be detailed later, is only a resistor or a wire, the negative feedback operation of the op-amp 310 will not be affected when the first set of switches SP6 and SP7 are closed, making the resistor RN the feedback resistor. This is because the input impedance of the op-amp is very large, and the resistance values ​​of the resistor RN and the voltage-voltage feedback network 320 can be ignored. The voltage fed back to the inverting input is always equal to the output voltage of the op-amp.

[0077] Compared to Figure 3B The switch arrangement shown is as follows: Figure 3C The structure can reduce the number of switches, further reducing the circuit area of ​​the buffer.

[0078] The following is combined with Figures 4 to 10 The present disclosure will discuss specific circuit constructions of buffers according to some embodiments, providing examples of specific arrangements of two sets of switches and specific implementations of voltage-voltage feedback networks. It should be understood that, although in Figures 4 to 10 Some components are represented by the same reference numerals, but this does not mean that these components have the same structural or device parameters in all the examples in the figures. Rather, they may adopt the same or different structural or device parameters depending on the specific circumstances of each example. Furthermore, it should be understood that in all the figures of this disclosure, sometimes different reference numerals are used to identify the same or similar components for distinction. However, this does not mean that these components have different structural or device parameters from one another. Rather, they may adopt the same or different structural or device parameters depending on the specific circumstances of each example.

[0079] Figure 4 The buffer structure corresponds to the aforementioned Figure 3A The structure shown differs only in that it provides a specific implementation of the voltage-voltage feedback network; however, it should be understood that the voltage-voltage feedback network in this disclosure is not limited to this.

[0080] Figure 4 It can also be referred to as an inverting input amplifier, wherein the voltage-voltage feedback network includes a first feedback resistor RF1 coupled between its first and second terminals.

[0081] The preamplifier circuit 440 can be, for example, a resistive DAC with an output impedance of RS and an output voltage of Vi. The buffer disclosed herein is used to improve the driving capability of the DAC, so the output terminal VO_BUF of the buffer can be regarded as the output terminal of the DAC.

[0082] The output voltage of the buffer is shown in the following formula:

[0083]

[0084] Output common-mode level is The gain is -RF1 / RS. The gain of this buffer can be adjusted by the values ​​of the feedback resistors RF1 and RS. When RF1 = RS, the gain of the buffer is -1. Additionally, in some examples, RF1 can be set to M * RS, meaning RF1 is M times RS, in which case the buffer provides M times gain amplification.

[0085] Figure 4 The small-signal stability analysis of the negative feedback loop is combined with the previous analysis. Figure 1A and Figure 1B The analysis is the same, the only difference being the application of large signals.

[0086] Therefore, in accordance with the aforementioned Figure 3A same, Figure 4 The buffer can be selectively configured with or without isolation resistors in the negative feedback loop by adding four switches SP1, SP2, SN1 and SN2 to adapt to different load conditions, which will not be elaborated here.

[0087] Additionally, in some cases where the preamplifier circuit 440 is a resistive DAC, the value of the aforementioned first feedback resistor RF1 can be set to be equal to the value of the output resistor RS of the resistive DAC (therefore, the gain of the buffer is -1), the value of the fixed voltage VCM can be set to half the value of the maximum output voltage Vrf of the resistive DAC, and the output voltage of the resistive DAC (i.e., Figure 4 Vi) is the analog voltage obtained by inverting and quantizing the input digital code value. The final output voltage of the buffer is equal to the analog voltage obtained by normally converting the input digital code value to the resistive DAC, as described below:

[0088] For example, this resistive DAC is a 12-bit DAC. It first inverts the input digital code value (DACDOR) and then quantizes it to obtain the analog voltage.

[0089]

[0090] go through Figure 4 A -1 inverting amplifier is used to drive the amplification (where VCM = 0.5 * Vrf), resulting in a large output signal.

[0091]

[0092] Its advantages are Figure 4 The input voltage of the op-amp input pair transistors is always Vrf / 2, thus eliminating the need for rail-to-rail input op-amps and avoiding errors caused by misalignment between PMOS and NMOS input pairs.

[0093] It should be understood that this disclosure is not limited to the case where RF1 = RS discussed above. RF1 can also be set to M * RS, with the value of M chosen as needed. In this case, the buffer gain is -M times. A similar configuration can be used.

[0094]

[0095] The rest of the content can be changed similarly, and will not be repeated here.

[0096] Figure 5 The buffer structure corresponds to the aforementioned Figure 2B The structure shown differs only in that it uses the aforementioned Figure 3A The arrangement of the two sets of switches is shown, and a specific implementation of the voltage-voltage feedback network is given. However, it should be understood that the voltage-voltage feedback network in the scheme of this disclosure is not limited to this.

[0097] Figure 5 It can also be called a non-inverting input amplifier, wherein the voltage-voltage feedback network includes a second feedback resistor RF2 coupled between its first and second terminals, and a third feedback resistor RF3 coupled between its first terminal and ground.

[0098] The output voltage of the buffer is shown in the following formula:

[0099]

[0100] The gain is 1 + RF2 / RF3. The gain of this buffer can be adjusted by the values ​​of the feedback resistors RF2 and RF3. When RF3 is infinite, it is an open circuit (at this point, it can also be considered as a voltage-to-voltage feedback network consisting only of the second feedback resistor RF2, similar to...). Figure 1A and Figure 1BThe feedback network structure shown is a follower-structured unity-gain buffer, meaning the output voltage of the buffer follows the input voltage Vi.

[0101] Figure 5 The small-signal stability analysis of the negative feedback loop is combined with the previous analysis. Figure 1A and Figure 1B The analysis is the same, but the switch arrangement is the same as... Figure 4 The content is the same as the preceding content, and will not be repeated here.

[0102] Figure 6 The buffer structure corresponds to the aforementioned Figure 3B The structure shown differs only in that the sources of transistors MP1 and MN1 in the output stage of the operational amplifier are coupled to the power supply voltage VDD and ground, respectively, and the aforementioned method is used. Figure 4 The specific implementation method of the voltage-voltage feedback network shown.

[0103] In some examples, the output stage of the op-amp can also be referred to as the last driving amplification stage of the op-amp, and the transistors MP1 and MN1 therein are the power transistors in the last driving stage of the op-amp.

[0104] Figure 6 The working principle of the buffer and Figure 4 They are basically the same, the difference being the arrangement of the two sets of switches.

[0105] Similar to the previous combination Figure 3B The switch arrangement discussed is for Figure 6 The buffer, when driving a small capacitive load, has the first set of switches SP3, SP4, and SP5 closed, and the second set of switches SN3, SN4, and SN5 open. MP1, SP3, SP4, and MN1 form the rail-to-rail push-pull output stage of the op-amp, and the output of the op-amp is directly connected to the output of the buffer. SP5 and RF1 form the feedback resistor, and the resistance of SP5 is negligible compared to RF1. When driving a large capacitive load, the first set of switches SP3, SP4, and SP5 are open, and the second set of switches SN3, SN4, and SN5 are closed. MP1, SN3, SN4, and MN1 form the rail-to-rail push-pull output stage of the op-amp, and RF1 is the feedback resistor. The output of the op-amp reaches the output terminal VO_BUF of the buffer through switch SN5 and isolation resistor RN. The internal resistance of SN5 also plays an isolation role (the internal resistance of SN5 can be set as needed, and its size is not limited).

[0106] Figure 6 The remaining working principles of the buffer will not be elaborated here.

[0107] Figure 7 The buffer structure corresponds to the aforementioned Figure 2FThe structure shown differs only in that the sources of transistors MP1 and MN1 in the output stage (or the last driving amplification stage of the op-amp) are coupled to the power supply voltage VDD and ground, respectively, employing the aforementioned... Figure 3B The arrangement of the two sets of switches shown employs the aforementioned method. Figure 5 The specific implementation method of the voltage-voltage feedback network shown.

[0108] It should be understood that Figure 7 The working principle of the buffer and Figure 5 They are basically the same, the difference being the arrangement of the two sets of switches, as already discussed earlier. Figure 3B and Figure 6 The arrangement of switches has been discussed, and will not be repeated here.

[0109] Figure 8 The buffer structure corresponds to the aforementioned Figure 3C The structure shown differs only in that the sources of transistors MP1 and MN1 in the op-amp output stage (or the last driving amplification stage) are coupled to the power supply voltage VDD and ground, respectively. A specific implementation of the voltage-voltage feedback network is also given. However, it should be understood that the voltage-voltage feedback network in the scheme disclosed herein is not limited to this.

[0110] Figure 8 The voltage-voltage feedback network in the middle can be regarded as Figure 7 A simplified implementation of the voltage-voltage feedback network in the model eliminates the feedback resistors RF2 and RF3, and includes only a single wire coupled between its first and second terminals, thus forming a unity-gain amplifier with a follower structure, i.e., Vo = Vi.

[0111] thus, Figure 8 The switches are arranged in Figure 7 Based on the previous version, switches SN5 and SP5 have been removed.

[0112] Similar to the previous combination Figure 3C The switch arrangement discussed is for Figure 8 When driving a small capacitive load, the first set of switches SP6 and SP7 are closed, and the second set of switches SN6 and SN7 are open. MP1, SP6, SP7, and MN1 form the rail-to-rail push-pull output stage of the op-amp. The output of the op-amp is directly connected to the output of the buffer. At this time, the resistor RN forms a feedback resistor in the feedback branch, but it has no effect on the voltage fed back to the input terminal, and Vo is still equal to Vi. When driving a large capacitive load, the first set of switches SP6 and SP7 are open, and the second set of switches SN6 and SN7 are closed. MP1, SN6, SN7, and MN1 form the rail-to-rail push-pull output stage of the op-amp. The output of the op-amp reaches the output terminal VO_BUF of the buffer through the isolation resistor RN. At this time, the resistor RN acts as an isolation resistor.

[0113] Figure 8 The remaining working principles of the buffer will not be elaborated here.

[0114] In some embodiments, as described above Figures 2E to 2G , Figures 3B to 3C and Figures 6 to 8 The buffer structure shown can also be supplemented with four switch-controlled Miller compensation branches to perform Miller compensation under two capacitive load conditions, further improving the stability of the buffer.

[0115] For example, the buffer of this disclosure may further include a first Miller compensation capacitor, a second Miller compensation capacitor, a third Miller compensation capacitor, and a fourth Miller compensation capacitor; the first set of switches may further include an eleventh switch and a twelfth switch; and the second set of switches may further include a thirteenth switch and a fourteenth switch, wherein:

[0116] The eleventh switch and the first Miller compensation capacitor are connected in series between the gate of the first PMOS transistor (MP1) and the output of the buffer.

[0117] The twelfth switch and the second Miller compensation capacitor are connected in series between the gate of the first NMOS transistor (MN1) and the output of the buffer.

[0118] The thirteenth switch and the third Miller compensation capacitor are connected in series between the gate of the first PMOS transistor (MP1) and the second terminal of the voltage-voltage feedback network.

[0119] The fourteenth switch and the fourth Miller compensation capacitor are connected in series between the gate of the first NMOS transistor (MN1) and the second terminal of the voltage-voltage feedback network.

[0120] In some cases, the eleventh and thirteenth switches are both PMOS switches, while the twelfth and fourteenth switches are both NMOS switches.

[0121] Therefore, when driving different capacitive loads, the coupling position of the Miller compensation capacitor can also change with the output position of the op-amp, thus providing more accurate Miller compensation. Furthermore, in some cases, different Miller compensation capacitor values ​​can be used for different capacitive loads, thereby further improving the stability of the buffer. That is, the capacitance values ​​of the first and third Miller compensation capacitors mentioned above can be different, and the capacitance values ​​of the second and fourth Miller compensation capacitors can also be different.

[0122] The following will combine Figure 9 and Figure 10 This document describes an example of a buffer with four controllable Miller compensation capacitors added, according to some embodiments of the present disclosure.

[0123] Figure 9 The buffer structure corresponds to the aforementioned Figure 6 The structure shown differs only in the addition of four controllable Miller compensation capacitors. However, it should be understood that the arrangement of these four controllable Miller compensation capacitors is not only applicable to… Figure 6 The buffer structure shown is not applicable to all other buffer structures.

[0124] like Figure 9 As shown, in Figure 6 Based on the buffer structure shown, the following was added:

[0125] The switch SP8 and Miller compensation capacitor CP1 are connected in series between the gate of PMOS transistor MP1 and the output terminal VO_BUF of the buffer.

[0126] Switch SP9 and Miller compensation capacitor CP2 are connected in series between the gate of NMOS transistor MN1 and the output terminal VO_BUF of the buffer.

[0127] The switch SN8 and Miller compensation capacitor CN1 are connected in series between the gate of PMOS transistor MP1 and one end of feedback resistor RF1.

[0128] Switch SN9 and Miller compensation capacitor CN2 are connected in series between the gate of NMOS transistor MN1 and one end of feedback resistor RF1.

[0129] When driving a small capacitive load, switches SP8 and SP9 are closed, and switches SN8 and SN9 are open. Capacitors CP1 and CP2 form Miller compensation capacitors between the current output node of the op-amp (which is also the output node of the buffer) and the gate of each output transistor, respectively. When driving a large capacitive load, switches SP8 and SP9 are open, and switches SN8 and SN9 are closed. Capacitors CN1 and CN2 form Miller compensation capacitors between the current output node of the op-amp (which is also one end of the voltage-voltage feedback network) and the gate of each output transistor, respectively.

[0130] Therefore, even when driving different capacitive loads and configuring different negative feedback loops, the Miller compensation capacitors remain coupled to the current output node of the op-amp, thus providing more accurate Miller compensation. Furthermore, as mentioned earlier, in some examples, to further improve the stability of the buffer, different Miller compensation capacitor values ​​can be designed for different negative feedback loops. For example, the capacitance values ​​of capacitors CP1 and CN1 can be different, and the capacitance values ​​of capacitors CP2 and CN2 can also be different.

[0131] Figure 10 The buffer structure corresponds to the aforementioned Figure 7 The structure shown is different only in that it adds the elements mentioned earlier. Figure 9 The four controllable Miller compensation capacitors shown are illustrated. Therefore, Figure 10 The working principle can be referred to the above. Figure 7 and Figure 9 The details will not be repeated here.

[0132] Furthermore, in some embodiments, all components included in the buffer of this disclosure can be integrated within the same integrated circuit (IC) chip. That is, embodiments of this disclosure provide an integrated circuit that includes the buffer of any of the foregoing embodiments.

[0133] In some cases, the integrated circuit may also include a pre-amplifier circuit whose output is coupled to a buffer. That is, the pre-amplifier circuit and the buffer are both integrated within the same IC chip. This pre-amplifier circuit can be a circuit module that can be equivalent to a voltage source with an output resistor.

[0134] In addition, in some cases, the first and second sets of switches in the buffer within the integrated circuit are controlled by signals from outside the integrated circuit, or by configuring register bits inside the integrated circuit.

[0135] For example, the output terminal VO_BUF of the buffer can serve as an external terminal (pad) of the IC chip. The closing of one of the two sets of switches can be controlled based on the size of the capacitive load connected to the IC chip terminal, thus configuring a suitable negative feedback loop. A control signal can be used to control the on / off state of the two sets of switches. For example, the control terminal of the first set of switches receives this control signal, while the control terminal of the second set of switches receives its inverted form. This control signal can be received directly from outside the IC chip or generated by configuring registers within the IC chip.

[0136] For example, all components of the buffer can be integrated into an MCU (Micro Controller Unit) chip, with the first and second sets of switches controlled by configuring register bits within the MCU chip. Alternatively, the preceding circuitry (such as a resistive DAC) can be integrated with the buffer into the MCU chip. This allows for easy configuration of the buffer's negative feedback loop as needed, ensuring the buffer's stability.

[0137] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A buffer, comprising: An operational amplifier whose positive or negative input terminal receives the output of the preceding circuit. The voltage-voltage feedback network for the operational amplifier has its first terminal coupled to either the positive or negative input terminal of the operational amplifier. An isolation resistor, the first end of which is coupled to the output of the buffer; as well as The first set of switches and the second set of switches are controlled such that when the buffer drives a first capacitive load, the first set of switches closes and the second set of switches opens, and when the buffer drives a second capacitive load, the first set of switches opens and the second set of switches closes, such that: When the buffer drives the first capacitive load, the output of the operational amplifier is coupled to the output of the buffer via at least one switch in the first set of switches, and the second end of the voltage-voltage feedback network is coupled to the output of the buffer via at least one switch in the first set of switches, or the second end of the voltage-voltage feedback network is directly coupled to the second end of the isolation resistor so that the isolation resistor is used as the feedback resistor of the operational amplifier. When the buffer drives the second capacitive load, the output of the operational amplifier is coupled to the second terminal of the isolation resistor via at least one of the switches in the second set of switches, and the second terminal of the voltage-voltage feedback network is coupled to the output of the operational amplifier via at least one of the switches in the second set of switches.

2. The buffer according to claim 1, wherein, The first set of switches includes a first switch and a second switch. The second set of switches includes a third switch and a fourth switch. The first switch is coupled between the output of the operational amplifier and the output of the buffer, and the second switch is coupled between the second terminal of the voltage-voltage feedback network and the output of the buffer. The third switch is coupled between the output terminal of the operational amplifier and the second terminal of the isolation resistor, and the fourth switch is coupled between the second terminal of the voltage-voltage feedback network and the output terminal of the operational amplifier.

3. The buffer according to claim 1, wherein, The output stage of the operational amplifier includes a first PMOS transistor and a first NMOS transistor, wherein the drain of the first PMOS transistor and the drain of the first NMOS transistor are used as the output terminal of the operational amplifier. The first group of switches includes a fifth switch, a sixth switch, and a seventh switch. The second group of switches includes the eighth, ninth, and tenth switches. Specifically, the fifth switch is coupled between the drain of the first PMOS transistor and the output terminal of the buffer; the sixth switch is coupled between the drain of the first NMOS transistor and the output terminal of the buffer; and the seventh switch is coupled between the second terminal of the voltage-voltage feedback network and the output terminal of the buffer. The eighth switch is coupled between the drain of the first PMOS transistor and the second terminal of the voltage-voltage feedback network, the ninth switch is coupled between the drain of the first NMOS transistor and the second terminal of the voltage-voltage feedback network, and the tenth switch is coupled between the second terminal of the voltage-voltage feedback network and the second terminal of the isolation resistor.

4. The buffer according to claim 3, wherein, The buffer also includes a first Miller compensation capacitor, a second Miller compensation capacitor, a third Miller compensation capacitor, and a fourth Miller compensation capacitor. The first group of switches also includes an eleventh switch and a twelfth switch; The second group of switches also includes a thirteenth switch and a fourteenth switch; The eleventh switch and the first Miller compensation capacitor are connected in series between the gate of the first PMOS transistor and the output terminal of the buffer. The twelfth switch and the second Miller compensation capacitor are connected in series between the gate of the first NMOS transistor and the output of the buffer. The thirteenth switch and the third Miller compensation capacitor are connected in series between the gate of the first PMOS transistor and the second terminal of the voltage-voltage feedback network. The fourteenth switch and the fourth Miller compensation capacitor are connected in series between the gate of the first NMOS transistor and the second terminal of the voltage-voltage feedback network.

5. The buffer according to any one of claims 1-4, wherein, The non-inverting input of the operational amplifier receives a fixed voltage; The inverting input of the operational amplifier receives the output of the preceding circuit and is coupled to the first terminal of the voltage-voltage feedback network. The voltage-voltage feedback network includes a first feedback resistor coupled between its first and second terminals.

6. The buffer according to claim 5, wherein, The resistance value of the first feedback resistor is equal to the resistance value of the output resistor of the preceding circuit.

7. The buffer according to claim 1, wherein, The non-inverting input of the operational amplifier receives the output of the preceding circuit. The inverting input terminal of the operational amplifier is coupled to the first terminal of the voltage-voltage feedback network; The voltage-voltage feedback network includes a wire or a second feedback resistor coupled between its first and second ends.

8. The buffer according to claim 7, wherein, In the case where the voltage-voltage feedback network includes the second feedback resistor, the voltage-voltage feedback network also includes a third feedback resistor coupled between its first terminal and ground.

9. The buffer according to claim 7, wherein, The output stage of the operational amplifier includes a first PMOS transistor and a first NMOS transistor, wherein the drain of the first PMOS transistor and the drain of the first NMOS transistor are used as the output terminal of the operational amplifier. The first group of switches includes the fifteenth switch and the sixteenth switch. The second group of switches includes the seventeenth switch and the eighteenth switch. The second terminal of the voltage-voltage feedback network is directly coupled to the second terminal of the isolation resistor. The fifteenth switch is coupled between the drain of the first PMOS transistor and the output terminal of the buffer, and the sixteenth switch is coupled between the drain of the first NMOS transistor and the output terminal of the buffer. The seventeenth switch is coupled between the drain of the first PMOS transistor and the second terminal of the voltage-voltage feedback network, and the eighteenth switch is coupled between the drain of the first NMOS transistor and the second terminal of the voltage-voltage feedback network.

10. The buffer according to claim 5, wherein, The front-end circuit is a resistive DAC; The resistance value of the first feedback resistor is equal to the resistance value of the output resistor of the resistive DAC; The value of the fixed voltage is equal to half the value of the maximum output voltage of the resistive DAC; as well as The output voltage of the resistive DAC is an analog voltage obtained by inverting and quantizing the input digital code value.

11. The buffer according to claim 2, wherein, The first switch, the second switch, the third switch, and the fourth switch are all CMOS transmission gates.

12. The buffer according to claim 3, wherein, Both the fifth switch and the eighth switch are PMOS switches; Both the sixth switch and the ninth switch are NMOS switches; Both the seventh switch and the tenth switch are CMOS transmission gates.

13. The buffer according to claim 4, wherein, Both the eleventh switch and the thirteenth switch are PMOS switches; Both the twelfth and fourteenth switches are NMOS switches.

14. The buffer according to claim 9, wherein, Both the fifteenth switch and the seventeenth switch are PMOS switches; Both the sixteenth and eighteenth switches are NMOS switches.

15. The buffer according to claim 1, wherein, The capacitance of the second capacitive load is greater than the capacitance of the first capacitive load.

16. An integrated circuit, comprising: The buffer according to any one of claims 1-15.

17. The integrated circuit according to claim 16, further comprising: The output of the preamplifier circuit is coupled to the buffer. The preceding circuit is a circuit module that can be equivalent to a voltage source with an output resistor.

18. The integrated circuit according to claim 16, wherein, The first set of switches and the second set of switches are controlled by signals from outside the integrated circuit; or The first set of switches and the second set of switches are controlled by configuring register bits inside the integrated circuit.

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