Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a first gate dielectric layer, a first gate, a second gate dielectric layer, a second gate and a gate extraction electrode. The substrate includes a well region of a first conductivity type. A trench is arranged in the well region. The first gate dielectric layer at least covers the sidewall of the trench. The thickness of the first gate dielectric layer at the top of the trench is greater than that at the bottom of the trench. The first grid electrode covers the surface, away from the well region, of the first grid dielectric layer and fills the groove. The second gate dielectric layer is located on the surface of the well region. The second gate is located on the surface of the second gate dielectric layer away from the well region. The gate extraction electrode is electrically connected with the first gate and the second gate. The specific on-resistance of the semiconductor device can be reduced, and the on-state on-current can be increased, so that the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development and progress of semiconductor technology, semiconductor devices have become an indispensable and important electronic component in modern industry.

[0003] In semiconductor device applications, the specific on-resistance determines the device's power consumption and even the overall chip's energy consumption. To reduce the specific on-resistance and increase the on-state current of semiconductor devices, current technologies employ conventional electric field optimization techniques such as surface field reduction, superjunction technology, and field plate technology. However, due to the "silicon limit," these techniques have an upper limit on their performance improvement for semiconductor devices. Summary of the Invention

[0004] Based on this, this application provides a semiconductor structure and its fabrication method, which can reduce the specific on-resistance of semiconductor devices and increase the on-state conduction current, thereby improving the performance of semiconductor devices.

[0005] This application provides a semiconductor structure, including: a substrate, a first gate dielectric layer, a first gate, a second gate dielectric layer, a second gate, and a gate lead-out electrode. The substrate includes a well region of a first conductivity type. A trench is formed within the well region. The first gate dielectric layer at least covers the sidewalls of the trench. The thickness of the first gate dielectric layer at the top of the trench is greater than its thickness at the bottom of the trench. The first gate covers the surface of the first gate dielectric layer away from the well region and fills the trench. The second gate dielectric layer is located on the surface of the well region. The second gate is located on the surface of the second gate dielectric layer away from the well region. The gate lead-out electrode is electrically connected to both the first gate and the second gate.

[0006] In one embodiment, the material of the first gate includes doped polycrystalline silicon.

[0007] In one embodiment, the ion concentration of doped polysilicon at the top of the trench is lower than the ion concentration at the bottom of the trench.

[0008] In one embodiment, the doping concentration of the polysilicon gradually increases from the top to the bottom of the trench.

[0009] In one embodiment, the semiconductor structure further includes a bottom semiconductor layer and a buried dielectric layer. The buried dielectric layer is located on the bottom semiconductor layer, and the substrate is located on the surface of the buried dielectric layer away from the bottom semiconductor layer. The bottom of the first gate is in direct contact with the buried dielectric layer.

[0010] In one embodiment, the semiconductor structure further includes: a drift region of a first conductivity type, a body region of a second conductivity type, a source region, a drain region, a source region lead-out electrode, and a drain region lead-out electrode. The drift region of the first conductivity type is located within the well region and on the side of the second gate away from the first gate, and is spaced apart from the second gate. The body region of the second conductivity type is located within the well region and between the second gate and the first gate. The source region is located within the body region. The drain region is located within the drift region. The source region lead-out electrode is electrically connected to the source region. The drain region lead-out electrode is electrically connected to the drain region.

[0011] In one embodiment, the source region includes a first source diffusion region of a first conductivity type, a second source diffusion region of a second conductivity type, and a third source diffusion region of the first conductivity type, arranged sequentially from the second gate in a direction away from the second gate. The drain region includes a drain region of the second conductivity type.

[0012] In one embodiment, the thickness of the first gate dielectric layer gradually decreases from the top of the trench to the bottom of the trench.

[0013] This application also provides a method for fabricating a semiconductor structure, comprising: obtaining a substrate, the substrate including a well region of a first conductivity type; forming a trench in the well region; forming a first gate dielectric layer covering at least the sidewalls of the trench; the thickness of the first gate dielectric layer at the top of the trench being greater than its thickness at the bottom of the trench; forming a first gate electrode in the trench in which the first gate dielectric layer is formed; forming a second gate dielectric layer on the surface of the well region; forming a second gate electrode on the surface of the second gate dielectric layer away from the well region; and forming a gate lead-out electrode, the gate lead-out electrode being electrically connected to both the first gate electrode and the second gate electrode.

[0014] In one embodiment, the step of forming a first gate dielectric layer that at least covers the sidewalls of the trench includes: forming a first gate dielectric layer with a thickness that gradually decreases from the top of the trench to the bottom of the trench using a thermal oxidation process.

[0015] In one embodiment, the step of forming a first gate within a trench includes: filling the trench with polysilicon, the polysilicon comprising undoped or lightly doped polysilicon; performing ion implantation on the polysilicon to increase the doping concentration; and performing high-temperature push-well formation to obtain the first gate.

[0016] In one embodiment, the step of ion implanting polysilicon to increase the doping concentration of polysilicon includes performing multiple ion implantations of different energies, such that the doping concentration of polysilicon in the first gate gradually increases from the top of the trench to the bottom of the trench.

[0017] In one embodiment, the step of obtaining a substrate includes: obtaining a wafer having a bottom semiconductor layer, a buried dielectric layer and the substrate; the buried dielectric layer is located on the bottom semiconductor layer and the substrate is located on the surface of the buried dielectric layer away from the bottom semiconductor layer; the step of forming a trench in the well region includes: forming a trench whose bottom extends to the buried dielectric layer.

[0018] The semiconductor structure and its fabrication method provided in this application have, or at least have, the following advantages:

[0019] In this embodiment, in addition to the second gate dielectric layer and the second gate located on the surface of the substrate well region, a first gate dielectric layer and a first gate are sequentially disposed within the trench of the well region. The thickness of the first gate dielectric layer at the top of the trench is greater than its thickness at the bottom of the trench. By using gate lead-out electrodes to lead out the first gate and the second gate together, the threshold voltages of the first gate and the second gate can be made consistent, ensuring that the first gate and the second gate in the trench can be turned on simultaneously. Thus, when the device corresponding to this semiconductor structure is turned on, the first gate dielectric layer on the trench sidewall and the first gate in the trench will form a new conduction path along the trench sidewall near the trench under the influence of the potential difference. This newly added current conduction path along the trench sidewall can significantly increase the on-state conduction current of the semiconductor device without substantially changing the device's breakdown voltage, thereby increasing the device's current density and reducing the device's specific on-resistance, and thus improving the performance of the semiconductor device.

[0020] Furthermore, this application increases the doping concentration of polysilicon by first filling the trench with undoped or lightly doped polysilicon, followed by ion implantation and high-temperature push-in, to obtain the first gate. This facilitates adjusting the different doping concentrations of the first gate from the top to the bottom of the trench to match the gradually decreasing thickness of the first gate dielectric layer from the top to the bottom of the trench. This further ensures that the first and second gates are turned on simultaneously, thereby significantly increasing the on-state conduction current and reducing the specific on-resistance while essentially maintaining the device breakdown voltage. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure provided in some embodiments of this application;

[0023] Figure 2This is a schematic flowchart illustrating the method for fabricating semiconductor structures provided in some embodiments of this application;

[0024] Figure 3 A schematic diagram of the process for forming the first gate in a method for fabricating a semiconductor structure provided in some embodiments of this application;

[0025] Figure 4 A schematic diagram of the process for forming the drift region, body region, drain region and source region in the semiconductor structure fabrication method provided in some embodiments of this application;

[0026] Figure 5 This is a schematic diagram of another process for forming the drain and source regions in the semiconductor structure fabrication method provided in some embodiments of this application;

[0027] Figure 6 A schematic cross-sectional view of the structure obtained in step S100 of the method for fabricating a semiconductor structure provided in some embodiments of this application;

[0028] Figure 7(a) is a schematic cross-sectional view of the structure obtained after forming an etch barrier material layer in the semiconductor structure fabrication method provided in some embodiments of this application; Figure 7(b) is a schematic cross-sectional view of the structure obtained after forming a photoresist in the semiconductor structure fabrication method provided in some embodiments of this application; Figure 7(c) is a schematic cross-sectional view of the structure obtained after forming an etch barrier layer in the semiconductor structure fabrication method provided in some embodiments of this application; Figure 7(d) is a schematic cross-sectional view of the structure obtained in step S200 in the semiconductor structure fabrication method provided in some embodiments of this application.

[0029] Figure 8 A schematic cross-sectional view of the structure obtained in step S300 of the semiconductor structure fabrication method provided in some embodiments of this application;

[0030] Figure 9 A schematic cross-sectional view of the structure obtained after filling a trench with polysilicon in a method for fabricating a semiconductor structure provided in some embodiments of this application;

[0031] Figure 10 A schematic cross-sectional view of the structure obtained in step S401 of the semiconductor structure fabrication method provided in some embodiments of this application;

[0032] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S402 of the semiconductor structure fabrication method provided in some embodiments of this application;

[0033] Figure 12 A schematic cross-sectional view of the structure obtained after forming a gate material layer and a gate oxide material layer in the method for fabricating a semiconductor structure provided in some embodiments of this application;

[0034] Figure 13 A schematic cross-sectional view of the structure obtained in step S600 of the method for fabricating a semiconductor structure provided in some embodiments of this application;

[0035] Figure 14 A schematic cross-sectional view of the structure obtained in step S652 of the semiconductor structure fabrication method provided in some embodiments of this application;

[0036] Figure 15 This is a schematic cross-sectional view of the structure obtained in step S653 of the method for preparing a semiconductor structure according to some embodiments of this application.

[0037] Explanation of reference numerals in the attached figures:

[0038] 1-Substrate; 11-Well region; 111-Trench; 112-Drift region; 113-Bulk region; 114-Source region; 1141-First source diffusion region; 1142-Second source diffusion region; 1143-Third source diffusion region; 115-Drain region; 120-Etch barrier layer; 12-Etch barrier layer; 13-Photoresist; 21-First gate dielectric layer; 220-Polysilicon; 22-First gate; 310-Gate oxide layer; 31-Second gate dielectric layer; 320-Gate material layer; 32-Second gate; 4-Gate lead-out electrode; 5-Bottom semiconductor layer; 6-Buried dielectric layer; 7-Source lead-out electrode; 8-Drain lead-out electrode. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0041] It should be understood that although the terms "first" and "second" may be used to describe various elements, components, areas, layers, collector structures, and / or portions, these elements, components, areas, layers, collector structures, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, collector structure, or portion from another element, component, area, layer, collector structure, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, collector structure, or portion discussed below may be referred to as a second element, component, area, layer, or portion; for example, the first collector structure may be referred to as the second collector structure, and similarly, the second collector structure may be referred to as the first collector structure; the first collector structure and the second collector structure are different collector structures. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the devices in the figures are flipped, elements or features described as "below" or "under" or "beneath" other elements or features will be oriented "on" other elements or features. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] With the continuous development and progress of semiconductor technology, semiconductor devices have become an indispensable and important electronic component in modern industry. The trench structure applied on silicon-on-insulator (SOI) substrate material is mainly used to achieve mutual isolation between different devices or functional modules. The filling medium of the trench is usually an insulating oxide or a low-doped or undoped polysilicon, and the trench is usually adopted with a scheme of not leading out or leading out and grounding.

[0044] In semiconductor device applications, the specific on-resistance determines the device's power consumption and even the overall chip's energy consumption. To reduce the specific on-resistance and increase the on-state current of semiconductor devices, current technologies employ conventional electric field optimization techniques such as surface field reduction, superjunction technology, and field plate technology. However, due to the "silicon limit," these techniques have an upper limit on their performance improvement for semiconductor devices.

[0045] Based on this, this application provides a semiconductor structure and its fabrication method, which can reduce the specific on-resistance of semiconductor devices and increase the on-state conduction current, thereby improving the performance of semiconductor devices. Details will be described in subsequent embodiments.

[0046] It should be noted that in the embodiments of this application, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type. The following description uses N-type as the first conductivity type and P-type as the second conductivity type as an example.

[0047] Please see Figure 1 This application provides a semiconductor structure according to some embodiments. The semiconductor structure includes: a substrate 1, a first gate dielectric layer 21, a first gate 22, a second gate dielectric layer 31, a second gate 32, and a gate lead-out electrode 4. The substrate 1 includes a well region 11 of a first conductivity type. A trench 111 is formed within the well region 11. The first gate dielectric layer 21 at least covers the sidewalls of the trench 111. The thickness of the first gate dielectric layer 21 at the top of the trench 111 is greater than its thickness at the bottom of the trench 111. The first gate 22 covers the surface of the first gate dielectric layer 21 away from the well region 11 and fills the trench 111. The second gate dielectric layer 31 is located on the surface of the well region 11. The second gate 32 is located on the surface of the second gate dielectric layer 31 away from the well region 11. The gate lead-out electrode 4 is electrically connected to both the first gate 22 and the second gate 32.

[0048] In the aforementioned semiconductor structure, in addition to the second gate dielectric layer 31 and the second gate 32 located on the surface of the well region 11 of the substrate 1, a first gate dielectric layer 21 and a first gate 22 are sequentially disposed within the trench 111 of the well region 11. The thickness of the first gate dielectric layer 21 at the top of the trench 111 is greater than its thickness at the bottom of the trench 111. By using the gate lead-out electrode 4 to lead out the first gate 22 and the second gate 32 together, the threshold voltages of the first gate 22 and the second gate 32 can be made consistent, which means that the first gate 22 and the second gate 32 within the trench 111 can be turned on simultaneously. Thus, when the device corresponding to this semiconductor structure is turned on, the first gate dielectric layer 21 on the sidewall of the trench 111 and the first gate 22 within the trench 111 will form a new conduction path along the sidewall of the trench 111 near the trench 111 under the influence of the potential difference. The newly added current conduction path along the sidewall of trench 111 can significantly increase the on-state conduction current of the semiconductor device without changing the device's withstand voltage, thereby increasing the device's current density and reducing the device's specific on-resistance, and thus improving the performance of the semiconductor device.

[0049] Furthermore, the aforementioned semiconductor structure can be combined with electric field optimization techniques (such as surface field technology, superjunction technology, field plate technology, etc.) to further improve the performance of semiconductor devices.

[0050] In some embodiments, the first gate dielectric layer 21 and the second gate dielectric layer 31 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the first gate dielectric layer 21 and the second gate dielectric layer 31 may comprise dielectric materials with generally higher dielectric constants having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment, the first gate dielectric layer 21 and the second gate dielectric layer 31 are gate oxide layers.

[0051] In some embodiments, the material of the first gate 22 includes doped polysilicon. Exemplarily, the material of the first gate 22 includes heavily doped polysilicon. This further ensures that the first gate 22 and the second gate 32 are simultaneously turned on. At this time, the heavily doped polysilicon (i.e., the first gate 22) in the trench 111 and the first gate dielectric layer 21 on the trench sidewall form a conduction path along the trench sidewall under the influence of the potential difference. This further ensures a significant increase in the on-state conduction current and a reduction in the specific on-resistance while substantially maintaining the device's breakdown voltage.

[0052] In some examples, heavily doped polysilicon includes P-type doped polysilicon.

[0053] In some examples, the doping concentration of the heavily doped polysilicon is 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 For example, the doping concentration of heavily doped polycrystalline silicon can be 1×10⁻⁶. 18 cm -3 5×10 18 cm -3 1×10 19 cm -3 5×10 19 cm -3 Or 1×10 20 cm -3 etc.

[0054] In some embodiments, the doped polysilicon of the first gate 22 has a lower ion concentration at the top of the trench 111 and a higher ion concentration at the bottom of the trench 111. Further, the doping concentration of the doped polysilicon gradually increases from the top to the bottom of the trench 111.

[0055] In some embodiments, please continue reading Figure 1The semiconductor structure also includes a bottom semiconductor layer 5 and a buried dielectric layer 6. The buried dielectric layer 6 is located on the bottom semiconductor layer 5, and the substrate 1 is located on the surface of the buried dielectric layer 6 away from the bottom semiconductor layer 5. The bottom of the trench 111 extends to the buried dielectric layer 6. The bottom semiconductor layer 5, the buried dielectric layer 6, and the silicon (Si) substrate together constitute a silicon-on-insulator (SOI) structure. Figure 1 In the embodiment shown, the bottom of the first gate 22 is in direct contact with the buried dielectric layer 6.

[0056] It should be noted that, compared to dual-gate semiconductor devices formed on ordinary silicon substrates, the SOI-based dual-gate semiconductor devices of this application have better parasitic parameters, smaller isolation area under the same voltage application range, and superior performance in terms of high temperature resistance and radiation resistance.

[0057] In some embodiments, please continue reading Figure 1 Trench 111 penetrates substrate 1, and the bottom of trench 111 extends to buried dielectric layer 6. In some examples, the thickness of substrate 1 is less than 10 micrometers. In some examples, the thickness of substrate 1 is greater than 10 micrometers. In some examples, the thickness of substrate 1 is greater than 20 micrometers.

[0058] In some embodiments, please continue reading Figure 1 The semiconductor structure further includes: a drift region 112 of a first conductivity type, a body region 113 of a second conductivity type, a source region 114, a drain region 115, a source region lead-out electrode 7, and a drain region lead-out electrode 8. The drift region 112 of the first conductivity type is located within the well region 11 and is situated on the side of the second gate 32 away from the first gate 22, with a gap between them. The body region 113 of the second conductivity type is located within the well region 11 and is situated between the second gate 32 and the first gate 22. The source region 114 is located within the body region 113. The drain region 115 is located within the drift region 112. The source region lead-out electrode 7 is electrically connected to the source region 114. The drain region lead-out electrode 8 is electrically connected to the drain region 115.

[0059] In some embodiments, please continue reading Figure 1 The source region 114 includes a first source diffusion region 1141 of a first conductivity type, a second source diffusion region 1142 of a second conductivity type, and a third source diffusion region 1143 of a first conductivity type, arranged sequentially from the second gate 32 away from the second gate 32. The drain region 115 includes a drain region of the second conductivity type.

[0060] In some examples, the first source diffusion region 1141 and the third source diffusion region 1143 of the first conductivity type can both be heavily doped (e.g., N+) regions of the first conductivity type. The second source diffusion region 1142 and the drain region of the second conductivity type can both be heavily doped (e.g., P+) regions of the second conductivity type.

[0061] In some embodiments, the thickness of the first gate dielectric layer 21 gradually decreases from the top of the trench 111 to the bottom of the trench 111.

[0062] In some embodiments, the thickness of the first gate dielectric layer 21 gradually and uniformly decreases from the top of the trench 111 to the bottom of the trench 111.

[0063] Some embodiments of this application also provide a method for fabricating a semiconductor structure, used to fabricate the semiconductor structure described in the foregoing embodiments. Please refer to... Figure 2 and combined Figure 1 It is understood that the method for fabricating a semiconductor structure includes steps S100 to S600.

[0064] S100, Obtain a substrate, the substrate including a well region of a first conductivity type.

[0065] S200 forms a trench within the trap area.

[0066] S300, forming a first gate dielectric layer that at least covers the sidewalls of the trench; the thickness of the first gate dielectric layer at the top of the trench is greater than its thickness at the bottom of the trench.

[0067] S400, a first gate is formed in a trench in which a first gate dielectric layer is formed.

[0068] S500 forms a second gate dielectric layer on the surface of the well region.

[0069] S600, a second gate is formed on the surface of the second gate dielectric layer away from the well region.

[0070] S700 forms a gate lead-out electrode, which is electrically connected to both the first gate and the second gate.

[0071] In the above-described semiconductor structure fabrication method, in addition to the second gate dielectric layer 31 and the second gate 32 located on the surface of the well region 11 of the substrate 1, a first gate dielectric layer 21 and a first gate 22 are sequentially disposed in the trench 111 of the well region 11. The thickness of the first gate dielectric layer 21 at the top of the trench 111 is greater than its thickness at the bottom of the trench 111. By using the gate lead-out electrode 4 to lead out the first gate 22 and the second gate 32 together, the threshold voltages of the first gate 22 and the second gate 32 can be made consistent, ensuring that the first gate 22 and the second gate 32 in the trench 111 can be turned on simultaneously. Thus, when the device corresponding to this semiconductor structure is turned on, the first gate dielectric layer 21 on the sidewall of the trench 111 and the first gate 22 in the trench 111 will form a new conduction path along the sidewall of the trench 111 near the trench 111 under the influence of the potential difference. The newly added current conduction path along the sidewall of trench 111 significantly increases the on-state conduction current of the semiconductor device without substantially changing the device's breakdown voltage, thereby increasing the device's current density and reducing its specific on-resistance, and ultimately improving the semiconductor device's performance. Furthermore, the aforementioned semiconductor structure fabrication method can be combined with electric field optimization techniques (such as surface field technology, superjunction technology, and field plate technology) to further enhance the semiconductor device's performance.

[0072] In some embodiments, step S100 includes: obtaining a wafer having a bottom semiconductor layer, a buried dielectric layer, and a substrate. The buried dielectric layer is located on the bottom semiconductor layer, and the substrate is located on the surface of the buried dielectric layer away from the bottom semiconductor layer.

[0073] In some embodiments, step S200 includes: forming a trench with its bottom extending to the buried medium layer.

[0074] In some embodiments, step S200 includes: trench 111, forming a trench extending through the bottom of substrate 1 to the buried dielectric layer. In some examples, the thickness of substrate 1 is less than 10 micrometers. In some examples, the thickness of substrate 1 is greater than 10 micrometers. In some examples, the thickness of substrate 1 is greater than 20 micrometers.

[0075] In some embodiments, step S300 includes: forming a first gate dielectric layer with a gradually decreasing thickness from the top of the trench to the bottom of the trench using a thermal oxidation process.

[0076] In some embodiments, please refer to Figure 3 Step S400 includes:

[0077] S401, filling the trench with polysilicon, including undoped polysilicon or lightly doped polysilicon.

[0078] S402, ion implantation is performed on polysilicon to increase the doping concentration of polysilicon, and high-temperature push-well is performed to obtain the first gate.

[0079] In some embodiments, please refer to Figure 4 After step S600 and before step S700, the method further includes:

[0080] S651, a drift region of a first conductivity type is formed in the well region. The drift region is located on the side of the second gate away from the first gate and has a gap with the second gate.

[0081] S652, a body region of a second conductivity type is formed in the well region, the body region being located between the second gate and the first gate.

[0082] S653 forms a drain region within the drift region and a source region within the volume region.

[0083] In some embodiments, while forming the gate electrode in step S700, a source electrode and a drain electrode are also formed. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region.

[0084] In some embodiments, please refer to Figure 5 Step S653 includes:

[0085] S6531 forms an ion implantation region of the first conductivity type within the bulk region and a drain region within the drift region.

[0086] S6532, ion implantation of a second conductivity type is performed in the ion implantation region to form a second source diffusion region of the second conductivity type, and the ion implantation region is divided into a first source diffusion region of the first conductivity type and a third source diffusion region of the first conductivity type; the first source diffusion region, the second source diffusion region and the third source diffusion region together constitute the source region.

[0087] It should be understood that, although Figures 2 to 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 2 to 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0088] To more clearly illustrate the semiconductor structure fabrication method provided in the embodiments of this application, the following is combined with... Figure 1 as well as Figures 6 to 15Some possible implementations of the method for fabricating this semiconductor structure are described in detail.

[0089] In step S100, please refer to Figure 6 A wafer having a bottom semiconductor layer 5, a buried dielectric layer 6, and a substrate 1 is obtained. The buried dielectric layer 6 is located on the bottom semiconductor layer 5, and the substrate 1 is located on the surface of the buried dielectric layer 6 away from the bottom semiconductor layer 5.

[0090] In some examples, the bottom semiconductor layer 5 can be a silicon layer. The buried dielectric layer 6 includes an oxide layer, such as a silicon oxide layer.

[0091] In some examples, substrate 1 includes a well region 11 of a first conductivity type.

[0092] In some examples, substrate 1 can be a silicon (Si) substrate. The bottom semiconductor layer 5, the buried dielectric layer 6, and the silicon (Si) substrate together constitute a silicon-on-insulator (SOI) structure.

[0093] It should be noted that, compared to dual-gate semiconductor devices formed on ordinary silicon substrates, the SOI-based dual-gate semiconductor devices of this application have better parasitic parameters, smaller isolation area under the same voltage application range, and superior performance in terms of high temperature resistance and radiation resistance.

[0094] In some examples, a well region 11 of a first conductivity type can be obtained by implanting ions of a first conductivity type into the substrate 1.

[0095] In step S200, please refer to Figures 7(a) to 7(d) The trench 111 formed in the trap area 11 includes forming a trench 111 whose bottom extends to the burial medium layer 6.

[0096] In some examples, forming a trench 111 within the trap region 11 includes:

[0097] Please refer to Figure 7(a), where an etching barrier material layer 120 is formed on the surface of the trap region 11 away from the buried medium layer 6 using physical vapor deposition or chemical vapor deposition processes;

[0098] Please refer to Figure 7(b) to perform the coating, exposure and development of photoresist 13, and expose and remove the photoresist 13 that is needed to form the trench 111 area;

[0099] Please refer to Figure 7(c), an etch barrier layer 120 is formed by etching the photoresist 13;

[0100] Please refer to Figure 7(d), where the trench 111 is formed in the well region 11 by reactive ion etching based on the etch barrier layer 12.

[0101] In step S300, please refer to Figure 8 A first gate dielectric layer 21 with gradually decreasing thickness from the top to the bottom of trench 111 is formed using a thermal oxidation process. A thermal oxide layer is formed in trench 111 by means of thermal oxidation, etc. Because the concentration of oxidizing gas is different between the top and bottom of trench 111, the thermal oxide layer at the top of trench 111 is thicker.

[0102] In step S401, please refer to Figure 9 and Figure 10 The trench 111 is filled with polysilicon 220, which includes undoped polysilicon or lightly doped polysilicon.

[0103] In some examples, a deposition process can be used to fill the trench 111 with polysilicon 220. And, as... Figure 10 As shown, the excess polysilicon 220 on the top of the etch barrier layer 12 and the trench 111 is removed and planarized using processes such as wet polishing.

[0104] In step S402, please refer to Figure 11 Ion implantation is performed on polysilicon 220 to increase the doping concentration of polysilicon, and high-temperature push-well is performed to obtain the first gate 22.

[0105] For example, photoresist 131 is used as a barrier layer to perform impurity ion implantation and high-temperature push-well on polysilicon 220 within trench 111. Because the thickness of the first gate dielectric layer 21 differs at the top and bottom of trench 111, special optimization of ion implantation is required to ensure that the first gate 22 at trench 111 can be turned on simultaneously with the subsequently formed second gate when the device operates. This involves performing multiple implantations at different energies and adjusting the impurity ion implantation concentration for each implantation, resulting in a lower ion concentration at the top of trench 111 and a higher ion concentration at the bottom. Furthermore, the doping concentration of polysilicon 220 gradually increases from the top to the bottom of trench 111. The corresponding ion implantation combinations also need to be adjusted for different threshold voltage requirements to achieve flexible adjustment of device performance. In addition, the subsequent high-temperature push-well thermal process also needs to be coordinated with the impurity ion implantation to meet design requirements. Figure 11 In the diagram, arrows indicate the implantation of impurity ions.

[0106] This application increases the doping concentration of polysilicon 220 by first filling trench 111 with undoped or lightly doped polysilicon, and then performing ion implantation and high-temperature push-in on the polysilicon 220, thus obtaining the first gate 22. This facilitates the adjustment of different doping concentrations of the first gate 22 from the top to the bottom of trench 111 to match the gradually decreasing thickness of the first gate dielectric layer 21 from the top to the bottom of trench 111. This further ensures that the first gate 22 and the second gate 32 are turned on simultaneously, thereby significantly increasing the on-state conduction current and reducing the specific on-resistance while essentially maintaining the device breakdown voltage.

[0107] In steps S500 and S600, please refer to Figure 12 and Figure 13 A second gate dielectric layer 31 is formed on the surface of the well region 11. A second gate 32 is formed on the surface of the second gate dielectric layer 31 away from the well region 11.

[0108] In some examples, forming a second gate dielectric layer 31 on the surface of the well region 11 and forming a second gate 32 on the surface of the second gate dielectric layer 31 away from the well region 11 includes:

[0109] Please see Figure 12 A gate oxide material layer 310 is formed on the surface of the well region 11, the first gate dielectric layer 21 and the first gate 22 by a thermal oxidation process; a gate material layer 320 is formed on the surface of the gate oxide material layer 310 by a deposition process.

[0110] Please see Figure 13 Photolithography and reactive ion etching are performed on the gate material layer 320 and the gate oxide material layer 310 to obtain the second gate 32 and the second gate dielectric layer 31.

[0111] In step S651, please refer to Figure 14 A drift region 112 of a first conductivity type is formed in the well region 11. The drift region 112 is located on the side of the second gate 32 away from the first gate 33 and has a gap with the second gate 32.

[0112] In some examples, an ion implantation process can be used to form a drift region 112 of a first conductivity type within the trap region 11.

[0113] In step S652, please refer to... Figure 14 A body region 113 of a second conductivity type is formed in the well region 11, and the body region 113 is located between the second gate 32 and the first gate 22.

[0114] In some examples, an ion implantation process can be used to form a body region 113 of a second conductivity type within the well region 11.

[0115] In step S6531, please refer to Figure 15 An ion implantation region of the first conductivity type is formed in the body region 113, and a drain region 115 is formed in the drift region 112.

[0116] In step S6532, please refer to... Figure 15 Ions of a second conductivity type are implanted in the ion implantation region to form a second source diffusion region 1142 of the second conductivity type, and the ion implantation region is divided into a first source diffusion region 1141 of the first conductivity type and a third source diffusion region 1143 of the first conductivity type; the first source diffusion region 1141, the second source diffusion region 1142 and the third source diffusion region 1143 together constitute the source region 114.

[0117] In step S700, please refer to Figure 1 A gate electrode 4 is formed, which is electrically connected to both the first gate 22 and the second gate 32. Simultaneously with forming the gate electrode 4 in step S700, a source electrode 7 and a drain electrode 8 are also formed. The source electrode 7 is electrically connected to the source region 114. The drain electrode 8 is electrically connected to the drain region 115.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a well region of a first conductivity type; The well region has trenches; A first gate dielectric layer covers at least the sidewalls of the trench, and the thickness of the first gate dielectric layer at the top of the trench is greater than its thickness at the bottom of the trench. A first gate covers the surface of the first gate dielectric layer away from the well region; A second gate dielectric layer is located on the surface of the well region; The second gate is located on the surface of the second gate dielectric layer away from the well region; The gate lead-out electrode is electrically connected to both the first gate and the second gate.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the first gate includes doped polycrystalline silicon.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: Bottom semiconductor layer; A buried dielectric layer is located on the bottom semiconductor layer, and the substrate is located on the surface of the buried dielectric layer away from the bottom semiconductor layer; The bottom of the first gate is in direct contact with the buried dielectric layer.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: A drift region of the first conductivity type is located within the well region and on the side of the second gate away from the first gate, and is spaced apart from the second gate; A body region of the second conductivity type is located within the well region and between the second gate and the first gate; The source region is located within the body region; The leak region is located within the drift region; An electrode is led out from the source region and electrically connected to the source region; An electrode is led out from the drain region and electrically connected to the drain region.

5. The semiconductor structure as described in claim 4, characterized in that, The source region includes a first source diffusion region of a first conductivity type, a second source diffusion region of a second conductivity type, and a third source diffusion region of a first conductivity type arranged sequentially from the second gate away from the second gate. The drain region includes a drain region of the second conductivity type.

6. The semiconductor structure as described in claim 2, characterized in that, From the top to the bottom of the trench, the thickness of the first gate dielectric layer gradually decreases, and / or the doping concentration of the doped polysilicon gradually increases.

7. A method for fabricating a semiconductor structure, characterized in that, include: Obtain a substrate, the substrate comprising a well region of a first conductivity type; A trench is formed within the well region; A first gate dielectric layer is formed that at least covers the sidewalls of the trench; The thickness of the first gate dielectric layer at the top of the trench is greater than its thickness at the bottom of the trench; A first gate is formed within a trench in which the first gate dielectric layer is formed; A second gate dielectric layer is formed on the surface of the well region; A second gate is formed on the surface of the second gate dielectric layer away from the well region; A gate lead-out electrode is formed, which is electrically connected to both the first gate and the second gate.

8. The method for preparing a semiconductor structure as described in claim 7, characterized in that, The step of forming the first gate in the trench where the first gate dielectric layer is formed includes: The trench is filled with polysilicon, which includes undoped polysilicon or lightly doped polysilicon. The polysilicon is subjected to ion implantation to increase the doping concentration, and then subjected to high-temperature push-in to obtain the first gate.

9. The method for preparing a semiconductor structure as described in claim 8, characterized in that, The step of forming a first gate dielectric layer that at least covers the sidewalls of the trench includes: forming a first gate dielectric layer with a gradually decreasing thickness from the top to the bottom of the trench using a thermal oxidation process; and / or The step of ion implanting the polysilicon to increase the doping concentration of the polysilicon includes performing multiple ion implantations of different energies, such that the doping concentration of the polysilicon of the first gate gradually increases from the top of the trench to the bottom of the trench.

10. The method for preparing the semiconductor structure according to claim 7, characterized in that, The step of obtaining the substrate includes: obtaining a wafer having a bottom semiconductor layer, a buried dielectric layer and the substrate, wherein the buried dielectric layer is located on the bottom semiconductor layer and the substrate is located on the surface of the buried dielectric layer away from the bottom semiconductor layer; The step of forming a trench within the trap area includes: forming the trench with its bottom extending to the burial medium layer.

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