Display panel, display device and tiled display device

Abstract

The invention discloses a display panel, a display device and a tiled display device. The display panel comprises a substrate and a plurality of connecting leads. The substrate comprises a first surface, a second surface and at least one side face, the first surface and the second surface are oppositely arranged, the at least one side face is connected with the first surface and the second surface, and the at least one side face is a selected side face. Each of the plurality of connection leads extends from the first surface to the second surface through the selected side surface. The plurality of connecting leads comprise a first connecting lead and a second connecting lead, and the first connecting lead and the second connecting lead are adjacent and arranged on different layers in the direction perpendicular to the surface of the substrate. The display panel is used for displaying images.

Description

Display panel, display device, and spliced ​​display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a spliced ​​display device. Background Art

[0002] The use of micro light-emitting diodes (Micro LEDs) or sub-millimeter light-emitting diodes (Mini LEDs) as pixels in display panels has attracted widespread attention and research. Currently, due to the massive transfer yield issues of Micro LED and Mini LED display panels, large-scale display devices cannot be produced in one go. Instead, a large-scale spliced ​​display device is typically assembled by splicing together smaller display devices.

[0003] Summary of the Invention

[0004] In one aspect, a display panel is provided, including a substrate and a plurality of connecting leads.

[0005] The substrate includes a first surface and a second surface that are opposite to each other, and at least one side surface connecting the first surface and the second surface, wherein the at least one side surface is a selected side surface.

[0006] Each of the plurality of connecting leads extends from the first surface, through the selected side surface, to the second surface.

[0007] The plurality of connection leads include a first connection lead and a second connection lead, wherein the first connection lead and the second connection lead are adjacent to each other in a direction perpendicular to the surface of the substrate and are arranged in different layers.

[0008] In some embodiments, the orthographic projections of the first connecting lead and the second connecting lead on the substrate at least partially overlap.

[0009] In some embodiments, the first connecting wire and the second connecting wire have different line widths.

[0010] In some embodiments, the first connecting lead and the second connecting lead transmit different signals.

[0011] In some embodiments, one of the first connecting lead and the second connecting lead is in contact with a surface of the substrate.

[0012] In some embodiments, the display panel further includes a plurality of front electrodes and a plurality of back electrodes.

[0013] A plurality of front electrodes are arranged on one side of the first surface of the substrate. The plurality of front electrodes include a first electrode and a second electrode. The first electrode and the second electrode are arranged adjacent to each other.

[0014] A plurality of back electrodes are arranged on one side of the second surface of the substrate, and the plurality of back electrodes include a third electrode and a fourth electrode, and the third electrode and the fourth electrode are arranged adjacent to each other.

[0015] The first connecting lead is used to connect the first electrode and the third electrode; the second connecting lead is used to connect the second electrode and the fourth electrode.

[0016] The orthographic projections of the first electrode and the third electrode on the second surface at least partially overlap, and the orthographic projections of the second electrode and the fourth electrode on the second surface at least partially overlap.

[0017] In some embodiments, the first electrode and the second electrode are disposed in the same layer, and / or the third electrode and the fourth electrode are disposed in the same layer.

[0018] In some embodiments, one of the first connecting lead and the second connecting lead is directly connected to the front electrode and the back electrode, and the other is connected to the front electrode and the back electrode through a via.

[0019] In some embodiments, the first electrode and the second electrode are arranged in different layers, and the first electrode is closer to the first surface than the second electrode.

[0020] And / or, the third electrode and the fourth electrode are arranged in different layers, and the third electrode is closer to the second surface than the fourth electrode.

[0021] In some embodiments, the first connecting lead is closer to the substrate than the second connecting lead.

[0022] In some embodiments, the orthographic projection of the first electrode on the first surface at least partially overlaps with the orthographic projection of the second electrode on the first surface.

[0023] And / or, the orthographic projection of the third electrode on the second surface at least partially overlaps with the orthographic projection of the fourth electrode on the second surface.

[0024] In some embodiments, the display panel further comprises a plurality of pixel units located on the first surface, wherein the plurality of pixel units include two pixel units adjacent to each other in the first direction and both close to the selected side surface, and the first electrode and the second electrode are disposed between the two pixel units.

[0025] In some embodiments, the display panel further includes a plurality of pixel units located on the first surface, wherein the plurality of pixel units include two pixel units that are adjacent in the first direction and are both close to the selected side surface.

[0026] The first connecting lead and the second connecting lead are arranged between the two pixel units.

[0027] In some embodiments, the display panel further includes a plurality of pixel units located on the first surface, wherein the plurality of pixel units include two pixel units that are adjacent in the first direction and are both close to the selected side surface.

[0028] In the second direction, the first electrode and the second electrode at least partially overlap with the two pixel units. The second direction is perpendicular to the first direction.

[0029] In some embodiments, the display panel further includes a first insulating layer, wherein the first insulating layer is located between the first connecting lead and the second connecting lead.

[0030] In some embodiments, the display panel further includes at least one recessed area located at least on a selected side surface of the substrate.

[0031] The one of the first connecting lead and the second connecting lead that is closer to the substrate has an orthographic projection on the selected side surface located within the recessed area.

[0032] In some embodiments, a ratio of a size of the recessed area along the first direction to a size of the first connecting lead along the first direction is 1-2.

[0033] In some embodiments, the display panel further includes a protective layer that covers at least the second connecting lead, and the front electrode and the back electrode connected to the second connecting lead.

[0034] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments and a circuit board, wherein the circuit board is electrically connected to the display panel and configured to drive the display panel to display an image.

[0035] In yet another aspect, a spliced ​​display device is provided, comprising a plurality of display panels according to any one of the above embodiments and at least one circuit board.

[0036] A plurality of the display panels are spliced ​​together, and each of the at least one circuit board is electrically connected to at least one of the display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0038] FIG1 is a structural diagram of a spliced ​​display device according to some embodiments;

[0039] FIG2 is a structural diagram of a display device according to some embodiments;

[0040] FIG3 is a cross-sectional view of the display panel along section line BB in FIG2 ;

[0041] FIG4 is a structural diagram of a local area of ​​a display panel according to some embodiments;

[0042] FIG5A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0043] FIG5B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0044] FIG6 is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0045] FIG7 is a structural diagram of a display panel according to some embodiments;

[0046] FIG8A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0047] FIG8B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0048] FIG9A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0049] FIG9B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0050] FIG9C is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0051] FIG9D is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0052] FIG10A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0053] FIG10B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0054] FIG10C is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0055] FIG10D is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0056] FIG11A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0057] FIG11B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0058] FIG12A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0059] FIG12B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0060] FIG13A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0061] FIG13B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0062] FIG13C is a cross-sectional view of the display panel in FIG12A along section line HH;

[0063] FIG13D is another cross-sectional view of the display panel in FIG12A along section line HH;

[0064] FIG13E is another cross-sectional view of the display panel in FIG12A along section line HH;

[0065] FIG14A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0066] FIG14B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0067] FIG15A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0068] FIG15B is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0069] FIG15C is another structural diagram of a partial area of ​​a display panel according to some embodiments;

[0070] FIG16 is a cross-sectional view of the display panel along section line GG in FIG15A ;

[0071] FIG17 is another cross-sectional view of the display panel along section line GG in FIG15A ;

[0072] FIG18 is a cross-sectional view of a local area of ​​a display panel according to some embodiments;

[0073] FIG19A is another structural diagram of a partial area of ​​a display panel according to some embodiments;

[0074] FIG19B is another structural diagram of a partial area of ​​a display panel according to some embodiments;

[0075] FIG20A is another structural diagram of a local area of ​​a display panel according to some embodiments;

[0076] FIG. 20B is another structural diagram of a local area of ​​a display panel according to some embodiments. DETAILED DESCRIPTION

[0077] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0078] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0079] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0080] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0081] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0082] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0083] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0084] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0085] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0086] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0087] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0088] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0089] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0090] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the spliced ​​display device or the display device. The XY plane is perpendicular to the Z direction. The first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0091] As shown in FIG1 , some embodiments of the present disclosure provide a spliced ​​display device 1000 comprising a plurality of spliced ​​display panels 10 and at least one circuit board (not shown). Each circuit board is electrically connected to at least one display panel 10 and is configured to control the light emission of the display panel 10 to implement the display function of the display panel 10.

[0092] By splicing a plurality of display panels 10 to form a large-sized spliced ​​display device 1000 , product reliability can be improved, and transportation costs and maintenance costs can be reduced.

[0093] For example, the number of circuit boards in the spliced ​​display device 1000 may be one, and the multiple display panels 10 are connected to the same circuit board.

[0094] The number of circuit boards may also be multiple. For example, each display panel 10 in a plurality of display panels 10 is connected to a circuit board, that is, the display panels 10 and the circuit boards are connected one-to-one. For another example, the plurality of display panels 10 are divided into multiple groups, and each group of display panels 10 is connected to a circuit board, wherein the number of display panels 10 in each group of display panels 10 may be the same or different.

[0095] Illustratively, the circuit board includes but is not limited to a PCB (Printed Circuit Board) and an FPC (Flexible Printed Circuit Board).

[0096] As shown in FIG. 2 , some embodiments of the present disclosure further provide a display device 100 . The display device 100 may be an independent display device, or may be used to splice together to form the spliced ​​display device 1000 .

[0097] For example, the display device 100 can be any product or component with a display function, such as a television, a monitor, a laptop computer, a tablet computer, a mobile phone, a navigator, etc. FIG2 illustrates the display device 100 as a mobile phone.

[0098] Exemplarily, the display device 100 may be a micro light-emitting diode display device (Micro Light-emitting Diode, referred to as Micro LED) or a sub-millimeter light-emitting diode display device (Mini Light-emitting Diode, referred to as Mini LED).

[0099] The display device 100 may also be an electroluminescent display device or a photoluminescent display device. If the display device 100 is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device 100 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0100] 2 , the display device 100 includes a display panel 10 and a circuit board (not shown). The circuit board is electrically connected to the display panel 10 and is configured to drive the display panel 10 to display images.

[0101] The display panel 10 is described in detail below.

[0102] The display panel 10 may be a Micro LED display panel, a Mini LED display panel, or an OLED display panel.

[0103] For example, when the display panel 10 is a Micro LED display panel or a Mini LED display panel, the Micro LED display panel or the Mini LED display panel includes: an array substrate and micro light emitting diodes or sub-millimeter light emitting diodes located on the array substrate.

[0104] For another example, when the display panel 10 is an OLED display panel, the OLED display panel includes: an array substrate and a pixel defining layer located on the array substrate, wherein an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer and a cathode are sequentially arranged in the pixel defining area of ​​the pixel defining layer.

[0105] The following uses the display panel 10 as a Micro LED display panel or a Mini LED display panel as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation methods of the present disclosure include but are not limited to this, and any other display panels can also be considered as long as the same technical concept is applied.

[0106] Exemplarily, the display panel 10 may be a rectangular structure, a circular structure, or other shapes with corners, which is not specifically limited in the present disclosure.

[0107] It should be noted that the aforementioned "rectangular structure" means that the shape of the boundary of the display panel 10 is rectangular as a whole, but is not limited to a standard rectangle. That is, the "rectangle" here includes not only a standard rectangular shape, but also a shape similar to a rectangle taking into account process conditions. For example, the long and short sides of the rectangle are curved at each intersection (i.e., at the corners), that is, the corners are smooth, so that the shape of the boundary of the display panel 10 in a plan view is a rounded rectangle.

[0108] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 10 as a rectangular structure as an example. However, the embodiments of the present disclosure include but are not limited to this. The shape of the display panel 10 may also be any other shape.

[0109] In some embodiments, as shown in Figure 3, which is a cross-sectional view of the display panel 10 along the section line BB in Figure 2, the display panel 10 has a display area AA for displaying images and a peripheral area AN located on at least one side of the display area AA.

[0110] For example, the peripheral area AN is located at one side of the display area AA.

[0111] For another example, the peripheral area AN is located on two opposite sides of the display area AA.

[0112] For another example, the peripheral area AN surrounds the display area AA.

[0113] It should be noted that the specific configuration of the peripheral area AN is related to the specific design of the display panel 10 and can be designed according to actual needs. It is only used as an example here and is not intended to limit the present disclosure.

[0114] In some embodiments, as shown in FIG3 , a plurality of pixel units P are provided in the display area AA of the display panel 10 . Each pixel unit P includes at least three sub-pixels 3 of three colors. The sub-pixel 3 is the smallest pixel unit in the display area AA.

[0115] The above “each pixel unit P includes at least three colors of sub-pixels 3” means that each pixel unit P may include three, four or more sub-pixels 3, and the multiple sub-pixels 3 included in each pixel unit P may be a row, a column or a group of sub-pixels 3, a group of sub-pixels 3 may be multiple sub-pixels 3 adjacent to each other, and the multiple adjacent sub-pixels 3 are arranged in a row, a column, an L-shape, a rectangle or a diamond, etc. At the same time, the luminous areas of the multiple sub-pixels 3 included in each pixel unit P may be the same or different. The above is only an exemplary description and is not intended to limit the present disclosure. Adaptive design can be carried out according to actual needs.

[0116] In some examples, the multiple sub-pixels 3 emit light of the same color, and the display panel 10 may further include a color filter layer disposed on the light-emitting sides of the multiple sub-pixels 3 .

[0117] For example, multiple sub-pixels 3 emit white light, red light, green light, blue light or other color light. In this case, the color light emitted by the sub-pixel 3 remains the same color light after passing through the color filter layer, or is converted into other color light and emitted. Therefore, when multiple sub-pixels 3 emit the same color light, the display panel 10 can achieve multi-color light output.

[0118] In other examples, multiple sub-pixels 3 emit light of different colors. For example, multiple sub-pixels 3 include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, thereby realizing multi-color light output of the display panel 10.

[0119] Exemplarily, the pixel unit P includes a driving component and a light-emitting component. For example, the driving component may include a thin film transistor, and the light-emitting component may include a miniLED or a microLED.

[0120] Exemplarily, the plurality of pixel units P are arranged in a plurality of rows and columns, that is, the plurality of pixel units P are arrayed along the first direction X and the second direction Y, respectively.

[0121] In some embodiments, the peripheral area AN of the display panel 10 may be used to dispose peripheral circuits and signal lines of the display area AA.

[0122] In some embodiments, referring to FIG. 3 , the display panel 10 further includes a substrate 1. The substrate 1 includes a first surface 1a and a second surface 1b disposed opposite each other, and at least one side surface 1c connecting the first surface 1a and the second surface 1b. The aforementioned pixel units P are disposed on the first surface 1a of the substrate 1.

[0123] Illustratively, the material of substrate 1 can be a rigid material. For example, the material of substrate 1 includes, but is not limited to, glass, quartz, plastic, etc. The material of substrate 1 can also be a flexible material. For example, the material of substrate 1 includes, but is not limited to, FPC, PI-based film (Polyimide Film), etc.

[0124] It should be noted that the material selection of the substrate 1 is related to the specific design of the display panel 10 and can be selected according to actual needs. It is only used as an example here and is not intended to limit the present disclosure.

[0125] Exemplarily, as shown in FIG3 , the side surface 1 c is perpendicular or substantially perpendicular to the first surface 1 a and the second surface 1 b .

[0126] 3 , the substrate 1 further includes a first chamfered surface 1d and a second chamfered surface 1e. The first chamfered surface 1d connects the first surface 1a of the substrate 1 and the side surface 1c of the substrate 1, and the second chamfered surface 1e connects the second surface 1b of the substrate 1 and the side surface 1c of the substrate 1.

[0127] For example, the first chamfered surface 1d and the second chamfered surface 1e can be arranged as arc surfaces or as inclined surfaces. FIG3 only illustrates the example that the first chamfered surface 1d and the second chamfered surface 1e can be arranged as arc surfaces.

[0128] For example, when the first chamfered surface 1d of the substrate 1 is an arc surface, the first surface 1a can smoothly transition from the first chamfered surface 1d to the side surface 1c, or the side surface 1c can smoothly transition from the first chamfered surface 1d to the first surface 1a.

[0129] Similarly, when the second chamfered surface 1e of the substrate 1 is also configured as an arc, the second surface 1b can smoothly transition from the second chamfered surface 1e to the side surface 1c, or the side surface 1c can smoothly transition from the second chamfered surface 1e to the second surface 1b.

[0130] For another example, when the first chamfered surface 1d of the substrate 1 is arranged in an inclined surface, the angle between the first chamfered surface 1d and the first surface 1a of the substrate 1 and the angle between the first chamfered surface 1d and the side surface 1c of the substrate 1 are both obtuse angles, and the first surface 1a can be relatively smoothly transitioned from the first chamfered surface 1d to the side surface 1c, or the side surface 1c can be relatively smoothly transitioned from the first chamfered surface 1d to the first surface 1a.

[0131] Similarly, when the second chamfered surface 1e of the substrate 1 is also inclined, the second surface 1b can transition relatively smoothly from the second chamfered surface 1e to the side surface 1c, or the side surface 1c can transition relatively smoothly from the second chamfered surface 1e to the second surface 1b.

[0132] Some embodiments of the present disclosure are schematically described below by taking an example where the substrate 1 includes a first surface 1 a , a second surface 1 b , a side surface 1 c , a first chamfered surface 1 d , and a second chamfered surface 1 e .

[0133] In some embodiments, referring to Figures 3 and 4 , the display panel 10 further includes a plurality of connecting leads 2. The plurality of connecting leads 2 are arranged at intervals along a first direction X. On the first surface 1a of the substrate 1, the first direction X is perpendicular to the extending direction (second direction Y) of the connecting leads 2.

[0134] Each of the plurality of connecting leads 2 extends from the first surface 1a of the substrate 1, through the side surface 1c of the substrate 1, to the second surface 1b of the substrate 1. For ease of description, the side surface 1c where the connecting leads 2 are located is collectively referred to as a selected side surface 1cc.

[0135] It should be noted that when the substrate 1 includes multiple side surfaces 1c, the present disclosure does not limit the structure of the other side surfaces 1c (i.e., the side surfaces 1c other than the selected side surface 1cc) among the multiple side surfaces 1c. For example, when the display panel 10 has a rectangular structure, it has four side surfaces 1c. For example, the four side surfaces 1c of the substrate 1 can all be selected side surfaces 1cc; for another example, as shown in FIG3 , one of the four side surfaces 1c of the substrate 1 is the selected side surface 1cc, and the structures of the other three side surfaces 1c are not limited.

[0136] Please continue to refer to Figure 3. It can be understood that when the substrate 1 has a first chamfered surface 1d and a second chamfered surface 1e, each of the multiple connecting leads 2 extends from the first surface 1a of the substrate 1, passes through the first chamfered surface 1d of the substrate 1, the selected side surface 1cc of the substrate 1 and the second chamfered surface 1e of the substrate 1 in sequence, and extends to the second surface 1b of the substrate 1. When multiple connecting leads 2 pass through the first chamfered surface 1d, since the first surface 1a of the substrate 1 can transition relatively smoothly from the first chamfered surface 1d to the selected side 1cc, or the selected side 1cc can transition relatively smoothly from the first chamfered surface 1d to the first surface 1a, compared with the case where the first surface 1a is directly connected to the selected side 1cc (in this case, the angle between the first surface 1a and the selected side 1cc is 90°), in the embodiment of the present disclosure, each connecting lead 2 in the multiple connecting leads 2 is subjected to less stress at the corner between the first surface 1a and the selected side 1cc (i.e., the first chamfered surface 1d), thereby reducing the problem of wire breakage caused by excessive stress concentration. In this way, the multiple connecting leads 2 are not easily broken at the corner between the first surface 1a and the selected side 1cc (i.e., the first chamfered surface 1d), thereby ensuring that the multiple connecting leads 2 can stably connect the relatively arranged first surface 1a and second surface 1b of the substrate 1, thereby improving the stability of the display panel 10.

[0137] Similarly, when multiple connecting leads 2 pass through the second chamfered surface 1e, the stress on each connecting lead 2 in the multiple connecting leads 2 at the corner between the second surface 1b and the selected side surface 1cc (i.e., the second chamfered surface 1e) is relatively small, reducing the problem of wire breakage caused by excessive stress concentration. In this way, the multiple connecting leads 2 are not easily broken at the corner between the second surface 1b and the selected side surface 1cc (i.e., the second chamfered surface 1e), ensuring that the multiple connecting leads 2 can effectively connect the relatively arranged first surface 1a and second surface 1b of the substrate 1, further improving the reliability of the display panel 10.

[0138] In some embodiments, the connecting lead 2 can be prepared by patterning after plating, or can be directly prepared by a printing process.

[0139] Exemplarily, the connecting lead 2 is prepared by a printing process as follows: a conductive paste is set on the first surface 1a, the selected side surface 1cc and the second surface 1b of the substrate 1 (when the substrate 1 includes a first chamfered surface 1d and a second chamfered surface 1e, a conductive paste is also required to be set on the first chamfered surface 1d and the second chamfered surface 1e of the substrate 1), and then the conductive paste is cured by laser or heating to form the connecting lead 2.

[0140] The above-mentioned printing process may include, for example, screen printing, pad printing, transfer printing and printing.

[0141] When the printing process is a printing process, the printing process can be a three-dimensional printing process. Referring to FIG. 4 , the three-dimensional printing process uses a printing needle T of a certain diameter to squeeze the conductive paste in the needle tube to a specific position on the substrate 1 using air pressure. After the conductive paste solidifies, it forms a connecting lead 2.

[0142] The conductive paste may be, for example, silver paste. The silver paste may include silver powder and resin. The silver powder melts at high temperatures, allowing the silver powder and resin to fuse and connect with each other, achieving a conductive effect.

[0143] 3 , the display panel 10 further includes a plurality of front electrodes 4 and a plurality of back electrodes 5. The front electrodes 4 are located on the first surface 1a of the substrate 1, and the back electrodes 5 are located on the second surface 1b of the substrate 1.

[0144] For example, as shown in FIG5A , FIG5A is a structural diagram of a local area of ​​a display panel 10 according to some embodiments of the present disclosure. A plurality of front electrodes 4 are arranged at intervals along a first direction X. A plurality of front electrodes 4 can be provided in the display area AA of the display panel 10, with the boundary of the first surface 1a of the substrate 1 close to the selected side surface 1cc as the first boundary 1aa. In a row of pixel units P closest to the first boundary 1aa, at least one front electrode 4 is located between two adjacent pixel units P, that is, the front electrode 4 and the pixel unit P intersect at the same time with at least one straight line (for example, straight line CC) parallel to the first boundary 1aa, which is conducive to increasing the area ratio of the display area AA on the first surface 1a of the substrate 1, that is, the front electrode 4 does not occupy the area of ​​the peripheral area AN, which can reduce the area ratio of the peripheral area AN of the display panel 10 on the first surface 1a of the substrate 1, narrow the frame to a large extent, and improve the display effect of the display panel 10.

[0145] Alternatively, as shown in FIG5B , FIG5B is a structural diagram of a local area of ​​the display panel 10 according to some embodiments of the present disclosure. A plurality of front electrodes 4 are arranged at intervals along the first direction X. A plurality of front electrodes 4 are located in the peripheral area AN of the display panel 10, and the front electrode 4 is closer to the first boundary 1aa than the pixel unit P. There is no straight line parallel to the first boundary 1aa that intersects the front electrode 4 and the pixel unit P at the same time. In this case, although the area proportion of the peripheral area AN of the display panel 10 on the first surface 1a of the substrate 1 will increase, the front electrode 4 can be set in a larger space. Accordingly, when the shape and size of the front electrode 4 remain unchanged, a larger number of front electrodes 4 can be set, thereby reducing the difficulty of design.

[0146] The following takes the example of multiple front electrodes 4 being located in the display area AA of the display panel 10 to schematically illustrate some embodiments of the present disclosure, but the implementation methods of the present disclosure include but are not limited to this. For example, multiple front electrodes 4 can also be located in the peripheral area AN of the display panel 10.

[0147] For example, as shown in Figure 6, which is a structural diagram of a local area of ​​a display panel 10 according to some embodiments of the present disclosure, a plurality of back electrodes 5 are arranged along a first direction X at intervals.

[0148] In some embodiments, please continue to refer to Figures 3, 5A and 6. One end of each connecting lead 2 of the multiple connecting leads 2 is connected to a front electrode 4 located on the first surface 1a of the substrate 1, and the other end is connected to a back electrode 5 located on the second surface 1b of the substrate 1, which can transfer the binding area of ​​the display panel 10 to the second surface 1b of the display panel 10, thereby reducing the area of ​​the peripheral area AN of the display panel 10, which is beneficial to improving the screen-to-body ratio of the display panel 10.

[0149] Furthermore, the screen-to-body ratio of the display device 100 including the display panel 10 can be increased, which is beneficial for the display device 100 to achieve a narrow frame and enhance the display effect of the display device 100 .

[0150] Furthermore, when the spliced ​​display device 1000 includes multiple display panels 10, taking the example of a peripheral area AN of the display panel 10 being located on one side of the display area AA of the display panel 10, as shown in FIG1 , the multiple display panels 10 are arranged in multiple columns along a first direction X and in multiple rows along a second direction Y. In the spliced ​​multiple display panels 10, the peripheral areas AN of the display panels 10 are all arranged along the first direction X. Thus, among the multiple display panels 10 arranged in a row along the first direction X, there is substantially no splicing seam between two adjacent display panels 10 along the first direction X; whereas, among the multiple display panels 10 arranged in a column along the second direction Y, there is a splicing seam between two adjacent display panels 10. In other words, the size of the splicing seam between two adjacent display panels 10 in the multiple display panels 10 arranged in a row along the first direction X is smaller than the size of the splicing seam between two adjacent display panels 10 in the multiple display panels 10 arranged in a column along the second direction Y.

[0151] When viewing the spliced ​​display device 1000, since the area of ​​the peripheral region AN of the display panel 10 is relatively small, the size of the splicing gap between two adjacent display panels 10 among the multiple display panels 10 arranged in a row along the second direction Y is also relatively small. The splicing gap between two adjacent display panels 10 is difficult to be detected by the naked eye within the viewing distance, thereby making the display image of the spliced ​​display device 1000 more complete and presenting a better display effect.

[0152] With the continuous development of the display panel 10, users have increasingly higher requirements for the refresh rate, brightness, and resolution (Pixels Per Inch, PPI) of the display panel 10. The improvement of the refresh rate, brightness, and resolution (Pixels Per Inch, PPI) of the display panel 10 requires more signals to be transmitted from the circuit board to the AA area of ​​the display panel 10. This can be achieved by increasing the number of connecting leads 2.

[0153] Please continue to refer to Figure 4. When the number of connecting leads 2 increases, the line width K1 of each connecting lead 2 can be reduced, and / or the spacing d1 between two adjacent connecting leads 2 can be reduced to achieve the arrangement of more connecting leads 2 on the substrate 1 (specifically, the first surface 1a, the first chamfered surface 1d, the selected side surface 1cc, the second chamfered surface 1e and the second surface 1b of the substrate 1), thereby increasing the density of the connecting leads 2.

[0154] It should be noted that the aforementioned “line width of the connecting lead 2 ” refers to the dimension of the connecting lead 2 along the first direction X. The following description of “line width of the connecting lead 2 ” also follows this description.

[0155] The above-mentioned “spacing between two adjacent connecting leads 2 ” refers to the distance between two adjacent connecting leads 2 along the first direction X. The description of “spacing between two adjacent connecting leads 2 ” below also follows this description.

[0156] When the line width K1 of the connecting lead 2 is reduced, for example, when the connecting lead 2 is formed by a printing process, the accuracy requirements of the printing needle T are high, which will increase the difficulty of preparing the connecting lead 2. Moreover, since the line width K1 of the connecting lead 2 is small, there may be a risk of short circuit in some areas of the connecting lead 2, which will reduce the reliability of the connecting lead 2 and easily affect the normal display of the display panel 10.

[0157] When the distance d1 between two adjacent connection leads 2 is reduced, a short circuit is likely to occur between the two adjacent connection leads 2 , which will also affect the normal display of the display panel 10 .

[0158] Based on this, in some embodiments, as shown in FIG7 , which is a structural diagram of a display panel 10 according to some embodiments, the plurality of connecting leads 2 include a first connecting lead 21 and a second connecting lead 22 , which are adjacent to each other in a direction perpendicular to the surface of the substrate 1 and are arranged in different layers.

[0159] By arranging the adjacent first connecting leads 21 and the second connecting leads 22 in different layers within the multiple connecting leads 2, that is, the multiple connecting leads 2 are not located in the same film layer, the arrangement of the multiple connecting leads 2 is changed from a planar arrangement to a three-dimensional arrangement. On the one hand, the restriction of the planar space on the arrangement of the multiple connecting leads 2 can be reduced, and the line width K1 of the connecting lead 2 can be widened, which is conducive to reducing the difficulty of preparing the connecting leads 2, and improving the reliability of the connecting leads 2, thereby ensuring the normal display of the display panel 10.

[0160] On the other hand, the spacing d1 between two adjacent first connecting leads 21 and two adjacent second connecting leads 22 can be increased to reduce the probability of short circuit between the two adjacent first connecting leads 21 and two adjacent second connecting leads 22, further ensuring the normal display of the display panel 10.

[0161] It should be noted that, in order to facilitate the description of the first connection lead 21 and the second connection lead 22 , the second connection lead 22 is made transparent in FIG. 7 to expose the first connection lead 21 which is relatively closer to the substrate 1 .

[0162] For example, since the first connecting lead 21 and the second connecting lead 22 are arranged in different layers, that is, the first connecting lead 21 and the second connecting lead 22 are respectively located in different film layers, when forming the first connecting lead 21 and the second connecting lead 22, one of the first connecting lead 21 and the second connecting lead 22 can be formed first, and then the other of the first connecting lead 21 and the second connecting lead 22 can be formed.

[0163] For example, referring to FIG. 7 , since the first connecting lead 21 is closer to the substrate 1 than the second connecting lead 22 , the first connecting lead 21 may be formed first, and then the second connecting lead 22 may be formed on the side of the first connecting lead 21 away from the substrate 1 .

[0164] For example, in addition to the film layer for providing the first connecting leads 21 and the film layer for providing the second connecting leads 22, other film layers for providing the connecting leads 2 may be formed. The film layer for providing the first connecting leads 21, the film layer for providing the second connecting leads 22, and the other film layers for providing the connecting leads 2 may be stacked in a direction perpendicular to the surface of the substrate 1. This can further reduce the restrictions imposed by the planar space on the arrangement of multiple connecting leads 2, further reducing the difficulty of preparing the connecting leads 2, improving the reliability of the connecting leads 2, and ensuring the normal display of the display panel 10.

[0165] Exemplarily, the first connection lead 21 and the second connection lead 22 transmit different signals. For example, the signals transmitted by the first connection lead 21 and the second connection lead 22 may include a Vdd signal, a Vss signal, a Data signal, a Vinit signal, and a Reset signal.

[0166] Exemplarily, one of the first connection lead 21 and the second connection lead 22 is in contact with the surface of the substrate 1 .

[0167] For example, referring to FIG7 , since the first connecting lead 21 is closer to the substrate 1 than the second connecting lead 22, the first connecting lead 21 may contact the surface of the substrate 1. For example, referring to FIG7 , since the first connecting lead 21 and the second connecting lead 22 are adjacent in a direction perpendicular to the surface of the substrate 1 (for example, on a selected side surface 1cc of the substrate 1, along the second direction Y, the first connecting lead 21 and the second connecting lead 22 are adjacent), the orthographic projections of the first connecting lead 21 and the second connecting lead 22 on the substrate 1 may at least partially overlap.

[0168] Please continue to refer to Figure 7, taking the orthographic projections of the first connecting lead 21 and the second connecting lead 22 on the plane where the selected side surface 1cc of the substrate 1 is located as an example, for example, in area FF, the orthographic projections of the first connecting lead 21 and the second connecting lead 22 on the plane where the selected side surface 1cc of the substrate 1 are located partially overlap.

[0169] For another example, in region DD, the area of ​​the orthographic projection of the first connecting lead 21 on the substrate 1 is smaller than the area of ​​the orthographic projection of the second connecting lead 22 on the substrate 1 , and the orthographic projection of the first connecting lead 21 on the substrate 1 falls within the range of the orthographic projection of the second connecting lead 22 on the substrate 1 .

[0170] For another example, in region EE, the area and shape of the orthographic projection of the first connecting lead 21 on the substrate 1 are the same as the area and shape of the orthographic projection of the second connecting lead 22 on the substrate 1, and the orthographic projection of the first connecting lead 21 on the substrate 1 coincides with the orthographic projection of the second connecting lead 22 on the selected side 1cc of the substrate 1.

[0171] 7 , the first connection lead 21 has a line width of K1 and the second connection lead 22 has a line width of K1′. The line widths K1 and K1′ of the first connection lead 21 and 22 may be the same. For example, in region EE, K1 is equal to K1′.

[0172] Alternatively, the line width K1 of the first connecting lead 21 and the line width K1' of the second connecting lead 22 may be different. While ensuring the reliability of the first connecting lead 21 and the second connecting lead 22, the line width K1 of the first connecting lead 21 and the line width K1' of the second connecting lead 22 can be set based on actual needs.

[0173] For example, the line width K1 of the first connecting lead 21 can be set according to the area of ​​the orthographic projection of the front electrode 4 connected to the first connecting lead 21 on the first surface 1a of the substrate 1, or the area of ​​the orthographic projection of the back electrode 5 connected to the first connecting lead 21 on the second surface 1b of the substrate 1, so that the area of ​​the orthographic projection of the front electrode 4 connected to the first connecting lead 21 on the first surface 1a of the substrate 1, or the area of ​​the orthographic projection of the back electrode 5 connected to the first connecting lead 21 on the second surface 1b of the substrate 1, is positively correlated with the line width K1 of the first connecting lead 21, that is, the larger the area of ​​the orthographic projection of the front electrode 4 connected to the first connecting lead 21 on the first surface 1a of the substrate 1, or the larger the area of ​​the orthographic projection of the back electrode 5 connected to the first connecting lead 21 on the second surface 1b of the substrate 1, the larger the line width K1 of the first connecting lead 21.

[0174] Similarly, the line width K1' of the second connecting lead 22 can be set according to the area of ​​the orthographic projection of the front electrode 4 connected to the second connecting lead 22 on the first surface 1a of the substrate 1, or the area of ​​the orthographic projection of the back electrode 5 connected to the second connecting lead 22 on the second surface 1b of the substrate 1, so that the area of ​​the orthographic projection of the front electrode 4 connected to the second connecting lead 22 on the first surface 1a of the substrate 1, or the area of ​​the orthographic projection of the back electrode 5 connected to the second connecting lead 22 on the second surface 1b of the substrate 1, is positively correlated with the line width K1' of the second connecting lead 22, that is, the larger the area of ​​the orthographic projection of the front electrode 4 connected to the second connecting lead 22 on the first surface 1a of the substrate 1, or the larger the area of ​​the orthographic projection of the back electrode 5 connected to the second connecting lead 22 on the second surface 1b of the substrate 1, the larger the line width K1' of the second connecting lead 22.

[0175] For example, the line width K1 of the first connection lead 21 may be greater than the line width K1 ′ of the second connection lead 22 . Alternatively, as shown in FIG. 7 , in region DD, the line width K1 of the first connection lead 21 may be smaller than the line width K1 ′ of the second connection lead 22 .

[0176] For example, as shown in Figures 9A, 9C, 10A, and 10C, each of which is a structural diagram of a local area of ​​a display panel 10 according to some embodiments of the present disclosure, based on the embodiment shown in Figure 5A, the plurality of front electrodes 4 are located within the display area AA of the display panel 10. The connecting leads 2 (i.e., the first connecting lead 21 and the second connecting lead 22) connected to the plurality of front electrodes 4 can also be provided between two adjacent pixel units P along the first direction X.

[0177] In some embodiments, as shown in Figures 8A, 8B, 9A, 9B, 9C, and 9D, each of which is a structural diagram of a partial area of ​​a display panel 10 according to some embodiments of the present disclosure, the display panel 10 further includes a first insulating layer 61. The first insulating layer 61 is located between the first connecting lead 21 and the second connecting lead 22. The first insulating layer 61 can insulate the first connecting lead 21 and the second connecting lead 22 from each other, preventing a short circuit between the first connecting lead 21 and the second connecting lead 22, thereby ensuring normal display of the display panel 10.

[0178] For example, the material used to form the first insulating layer 61 may include a thermosetting resin or a UV resin, etc. The first insulating layer 61 may be formed by a printing process.

[0179] The material used to form the first insulating layer 61 may also include silicon nitride, silicon oxide, silicon oxynitride, etc. The first insulating layer 61 may also be formed by a chemical vapor deposition process.

[0180] Exemplarily, the first insulating layer 61 covers at least the first connecting lead 21 , and the front electrode 4 and the back electrode 5 connected to the first connecting lead 21 .

[0181] For example, as shown in Figures 8A and 8B, the first insulating layer 61 may only cover the first connection lead 21, and the front electrode 4 and the back electrode 5 connected to the first connection lead 21. In addition to providing insulation, the material used to form the first insulating layer 61 can also be saved, which helps reduce the production cost of the display panel 10.

[0182] It should be noted that the first insulating layer 61 includes a plurality of separated insulating blocks 61a, each insulating block 61a correspondingly covers a first connecting lead 21 and the front electrode 4 and the back electrode 5 connected to the first connecting lead 21. Figures 8A and 8B illustrate the situation where the insulating block 61a completely overlaps with the positive projection of the first connecting lead 21, so the first connecting lead 21 is not shown.

[0183] For another example, as shown in Figures 9A and 9B , the first insulating layer 61 may also cover the selected side surface 1cc of the substrate 1. When the first insulating layer 61 covering the selected side surface 1cc of the substrate 1 is formed, the first insulating layer 61 located on the selected side surface 1cc may also cover the portion of the first connecting lead 21 located on the selected side surface 1cc. This eliminates the need to separately form the first insulating layer 61 covering the portion of the first connecting lead 21 located on the selected side surface 1cc in the area where the first connecting lead 21 is provided. This helps reduce the difficulty in preparing the first insulating layer 61 and improves the efficiency of preparing the first insulating layer 61.

[0184] For another example, as shown in Figures 9A and 9B, when the substrate 1 includes a first chamfered surface 1d and a second chamfered surface 1e, the first insulating layer 61 can also cover the first chamfered surface 1d and the second chamfered surface 1e. When the first insulating layer 61 covering the first chamfered surface 1d and the second chamfered surface 1e is formed on the first chamfered surface 1d and the second chamfered surface 1e of the substrate 1, the first insulating layer 61 located on the first chamfered surface 1d and the second chamfered surface 1e can also cover the portion of the first connecting lead 21 located on the first chamfered surface 1d and the second chamfered surface 1e. This eliminates the need to separately form the first insulating layer 61 covering the portion of the first connecting lead 21 located on the first chamfered surface 1d and the second chamfered surface 1e in the area where the first connecting lead 21 is provided. This helps reduce the difficulty of preparing the first insulating layer 61 and improves the efficiency of preparing the first insulating layer 61.

[0185] For another example, as shown in FIG9B , on the second surface 1b of the substrate 1, the first insulating layer 61 may further cover the region between two adjacent back electrodes 5 along the first direction X. When the first insulating layer 61 covering the back electrodes 5 and the region between two adjacent back electrodes 5 along the first direction X is formed on the second surface 1b of the substrate 1, the first insulating layer 61 covering the back electrodes 5 and the first insulating layer 61 covering the region between two adjacent back electrodes 5 along the first direction X may be formed simultaneously, without the need to separately form the first insulating layer 61 covering the portion of the first connecting lead 21 located on the second surface 1b in the region where the first connecting lead 21 is provided. This helps to further reduce the difficulty of preparing the first insulating layer 61 and further improve the efficiency of preparing the first insulating layer 61.

[0186] For another example, as shown in Figure 9C, on the first surface 1a of the substrate 1, the first insulating layer 61 can also cover the front electrode 4 that is not connected to the first connecting lead 21, which is beneficial to increasing the coverage area of ​​the first insulating layer 61, avoiding insufficient coverage of the front electrode 4 connected to the first connecting lead 21 by the first insulating layer 61, and is beneficial to improving the insulation performance of the first insulating layer 61.

[0187] As shown in Figure 9D, on the second surface 1b of the substrate 1, the first insulating layer 61 can also cover the back electrode 5 that is not connected to the first connecting lead 21, which is beneficial to increasing the coverage area of ​​the first insulating layer 61 and avoiding insufficient coverage of the back electrode 5 connected to the first connecting lead 21 by the first insulating layer 61, which is beneficial to further improve the insulation performance of the first insulating layer 61.

[0188] It should be noted that, in order to facilitate the description of the first connection leads 21 and the first insulating layer 61 , the first insulating layer 61 is made transparent in FIG. 9A and FIG. 9B to expose the first connection leads 21 .

[0189] The following is a schematic description of some embodiments of the present disclosure, taking the first insulating layer 61 covering the selected side surface 1cc, the first chamfered surface 1d, the second chamfered surface 1e, the first connecting lead 21, and the front electrode 4 and the back electrode 5 connected to the first connecting lead 21 as an example.

[0190] It is understood that as shown in Figures 10A, 10B, 10C, and 10D, which are all structural diagrams of a partial area of ​​the display panel 10 according to some embodiments of the present disclosure, the second connecting lead 22 is located on a side of the first insulating layer 61 away from the first connecting lead 21, that is, the first connecting lead 21 and the second connecting lead 22 are located on opposite sides of the first insulating layer 61.

[0191] Exemplarily, please continue to refer to Figures 10A and 10B. When the first insulating layer 61 does not cover the front electrode 4 and the back electrode 5 that are not connected to the first connecting lead 21, the first connecting lead 21 and the front electrode 4 and the back electrode 5 are directly connected.

[0192] The second connecting lead 22 is also directly connected to the front electrode 4 and the back electrode 5 .

[0193] Alternatively, referring to FIG. 10C and FIG. 10D , when the first insulating layer 61 covers the front electrode 4 and the back electrode 5 that are not connected to the first connecting lead 21 , the first connecting lead 21 and the front electrode 4 and the back electrode 5 are directly connected.

[0194] The second connection lead 22 and the front electrode 4 , as well as the back electrode 5 are connected through a via L. The via L, for example, passes through the first insulating layer 61 .

[0195] In some embodiments, as shown in Figures 11A, 11B, 12A, and 12B, each of which is a structural diagram of a partial area of ​​a display panel 10 according to some embodiments of the present disclosure, the display panel 10 further includes a protective layer 62. The protective layer 62 covers at least the second connection lead 22, and the front electrode 4 and the back electrode 5 connected to the second connection lead 22.

[0196] The protective layer 62 can not only play an insulating role to prevent the second connecting lead 22, the front electrode 4 and the back electrode 5 connected to the second connecting lead 22 and other circuits in the display panel 10 from short circuiting, but also protect the second connecting lead 22, the front electrode 4 and the back electrode 5 connected to the second connecting lead 22, and prevent the second connecting lead 22, and the front electrode 4 and the back electrode 5 connected to the second connecting lead 22 from corrosion or oxidation due to exposed surfaces.

[0197] 11A and 11B , the protective layer 62 may only cover the second connection lead 22, and the front electrode 4 and the back electrode 5 connected to the second connection lead 22. Besides providing insulation, the protective layer 62 can also be saved in material, thereby reducing the manufacturing cost of the display panel 10.

[0198] For another example, as shown in Figures 12A and 12B , the protective layer 62 may also cover the selected side surface 1cc of the substrate 1. When the protective layer 62 covering the selected side surface 1cc of the substrate 1 is formed, the protective layer 62 located on the selected side surface 1cc may also cover the portion of the second connecting lead 22 located on the selected side surface 1cc. This eliminates the need to separately form the protective layer 62 covering the portion of the second connecting lead 22 located on the selected side surface 1cc in the area where the second connecting lead 22 is provided. This helps reduce the difficulty in preparing the protective layer 62 and improves the efficiency of preparing the protective layer 62.

[0199] For another example, as shown in Figures 12A and 12B, when the substrate 1 includes a first chamfered surface 1d and a second chamfered surface 1e, the protective layer 62 can also cover the first chamfered surface 1d and the second chamfered surface 1e. When the protective layer 62 covering the first chamfered surface 1d and the second chamfered surface 1e of the substrate 1 is formed, the protective layer 62 located on the first chamfered surface 1d and the second chamfered surface 1e can simultaneously cover the portion of the second connecting lead 22 located on the first chamfered surface 1d and the second chamfered surface 1e. This eliminates the need to separately form the protective layer 62 covering the portion of the second connecting lead 22 located on the first chamfered surface 1d and the second chamfered surface 1e in the area where the second connecting lead 22 is provided. This helps reduce the difficulty of preparing the protective layer 62 and improves the efficiency of preparing the protective layer 62.

[0200] For another example, as shown in FIG12B , on the second surface 1b of the substrate 1, the protective layer 62 may further cover the region between two adjacent back electrodes 5 along the first direction X. When the protective layer 62 covering the back electrodes 5 and the region between two adjacent back electrodes 5 along the first direction X is formed on the second surface 1b of the substrate 1, the protective layer 62 covering the back electrodes 5 and the protective layer 62 covering the region between two adjacent back electrodes 5 along the first direction X may be formed simultaneously, without the need to separately form the protective layer 62 covering the portion of the second connecting lead 22 located on the second surface 1b in the region where the second connecting lead 22 is provided. This helps to further reduce the difficulty of preparing the protective layer 62 and further improve the efficiency of preparing the protective layer 62.

[0201] It should be noted that, in order to facilitate the description of the second connection leads 22 and the protection layer 62 , the protection layer 62 is made transparent in FIG. 12A and FIG. 12B to expose the second connection leads 22 .

[0202] For example, the material used to form the protective layer 62 may include a thermosetting resin or a UV resin, etc. The protective layer 62 may be formed by a printing process.

[0203] The material used to form the protection layer 62 may also include silicon nitride, silicon oxide, silicon oxynitride, etc. The protection layer 62 may also be formed by a chemical vapor deposition process.

[0204] In the spliced ​​display device 1000, the size of the seam (the gap between two adjacent display panels 10) is an important factor affecting the display effect of the spliced ​​display device 1000. Because the first connecting lead 21, the first insulating layer 61, the second connecting lead 22, and the protective layer 62 are sequentially arranged along the second direction Y on the selected side surface 1cc of the substrate 1, the first connecting lead 21, the first insulating layer 61, the second connecting lead 22, and the protective layer 62 form a spacer on the selected side surface 1cc of the substrate 1, which is not conducive to narrowing the frame of the display panel 10. As a result, the seam increases when the display panels 10 are spliced ​​together. In the spliced ​​display device 1000, display abnormalities in the seam area, such as bright seams, are easily generated, affecting the display effect of the spliced ​​display device 1000.

[0205] 13A and 13B , which are both structural diagrams of a local area of ​​a display panel 10 according to some embodiments of the present disclosure, further include at least one recessed region Q located at least on a selected side surface 1cc of the substrate 1 .

[0206] It should be noted that the above-mentioned recessed area Q means that a groove is provided on at least a selected side surface 1cc of the substrate 1 to form the recessed area Q, that is, the recessed area Q is recessed toward the inside of the substrate 1 .

[0207] For example, referring to FIG. 13A , the recessed region Q may be located only on a selected side surface 1 cc of the substrate 1 .

[0208] Alternatively, referring to FIG. 13B , the recessed region Q may also extend to the first chamfered surface 1 d and the second chamfered surface 1 e of the substrate 1 based on being located on the selected side surface 1 cc of the substrate 1 .

[0209] Alternatively, the recessed region Q may further extend to the first surface 1 a and the second surface 1 b of the substrate 1 .

[0210] 13A and 13B , the orthographic projection of the one of the first connecting lead 21 and the second connecting lead 22 that is closer to the substrate 1 on the selected side surface 1 cc of the substrate 1 is located within the recessed region Q.

[0211] 13A and 13B , the first connecting lead 21 is closer to the substrate 1 than the second connecting lead 22 , and the orthographic projection of the first connecting lead 21 on the selected side surface 1 cc of the substrate 1 is located within the recessed region Q.

[0212] In the following, some embodiments of the present disclosure are schematically described by taking the example that the first connecting lead 21 is closer to the substrate 1 than the second connecting lead 22 .

[0213] For example, please continue to refer to FIG. 13A , the display panel 10 may include a plurality of recessed areas Q, and the orthographic projection of a first connecting lead 21 on the selected side surface 1 cc of the substrate 1 is located within a recessed area Q.

[0214] Alternatively, please continue to refer to FIG. 13B , the orthographic projections of a plurality of (eg, three) first connecting leads 21 on the selected side surface 1 cc of the substrate 1 are located within a recessed area Q.

[0215] In some embodiments, please continue to refer to Figures 13A and 13B. When the orthographic projection of a first connecting lead 21 on the selected side surface 1cc of the substrate 1 is located within a recessed area Q, the ratio of the dimension K3 of the recessed area Q along the first direction X to the dimension K1 of the first connecting lead 21 along the first direction X (i.e., the line width of the first connecting lead 21) is 1 to 2.

[0216] For example, the ratio of the dimension K3 of the recessed area Q along the first direction X to the dimension K1 of the first connection lead 21 along the first direction X (ie, the line width of the first connection lead 21 ) may be 1, 1.2, 1.3, 1.5, 1.6, 1.8 or 2.

[0217] It can be understood that when the ratio of the dimension K3 of the recessed area Q along the first direction X to the dimension K1 of the first connecting lead 21 along the first direction X (i.e., the line width of the first connecting lead 21) is greater than 1, the dimension K3 of the recessed area Q along the first direction X is greater than the dimension K1 of the first connecting lead 21 along the first direction X (i.e., the line width of the first connecting lead 21), which facilitates the formation of the first connecting lead 21 in the recessed area Q and reduces the probability that the orthographic projection of the first connecting lead 21 on the selected side surface 1cc of the substrate 1 is located outside the recessed area Q due to the misalignment of the first connecting lead 21 and the recessed area Q.

[0218] When the ratio of the dimension K3 of the recessed area Q along the first direction X to the dimension K1 of the first connecting lead 21 along the first direction X (i.e., the line width of the first connecting lead 21) is 1, the dimension K3 of the recessed area Q along the first direction X and the dimension K1 of the first connecting lead 21 along the first direction X (i.e., the line width of the first connecting lead 21) are the same, and the dimension K3 of the recessed area Q along the first direction X is relatively small, which can reduce the cost of forming the recessed area Q and further reduce the production cost of the display panel 10.

[0219] As shown in Figures 13C, 13D, and 13E, Figures 13C, 13D, and 13E are all cross-sectional views of the display panel 10 along the section line HH in Figure 12A. It should be noted that Figures 13C, 13D, and 13E are cross-sectional views of the display panel 10 along the section line HH in Figure 12A, respectively, when the depth of the recessed region Q of the display panel 10 (i.e., the dimension of the recessed region Q along the second direction Y) is different.

[0220] The depth of the recessed area Q (i.e., the dimension of the recessed area Q along the second direction Y) is S1. Since the positive projection of the first connecting lead 21 on the selected side surface 1cc of the substrate 1 is located in the recessed area Q, at least part of the first connecting lead 21 is located in the recessed area Q.

[0221] When at least a portion of the first connecting lead 21 is located within the recessed area Q, the position of the first connecting lead 21, the first insulating layer 61, the second connecting lead 22 and the protective layer 62 on the selected side 1cc of the substrate 1 can be reduced, that is, the spacing S6 between the side of the protective layer 62 away from the selected side 1cc and the selected side 1cc is reduced, which is beneficial to the narrowing of the frame of the display panel 10, thereby reducing the distance of the seam when the display panels 10 are spliced, making the seam between two adjacent display panels 10 difficult to be detected by the naked eye within the viewing distance when the spliced ​​display device 1000 is actually viewed, avoiding display abnormalities in the seam area of ​​the spliced ​​display device 1000, ensuring the normal display of the spliced ​​display device 1000, and presenting a better display effect.

[0222] As shown in Figures 13C, 13D, and 13E, and in conjunction with Figure 15B, Figure 15B is a structural diagram of a local area of ​​the display panel 10 according to some embodiments of the present disclosure. The minimum distance between the edge of the front electrode 4 closest to the selected side 1cc of the substrate 1 among the multiple front electrodes 4 and the first boundary 1aa of the first surface 1a is d2. It can be understood that the depth of the recessed area Q (i.e., the dimension of the recessed area Q along the second direction Y) S1 should be less than or equal to d2 to avoid exposing a side surface of a portion of the front electrode 4 close to the substrate 1.

[0223] For example, the minimum distance d2 between the edge of the front electrode 4 closest to the selected side surface 1cc of the substrate 1 and the first boundary 1aa of the first surface 1a can be

[0224] For example, the minimum distance d2 between the edge of the front electrode 4 closest to the selected side surface 1cc of the substrate 1 among the plurality of front electrodes 4 and the first boundary 1aa of the first surface 1a can be

[0225] Please continue to refer to Figures 13C, 13D and 13E. The thickness of the first connecting lead 21 (i.e., the dimension of the first connecting lead 21 along the second direction Y) is S2, the thickness of the first insulating layer 61 (i.e., the dimension of the first insulating layer 61 along the second direction Y) is S3, the thickness of the second connecting lead 22 (i.e., the dimension of the second connecting lead 22 along the second direction Y) is S4, and the thickness of the protective layer 62 (i.e., the dimension of the protective layer 62 along the second direction Y) is S5.

[0226] For example, as shown in Figure 13C, the depth of the recessed area Q (i.e., the dimension of the recessed area Q along the second direction Y) S1 can be smaller than the thickness of the first connecting lead 21 (i.e., the dimension of the first connecting lead 21 along the second direction Y) S2, and a portion of the first connecting lead 21 is located within the recessed area Q.

[0227] Alternatively, as shown in FIG13D , the depth S1 of the recessed area Q (i.e., the dimension of the recessed area Q along the second direction Y) can be equal to the thickness S2 of the first connecting lead 21 (i.e., the dimension of the first connecting lead 21 along the second direction Y), and the first connecting lead 21 is entirely located within the recessed area Q. The spacing S6 between the side of the protective layer 62 away from the selected side surface 1cc and the selected side surface 1cc can be further reduced, which is beneficial for narrowing the frame of the display panel 10, thereby reducing the distance of the seam when the display panels 10 are spliced, avoiding display abnormalities in the seam area of ​​the spliced ​​display device 1000, and ensuring normal display of the spliced ​​display device 1000.

[0228] Alternatively, as shown in FIG13E , the depth S1 of the recessed region Q (i.e., the dimension of the recessed region Q along the second direction Y) may be greater than the thickness S2 of the first connecting lead 21 (i.e., the dimension of the first connecting lead 21 along the second direction Y). For example, the depth S1 of the recessed region Q (i.e., the dimension of the recessed region Q along the second direction Y) is equal to the sum of the thickness S2 of the first connecting lead 21 (i.e., the dimension of the first connecting lead 21 along the second direction Y), the thickness S3 of the first insulating layer 61 (i.e., the dimension of the first insulating layer 61 along the second direction Y), and the thickness S4 of the second connecting lead 22 (i.e., the dimension of the second connecting lead 22 along the second direction Y). The first connecting lead 21, the first insulating layer 61, and the second connecting lead 22 are all located within the recessed region Q. The spacing S6 between the side of the protective layer 62 away from the selected side 1cc and the selected side 1cc can be further reduced, which is beneficial to narrowing the frame of the display panel 10, thereby reducing the distance of the seam when the display panels 10 are spliced, avoiding abnormal display in the seam area of ​​the spliced ​​display device 1000, and ensuring the normal display of the spliced ​​display device 1000.

[0229] As the number of connecting leads 2 increases, the number of front electrodes 4 and back electrodes 5 connected to the corresponding connecting leads 2 also increases accordingly. As shown in Figures 14A and 14B, Figures 14A and 14B are structural diagrams of a local area of ​​a display panel 10 according to some embodiments of the present disclosure. By reducing the size of the front electrodes 4 and the size of the back electrodes 5, a larger number of front electrodes 4 can be arranged on the first surface 1a of the substrate 1, and a larger number of back electrodes 5 can be arranged on the second surface 1b of the substrate 1, that is, the density of the front electrodes 4 and the back electrodes 5 can be increased.

[0230] It should be noted that the aforementioned "size of the front electrode 4" refers to the area of ​​the orthographic projection of the front electrode 4 on the first surface 1a of the substrate 1, and the aforementioned "size of the back electrode 5" refers to the area of ​​the orthographic projection of the back electrode 5 on the second surface 1b of the substrate 1. This description also applies to the following descriptions of the "size of the front electrode 4" and the "size of the back electrode 5."

[0231] When the size of the front electrode 4 is reduced, the overlapping area between the connecting lead 2 and the front electrode 4 will also be reduced, which may easily lead to poor overlapping between the connecting lead 2 and the front electrode 4, affecting the conductive performance of the connecting lead 2 and the front electrode 4, and may cause the display panel 10 to fail to display normally.

[0232] Based on this, an embodiment of the arrangement of the front electrode 4 will be described below.

[0233] In some embodiments, as shown in Figures 15A, 15B and 15C, Figures 15A, 15B and 15C are all structural diagrams of a local area of ​​the display panel 10 according to some embodiments of the present disclosure. A plurality of front electrodes 4 are arranged at intervals along the first direction X and the second direction Y, respectively. Compared with the plurality of front electrodes 4 being arranged at intervals only along the first direction X, the plurality of front electrodes 4 are arranged to be arranged at intervals along the first direction X and the second direction Y, respectively. This can reduce the restriction of the dimension K2 of the first surface 1a of the substrate 1 along the first direction X on the arrangement of the plurality of front electrodes 4, ensure the size of the front electrode 4, increase the overlap area between the connecting lead 2 and the front electrode 4, avoid the problem of poor overlap between the connecting lead 2 and the front electrode 4, and help improve the conductive performance of the connecting lead 2 and the front electrode 4, thereby ensuring the normal display of the display panel 10.

[0234] For example, referring to Figures 15A, 15B, and 15C, the plurality of front electrodes 4 include first electrodes 41 and second electrodes 42, which are disposed adjacent to each other. The first electrodes 41 are arranged at intervals along the first direction X. The second electrodes 42 are also arranged at intervals along the first direction X, and the first electrodes 41 and the second electrodes 42 are alternately arranged along the second direction Y.

[0235] It should be noted that, in Figures 15A, 15B and 15C, a first electrode 41 and a second electrode 42 are alternately arranged along the second direction Y as an example for illustration, however, the arrangement of the first electrode 41 and the second electrode 42 in the present disclosure is not limited to this, for example, multiple first electrodes 41 and multiple second electrodes 42 can also be alternately arranged along the second direction Y.

[0236] For example, referring to Figures 15A and 15B , the plurality of pixel units P include two pixel units P that are adjacent in the first direction X and both close to the selected side surface 1cc of the substrate 1, and the first electrode 41 and the second electrode 42 are disposed between the two adjacent pixel units P. It will be understood that the first electrode 41 and the second electrode 42 do not overlap with the two pixel units P that are adjacent in the first direction X and both close to the selected side surface 1cc of the substrate 1 in the second direction Y.

[0237] Alternatively, as shown in Figure 15C, the multiple pixel units P include two pixel units P that are adjacent in the first direction X and both close to the selected side 1cc of the substrate 1. In the second direction Y, the first electrode 41 and the second electrode 42 at least partially overlap with the two pixel units P that are adjacent in the first direction X and both close to the selected side 1cc of the substrate 1, and there is an overlapping area J12.

[0238] The following uses the example of a first electrode 41 and a second electrode 42 disposed between two adjacent pixel units P (i.e., two pixel units P adjacent to each other in the first direction X and both close to the selected side surface 1cc of the substrate 1) to schematically illustrate some embodiments of the present disclosure. For example, referring to Figures 15A and 15B , the first electrode 41 is closer to the selected side surface 1cc of the substrate 1 than the second electrode 42.

[0239] For example, as shown in FIG15A , the first electrode 41 and the second electrode 42 may have the same size. Alternatively, as shown in FIG15B , the first electrode 41 and the second electrode 42 may have different sizes, which may be designed based on actual needs.

[0240] For example, please continue to refer to FIG. 15A and FIG. 15B . Along the second direction Y, the first electrode 41 and the second electrode 42 have at least a partial overlapping area.

[0241] For example, as shown in FIG. 15A , along the second direction Y, the first electrodes 41 and the second electrodes 42 may be staggered and arranged, and the first electrodes 41 and the second electrodes 42 partially overlap in the second direction Y to form an overlapping region J2 .

[0242] For another example, as shown in FIG15A , along the second direction Y, the first electrode 41 and the second electrode 42 may be arranged in an array, and the size of the first electrode 41 is the same as the size of the second electrode 42 , and the first electrode 41 and the second electrode 42 completely overlap in the second direction Y, and there is an overlapping area J1 .

[0243] For another example, as shown in FIG15B , along the second direction Y, the first electrode 41 and the second electrode 42 may be arranged in an array, and the size of the first electrode 41 is different from the size of the second electrode 42 . The first electrode 41 and the second electrode 42 completely overlap in the second direction Y, and there is an overlapping area J3 .

[0244] In some embodiments, a plurality of front electrodes 4 (first electrodes 41 and second electrodes 42 ) may be disposed within a conductive layer located on the first surface 1 a of the substrate 1 .

[0245] As shown in Figures 16 and 17, both Figures 16 and 17 are cross-sectional views of the display panel 10 in Figure 15A along the section line GG. It should be noted that Figures 16 and 17 are cross-sectional views of the display panel 10 in Figure 15A along the section line GG when the front electrode 4 and the back electrode 5 of the display panel 10 are arranged in different ways.

[0246] The first surface 1a of the substrate 1 includes a second insulating layer 83, a first conductive layer 81, a third insulating layer 84, a second conductive layer 82, and a fourth insulating layer 85 stacked in sequence. The first conductive layer 81 is closer to the first surface 1a of the substrate 1 than the second conductive layer 82.

[0247] Illustratively, the first conductive layer 81 may be provided with a gate electrode of a thin film transistor in a driving component in the pixel unit P; and the second conductive layer 82 may be provided with a source and drain electrode of the thin film transistor.

[0248] Exemplarily, the first conductive layer 81 and the second conductive layer 82 can be obtained by depositing one or more metal materials such as MO (molybdenum) / , Ti (titanium) / , Al / (aluminum), Cu (molybdenum / titanium / aluminum / copper), and ITO (Indium Tin Oxide) using a PVD (Physical Vapor Deposition) process.

[0249] For example, the first conductive layer 81 or the second conductive layer 82 can be formed by depositing MO / Al / MO (molybdenum / aluminum / molybdenum), MO / Cu / MO (molybdenum / copper / molybdenum), Ti / Cu / Ti (titanium / copper / titanium), or ITO / Cu (indium tin oxide / copper) using a PVD (Physical Vapor Deposition) process. The second conductive layer 82 has a greater antioxidant capacity than the first conductive layer 81.

[0250] In some embodiments, as shown in FIG. 17 , the first electrode 41 and the second electrode 42 may be provided in the same layer.

[0251] Exemplarily, the first electrode 41 and the second electrode 42 are both located in the first conductive layer 81 .

[0252] In some other embodiments, referring to FIG. 16 , the first electrode 41 and the second electrode 42 may be provided in different layers, and the first electrode 41 is closer to the first surface 1 a of the substrate 1 than the second electrode 42 .

[0253] By arranging the first electrode 41 and the second electrode 42 in different conductive layers (the first conductive layer 81 and the second conductive layer 82), the multiple front electrodes 4 are not located in the same plane, and the arrangement of the multiple front electrodes 4 (the first electrode 41 and the second electrode 42) is changed from a planar arrangement to a three-dimensional arrangement, that is, the multiple front electrodes 4 can not only be arranged at intervals along the first direction X and the second direction Y, but also can be arranged at intervals along the third direction Z. This can reduce the restrictions of the plane space on the arrangement of the front electrodes 4 (the first electrode 41 and the second electrode 42), ensure the size of the front electrode 4, further increase the overlapping area between the connecting lead 2 and the front electrode 4, avoid the problem of poor overlapping between the connecting lead 2 and the front electrode 4, and help to further improve the conductive performance of the connecting lead 2 and the front electrode 4, and ensure the normal display of the display panel 10.

[0254] Exemplarily, in addition to the conductive layer for setting the first electrode 41 and the conductive layer for setting the second electrode 42, other conductive layers for setting the front electrode 4 may be formed. The conductive layer for setting the first electrode 41, the conductive layer for setting the second electrode 42, and the other conductive layers for setting the front electrode 4 may be stacked in the third direction Z. This can further reduce the restrictions on the arrangement of the front electrode 4 in the plane space, ensure the size of the front electrode 4, further increase the overlap area between the connecting lead 2 and the front electrode 4, avoid the problem of poor overlap between the connecting lead 2 and the front electrode 4, and help to further improve the conductive performance of the connecting lead 2 and the front electrode 4, ensuring the normal display of the display panel 10.

[0255] For example, the first electrode 41 may be located on the first conductive layer 81 , and the second electrode 42 may be located on the second conductive layer 82 .

[0256] For example, please continue to refer to Figure 16. The orthographic projection of the first electrode 41 on the first surface 1a of the substrate 1 does not overlap with the orthographic projection of the second electrode 42 on the first surface 1a of the substrate 1, that is, the orthographic projection of the first electrode 41 on the first surface 1a of the substrate 1 does not overlap with the orthographic projection of the second electrode 42 on the first surface 1a of the substrate 1.

[0257] Alternatively, as shown in FIG18 , which is a cross-sectional view of a partial area of ​​the display panel 10 according to some embodiments of the present disclosure, the orthographic projection of the first electrode 41 on the first surface 1 a of the substrate 1 partially overlaps with the orthographic projection of the second electrode 42 on the first surface 1 a of the substrate 1, that is, the orthographic projection of the first electrode 41 on the first surface 1 a of the substrate 1 and the orthographic projection of the second electrode 42 on the first surface 1 a of the substrate 1 have an overlapping area J4.

[0258] In some embodiments, please continue to refer to FIG. 16 , FIG. 17 and FIG. 18 , the display panel 10 further includes a plurality of openings K for exposing the plurality of front electrodes 4 (the first electrodes 41 and the second electrodes 42 ).

[0259] For example, as shown in FIG. 17 , the opening K may penetrate the third insulating layer 84 and expose the first electrode 41 and the second electrode 42 located in the first conductive layer 81 .

[0260] 16 and 18 , the opening K may penetrate the fourth insulating layer 85 and expose the second electrode 42 located in the second conductive layer 82. The opening K may also penetrate the fourth insulating layer 85 and the third insulating layer 84 in sequence and expose the first electrode 41 located in the first conductive layer 81.

[0261] An embodiment of the arrangement of the back electrode 5 will be described below.

[0262] In some embodiments, as shown in Figures 19A and 19B, Figures 19A and 19B are both structural diagrams of a local area of ​​a display panel 10 according to some embodiments of the present disclosure. A plurality of back electrodes 5 are arranged at intervals along the first direction X and the second direction Y, respectively. Compared to the case where a plurality of back electrodes 5 are arranged at intervals only along the first direction X, the plurality of back electrodes 5 are arranged to be arranged at intervals along the first direction X and the second direction Y, respectively. This can reduce the restriction of the dimension K2 of the second surface 1b of the substrate 1 along the first direction X on the arrangement of the plurality of back electrodes 5, ensure the size of the back electrode 5, increase the overlap area between the connecting lead 2 and the back electrode 5, avoid the problem of poor overlap between the connecting lead 2 and the back electrode 5, and help improve the conductive performance of the connecting lead 2 and the back electrode 5, thereby ensuring the normal display of the display panel 10.

[0263] For example, referring to Figures 19A and 19B , the plurality of back electrodes 5 include a third electrode 51 and a fourth electrode 52, which are disposed adjacent to each other. The third electrodes 51 are arranged at intervals along the first direction X. The fourth electrodes 52 are also arranged at intervals along the first direction X, and the third electrodes 51 and the fourth electrodes 52 are alternately arranged along the second direction Y.

[0264] It should be noted that, in Figures 19A and 19B, a third electrode 51 and a fourth electrode 52 are alternately arranged along the second direction Y as an example for illustration, however, the arrangement of the third electrode 51 and the fourth electrode 52 in the present disclosure is not limited to this. For example, multiple third electrodes 51 and multiple fourth electrodes 52 can also be alternately arranged along the second direction Y.

[0265] For example, referring to FIG. 19A and FIG. 19B , the third electrode 51 is closer to the selected side surface 1 cc of the substrate 1 than the fourth electrode 52 .

[0266] For example, as shown in FIG19A , the third electrode 51 and the fourth electrode 52 may have the same size. Alternatively, as shown in FIG19B , the third electrode 51 and the fourth electrode 52 may have different sizes, and the sizes of the third electrode 51 and the fourth electrode 52 may be designed based on actual needs.

[0267] For example, please continue to refer to FIG. 19A and FIG. 19B , along the second direction Y, the third electrode 51 and the fourth electrode 52 have at least a partial overlapping area.

[0268] For example, as shown in FIG. 19A , along the second direction Y, the third electrode 51 and the fourth electrode 52 may be staggered and arranged, and the third electrode 51 and the fourth electrode 52 partially overlap in the second direction Y to form an overlapping region J9 .

[0269] For another example, as shown in FIG19A , along the second direction Y, the third electrode 51 and the fourth electrode 52 can be arranged in an array, and the size of the third electrode 51 is the same as the size of the fourth electrode 52. The third electrode 51 and the fourth electrode 52 completely overlap in the second direction Y, and there is an overlapping area J8.

[0270] For another example, as shown in FIG19B , along the second direction Y, the third electrode 51 and the fourth electrode 52 can be arranged in an array, and the size of the third electrode 51 is different from the size of the fourth electrode 52. The third electrode 51 and the fourth electrode 52 completely overlap in the second direction Y, and there is an overlapping area J10.

[0271] In some embodiments, a plurality of back electrodes 5 (third electrodes 51 and fourth electrodes 52 ) may be disposed in the conductive layer located on the second surface 1 b of the substrate 1 .

[0272] As shown in FIG16 , which is a cross-sectional view of the display panel 10 along section line GG in FIG15A , the second surface 1 b of the substrate 1 includes a third conductive layer 91, a fifth insulating layer 93, a fourth conductive layer 92, and a sixth insulating layer 94 stacked in sequence. The third conductive layer 91 is closer to the second surface 1 b of the substrate 1 than the fourth conductive layer 92.

[0273] Illustratively, the third conductive layer 91 and the fourth conductive layer 92 can be obtained by depositing one or more metal materials such as MO (molybdenum), Ti (titanium), Al (aluminum), Cu (copper), ITO (Indium Tin Oxide) using a PVD (Physical Vapor Deposition) process.

[0274] For example, the third conductive layer 91 or the fourth conductive layer 92 can be formed by depositing MO / Al / MO (molybdenum / aluminum / molybdenum), MO / Cu / MO (molybdenum / copper / molybdenum), Ti / Cu / Ti (titanium / copper / titanium), or ITO / Cu (indium tin oxide / copper) using a PVD (Physical Vapor Deposition) process. The fourth conductive layer 92 has a greater antioxidant capacity than the third conductive layer 91.

[0275] In some embodiments, as shown in FIG17 , which is a cross-sectional view of the display panel 10 along the section line GG in FIG15A , the third electrode 51 and the fourth electrode 52 may be provided in the same layer.

[0276] Exemplarily, the third electrode 51 and the fourth electrode 52 are both located in the third conductive layer 91 .

[0277] In some other embodiments, referring to FIG. 16 , the third electrode 51 and the fourth electrode 52 may be provided in different layers, and the third electrode 51 is closer to the second surface 1 b of the substrate 1 than the fourth electrode 52 .

[0278] By arranging the third electrode 51 and the fourth electrode 52 in different conductive layers (the third conductive layer 91 and the fourth conductive layer 92), the multiple back electrodes 5 are not located in the same plane, and the arrangement of the multiple back electrodes 5 (the third electrode 51 and the fourth electrode 52) is changed from a planar arrangement to a three-dimensional arrangement, that is, the multiple back electrodes 5 can not only be arranged at intervals along the first direction X and the second direction Y, but also can be arranged at intervals along the third direction Z. This can reduce the restrictions of the plane space on the arrangement of the back electrodes 5 (the third electrode 51 and the fourth electrode 52), ensure the size of the back electrode 5, further increase the overlapping area between the connecting lead 2 and the back electrode 5, avoid the problem of poor overlapping between the connecting lead 2 and the back electrode 5, and help to further improve the conductive performance of the connecting lead 2 and the back electrode 5, and ensure the normal display of the display panel 10.

[0279] Exemplarily, in addition to the conductive layer for setting the third electrode 51 and the conductive layer for setting the fourth electrode 52, other conductive layers for setting the back electrode 5 may be formed. The conductive layer for setting the third electrode 51, the conductive layer for setting the fourth electrode 52, and the other conductive layers for setting the back electrode 5 may be stacked in the third direction Z. This can further reduce the restrictions on the arrangement of the back electrode 5 in the plane space, ensure the size of the back electrode 5, further increase the overlap area between the connecting lead 2 and the back electrode 5, avoid the problem of poor overlap between the connecting lead 2 and the back electrode 5, and help further improve the conductive performance of the connecting lead 2 and the back electrode 5, ensuring the normal display of the display panel 10.

[0280] For example, the third electrode 51 may be located in the third conductive layer 91 , and the fourth electrode 52 may be located in the fourth conductive layer 92 .

[0281] For example, please continue to refer to Figure 16. The orthographic projection of the third electrode 51 on the second surface 1b of the substrate 1 does not overlap with the orthographic projection of the fourth electrode 52 on the second surface 1b of the substrate 1, that is, the orthographic projection of the third electrode 51 on the second surface 1b of the substrate 1 does not overlap with the orthographic projection of the fourth electrode 52 on the second surface 1b of the substrate 1.

[0282] Alternatively, as shown in FIG18 , which is a cross-sectional view of a display panel 10 according to some embodiments of the present disclosure, the orthographic projection of the third electrode 51 on the second surface 1 b of the substrate 1 partially overlaps with the orthographic projection of the fourth electrode 52 on the second surface 1 b of the substrate 1, that is, the orthographic projection of the third electrode 51 on the second surface 1 b of the substrate 1 and the orthographic projection of the fourth electrode 52 on the second surface 1 b of the substrate 1 have an overlapping area J5.

[0283] In some embodiments, please continue to refer to FIG. 16 , FIG. 17 and FIG. 18 , the opening K can also be used to expose a plurality of back electrodes 5 (the third electrode 51 and the fourth electrode 52 ).

[0284] For example, as shown in FIG. 17 , the opening K may penetrate the fifth insulating layer 93 and expose the third electrode 51 and the fourth electrode 52 located in the third conductive layer 91 .

[0285] 16 and 18 , the opening K may penetrate the sixth insulating layer 94 and expose the fourth electrode 52 located in the fourth conductive layer 92. The opening K may also penetrate the sixth insulating layer 94 and the fifth insulating layer 93 in sequence and expose the third electrode 51 located in the third conductive layer 91.

[0286] In some embodiments, referring to FIG. 9A and FIG. 9B , the first connecting lead 21 may be used to connect the first electrode 41 and the third electrode 51 .

[0287] Please continue to refer to FIG. 10A and FIG. 10B . The second connecting lead 22 can be used to connect the second electrode 42 and the fourth electrode 52 .

[0288] Exemplarily, multiple front electrodes 4 (i.e., first electrodes 41 and second electrodes 42) and multiple back electrodes 5 (i.e., third electrodes 51 and fourth electrodes 52) can have a gold-plated surface. When the material of the connecting lead 2 (i.e., first connecting lead 21 and second connecting lead 22) includes silver (Ag), the bonding performance of gold (Au) and silver (Ag) is better, which can reduce the contact resistance between the front electrode 4 and the connecting lead 2, and between the back electrode 5 and the connecting lead 2.

[0289] Exemplarily, the first electrode 41 and the third electrode 51 are disposed correspondingly, and the orthographic projections of the first electrode 41 and the third electrode 51 on the second surface 1b of the substrate 1 at least partially overlap. For example, the orthographic projections of the first electrode 41 and the third electrode 51 on the second surface 1b of the substrate 1 may partially overlap; or, as shown in FIG16 , the orthographic projections of the first electrode 41 and the third electrode 51 on the second surface 1b of the substrate 1 may completely overlap, with an overlapping region J6 existing.

[0290] The second electrode 42 and the fourth electrode 52 are disposed correspondingly, and the orthographic projections of the second electrode 42 and the fourth electrode 52 on the second surface 1b of the substrate 1 at least partially overlap. For example, the orthographic projections of the second electrode 42 and the fourth electrode 52 on the second surface 1b of the substrate 1 may partially overlap; or, as shown in FIG16 , the orthographic projections of the second electrode 42 and the fourth electrode 52 on the second surface 1b of the substrate 1 may completely overlap, with an overlapping region J7 existing.

[0291] In some embodiments, as shown in FIG20A and in combination with FIG16 , FIG20A is a structural diagram of a local area of ​​a display panel 10 according to some embodiments of the present disclosure. The display panel 10 further includes a plurality of first signal lines 71 located on the first surface 1a of the substrate 1. One end of one of the plurality of first signal lines 71 is connected to a front electrode 4 (the first electrode 41 or the second electrode 42) located on the first surface 1a of the substrate 1, and the other end is connected to a pixel unit P located on the first surface 1a of the substrate 1, for transmitting a signal to the pixel unit P to control the pixel unit P to emit light.

[0292] Exemplarily, the first signal line 71 may be located in the first conductive layer 81 , or the first signal line 71 may also be located in the second conductive layer 82 .

[0293] When the first electrode 41 and the second electrode 42 in the front electrode 4 are arranged in different layers, that is, one of the first electrode 41 and the second electrode 42 is located in the first conductive layer 81, and the other is located in the second conductive layer 82. Of the first electrode 41 and the second electrode 42, the one arranged in the same layer as the first signal line 71 can be directly connected to the first signal line 71, and the other can be connected to the first signal line 71 through the via L.

[0294] For example, as shown in FIG20A and in combination with FIG16 , the first electrode 41 is located on the first conductive layer 81, the second electrode 42 is located on the second conductive layer 82, and the first signal line 71 is located on the first conductive layer 81. That is, the first electrode 41 and the first signal line 71 are provided on the same layer, while the second electrode 42 and the first signal line 71 are provided on different layers. The first electrode 41 and the first signal line 71 are directly connected, while the second electrode 42 is connected to the first signal line 71 through a via L.

[0295] In some embodiments, as shown in FIG20B , which is a structural diagram of a partial region of a display panel 10 according to some embodiments of the present disclosure, the display panel 10 further includes a plurality of second signal lines 72 located on the second surface 1 b of the substrate 1. One end of one of the plurality of second signal lines 72 is connected to a back electrode 5 (the third electrode 51 or the fourth electrode 52) located on the second surface 1 b of the substrate 1, and the other end is connected to a circuit board (not shown) for transmitting a control signal output by the circuit board.

[0296] Exemplarily, the second signal line 72 may be located in the third conductive layer 91 , or the second signal line 72 may be located in the fourth conductive layer 92 .

[0297] When the third electrode 51 and the fourth electrode 52 in the back electrode 5 are provided in different layers, that is, one of the third electrode 5 and the fourth electrode 52 is located in the third conductive layer 91, and the other is located in the fourth conductive layer 92. One of the third electrode 5 and the fourth electrode 52 provided in the same layer as the second signal line 72 can be directly connected to the second signal line 72, and the other can be connected to the second signal line 72 through a via L.

[0298] For example, as shown in FIG20B and in combination with FIG16 , the third electrode 51 is located in the third conductive layer 91, the fourth electrode 52 is located in the fourth conductive layer 92, and the second signal line 72 is located in the third conductive layer 91. That is, the third electrode 51 and the second signal line 72 are provided in the same layer, while the fourth electrode 52 and the second signal line 72 are provided in different layers. The third electrode 51 and the second signal line 72 are directly connected, while the fourth electrode 52 is connected to the second signal line 72 through a via L.

[0299] In some embodiments, the above-mentioned pixel unit can be a light-emitting unit, and the light-emitting unit can include an LED. In this case, the above-mentioned display panel 10 can be considered as a light-emitting panel. The various embodiments of the display panel 10 described in the present disclosure, including but not limited to the setting method of the above-mentioned connecting lead 2, the setting method of the front electrode 4 and the setting method of the back electrode 5, the positional relationship between the connecting lead 2 and the front electrode 4 and the pixel unit P, the setting of the recessed area Q, etc. can be applied individually or in full to the light-emitting panel.

[0300] Exemplarily, the above-mentioned light-emitting panel can be used as a backlight source.

[0301] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A substrate comprising a first surface and a second surface disposed opposite to each other, and at least one side surface connecting the first surface and the second surface, wherein the at least one side surface is a selected side surface; a plurality of connecting leads, each of the plurality of connecting leads extending from the first surface, through the selected side surface, to the second surface; The plurality of connection leads include a first connection lead and a second connection lead, wherein the first connection lead and the second connection lead are adjacent to each other in a direction perpendicular to the surface of the substrate and are arranged in different layers.

2. The display panel according to claim 1, wherein Orthographic projections of the first connecting lead and the second connecting lead on the substrate at least partially overlap.

3. The display panel according to claim 1 or 2, wherein: The first connection lead and the second connection lead have different line widths.

4. The display panel according to any one of claims 1 to 3, wherein: The first connecting lead and the second connecting lead transmit different signals.

5. The display panel according to any one of claims 1 to 4, wherein: One of the first connecting lead and the second connecting lead is in contact with the surface of the substrate.

6. The display panel according to any one of claims 1 to 5, wherein: The display panel further includes: A plurality of front electrodes are arranged on one side of the first surface of the substrate; the plurality of front electrodes include a first electrode and a second electrode, and the first electrode and the second electrode are arranged adjacent to each other; A plurality of back electrodes are arranged on one side of the second surface of the substrate; the plurality of back electrodes include a third electrode and a fourth electrode, and the third electrode and the fourth electrode are arranged adjacent to each other; The first connecting lead is used to connect the first electrode and the third electrode; the second connecting lead is used to connect the second electrode and the fourth electrode; The orthographic projections of the first electrode and the third electrode on the second surface at least partially overlap, and the orthographic projections of the second electrode and the fourth electrode on the second surface at least partially overlap.

7. The display panel according to claim 6, wherein: The first electrode and the second electrode are arranged in the same layer, and / or the third electrode and the fourth electrode are arranged in the same layer.

8. The display panel according to claim 7, wherein: One of the first connection lead and the second connection lead is directly connected to the front electrode and the back electrode, and the other is connected to the front electrode and the back electrode through a via hole.

9. The display panel according to claim 6, wherein: The first electrode and the second electrode are arranged in different layers, and the first electrode is closer to the first surface than the second electrode; And / or, the third electrode and the fourth electrode are arranged in different layers, and the third electrode is closer to the second surface than the fourth electrode.

10. The display panel according to claim 8, wherein: The first connecting lead is closer to the substrate than the second connecting lead.

11. The display panel according to claim 9 or 10, wherein: The orthographic projection of the first electrode on the first surface at least partially overlaps with the orthographic projection of the second electrode on the first surface; And / or, the orthographic projection of the third electrode on the second surface at least partially overlaps with the orthographic projection of the fourth electrode on the second surface.

12. The display panel according to any one of claims 6 to 11, wherein: The display panel further includes a plurality of pixel units located on the first surface; The plurality of pixel units include two pixel units that are adjacent to each other in a first direction and are both close to the selected side surface, and the first electrode and the second electrode are disposed between the two pixel units.

13. The display panel according to any one of claims 1 to 12, wherein: The display panel further includes a plurality of pixel units located on the first surface; The plurality of pixel units include two pixel units that are adjacent to each other in a first direction and are both close to the selected side surface, and the first connecting lead and the second connecting lead are disposed between the two pixel units.

14. The display panel according to any one of claims 6 to 11, wherein: The display panel further includes a plurality of pixel units located on the first surface; The plurality of pixel units include two pixel units that are adjacent to each other in a first direction and are both close to the selected side surface, and in a second direction, the first electrode and the second electrode at least partially overlap with the two pixel units; The second direction is perpendicular to the first direction.

15. The display panel according to any one of claims 1 to 14, wherein: The display panel further includes a first insulating layer; The first insulating layer is located between the first connecting lead and the second connecting lead.

16. The display panel according to any one of claims 1 to 15, wherein: The display panel further comprises at least one recessed area located at least on a selected side surface of the substrate; The one of the first connecting lead and the second connecting lead that is closer to the substrate is located on the selected side. The orthographic projection is located within the concave area.

17. The display panel according to claim 16, wherein: A ratio of a size of the recessed area along the first direction to a size of the first connecting lead along the first direction is 1-2.

18. The display panel according to any one of claims 6 to 17, wherein: The display panel further includes a protective layer; the protective layer at least covers the second connecting lead, and the front electrode and the back electrode connected to the second connecting lead.

19. A display device comprising: The display panel according to any one of claims 1 to 18; a circuit board, the circuit board being electrically connected to the display panel; The circuit board is configured to drive the display panel to display an image.

20. A spliced ​​display device comprising a plurality of display panels according to any one of claims 1 to 18 and at least one circuit board; A plurality of the display panels are spliced ​​together, and each of the at least one circuit board is electrically connected to at least one of the display panels.

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