Processor and instruction scheduling method and electronic device

Abstract

The application provides a processor, an instruction scheduling method and an electronic device. The processor comprises an instruction sending module, a scoring module and an execution module connected with each other. The instruction sending module sends the corresponding hazard information of the executable instruction to the scoring module, and sends the corresponding decoding information of the executable instruction to the execution module. The scoring module writes the hazard information received in the last clock cycle into a target entry in a target table entry, and marks the target entry as an effective state. When the hazard information received in the last clock cycle has corresponding conflict hazard information, the scoring module modifies the conflict hazard information into an invalid state, and sends a cancellation signal to a conflict execution unit. The destination register corresponding to the conflict hazard information is the same as the destination register corresponding to the hazard information received in the last clock cycle. Through skipping the redundant write operation, the waiting time of the instruction execution is reduced, and the instruction execution efficiency and the overall performance of the processor are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chips, in particular to a processor and an instruction scheduling method and an electronic device. BACKGROUND

[0002] In a modern sequential processor pipeline, a write after write (WAW) conflict refers to the overlapping of write operations of multiple instructions on the same register target address in time. Such a conflict may cause the write result of a subsequent instruction to be incorrectly overwritten or lost, thereby causing a data inconsistency problem. To solve the WAW conflict, the prior art mainly relies on hardware scheduling and instruction rearrangement mechanisms.

[0003] When a WAW conflict is detected, the prior art suspends the execution of subsequent instructions until the previous instruction completes the write operation. This suspension mechanism causes the pipeline to be idle, and the operation unit and other hardware resources cannot be fully utilized, resulting in resource waste. Due to the need to suspend the execution of subsequent instructions and wait for the previous instruction to complete the write operation, the execution delay of subsequent instructions increases, affecting the overall performance of the processor, especially in high concurrency and high load scenarios, the performance decline is more obvious. SUMMARY

[0004] The purpose of the present application is to provide a processor and an instruction scheduling method and an electronic device to improve the above problems.

[0005] To achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0006] In a first aspect, the embodiments of the present application provide a processor, which comprises an instruction emission module, a scoring module and an execution module connected to each other;

[0007] When an executable instruction is acquired in a current clock cycle, the instruction emission module is configured to send adventure information corresponding to the executable instruction to the scoring module, and send decoding information corresponding to the executable instruction to the execution module;

[0008] Wherein, the executable instruction is a microcode instruction satisfying a write condition of the scoring module, and the adventure information includes a destination register identifier of the microcode instruction;

[0009] After entering the current clock cycle, the scoring module is configured to write the adventure information received in the last clock cycle into a target entry in a target table item, and mark the target entry as an effective state;

[0010] When the received conflict information in the last clock cycle exists corresponding conflict information, the scoring module is further configured to modify the conflict information into an invalid state, and send a cancel signal to a conflict execution unit;

[0011] The conflict information is the information in the scoring module in a valid state, and the destination register corresponding to the conflict information is the same as the destination register corresponding to the received information in the last clock cycle, and the conflict execution unit is the execution unit corresponding to the conflict information in the execution module.

[0012] Optionally, the instruction emitting module includes N decoding slots;

[0013] The n-th decoding slot is configured to decode the microcode instruction obtained in the current clock cycle, and send decoding information to the scoring module;

[0014] The decoding information includes an execution period corresponding to the microcode instruction, an execution unit identifier, a source register identifier, and a destination register identifier;

[0015] The scoring module is configured to identify whether the corresponding microcode instruction meets the write condition according to the decoding information sent by the n-th decoding slot in the current period, and feed back the identification result to the n-th decoding slot;

[0016] When the identification result is that the write condition is met, the scoring module is configured to cache the decoding information;

[0017] When the identification result is that the write condition is met, the n-th decoding slot is configured to send the decoding information corresponding to the executable instruction to the execution module.

[0018] Optionally, the scoring module includes a first score board, and the first score board includes K+1 table entries, and each table entry includes N record entries;

[0019] After entering the current clock cycle, the first score board is configured to write the conflict information sent by the n-th decoding slot received in the last clock cycle into the n-th record entry in a target table entry, and mark it as a valid state;

[0020] When the execution period of the microcode instruction is X, the target table entry is the X+1 table entry, and X is less than or equal to K;

[0021] After entering the current clock cycle, the first score board is further configured to move the record entry in the k-th table entry in a valid state to the corresponding record entry in the k-1 table entry, and mark it as a valid state.

[0022] Optionally, when receiving the decoding information of the nth decoding slot sent in the current period, the scoring module is configured to estimate whether the nth record entry in the target entry is in an occupied state in the next clock period;

[0023] If the nth record entry in the target entry is estimated to be in an idle state in the next clock period, the scoring module is configured to determine whether there is a risk conflict;

[0024] If there is no risk conflict, the scoring module is configured to determine that the identification result is that the microcode instruction obtained by the nth decoding slot in the current period satisfies the write condition;

[0025] If there is a risk conflict, the scoring module is configured to determine that the identification result is that the microcode instruction obtained by the nth decoding slot in the current period does not satisfy the write condition.

[0026] Optionally, if the nth record entry in the target entry is in an idle state in the next clock period, the scoring module is configured to determine whether the execution unit in the decoding information is the same as the occupied execution unit recorded in the scoring module, and if so, it is determined that there is a risk conflict.

[0027] Optionally, if the nth record entry in the target entry is in an idle state in the next clock period, the scoring module is configured to determine whether the source register in the decoding information is the same as the occupied register recorded in the scoring module, and if so, it is determined that there is a risk conflict.

[0028] Optionally, if the nth record entry in the target entry is in an idle state in the next clock period, the scoring module is configured to determine whether the destination register in the decoding information is a vector register or a floating point register;

[0029] If it is a vector register or a floating point register, the scoring module is configured to determine whether the destination register in the decoding information is the same as the occupied register recorded in the scoring module, and if so, it is determined that there is a risk conflict.

[0030] Optionally, the scoring module further comprises a second score board, and the second score board comprises a state flag bit of each destination register;

[0031] When it is determined that the microcode instruction corresponding to the ith record entry in the kth entry in the active state is an indefinite period instruction, the second score board is further configured to modify the state flag bit corresponding to the destination register in the ith record entry in the kth entry to an occupied state; and the first score board is further configured to erase the ith record entry in the kth entry;

[0032] The second scoreboard is configured to modify a state flag of a destination register corresponding to the completed non-deterministic period instruction to an idle state when receiving the non-deterministic period instruction completion indication.

[0033] The first scoreboard is configured to write the completed non-deterministic period instruction corresponding to the conflict information into the Ith record entry in the first table entry, where I represents a decoding slot number corresponding to the non-deterministic period instruction.

[0034] In a second aspect, an embodiment of the present application provides an instruction scheduling method applied to the processor, and the method comprises the following steps:

[0035] When an executable instruction is acquired in a current clock cycle, the instruction sending module sends conflict information corresponding to the executable instruction to the scoring module, and sends decoding information corresponding to the executable instruction to the execution module.

[0036] The executable instruction is a microcode instruction satisfying a write condition of the scoring module, and the conflict information comprises a destination register identifier of the microcode instruction.

[0037] After entering the current clock cycle, the scoring module writes the conflict information received in a previous clock cycle into a target entry in a target table entry, and marks the target entry as an effective state.

[0038] When the conflict information received in the previous clock cycle exists, the scoring module is further configured to modify the conflict information to an invalid state, and send a cancel signal to a conflict execution unit.

[0039] The conflict information is conflict information in an effective state in the scoring module, and a destination register corresponding to the conflict information is the same as a destination register corresponding to the conflict information received in the previous clock cycle, and the conflict execution unit is an execution unit corresponding to the conflict information in the execution module.

[0040] In a third aspect, an embodiment of the present application provides an electronic device comprising the processor.

[0041] Compared with the prior art, the processor, the instruction scheduling method and the electronic device provided by the embodiment of the present application have the following advantages: the processor comprises an instruction transmitting module, a scoring module and an execution module which are connected with each other; the instruction transmitting module sends the hazard information corresponding to the executable instruction to the scoring module, and sends the decoding information corresponding to the executable instruction to the execution module; the scoring module writes the hazard information received in the last clock cycle into a target entry in a target table item, and marks the target entry as an effective state; when the hazard information received in the last clock cycle has corresponding conflict hazard information, the scoring module modifies the conflict hazard information into an invalid state, and sends a cancel signal to a conflict execution unit, and the destination register corresponding to the conflict hazard information is the same as the destination register corresponding to the hazard information received in the last clock cycle. By skipping the redundant write operation, the waiting time of the instruction execution is reduced, so that the instruction execution efficiency and the overall performance of the processor are improved. In particular, in a high concurrency scenario, the instruction execution delay can be significantly reduced, and the throughput of the processor is improved.

[0042] In order to make the above objectives, characteristics and advantages of the present application more apparent, the following preferred embodiments are specifically described below, and the accompanying drawings are referred to for a detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0044] Figure 1 The architecture schematic diagram of the processor provided by the embodiment of the present application.

[0045] Figure 2 The architecture schematic diagram of the scoring module provided by the embodiment of the present application.

[0046] Figure 3 The architecture schematic diagram of the scoring module provided by the embodiment of the present application.

[0047] Figure 4 The architecture schematic diagram of the scoring module provided by the embodiment of the present application.

[0048] Figure 5 The architecture schematic diagram of the scoring module provided by the embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0051] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0052] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0053] In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly placed when the product of the present application is used, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0054] In the description of the present application, it is also necessary to explain that, unless otherwise explicitly specified and limited, the terms "set", "connected" should be understood broadly, for example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0055] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0056] The processor provided by the embodiments of the present application reduces the waiting time of instruction execution by skipping redundant write operations, thereby improving the efficiency of instruction execution and the overall performance of the processor. In particular, in a high concurrency scenario, the instruction execution delay can be significantly reduced, and the throughput of the processor can be improved.

[0057] Please refer to Figure 1 , Figure 1 The architecture schematic diagram of the processor provided by the embodiments of the present application is shown.

[0058] The processor comprises an instruction emission module, a score module and an execution module connected with each other.

[0059] The instruction emission module is connected with the score module and the execution module respectively, and the score module is connected with the execution module.

[0060] When the instruction emission module obtains an executable instruction in the current clock cycle, the instruction emission module is configured to send the hazard information corresponding to the executable instruction to the score module in the current clock, and send the decoding information corresponding to the executable instruction to the execution module.

[0061] Optionally, a relay register is arranged between the instruction emission module and the execution module, the decoding information is written into the relay register in the current clock cycle, and the execution module obtains the decoding information in the next clock cycle.

[0062] The executable instruction is a microcode instruction satisfying the write condition of the score module, and the hazard information comprises a destination register identifier and an execution unit identifier of the microcode instruction.

[0063] After entering the current clock cycle, the score module is configured to write the hazard information received in the last clock cycle into a target entry in a target table item, and mark the target entry as an effective state.

[0064] When the received conflict information in the last clock cycle exists corresponding conflict information, the scoring module is further configured to modify the conflict information into an invalid state, and send a cancel signal to the conflict execution unit to reset to an idle state, so as to release the execution unit and not execute the conflict instruction corresponding to the conflict information.

[0065] The conflict information is the information in the scoring module (previously written) in the valid state, and the destination register corresponding to the conflict information is the same as the destination register corresponding to the received information in the last clock cycle. The conflict execution unit is the execution unit corresponding to the conflict information in the execution module.

[0066] When the microcode instruction corresponding to the conflict information is marked as an invalid state, the microcode instruction does not need to be executed.

[0067] In the embodiment of the application, by dynamically canceling the redundant write operation, the write stage of the conflict instruction is directly skipped, and the pipeline idle caused by waiting for the completion of the previous instruction is avoided. The continuity of instruction execution is significantly improved, especially in a high conflict scenario (such as loop calculation).

[0068] After the redundant instruction is canceled, the occupied operation unit and register resource can be immediately released for subsequent instruction reuse. For example, in long-period operation (such as division), the operation unit does not need to wait for the completion of the conflict instruction, thereby improving the overall utilization rate of hardware resources.

[0069] For indefinite period instructions (such as division, cache miss memory loading), the cancel operation can be triggered at any stage of execution. For example, the state machine of the division instruction can be emptied, and the memory loading instruction can be canceled before the bus request, thereby avoiding the performance bottleneck caused by long-period instructions.

[0070] Compared with the traditional scheme relying on a complex scheduler (such as a reorder buffer), the simplified score board structure and light weight state clearing logic reduce the occupation of hardware resources. At the same time, reducing the pipeline idle period can significantly reduce the dynamic power consumption.

[0071] Please continue to refer to Figure 1 The processor can further include an instruction fetching module, a storage module, and a register module. The instruction fetching module is connected with the instruction emitting module, and is configured to fetch instructions and send the fetched instructions to the instruction emitting module.

[0072] The execution module is connected with the storage module and the register module, and can read corresponding data from the storage module, execute corresponding instructions, and write the execution result of the instructions into the destination register in the register module.

[0073] Optionally, the register module is also connected with an instruction emitting module, and the instruction emitting module can call the data in the register module.

[0074] On the basis of the foregoing, the present embodiment also provides an optional implementation for determining whether the microcode instruction obtained in the current clock cycle is executable or not according to the record information and the decoding information in the score module. Details are described below.

[0075] The instruction emitting module includes N decoding slots.

[0076] The nth decoding slot is used for decoding the microcode instruction obtained in the current clock cycle and sending the decoding information to the score module.

[0077] The decoding information includes the execution cycle corresponding to the microcode instruction, the execution unit identifier, the source register identifier and the destination register identifier.

[0078] The score module is used for identifying whether the corresponding microcode instruction meets the write-in condition according to the decoding information sent by the nth decoding slot in the current cycle, and feeding back the identification result to the nth decoding slot.

[0079] When the identification result is that the write-in condition is met (the microcode instruction is executable), the score module is used for buffering the decoding information, and writing the hazard information in the target entry into the target entry in the next clock cycle.

[0080] When the identification result is that the write-in condition is met, the nth decoding slot is used for sending the decoding information corresponding to the executable instruction to the execution module, and the execution module obtains the decoding information in the next clock cycle.

[0081] If the identification result is that the write-in condition is not met, the microcode instruction is not executable, and the score module does not need to buffer, and receives the decoding information again in the next clock cycle and judges again.

[0082] On the basis of the foregoing, the present embodiment also provides an optional implementation for the structure of the score module. Please refer to Figure 2 and Figure 3 , Figure 2 Fig. 1 is a schematic diagram of the architecture of the score module provided by the present embodiment, Figure 3 Fig. 2 is another schematic diagram of the architecture of the score module provided by the present embodiment. The score module under the VLIW architecture includes a first score board (also referred to as a main score board), and the first score board includes K+1 table items (K is the maximum execution cycle of the pipelined instruction), each table item includes N groups of record entries, and N is the total number of decoding slots in the processor.

[0083] In the accompanying drawings provided in the embodiments of the present invention, K=2 and N=4 are used as examples for illustration, but are not intended to be limiting.

[0084] Upon entering the current clock cycle, the first scoreboard is used to write the hazard information received from the nth decoder slot in the previous clock cycle into the nth record entry (target entry) in the target table and mark it as valid, 1≤n≤N.

[0085] When the execution cycle of the microcode instruction is X, the target entry is the (X+1)th entry, where X is less than or equal to K.

[0086] Please refer to Figure 2 The execution cycle of the hazard information sent by the 3rd decoding slot is 1, so its corresponding target entry is the 2nd entry. The execution cycle of the hazard information sent by the 1st, 2nd, and 3rd decoding slots is 2, so their corresponding target entries are the 3rd entries.

[0087] Optionally, when the nth decoding slot sends the hazard information in the previous clock cycle, it has already determined that in the next clock cycle (i.e., the current clock cycle), the nth record entry in the target table is in an idle state and there is no hazard conflict in the microcode instruction.

[0088] After entering the current clock cycle, the first scoreboard is also used to move the record entry that is in a valid state in the k-th entry to the corresponding record entry in the (k-1)-th entry and mark it as valid.

[0089] Optionally, a shift register is used to move the valid record entry in the k-th entry to the corresponding record entry in the (k-1)-th entry. The n-th record entry in the k-th entry corresponds to the n-th record entry in the (k-1)-th entry, where 2 ≤ k ≤ K+1. Optionally, the K entries can be moved simultaneously, or the movement can start from k=2 and continue until k=K+1.

[0090] like Figure 3 As shown, Figure 3 The corresponding previous clock cycle is Figure 2 As shown, in the current clock cycle, the valid record entries in the third entry can be moved to their corresponding entries in the second entry, and the valid record entries in the second entry can be moved to their corresponding entries in the first entry. Simultaneously, the hazard information received from the nth decoder slot in the previous clock cycle will be written to the nth record entry in the target entry. For example... Figure 3 In the previous clock cycle, the execution cycle corresponding to the hazard information sent by the nth decoding slot is 2, so it is written into the 4th record entry in the 3rd table.

[0091] In the scoring module of the VLIW architecture provided in this embodiment of the invention, the number of cycles in which a pipelined instruction is executed in the execution unit is dynamically represented by the entry number. This design can efficiently track the execution status of instructions and dynamically update write-back information. This is the core of the scoring board design, which significantly simplifies the hardware logic and supports the execution management of both indeterminate-cycle instructions and pipelined instructions, thereby improving hardware efficiency and instruction execution throughput. Managing hazard information through the first scoring board is convenient, fast, and accurate, which is beneficial to the efficient operation of the processor.

[0092] Please refer to Figure 4 , Figure 4 This is the third schematic diagram of the scoring module architecture provided in an embodiment of the present invention. Figure 4 As shown, the scoring module also includes a second scoring board (also known as an indefinite-cycle instruction scoring board), which includes status flag bits for each destination register. Figure 4 The example uses M destination registers for illustration.

[0093] When the microcode instruction corresponding to the i-th record entry in the k-th entry is determined to be an indefinite periodic instruction, the second scoreboard is also used to modify the status flag bit corresponding to the destination register in the i-th record entry in the k-th entry to the occupied state; the first scoreboard is also used to erase (or modify to the invalid state) the i-th record entry in the k-th entry, 1≤i≤N.

[0094] Please refer to Figure 5 , Figure 5 The fourth schematic diagram of the scoring module provided in the embodiment of the present invention. Figure 5 and Figure 3 For example, within the same clock cycle, taking the microcode instruction corresponding to the second record entry in the third entry, which is in a valid state, as an indefinite-period instruction. After writing the hazard information received from the nth decoder slot in the previous clock cycle into the nth record entry in the target entry, the first scoring board erases (or modifies) the second record entry in the third entry to an invalid state. The second scoring board is also used to modify the status flag bit corresponding to the destination register in the second record entry of the third entry to an occupied state.

[0095] In one alternative implementation, the second scoreboard is used to modify the status flag bit of the destination register corresponding to the completed indefinite period instruction to an idle state when it receives an indefinite period instruction completion indication.

[0096] The first scoreboard is used to write the hazard information corresponding to the completed indefinite periodic instruction into the I-th record entry in the first table when it receives the indefinite periodic instruction completion indication, where I represents the decoding slot number corresponding to the indefinite periodic instruction.

[0097] In an alternative embodiment, after entering the current clock cycle, the first scoreboard is further configured to erase all the entries recorded in the first table entry (or modify the invalid state), and after erasing, the valid entries in the second table entry are moved to the first table entry. The erasing of the first table entry is the earliest action after the current clock cycle.

[0098] In the embodiment of the present application, the first scoreboard (main scoreboard) and the second scoreboard (variable period instruction scoreboard) work together to improve the instruction correlation detection capability. Specifically, a double-layer structure design of the main scoreboard and the variable period instruction scoreboard is adopted. When the instruction cannot be confirmed as a variable period instruction at the decoding stage, it is first recorded in the main scoreboard; after confirmation at the execution stage, it is moved to the variable period instruction scoreboard, and returned to the main scoreboard until the end of execution. This dynamic instruction life cycle management method realizes accurate detection of instruction correlation. The processing of variable period instructions is more flexible, effectively solving the execution delay problem caused by the inability to distinguish variable period instructions in the traditional scheme. It reduces the conflict risk of register resource occupation and optimizes the pipeline performance. It enhances the support capability of multi-instruction correlation detection and scheduling in the out-of-order execution scenario. It solves the problem of variable period instruction and pipeline instruction correlation detection, dynamically adjusts the instruction scheduling process, and reduces the performance loss caused by conflicts.

[0099] Optionally, when receiving the decoding information sent by the nth decoding slot in the current period, the scoring module is configured to estimate whether the nth record entry in the target table entry is in an occupied state in the next clock cycle.

[0100] If the nth record entry in the target table entry is in an occupied state in the next clock cycle, the scoring module is configured to determine that the identification result is that the microcode instruction obtained by the nth decoding slot in the current period does not meet the write-in condition.

[0101] If the nth record entry in the target table entry is in an idle state in the next clock cycle, the scoring module is configured to determine whether there is an adventure conflict.

[0102] If there is no adventure conflict, the scoring module is configured to determine that the identification result is that the microcode instruction obtained by the nth decoding slot in the current period meets the write-in condition.

[0103] If there is an adventure conflict, the scoring module is configured to determine that the identification result is that the microcode instruction obtained by the nth decoding slot in the current period does not meet the write-in condition.

[0104] Optionally, if the nth record entry in the target table entry is in an idle state in the next clock cycle, the scoring module is configured to determine whether the execution unit in the decoding information is the same as the occupied execution unit recorded by the scoring module, and if they are the same, it is determined that there is an adventure conflict.

[0105] Optionally, if the n-th record entry in the target table entry is idle in the next clock cycle, the score module is configured to determine whether the source register in the decoded information is the same as the occupied register recorded in the score module, and if so, determine that there is a hazard conflict.

[0106] Optionally, if the n-th record entry in the target table entry is idle in the next clock cycle, the score module is configured to determine whether the destination register in the decoded information is a vector register or a floating point register (if not a vector register and a floating point register, the destination register is not considered in the process of determining the hazard conflict).

[0107] If it is a vector register or a floating point register, the score module is configured to determine whether the destination register in the decoded information is the same as the occupied register recorded in the score module, and if so, determine that there is a hazard conflict.

[0108] When the destination register in the decoded information is not a vector register and a floating point register, if the execution unit in the decoded information is different from the occupied execution unit recorded in the score module, and the source register in the decoded information is different from the occupied register recorded in the score module, it can be determined that there is no hazard conflict.

[0109] When the destination register in the decoded information is a vector register or a floating point register, if the execution unit in the decoded information is different from the occupied execution unit recorded in the score module, and the source register in the decoded information is different from the occupied register recorded in the score module, and the destination register in the decoded information is different from the occupied register recorded in the score module, it can be determined that there is no hazard conflict.

[0110] In the processor provided in the embodiment of the present application, if instruction 1 and instruction 2 write to the same destination register, instruction 2 will cause the table entry in the score board occupied by instruction 1 to be cleared, and the information of instruction 2 is written into the score module. At the same time, the state of the instruction in the execution unit needs to be erased. Since the timing of instruction 2 may be different, a cancellation mechanism needs to be set in each stage of instruction execution. Typical scenarios include division instructions and memory load instructions.

[0111] Division instruction: in some CPUs, the implementation of the division instruction is indefinite period. If there is no write-after-write cancellation mechanism, the subsequent instruction needs to wait for multiple periods until the division instruction is executed. For the division instruction implemented based on a state machine, the state of the state machine needs to be cleared when write-after-write cancellation occurs.

[0112] Memory load instruction: when the cache unit is not hit, the memory load instruction can need several cycles to complete. Before the instruction is sent to the bus, it can be canceled by the write-after-write signal, thus avoiding unnecessary waiting.

[0113] It should be noted that not all types of instructions can be canceled by the write-after-write. A typical example is the floating point operation instruction, which can change the exception flag at the end of the operation, that is, it can change the state of the processor. If this change of state is canceled by the subsequent instruction, it can cause instruction flow error.

[0114] The embodiment of the present application also provides an instruction scheduling method, which can be applied to the processor described above but is not limited to the processor.

[0115] S101, when the executable instruction is acquired in the current clock cycle, the instruction sending module sends the adventure information corresponding to the executable instruction to the scoring module, and sends the decoding information corresponding to the executable instruction to the execution module;

[0116] The executable instruction is the microcode instruction meeting the write condition of the scoring module, and the adventure information includes the destination register identifier of the microcode instruction.

[0117] S102, after entering the current clock cycle, the scoring module writes the adventure information received in the last clock cycle into the target entry in the target table item, and marks the target entry as an effective state;

[0118] S103, when the adventure information received in the last clock cycle exists corresponding conflict adventure information, the scoring module is also used for modifying the conflict adventure information to an invalid state, and sending a cancel signal to the conflict execution unit;

[0119] The conflict adventure information is the adventure information in the effective state in the scoring module, and the destination register corresponding to the conflict adventure information is the same as the destination register corresponding to the adventure information received in the last clock cycle. The conflict execution unit is the execution unit corresponding to the conflict adventure information in the execution module.

[0120] It should be noted that the instruction scheduling method provided by the embodiment can perform the functions and purposes shown in the device embodiment to achieve the corresponding technical effects. For brevity, the part not mentioned in the embodiment can refer to the corresponding content in the above embodiment.

[0121] The embodiment of the present application also provides an electronic device, which includes the processor described above.

[0122] In summary, the processor and instruction scheduling method and electronic device provided by the embodiments of the present application, the processor comprises an instruction transmitting module, a scoring module and an execution module connected with each other; the instruction transmitting module sends the hazard information corresponding to the executable instruction to the scoring module, and sends the decoding information corresponding to the executable instruction to the execution module; the scoring module writes the hazard information received in the last clock cycle into the target entry in the target table item, and marks the target entry as an effective state; when the hazard information received in the last clock cycle has corresponding conflict hazard information, the scoring module modifies the conflict hazard information to an invalid state, and sends a cancel signal to the conflict execution unit, the destination register corresponding to the conflict hazard information is the same as the destination register corresponding to the hazard information received in the last clock cycle. By skipping the redundant write operation, the waiting time of instruction execution is reduced, thereby improving the instruction execution efficiency and the overall performance of the processor. Especially in a high concurrency scenario, the instruction execution delay can be significantly reduced, and the throughput of the processor can be improved.

[0123] The preferred embodiments of the present application have been described above with the preferred embodiments, but the present application is not limited to the above and can be variously changed and modified by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0124] It is apparent for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, but can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as exemplary and non-restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to encompass all changes falling within the meaning and range of equivalents of the claims. Any reference signs in the claims should not be considered as limiting the involved claims.

Claims

1. A processor, comprising: The processor comprises an instruction emission module, a score module and an execution module connected with each other; When an executable instruction is acquired in a current clock cycle, the instruction emission module is configured to send the corresponding hazard information of the executable instruction to the score module, and send the corresponding decoding information of the executable instruction to the execution module; The executable instruction is a microcode instruction satisfying a write condition of the score module, and the hazard information comprises a destination register identifier of the microcode instruction; After entering the current clock cycle, the score module is configured to write the hazard information received in a previous clock cycle into a target entry in a target table item, and mark the target entry as an effective state; When the hazard information received in the previous clock cycle exists corresponding conflict hazard information, the score module is further configured to modify the conflict hazard information as an invalid state, and send a cancel signal to a conflict execution unit; The conflict hazard information is hazard information in an effective state in the score module, and the conflict hazard information corresponds to a destination register same as a destination register corresponding to the hazard information received in the previous clock cycle, and the conflict execution unit is an execution unit corresponding to the conflict hazard information in the execution module.

2. The processor of claim 1, wherein, The instruction emission module comprises N decoding slots; The nth decoding slot is configured to decode a microcode instruction acquired in a current clock cycle, and send decoding information to the score module; The decoding information comprises an execution period, an execution unit identifier, a source register identifier and a destination register identifier corresponding to the microcode instruction; The score module is configured to identify whether the corresponding microcode instruction satisfies the write condition according to the decoding information sent by the nth decoding slot in the current period, and feed back the identification result to the nth decoding slot; When the identification result is that the write condition is satisfied, the score module is configured to cache the decoding information; When the identification result is that the write condition is satisfied, the nth decoding slot is configured to send the corresponding decoding information of the executable instruction to the execution module.

3. The processor of claim 2, wherein, The score module comprises a first score board, and the first score board comprises K+1 table items, and each table item comprises N groups of record entries; After entering the current clock cycle, the first score board is configured to write the hazard information sent by the nth decoding slot in the previous clock cycle into the nth record entry in a target table item, and mark the nth record entry as an effective state; When the execution period of the microcode instruction is X, the target table item is an (X+1)th table item, and X is less than or equal to K; After entering the current clock cycle, the first score board is further configured to move the record entry in an effective state in a kth table item to a corresponding record entry in a (k-1)th table item, and mark the corresponding record entry as an effective state.

4. The processor of claim 3, wherein When the decoding information sent by the nth decoding slot in the current period is received, the score module is configured to estimate whether the nth record entry in the target table item is in an occupied state in a next clock cycle; If the n-th record entry in the target table entry is idle in the next clock cycle, the scoring module is configured to determine whether there is a hazard conflict; If there is no hazard conflict, the scoring module is configured to determine that the identification result is that the microcode instruction fetched by the n-th decode slot in the current cycle satisfies the write condition; If there is a hazard conflict, the scoring module is configured to determine that the identification result is that the microcode instruction fetched by the n-th decode slot in the current cycle does not satisfy the write condition.

5. The processor of claim 4, wherein, if the n-th record entry in the target table entry is idle in the next clock cycle, the scoring module is configured to determine whether the execution unit in the decode information is the same as the occupied execution unit recorded in the scoring module, and if so, determine that there is a hazard conflict.

6. The processor of claim 4, wherein, if the n-th record entry in the target table entry is idle in the next clock cycle, the scoring module is configured to determine whether the source register in the decode information is the same as the occupied register recorded in the scoring module, and if so, determine that there is a hazard conflict. If the n-th record entry in the target table entry is idle in the next clock cycle, the scoring module is configured to determine whether the destination register in the decode information is a vector register or a floating point register; If it is a vector register or a floating point register, the scoring module is configured to determine whether the destination register in the decode information is the same as the occupied register recorded in the scoring module, and if so, determine that there is a hazard conflict.

7. The processor of claim 4, wherein, The scoring module further comprises a second score board, and the second score board comprises a state marker bit of each destination register; When it is determined that the microcode instruction corresponding to the i-th record entry in the k-th table entry in the active state is an indefinite period instruction, the second score board is further configured to modify the state marker bit corresponding to the destination register in the i-th record entry in the k-th table entry to an occupied state; and the first score board is further configured to erase the i-th record entry in the k-th table entry; 8. The processor of claim 3, wherein, The second score board is configured to modify the state marker bit of the destination register corresponding to the completed indefinite period instruction to an idle state when receiving an indefinite period instruction completion indication; The first score board is configured to write the hazard information corresponding to the completed indefinite period instruction into the i-th record entry in the first table entry, where i represents the decode slot number corresponding to the indefinite period instruction. The method is applied to the processor of any one of claims 1 to 8, and the method comprises: When an executable instruction is fetched in a current clock cycle, an instruction launch module sends hazard information corresponding to the executable instruction to a scoring module, and sends decode information corresponding to the executable instruction to an execution module; 9. An instruction scheduling method, characterized by, The executable instruction is a microcode instruction satisfying a write condition of the scoring module, and the hazard information comprises a destination register identifier of the microcode instruction; After entering the current clock cycle, the scoring module writes hazard information received in a previous clock cycle into a target entry in a target table, and marks the target entry as active. ​ ​ When the received conflict information in the last clock cycle exists corresponding conflict information, the scoring module is further configured to modify the conflict information to an invalid state, and send a cancel signal to a conflict execution unit; The conflict information is the conflict information in the scoring module in the valid state, and the destination register corresponding to the conflict information is the same as the destination register corresponding to the received conflict information in the last clock cycle, and the conflict execution unit is the execution unit corresponding to the conflict information in the execution module.

10. An electronic device, comprising: A processor as claimed in any one of claims 1 to 8.

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