Server starting method, electronic device, and storage medium

Abstract

The application discloses a server starting method, an electronic device and a storage medium. The method comprises the following steps: after receiving a server starting instruction, a basic input and output system is controlled to enter a hardware initialization stage; a target mainboard configuration of a server mainboard is identified according to a pin state of a group of pins of a general input and output interface; and a target link configuration table matched with the target mainboard configuration is automatically found from a link configuration table set. In other words, in the case that the mainboard configuration of the server mainboard changes, the link configuration information matched with each mainboard configuration can be automatically adapted according to the pin state value of the general input and output interface. The technical problem of high complexity in the process of adapting bus link configuration information for different mainboard configurations in the prior art is solved, and the technical effect of improving the starting efficiency of the server is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a server starting method, an electronic device and a storage medium. BACKGROUND

[0002] In the existing server hardware configuration management, the lanes of the HSIO (High Speed I / O) bus of the server mainboard are usually configured according to the predefined hardware layout in the design stage. The configuration information is fixed in the management engine of the server.

[0003] However, the processing mode of the bus link configuration information can only meet the default hardware configuration of the server mainboard. When the type and hardware layout of the hardware components of the server mainboard change, the BIOS (Basic Input Output System) image needs to be recompiled, and the bus link configuration information needs to be manually updated in the management engine to adapt to the new hardware layout. Not only a lot of time is consumed, but also the complexity of the configuration process is increased, and the starting time of the server under the condition of the change of the hardware layout is also increased, which causes the technical problem of low efficiency in the server starting process. SUMMARY

[0004] The present application provides a server starting method, an electronic device and a storage medium to at least solve the problem of low efficiency in the server starting process under the condition of the change of the hardware layout in the related art.

[0005] According to an aspect of an embodiment of the present application, a server starting method is provided, including: in response to a starting instruction of a server, controlling a basic input output system of the server to enter a hardware initialization stage; determining a target mainboard configuration of a server mainboard based on a pin state of a general input output interface, wherein the target mainboard configuration includes a type of a hardware component, and the type of the hardware component includes at least one of a serial interface hard disk, a solid state disk, a graphics processor and a modular network device; searching for a target link configuration table matched with the target mainboard configuration from a link configuration table set, wherein the link configuration table set is used to describe link configuration information matched with different mainboard configurations obtained by signal multiplexing on an actual number of transmission links supported by a central processing unit; and starting the server based on link configuration information in the target link configuration table.

[0006] According to another aspect of the embodiments of the present application, a server starting device is also provided, comprising: a control unit configured to control a basic input / output system of the server to enter a hardware initialization stage in response to a starting instruction of the server; a first processing unit configured to determine a target motherboard configuration of a motherboard of the server based on a pin state of a general input / output interface, wherein the target motherboard configuration comprises types of hardware components, and the types of hardware components comprise at least one of a serial interface hard disk, a solid state disk, a graphic processor and a modular network device; a first searching unit configured to search for a target link configuration table matched with the target motherboard configuration from a link configuration table set, wherein the link configuration table set is used to describe link configuration information matched with different motherboard configurations by signal multiplexing on an actual number of transmission links supported by a central processing unit; and a starting unit configured to start the server based on link configuration information in the target link configuration table.

[0007] According to still another aspect of the embodiments of the present application, an electronic device is also provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute steps of any of the server starting methods by using the computer program.

[0008] According to still another aspect of the embodiments of the present application, a computer readable storage medium is also provided, wherein the computer readable storage medium stores a computer program, and the computer program is configured to execute steps of any of the server starting methods when running.

[0009] According to still another aspect of the embodiments of the present application, a computer program product or a computer program is provided, comprising computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to make the computer device execute steps of any of the server starting methods.

[0010] According to the above embodiments of the present application, in a server starting process, a basic input / output system is controlled to enter a hardware initialization stage, a motherboard configuration of a motherboard of the server is determined based on a pin state of a general input / output interface, and target link configuration information capable of meeting a hardware configuration of a current motherboard of the server is searched from a link configuration table set based on the motherboard configuration. In other words, when facing diversified server hardware configurations, only the pin state of the general input / output interface is used to quickly determine a target motherboard configuration and search for an adaptive target link configuration table. The allocation of HSIO bus Lane and the bandwidth splitting of transmission links are simplified, the configuration time is reduced, and the technical effect of improving the starting efficiency of the server is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0012] Figure 1 It is an application scenario diagram of a server starting method according to an embodiment of the present application.

[0013] Figure 2 It is a flow diagram of an optional server starting method according to an embodiment of the present application.

[0014] Figure 3 It is a physical design diagram of an optional server motherboard according to an embodiment of the present application.

[0015] Figure 4 It is an optional HSIO link connection diagram according to an embodiment of the present application.

[0016] Figure 5 It is an optional HSIO resource allocation diagram under different hardware configurations according to an embodiment of the present application.

[0017] Figure 6 It is a whole flow diagram of an optional server starting method according to an embodiment of the present application.

[0018] Figure 7 It is a swim lane diagram of an optional server starting method according to an embodiment of the present application.

[0019] Figure 8 It is a structural block diagram of an optional server starting device according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0021] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0022] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] According to one aspect of the embodiments of this application, a server startup method is provided. Optionally, in this embodiment, the above-described server startup method may be applied to, but is not limited to, [examples of applications such as...]. Figure 1 In the hardware scenario shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0024] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the server startup method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the server device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0025] The transmission device 106 is configured to receive or send data via a network. The network can include a wireless network provided by a communication service provider of the server device. In one example, the transmission device 106 includes a network interface controller (NIC) that can be connected to other network devices through a base station to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0026] The embodiments of the present application can be applied to the scenario of quickly adapting the HSIO bus lane multiplexing setting according to different hardware requirements under the condition of hardware configuration change of the server motherboard, but are not limited thereto. In order to facilitate understanding, specific examples of several application scenarios are given below.

[0027] (1) Multi-configuration server management in data centers: In a large-scale data center environment, servers may need to be replaced with different hardware configurations due to changes in load requirements, such as changing from a storage-intensive configuration to a compute-intensive configuration. The technical solution of the present application allows operations and maintenance personnel to set the jumper cap through simple GPIO (General-purpose input / output) pins, without the need for physical disassembly of hardware or recompilation of BIOS images, to quickly reconfigure the server motherboard, simplifying the hardware configuration process of the server.

[0028] (2) Dynamic allocation of cloud computing resources: In a cloud environment, user demand for computing resources is dynamically changing. By automatically identifying CPU (Central Processing Unit) models and HSIO bus lane numbers, the technical solution of the present application dynamically adjusts the bandwidth splitting and port enablement of PCI (Peripheral Component Interconnect) links to ensure that cloud servers can adjust hardware resources according to real-time requirements, achieving efficient use of resources and rapid response.

[0029] (3) Flexible deployment of edge computing devices: Edge computing devices often need to run in different physical environments and network conditions. The technical solution of the present application allows devices to adapt to different edge application requirements through software configuration updates without changing the hardware, such as increasing or decreasing storage, network interfaces, or adjusting PCI link bandwidth allocation, providing convenience for on-site upgrade and configuration change of edge computing devices.

[0030] (4) Server security and compliance enhancement: During the use of the server, it is crucial to prevent illegal configuration and ensure hardware compliance. The technical solution of the present application can ensure that the server BIOS image corresponds to the motherboard one by one by introducing the GPIO verification mechanism, effectively preventing unsupported hardware configuration, enhancing the security and stability of the server, and facilitating quick verification of server hardware configuration information in compliance checks.

[0031] By applying the technical solution of the present application to the above scenarios, not only the problems in traditional server configuration management are solved, but also technical support is provided for efficient and flexible deployment of servers.

[0032] The server startup method of the present application embodiment can be executed by the server device, or by the server device in combination with at least one of the terminal device (which can also be understood as the input / output device 108). Wherein, the terminal device executing the server startup method of the present application embodiment can also be executed by the client installed thereon.

[0033] Taking the server startup method in the present embodiment executed by the server as an example, Figure 2 is a flowchart of an optional server startup method according to the present application embodiment, as Figure 2 shown, the flow of the method can include steps S202 to S208.

[0034] Step S202, in response to the startup instruction of the server, the basic input / output system of the server enters the hardware initialization phase.

[0035] Step S204, based on the pin state of the general input / output interface, determine the target motherboard configuration of the server motherboard, wherein the target motherboard configuration includes the type of hardware components, and the type of hardware components includes at least one of serial interface hard disk, solid state disk, graphics processor and modular network device.

[0036] Step S206, find the target link configuration table matching the target motherboard configuration from the link configuration table set, wherein the link configuration table set is used to describe the link configuration information matched with different motherboard configurations by signal multiplexing on the actual number of transmission links supported by the central processing unit.

[0037] Step S208, based on the link configuration information in the target link configuration table, start the server.

[0038] In the related art, in order to improve the peripheral device utilization rate of the CPU, the PCI link can be set to multiple modes, such as a USB (Universal Serial Bus) mode, a SATA (Serial ATA, an interface of a storage device) mode, and a PCI mode. That is, one PCI link mode can be set to multiple non-PCI link modes. However, there is a technical problem that in the configuration interface of the ME (Management Engine), the Lane (transmission link or link) of the HSIO bus is set to a PCI link, a USB link, or a SATA link according to the requirements of hardware design. Meanwhile, when the PCI link is set, different bandwidths such as x8 or x4x4, x4x2x2, x2x2x4, x2x2x2x2 can be set according to the bandwidth requirements of the PCI link.

[0039] If the HSIO bus is not used, it is set to an Unused state. When the HSIO is set to a SATA device interface, the HSIO bus Lane needs to be set to a SATA interface mode. If the SATA mode is not used, it is set to an "SATA mode not set state". For the HSIO bus lane set to a PCI link, the port for controlling the PCI link needs to be enabled, and then the opening and enabling of the PCI link port are set according to the specific splitting situation. If there is only one configuration of the motherboard of the server, the above solution does not have any technical problems. However, if the hardware configuration of the motherboard of the server changes or the link changes, the configuration of the ME needs to be adjusted and re-adapted to meet the setting of the HSIO link of the server. In this way, different hardware configurations of different server motherboards need different ME configurations, and it is impossible to realize the setting and application of multiple HSIO parameters through one BIOS image.

[0040] That is, for the multi-form server motherboard, each hardware configuration needs a separate BIOS image and ME configuration file, which increases the complexity and cost of the management and maintenance of the server hardware. Meanwhile, the starting efficiency of the server is also reduced.

[0041] Since the HSIO bus supported by the CPU usually contains 20 HSIO bus lanes, and each lane is a multiplex signal, which can be used as a PCI link or a non-PCI link, such as a SATA link interface, a USB link interface, etc. Therefore, when configuring the ME, it needs to be configured and used according to the design of the hardware. For example, Lane0-lane7 of the HSIO link is set as a PCI link, Lane8-Lane9 is set as a PCI link network card device, Lane10-lane11 is set as a PCI link BMC management chip, Lane12-lane13 is set as a SATA link interface, Lane14-Lane15 is not used and is set as Unused, Lane16 is set as a USB link interface, i.e., a USB device, and Lane17-lane19 is not used and is set as Unused.

[0042] Since each PCI link can be multiplexed as a SATA interface link, and Lane12-lane13 of the HSIO link has been set as a SATA interface, Lane12 and Lane13 are set as a SATA link in the setting of the SATA interface, and the other lanes are set as non-SATA links. The above is only the setting of the Lane of the HSIO link, and the split setting of the set PCI link is not performed. For the split setting of the PCI link, since it contains two x8 PCI link controllers, Lane0-lane7 of the HSIO bus is set as a PCI link with x8 bandwidth, so only the first controller of the PCI link is enabled and RP0 is set as enabled. RP1-RP3 need to be closed, because RP0 can be used as an x8 enable control or as an x4, x2 enable setting, and Lane8-lane15 of the HSIO bus is a C1 controller of the PCI link and needs to be set as enabled, because it contains two x2 and four lanes that are not used, so it is set as an x2x2x4 mode, i.e., RP4, RP5, and RP6 are set as enabled, and RP7 is set as closed. The above is the default link configuration information of the ME, but the default link configuration information can only support the setting of a fixed HSIO bus lane link. If other configurations occur, the ME needs to be reconfigured or multiple BIOS images need to be compiled to realize arbitrary changes of different configurations.

[0043] In order to solve this problem, in the configuration of multiple types of link configuration information, the code level of BIOS is designed to dynamically support multiple different link configuration information. For example, when four types of link configuration information appear, the four types of link configuration information can be set as four link configuration tables in the form of a configuration table. According to the reading of GPIO or sensitive key information to confirm the specific configuration of the server motherboard, the corresponding configuration information is loaded, and the loaded configuration table is replaced or covered to the setting information in the ME.

[0044] The technical solution of the present application is an improved solution to solve the above problems. Before explaining the technical solution of the present application, the meanings of the professional terms or professional names involved are first introduced.

[0045] HSIO bus Lane: refers to the transmission link on the high-speed input / output bus provided by the CPU. Each Lane can be configured as different signal types such as PCI, USB, SATA, etc.

[0046] General-purpose input / output interface (GPIO): an input / output pin that can be controlled by software, used for hardware configuration identification and verification.

[0047] Link configuration table set: a set of HSIO bus Lane configuration information under multiple server motherboard configurations, which is indexed by the GPIO state (state value, such as high or low level) to select the appropriate link configuration table.

[0048] In the present embodiment, the physical design of the server motherboard can be but not limited to as shown in Figure 3 The components in Figure 3 are briefly described below.

[0049] CPU: high-speed data exchange with various devices through HSIO link. HSIO contains 20 lanes, each lane can be multiplexed as PCIe (point-to-point serial link), SATA, USB, etc. Different signal types to support diversified peripheral device requirements.

[0050] ME (Management Engine): built-in in the CPU, responsible for the power-on management, remote management and other functions of the server. ME initializes and controls the basic hardware resources of the server by reading the preset configuration information such as the signal type of the HSIO bus link and the bandwidth allocation.

[0051] BIOS (Basic Input / Output System): the startup program of the server, responsible for detecting the hardware state when the server starts, loading the correct ME configuration, and ensuring that the server starts as expected.

[0052] SATA Interface: Interface link for connecting SATA storage devices. Specific lanes in HSIO (e.g., Lane 12-Lane 13) are configured as SATA signals to enable data read / write functions for storage devices.

[0053] PCI Slots: Expansion card devices that support PCIe links, such as network cards, RAID (Redundant Array of Independent Disks) cards, NVMe hard drives (Non-Volatile Memory Express solid state drives), etc. Through dynamic splitting and bandwidth allocation of the HSIO link, different PCI slots can be configured as x8, x4, or x2 PCIe links as needed to meet the bandwidth requirements of different devices.

[0054] USB Interface: Used to connect USB devices such as keyboards, mice, external storage, etc. Lane 16 in the HSIO bus is configured as a USB signal to ensure the normal use of USB devices.

[0055] BMC (Baseboard Management Controller): Responsible for the out-of-band management and monitoring of the server. Specific lanes in HSIO (e.g., Lane 10-Lane 11) are configured as PCIe links to support BMC, allowing BMC to work independently of the main CPU and operating system.

[0056] GPIO (General Purpose Input / Output Interface): Used to read critical information such as Board ID (server motherboard board identification) to identify different motherboard configurations. By detecting the state of GPIO, the server can determine the model of the motherboard at startup, load the corresponding link configuration information, and even perform a shutdown process when configuration information cannot be determined to ensure hardware safety.

[0057] LPC (Low Pin Count) / SPI (Serial Peripheral Interface) / PCI: Provides a low-speed communication link between the BMC management chip and other components on the motherboard, ensuring that the management functions of the server can continue to operate even if the network is disconnected.

[0058] The various hardware components are closely connected through the carefully designed HSIO link, forming a complex signal transmission network. For example, Lane0-Lane7 and Lane8-Lane15 of HSIO are configured as PCIe links, supporting x8 and x2x2x2x2 or x2x2x4 bandwidth modes, respectively. Lane12-Lane13 are specially configured as SATA signals, and Lane16 carries USB signals. In addition, the enable and disable state of the HSIO bus Lane, the bandwidth splitting condition, etc. are adjusted through the link configuration information dynamically loaded by BIOS, ensuring that the server can run stably under various hardware configurations. Finally, through the verification function of GPIO, the server can ensure the compatibility of its hardware configuration with the BIOS image, avoid the access of illegal hardware, and enhance the overall security of the server.

[0059] It should be noted that the above "x8" represents a bandwidth configuration mode of a PCI Express (PCIe) link, specifically indicating that the link is configured with 8 data transmission channels. The PCI Express standard allows the link to operate with different numbers of data channels, and the number of these data channels is usually represented by "x" followed by a number, such as x1, x2, x4, x8, etc. The larger the number, the faster the data transmission speed.

[0060] When the server motherboard design needs to support multiple hardware configurations, the x8 bandwidth configuration mode allows the flexibility of HSIO link splitting. For example, an x8 link can be split into two x4 links or four x2 links to adapt to different peripheral requirements. This splitting and reconfiguration capability, combined with the dynamically loaded configuration information in the BIOS system, enables the server to intelligently adapt to different hardware environments without the need for physical changes to the hardware or recompilation of the BIOS image, improving the deployment efficiency of the server and the compatibility of the device.

[0061] In the implementation process of the technical scheme of the present application, after the server receives a start instruction, the BIOS will first identify the model of the CPU, which is crucial for determining the number of HSIO bus Lanes that the CPU can support.

[0062] For ease of understanding, in this embodiment, the HSIO link connection diagram shown in Figure 4 is taken as an example to explain and describe the technical scheme of the present application.

[0063] As shown in Figure 4As shown, assuming that the current CPU model supports 20 lanes of the HSIO bus, each lane is a multiplex signal, which can be used as a PCI link or a non-PCI link such as a SATA link interface, a USB link interface, etc. Therefore, during ME configuration, the hardware design needs to be configured for use, such as setting Lane0-lane7 of the HSIO link as a PCI link, setting Lane8-Lane9 as a PCI link for network card device use, setting Lane10-lane11 as a PCI link for BMC management chip use, setting Lane12-lane13 as a SATA link interface, setting Lane14-Lane15 as Unused, setting Lane16 as a USB link interface (USB device), and setting Lane17-lane19 as Unused. Since each PCI link can be multiplexed as a SATA interface link, and Lane12-lane13 of the HSIO link has been set as a SATA interface, Lane12 and Lane13 are set as a SATA link in the SATA interface setting, and the other lanes are set as non-SATA link interfaces.

[0064] After determining the target motherboard model (which can also be understood as a target motherboard configuration or a target motherboard hardware configuration) according to the state combination of the pins of the GPIO, the target link configuration table is found from the link configuration table set according to the target motherboard configuration. The BIOS has a link configuration table set stored in advance, and each configuration table corresponds to a motherboard configuration. According to the target motherboard configuration, the BIOS loads the corresponding target link configuration table from the configuration table set.

[0065] Finally, the BIOS uses the information in the target link configuration table to update the configuration of the HSIO bus Lane, including but not limited to the number of lanes, bandwidth splitting, etc. After the configuration is completed, the server will start according to the new settings, ensuring that all hardware components can work normally.

[0066] As can be seen from the above description, in the related art, the setting of the HSIO bus Lane is mainly set as a multiplex signal in the ME configuration according to the scheme designed by the hardware engineer, such as setting as SATA, PCI, USB, Unused, etc. After the HSIO bus is set as a SATA function, the corresponding HSIO bus lane is allocated to the SATA interface, and the non-SATA interface lane is set as a non-SATA mode. At the same time, the lane signal allocated from the HSIO bus to the PCI bus is set in the bandwidth splitting and splitting port enable of the controller in the PCI part, so as to realize the function of ME configuration management of the HSIO bus Lane.

[0067] But the defect in the related art is that only one configuration of the HSIO bus Lane can be implemented, and the HSIO bus setting cannot be dynamically adjusted after the motherboard configuration is changed or the CPU is replaced. Therefore, in the PEI (hardware initialization) stage of the BIOS code, various possible link configuration information is determined, such as HSIO bus Lane reduction or use of part of the HSIO bus Lane, or Lane allocated to SATA needs to be closed, HSIO bus Lane needs to be closed and not used, or the HSIO bus Lane needs to be allocated to the PCI link and the bandwidth splitting needs to be reset, or part of the port or the split port is closed, etc. These can be set through the static variable table set in the BIOS code.

[0068] Meanwhile, in order to ensure the safety and reliability of the server motherboard, two groups of GPIOs are introduced, one group of GPIOs is used to determine whether the motherboard configuration is a motherboard supporting the CPU model, and if not, a shutdown process is performed; and the other group of GPIOs is used to determine which configuration the current motherboard needs to support, and different link configuration information is loaded according to the combination of the GPIOs to confirm the combination of different motherboard configurations. The combination of GPIOs here can be extended to more than 4 groups, one of which is the default ME configuration, and the confirmed configuration information can also be updated to the ME configuration to overwrite the initial settings in the ME. If the motherboard has many configurations, the GPIO settings can be adjusted through the jumper cap to adjust the use of different configurations, without changing the type of hardware motherboard and CPU to achieve the change and switching of any configuration, which is convenient and fast. The use process of the two groups of GPIOs will be described in detail below in combination with specific embodiments.

[0069] Through the embodiments of the present application, not only the management process of the server hardware configuration is simplified, but also the flexibility of the system is improved, so that a single BIOS image can adapt to diversified hardware combinations, the maintenance cost and time loss caused by hardware changes are reduced, and the security of the system is also enhanced, the use of illegal configuration is effectively prevented through the verification of the GPIO state, and the stable operation of the server and the safety of the data are ensured.

[0070] In an exemplary embodiment, determining a target motherboard configuration of a server motherboard based on a pin state of a general-purpose input / output interface includes: determining a board card identifier of the server motherboard based on the pin state of the general-purpose input / output interface, wherein a mapping relationship exists between a motherboard configuration of the server motherboard, the board card identifier, and a link configuration table in a link configuration table set; and determining the target motherboard configuration of the server motherboard based on the board card identifier.

[0071] As can be known from the above description, different types of CPUs can support different numbers of HSIO bus lanes, or the same number of HSIO bus lanes but different signal types and bandwidth information of each lane. For example, 20 HSIO bus lanes can be supported, while other types can only support 16 or 12.

[0072] The BIOS determines the actual number of HSIO bus lanes supported by the CPU according to the type of the CPU. For example, 20. At the same time, the preset number of HSIO bus lanes set in the ME is queried (i.e., the preset number). In the case where the actual number and the preset number are inconsistent, the target motherboard configuration of the server motherboard is determined according to the pin state of the general-purpose input / output interface (i.e., GPIO).

[0073] In an optional example, before determining the target motherboard configuration of the server motherboard based on the pin state of the general-purpose input / output interface, the above method further comprises: reading the processor type of the central processor; determining the actual number of transmission links of the data transmission bus supported by the central processor based on the processor type; in the case where the actual number and the preset number of transmission links set in the management engine of the server are inconsistent, determining the motherboard configuration of the server motherboard based on the pin state of the general-purpose input / output interface.

[0074] That is, when the server starts, the type of the central processor on the server motherboard is read in advance, and the actual number of HSIO bus lanes supported by the central processor under the current type is obtained according to the processor type.

[0075] The actual number is compared with the preset number of HSIO bus lanes set in the management engine, and in the case where they are inconsistent, the state of the input / output interface is read, and the motherboard configuration of the server motherboard is determined according to the GPIO pin state.

[0076] In the case where the target motherboard configuration of the server motherboard determined according to the GPIO pin state is not the default motherboard configuration, the target link configuration table matching it is found from the link configuration table set.

[0077] Generally, according to different combinations of the level state (high or low) of two or more GPIO pins, a plurality of board card identifications are determined, and each GPIO pin state corresponds to a board card identification. Then the BIOS system reads a set of preset GPIO pin states. Different combinations of these GPIO pin states are associated with a plurality of motherboard configurations on the server motherboard.

[0078] Each board card identifier indicates a type of motherboard configuration, which means that a mapping relationship or index relationship between the motherboard configuration of the server motherboard and the board card identifier needs to be created in advance.

[0079] After obtaining the board card identifier, the BIOS system uses this information to search in the preset mapping table to determine the target motherboard configuration. The mapping table records in detail the specific motherboard configuration corresponding to different board card identifiers. For example, the 0x00 board card identifier described in the above embodiment corresponds to the motherboard configuration with 4 NVMe, and 0x01 corresponds to the motherboard configuration with 4 SATA hard disks.

[0080] In this embodiment, by reading the state of the GPIO pin, the specific board card identifier installed on the server motherboard is identified. After obtaining the board card identifier, the system will determine the corresponding target motherboard configuration through the mapping table. The target motherboard configuration indicates the specific hardware configuration of the server motherboard, such as the layout and number of PCIe, SATA, USB, etc. interfaces.

[0081] Specifically, as shown in Figure 3 According to the high / low level state of GPIO4 and GPIO5, Board ID (board card identifier) in 4 different combination states is formed, and the 4 different board card identifiers are used to indicate 4 different motherboard configurations (which can also be understood as the hardware configuration or hardware layout of the server motherboard).

[0082] For example, the board card identifier is 0x00 or 00, indicating a 4NVME configuration (motherboard + base plate + 4NVME board card); the board card identifier is 0x01 or 01, indicating a 4SATA configuration (motherboard + base plate + 4SATA board card); the board card identifier is 0x10 or 10, indicating a 3.5HDD (Hard Disk Drive, hard disk drive) configuration (motherboard + base plate + 3.5HDD board card); the board card identifier is 0x11 or 11, indicating a CPU+OCP (Open Compute Project, open computing project) configuration (motherboard + base plate + 3.5HDD board card), etc.

[0083] Obviously, Figure 3 As shown in the combination of the states of the 4 GPIO pins, indicating 4 different motherboard configurations is only an example and is not limited thereto.

[0084] In another optional embodiment, the above reading of the processor model of the central processor includes: in response to a start instruction of a server, controlling a basic input and output system of the server to perform a hardware initialization task; by executing the hardware initialization task, reading the processor model of the central processor.

[0085] When the server receives the start instruction, the BIOS system enters the PEI phase and performs a series of hardware initialization tasks. These tasks include, but are not limited to, CPU memory detection, peripheral detection, system clock setting, etc., to ensure that the server system can start in a stable hardware environment.

[0086] For example, when the server is ready to start, the BIOS system first detects whether the memory module is connected normally, then initializes the PCI bus, checks the status of each PCI device, and ensures that the network card, storage device, etc. can operate normally.

[0087] During the execution of the initialization task, the BIOS system reads the processor model of the CPU. This information is crucial for determining the hardware configuration of the server and the available range of HSIO bus lanes. For example, when the server starts, the BIOS detects that the CPU model is Model 1, and this model of server supports 20 HSIO bus lanes, of which the first 8 can be configured as PCIe x8, and the rest can be configured as SATA, USB, or other non-PCIe links. After obtaining this information, the BIOS can accurately load the HSIO configuration that matches the CPU model.

[0088] As can be seen, during the initialization task, the BIOS reads and confirms the processor model of the CPU, which will be used to determine the number and configurable range of HSIO bus lanes, and to load the corresponding link configuration information.

[0089] Through the hardware initialization tasks performed by the BIOS system, the server can automatically identify and adapt to the current hardware configuration, including the processor model, so as to load the correct HSIO bus lane settings at startup, providing a foundation for subsequent dynamic link adjustment.

[0090] By performing hardware initialization and reading the processor model during the server startup phase, it is ensured that the system can make corresponding configuration adjustments based on the latest hardware information of the server motherboard, enhancing the compatibility and adaptability of the server to different hardware configurations, and improving the overall running efficiency and performance.

[0091] By parsing the GPIO pin state to determine the board card identification, and combining the CPU model, the target configuration type of the server motherboard can be intelligently matched, and the appropriate link configuration table can be dynamically selected from a single BIOS image. This mechanism avoids the tedious process of frequently updating the BIOS image due to changes in hardware configuration, simplifies the configuration management of the server, and improves the operation and maintenance efficiency of the data center. At the same time, it also ensures the stability and compatibility of the server under different hardware combinations, provides a technical foundation for dynamic adjustment of hardware resources, and effectively meets the diversified needs of server application scenarios.

[0092] In one example embodiment, the determining the board card identification of the server motherboard based on the pin state of the general input and output interface comprises: reading a first state value of a first pin in the general input and output interface; reading a second state value of a second pin in the general input and output interface; and determining the board card identification of the server motherboard based on the first state value and the second state value.

[0093] As described in the above embodiments, as shown in Figure 3 According to the high / low of the level state of GPIO4 and GPIO5, four different combination states of Board ID (board card identification) are formed, and the four different board card identifications are used to indicate four different motherboard configurations.

[0094] For example, when GPIO4 and GPIO5 are both low, a first combination is formed according to the level state of the two pins, that is, the first board card identification is 0x00 or 00; when GPIO4 is low and GPIO5 is high, a second combination is formed, that is, the second board card identification is 0x01 or 01; when GPIO4 is high and GPIO5 is low, a third combination is formed, that is, the third board card identification is 0x10 or 10; and when GPIO4 and GPIO5 are both high, a fourth combination is formed, that is, the fourth board card identification is 0x11 or 11.

[0095] By creating a mapping relationship between each board card identification and a preset motherboard configuration, each board card identification can indicate a motherboard configuration. For example, 0x00 represents a 4NVME configuration (motherboard+baseboard+4NVME board card); 0x01 represents a 4SATA configuration (motherboard+baseboard+4SATA board card); 0x10 represents a 3.5HDD configuration (motherboard+baseboard+3.5HDD board card); 0x11 represents a CPU+OCP configuration (motherboard+baseboard+3.5HDD board card); and so on.

[0096] Obviously, the above-described combination mode of the level state of GPIO4 and GPIO5 two pins to determine the mapping relationship between the board card identification and the motherboard configuration is only one example, and is not limited thereto.

[0097] The board identification is an abstraction of the server motherboard hardware configuration, including the specific layout and quantity of PCIe, SATA, and USB interfaces. The board identification is also used to select the most suitable link configuration table from a preset link configuration table set for loading. The link configuration table describes in detail how to allocate the HSIO bus Lane, split the PCI link bandwidth, and turn on or off the corresponding interface port according to the specific hardware configuration on the server motherboard. Finally, the BIOS system will complete the effective configuration of the HSIO bus Lane based on the selected link configuration table, ensuring that the server can start smoothly according to the current hardware layout and provide the required network and storage capabilities, without the need to recompile and compile the BIOS image every time the hardware changes.

[0098] Through fine GPIO state reading, the server motherboard configuration is quickly identified and dynamically matched, and the hardware layout is determined. The inconvenience of frequent updating of the BIOS image due to changes in the hardware configuration in the past is solved, the time required for motherboard configuration identification and adjustment is shortened, and the response speed and flexibility of the server in the face of diversified deployment scenarios are improved.

[0099] In an exemplary embodiment, the above-mentioned searching for a target link configuration table matching the target motherboard from a link configuration table set includes: comparing the target hardware configuration information indicated by the target motherboard configuration with the default hardware configuration information to obtain a target comparison result; and in the case where the target comparison result indicates that the target hardware configuration information is inconsistent with the default hardware configuration information, searching for the target link configuration table matching the target motherboard configuration from the link configuration table set.

[0100] Assuming that the default hardware configuration information of the server is stored in the configuration file of the BIOS, which contains different hardware layouts and hardware types. The default hardware configuration information in the ME queried is compared with the target hardware configuration information to obtain a target comparison result.

[0101] If the comparison result shows that the hardware configuration information is inconsistent, the BIOS system will query the link configuration table set.

[0102] In addition, it can also be assumed that the configuration file of the BIOS also contains default link configuration information, for example, it contains a set of default allocation information of HSIO bus Lane, such as Lane0 to Lane15 allocated to PCIe link, Lane16 and Lane17 allocated to USB link. When the server starts, the BIOS system will first read the target hardware configuration information according to the GPIO state, and then find the link configuration table having a mapping relationship with the target hardware configuration information.

[0103] By comparing the link configuration information in the link configuration table with the default link configuration information in the ME, if they are inconsistent, the target link configuration table matching the target motherboard configuration is found from the link configuration table set.

[0104] By comparing the target hardware configuration information with the default hardware configuration information, the system can intelligently identify the hardware configuration difference and automatically select the matching link configuration table, realizing the dynamic optimization allocation of the server hardware resources. The tedious process of frequently modifying the BIOS image due to the hardware layout change is effectively avoided, the configuration adaptation time is shortened, and the flexibility of the server in the face of diversified hardware combinations is enhanced.

[0105] In an exemplary embodiment, the above finding of the target link configuration table matching the target motherboard configuration from the link configuration table set comprises: based on the mapping relationship between the target motherboard configuration and the link configuration table in the link configuration table set, the target link configuration table is found.

[0106] In this embodiment, by maintaining the mapping relationship between the motherboard configuration, the board card identifier and the link configuration table in the link configuration table set of the server motherboard, these link configuration information and the motherboard configuration are one-to-one corresponding, forming a fast finding and positioning mechanism.

[0107] Among them, all possible motherboard configurations and corresponding link configuration tables are included. For example, for the 4NVME configuration motherboard A, its link configuration table may indicate that the HSIO bus Lane[7:0] is allocated to the PCIe link, and Lane[13:12] is allocated to the SATA interface; while for the 4SATA configuration motherboard B, the link configuration table may show that the HSIO bus Lane[7:0] is split into a mixed layout of SATA and PCIe links, etc. The mapping relationship can be saved in a database table or an array structure, by one-to-one corresponding these link configuration information and the motherboard configuration, the purpose of quickly finding the link configuration information adapted to different motherboard configurations is realized.

[0108] That is, as long as the motherboard configuration of the current server is determined, the target link configuration table matching the motherboard configuration can be quickly found by using the above mapping relationship. This process does not need to traverse the entire configuration table set, but directly realizes the accurate finding of the target link configuration table according to the key parameter of the motherboard configuration.

[0109] By using the above pre-created mapping relationship, the target link configuration table matching the target motherboard configuration can be quickly found. This finding process is efficient and accurate, ensuring that the system can immediately apply the configuration information most suitable for the current hardware layout, without searching in the configuration table set, and improving the response speed of the system to the hardware configuration change.

[0110] In one example embodiment, the above-mentioned searching the target link configuration table from the link configuration table set matching the target motherboard configuration comprises: reading a third state value of a third pin in a general input-output interface; reading a fourth state value of a fourth pin in the general input-output interface; determining a configuration table identifier of each link configuration table in the link configuration table set based on the third state value and the fourth state value; searching a target configuration table identifier consistent with the target board card identifier from the configuration table identifier based on the target board card identifier corresponding to the target motherboard configuration; and searching the target link configuration table from the link configuration table set based on the target configuration table identifier, wherein the target motherboard configuration, the target board card identifier and the link configuration table in the link configuration table set have a mapping relationship, and the target configuration table identifier and the target link configuration table have a one-to-one correspondence.

[0111] When the server starts and enters the PEI (hardware initialization) phase, the system first reads the third pin in the GPIO and records its third state value. Assume that the state value of the pin is 0.

[0112] Then the fourth pin of the GPIO is read and its fourth state value is recorded. If the fourth pin state value is 1, a specific configuration table identifier is constructed in combination with the read value of the third pin.

[0113] For example, as shown in Figure 3 Fig. 1, assuming that the third pin is GPIO0 and the fourth pin is GPIO1, the configuration table identifier is 0x00 or 00 in the case of the third state value and the fourth state value being both 0; the configuration table identifier is 0x01 or 01 in the case of the third state value being 0 and the fourth state value being 1; the configuration table identifier is 0x10 or 10 in the case of the third state value being 1 and the fourth state value being 0; and the configuration table identifier is 0x11 or 11 in the case of the third state value and the fourth state value being both 1.

[0114] As can be known from the above description in the example embodiment, the motherboard configuration of the server motherboard, the board card identifier and the link configuration table in the link configuration table set have a mapping relationship. Then, according to the target board card identifier corresponding to the target motherboard configuration in the above example embodiment, the target configuration table identifier consistent with the target board card identifier is searched from the configuration table identifier.

[0115] The target link configuration table is searched from the link configuration table set according to the target configuration table identifier. The target board card identifier is determined through the state values of the first pin and the second pin described in the above example embodiment. Here, no further description is given.

[0116] That is, through the state values of the third and fourth pins of the GPIO, the system can determine a unique configuration table identifier for each link configuration table, which is used to find the target link configuration table. The system uses the mapping relationship between the configuration table identifier and the target motherboard configuration to accurately match the target configuration table identifier that matches the target motherboard hardware layout. Finally, based on the target configuration table identifier, the corresponding target link configuration table is quickly located and loaded, realizing dynamic adjustment and optimized configuration of the server hardware resources.

[0117] It should be noted that for the same motherboard configuration, the values of the board card identifier and the configuration table identifier can be the same or different, which is not limited in the embodiment.

[0118] In the embodiment, through the combination of the GPIO state value and the link configuration table identifier, and the mapping relationship between the configuration table identifier and the motherboard configuration, the system can quickly and accurately find the link configuration information suitable for the current hardware layout, avoiding the time-consuming and complexity brought by traditional manual configuration, and improving the startup efficiency of the server and the utilization efficiency of the hardware resources.

[0119] In an exemplary embodiment, the above method further comprises that at least one of the values of the plurality of parameters contained in any two link configuration tables in the link configuration table set is different: the number of transmission links of the data transmission bus, bandwidth splitting information, configuration information of the transmission link, bandwidth length, and state information of the bandwidth splitting port.

[0120] Assuming that the four possible motherboard configurations described in the above embodiment are still taken as an example for explanation and description. And assuming that in the HSIO resource allocation process, the allocation of HSIO[19:8] is fixed, and the allocation of HSIO[7:0] is flexible according to different motherboard configurations. Among them, HSIO[19:8] represents the 8th~19th lane of the HSIO bus as shown in Figure 4 HSIO[7:0] represents the 0th~7th lane of the HSIO bus.

[0121] For the board card identifier 0x00 or 00, it means that the hardware configuration of the current server motherboard is 4NVME configuration (motherboard+baseboard+4NVME board card); the board card identifier 0x01 or 01 means 4SATA configuration (motherboard+baseboard+4SATA board card); the board card identifier 0x10 or 10 means 3.5HDD configuration (motherboard+baseboard+3.5HDD board card); the board card identifier 0x11 or 11 means CPU+OCP configuration (motherboard+baseboard+3.5HDD board card), etc.

[0122] The configuration information in the link configuration table matched with the above four motherboard configurations in the link configuration table set can be set in the following manner, but not limited thereto. For details, refer to Figure 5 The configuration result is shown in the following table.

[0123] (1) 4NVME configuration: HSIO[7:0] is divided into PCIe x8 and is divided into 4 x4 through PCIe switch.

[0124] PCIe x8 means that 8 lanes are combined to form a PCIe interface with a bandwidth of x8. The PCIe switch re-distributes or splits the input PCIe signal to obtain the split 4 x4, that is, the original x8 PCIe signal is split into 4 independent x4 PCIe links, and each x4 PCIe link has sufficient bandwidth to support an NVMe SSD (Non-Volatile Memory Express Solid State Drive). Therefore, through this splitting method, the server can simultaneously connect and efficiently access 4 high-speed NVMe SSDs.

[0125] (2) 4SATA configuration: HSIO[7:0] is divided into [7:4] SATA x4, and HSIO[3:0] is divided into PCIe x4.

[0126] The 4th to 7th lanes of the HSIO bus are configured for the use of SATA interfaces, and are divided into a SATA x4 interface. SATA x4 means that the 4 lanes are integrated into a group to form a SATA interface, which can provide higher bandwidth and data transmission rate than the traditional SATA interface. Usually, a SATA interface only has one lane, but in this configuration, 4 lanes are used to provide greater bandwidth to meet the needs of high-speed SATA storage devices.

[0127] At the same time, HSIO[3:0] divided into PCIe x4 means that the 0th to 3rd lanes are reserved for building a PCIe x4 interface. PCIe is a high-speed serial computer expansion bus standard that can be used to connect various types of high-speed peripheral devices such as graphics cards, network cards, and RAID cards. By configuring these 4 lanes as PCIe x4, the server can maintain at least one high-speed PCIe slot for installing additional PCIe devices to expand computing, storage, or network functions.

[0128] In summary, the 4SATA configuration is a hybrid configuration in which 4 lanes of HSIO are used to create a high-speed SATA x4 interface to support 4 SATA storage devices, while the other 4 lanes are used to build a high-speed PCIex4 interface to maintain the PCIex4 interface expansion capability of the server. This configuration flexibly balances the storage and expansion requirements while maximizing the utilization of CPU resources.

[0129] (3) 3.5 HDD configuration: HSIO[7:0] is divided into [7:4] HDDx4 and [3:0] PCIEx4.

[0130] The first 8 lanes of HSIO (HSIO[7:0]) are allocated as two different interface types, HDD and PCIe, specifically, the 4th to 7th lanes are configured to support high-speed transmission HDD interface links, marked as HDDx4, and these 4 lanes are combined to provide a larger data transmission bandwidth for a SATA device. 3.5-inch hard drives generally require higher data transmission rates, so using HDDx4 can meet the performance requirements of large-capacity hard drives.

[0131] At the same time, the 0th to 3rd lanes are reserved and configured as a PCIex4 interface to support high-performance PCIe devices, such as RAID cards, network adapters, or other high-speed I / O expansion cards.

[0132] The above configuration ensures that the server has a hard drive link HDD interface while also retaining PCIe expansion capability, allowing additional PCIe devices to be installed to enhance the functionality of the server. This design allows the server to effectively balance the performance requirements of storage and external devices, and is particularly suitable for application scenarios that require large hard drive storage space but cannot compromise PCIe expansion. By reasonably allocating the lanes of the HSIO bus, the server can dynamically adjust its I / O resources without changing hardware to adapt to different business and workload requirements.

[0133] (4) GPU + OCP configuration: HSIO[7:0] is allocated as PCIex8 and divided into 2 x8 through a PCIe switch.

[0134] Among them, HSIO[7:0] refers to the first 8 lanes of the HSIO bus, and these 8 lanes are uniformly configured as a PCIe interface to connect various high-performance peripheral devices. x8 indicates that this interface has a transmission capacity of 8 lanes and can provide a higher data transmission bandwidth.

[0135] The 8-lane PCIex8 interface is further divided into two independent PCIex8 interfaces through a PCIe switch or a conversion switch. The role of the PCIe switch is to route and exchange signals between multiple PCIe devices, thereby enabling multiple devices to share PCIe bus resources. In the GPU+OCP configuration, a single PCIex8 interface is split into two x8 interfaces through a PCIe switch chip, which can be used to connect GPUs and other high-performance PCIe devices such as network interface cards or storage devices.

[0136] In this way, the server can efficiently support two high-speed PCIex8 devices in the case of limited physical HSIO resources. This configuration not only improves the server's support for graphics-intensive tasks, but also increases its flexibility and scalability in high-performance computing, machine learning, and data center fields. In particular, in the case of resource shortages, the effective use and dynamic configuration of resources through the PCIe switch meet the high-bandwidth, low-latency device connection requirements.

[0137] It should be noted that the configuration parameters in the above link configuration table include but are not limited to the number of HSIO bus lanes, bandwidth splitting, HSIO link settings, SATA link settings, bandwidth splitting port enable or disable settings, and bandwidth length settings.

[0138] Among them, the bandwidth splitting information will change according to the hardware requirements. In the x8 bandwidth requirement, all lanes may be allocated as a single PCIe link; while in the x4x2x2 mode, the same number of lanes will be split into three links, each with a bandwidth of x4, x2, and x2. The difference in bandwidth splitting details in each configuration table, such as the combination of Lane allocation to different bandwidth links, is a key parameter for the system to identify different hardware configuration requirements.

[0139] Each Lane may be configured as PCIe, SATA, USB, or Unused in different hardware configurations. For example, Lane12 may be part of a PCIe link in a 4NVME configuration, and may be configured as a SATA link in a 4SATA configuration. The difference in this configuration information ensures that the system can accurately apply the corresponding link settings for different hardware layouts.

[0140] The bandwidth length parameter reflects the maximum data transmission rate that the link can support. For example, in a PCIe x8 link, the bandwidth length is 8, while in a PCIe x4 link, the bandwidth length is 4. This parameter change directly affects the performance and resource utilization efficiency of the server, and is a key for the system to switch between different configurations.

[0141] In addition to the bandwidth split mode, the state (enabled or closed) of the port also affects the resource allocation of the link. For example, in the x8 mode, all RPs (Root Port) can be set to the enabled state, while in the x2x2x4 mode, only RP4, RP5, RP6 are enabled, and the rest of the RPs are in the closed state. This difference ensures that the system can adjust the resource allocation of the PCIe link according to specific needs, optimizing server performance.

[0142] By ensuring the difference in key parameters of each configuration table in the link configuration table set, the high flexibility of server hardware configuration and the accuracy of resource allocation are achieved. This mechanism can accurately identify and adapt to different hardware layout requirements, quickly load the most matching link configuration information at server startup, optimize data transmission efficiency, improve server performance and running stability, and reduce the time and cost required for maintaining complex hardware configurations.

[0143] As described in the above embodiments, the reason why multiple link configuration information in multiple link configuration tables can be generated is that the 20 lane links supported by the CPU are all reusable signal links. This allows the same transmission link to support different types of hardware components, such as serial interface hard drives, solid state drives, graphics processors, and modular network devices, according to different motherboard configurations.

[0144] For ease of understanding, the following specific embodiments of signal multiplexing are provided in the embodiments of the present application.

[0145] Embodiment 1: Assuming that a first link configuration table in the link configuration table set matching a first motherboard configuration is configured, wherein in the first link configuration table, a first group of links in the actual number of transmission links supported by the central processing unit are set as high-speed serial differential signal links, and a second group of links are set as universal serial bus links; wherein a first part of the links in the first group of links are set as storage device interface links in a link configuration table different from the first link configuration table in the link configuration table set, or a second part of the links in the first group of links are set as hard drive links in a link configuration table different from the first link configuration table in the link configuration table set.

[0146] In combination with Figure 5 As shown in the figure, assuming that a first group of links in the 20 lane links supported by the current CPU are pre-configured as high-speed serial differential signal links, i.e. PCIe links, and a second group of links are pre-configured as universal serial bus links, i.e. USB links.

[0147] Among them, the first group of links can be but are not limited to, such as Figure 5The second group of links can be, but are not limited to, 4 links numbered 16-19.

[0148] Suppose that the first part of the first group of links (e.g., lane links numbered 0-12) can also be set as SATA links in a link configuration table other than the first link configuration table, or the second part of the first group of links (e.g., lane links numbered 13-16) can also be set as hard disk drive links, i.e., HDD links, in a link configuration table other than the first link configuration table.

[0149] Then, by signal multiplexing the first part of the first group of links, the following embodiment 2 can be obtained.

[0150] Embodiment 2: configuring a second link configuration table in the set of link configuration tables that matches a second mainboard configuration, wherein in the second link configuration table, the first part of the first group of links in the actual number of transmission links supported by the central processor is set as the storage device interface link, and the third part of the first group of links other than the first part is set as the high-speed serial differential signal link.

[0151] Among them, embodiment 2 is obtained by adjusting the multiplexing of the first part of the links based on the pre-fixed configuration mode in embodiment 1.

[0152] Similarly, by signal multiplexing the second part of the first group of links, the following embodiment 3 can be obtained.

[0153] Embodiment 3: configuring a third link configuration table in the set of link configuration tables that matches a third mainboard configuration, wherein in the third link configuration table, the second part of the first group of links in the actual number of transmission links supported by the central processor is set as the hard disk drive link, and the fourth part of the first group of links other than the second part is set as the high-speed serial differential signal link.

[0154] Among them, embodiment 3 is obtained by adjusting the multiplexing of the second part of the links based on the pre-fixed configuration mode in embodiment 1.

[0155] It should be noted that the above-mentioned multiplexing adjustment of the first part or the second part of the first group of links is only an example and is not limited thereto.

[0156] In addition to the signal multiplexing adjustment on the first group of links, multiplexing adjustment can also be performed on the first group of links and the second group of links simultaneously, thereby obtaining the following embodiment 4.

[0157] In the fourth link configuration table, the second part of links in the first group of links supported by the actual number of transmission links of the central processing unit is set as the hard disk drive link, and the fifth part of links in the first group of links other than the second part of links is set as the high-speed serial differential signal link; at least part of the links in the second group of links is set as the storage device interface link, and the target link configuration table is one of the first link configuration table, the second link configuration table, the third link configuration table, and the fourth link configuration table.

[0158] Obviously, at least part of the links in the second group of links includes part or all of the lane links numbered 13-16. That is, in the fourth link configuration table, the types of the lane links numbered 13-15 can be multiplexed from universal serial bus links (USB links) to SATA links, or all of the lane links numbered 13-16 can be multiplexed to SATA links, which is not limited in this embodiment.

[0159] By pre-fixing the lane link information in the first link configuration table and based on the fixed configuration mode, a plurality of link configuration tables shown in embodiments 2-4 are obtained in different multiplexing modes, thereby realizing a plurality of link configuration tables that can adapt to a plurality of motherboard configurations by changing as few multiplexed lanes as possible under a limited number of lane links.

[0160] In an exemplary embodiment, the starting of the server based on the link configuration information in the target link configuration table includes: starting a basic input and output system based on the link configuration information in the target link configuration table, wherein the basic input and output system is used to initialize the hardware environment in the server starting process; and starting the server in response to completion of the starting of the basic input and output system.

[0161] When the server starts, it first determines the link configuration information that matches the hardware layout of the server motherboard through a series of mechanisms. Based on this information, the server can accurately locate the target link configuration table in the link configuration table set. For example, if the server detects that the hardware configuration requirement is 4NVME, the system will read the link configuration information in the corresponding configuration table, including the Lane allocation of the HSIO bus, the bandwidth splitting situation, the port enable state and other details, which will be used to guide the boot process of the BIOS. According to the information in the target link configuration table, the BIOS performs initial settings on the hardware environment of the server, ensuring that all transmission links (such as PCIe, SATA, USB) can be activated according to the correct signal type, bandwidth size and port state, laying the foundation for subsequent operating system loading and server functions.

[0162] After the BIOS system completes the initialization of the hardware environment, it will notify the server main system (such as the operating system) that the hardware resources are ready and can start executing higher-level startup tasks. At this stage, the server will start the operating system according to the initialization result of the BIOS, and execute application programs and services. For example, after completing the BIOS initialization under the 4NVME configuration, the server will enable all necessary PCIe links to ensure smooth and unobstructed high-speed data transmission links to support high-performance computing or big data storage application scenarios. This process seamlessly connects BIOS initialization and server startup, minimizing startup delay and improving user perception of system response speed.

[0163] Through the refined BIOS initialization process and the linkage of the startup phase, the server can quickly and accurately start under different hardware configurations, ensuring effective use of resources and stable operation of the system, providing users with an efficient and reliable server startup experience. This approach not only improves the startup speed of the server, but also enhances its adaptability to changing hardware environments, reduces maintenance costs, and improves overall system performance.

[0164] In an exemplary embodiment, after the target link configuration table that matches the target motherboard configuration is found from the link configuration table set, the above method further includes at least one of the following: writing the target link configuration information back to the management engine of the server; updating the target link configuration information to the management engine.

[0165] After the target link configuration information corresponding to the current server motherboard configuration is matched according to the method in the above embodiment, the target link configuration information is updated to the startup parameter setting of the hardware control platform, and the target hardware configuration information can also be updated and written back to the ME. When the server continues to start after the update is complete, it starts according to the target hardware configuration information.

[0166] In the initial stage of server startup, the BIOS system loads and applies the corresponding target link configuration table according to the detected hardware configuration information. In order to ensure that the management engine can continuously monitor and maintain the correct link state during server operation, the system needs to write back the currently effective target link configuration information to the ME. For example, assuming that the current hardware configuration of the server is 4 NVME, then after completing hardware initialization, the BIOS will set the HSIO bus Lane0~Lane7 as PCIe link, Lane8~Lane9 as PCIe network card device, Lane10~Lane11 as BMC management chip, Lane12~Lane13 as SATA interface, and Lane14~Lane15 as unused state. Detailed information is written back to the ME, so that the ME can real-time master the latest state of the link configuration and adjust or diagnose faults when necessary.

[0167] During the operation of the server, the hardware configuration may change, such as plugging in or unplugging PCIe devices, adjusting the use requirements of SATA or USB interfaces. In order to enable these changes to be timely reflected and processed at the system level, the server triggers the BIOS to re-read and confirm the latest hardware configuration requirements, and updates the target link configuration table, and then writes back the updated link configuration information to the ME, realizing real-time synchronization of link configuration information.

[0168] Through the above-mentioned manner, it is ensured that the server can always accurately master and timely adjust the link state in the face of changing hardware environment throughout the life cycle, thereby enhancing the stability and response capability of the server, reducing the operation and maintenance cost, and improving the overall system performance.

[0169] In an exemplary embodiment, the above-mentioned method further includes at least one of the following: writing back or updating the target link configuration information to the management engine after the server startup is completed; and writing back or updating the target link configuration information to the management engine after restarting the server.

[0170] The embodiment further refines the link configuration information management strategy in the server startup and restart process, and particularly emphasizes the importance of writing back or updating the determined target link configuration information to the management engine after the server completes startup or restart 1 time. It is ensured that the server can accurately and correctly maintain the correct link configuration state after initial startup or restart, thereby guaranteeing the efficiency of data transmission and the stability of system operation.

[0171] This is because when the server completes the startup process, the BIOS has initialized all necessary links according to the hardware configuration information, and confirmed the key parameters such as the bandwidth, signal type, port enable state and the like of the working link. To ensure that the management engine continuously tracks and manages this information, after the startup is completed, the system will write back the target link configuration information to the management engine, updating the internal configuration data thereof.

[0172] After the server is restarted, in order to quickly recover to the correct running state, the system will again perform the hardware initialization process of the BIOS, reload the target link configuration table, and write back or update the latest configuration information to the ME. For example, if the server is restarted after a hardware upgrade, the BIOS will re-detect the changes in the hardware configuration, and the HSIO bus Lane originally used for SATA is now allocated to a PCIe device, so that during the restart process, the changed link configuration information will be synchronized to the ME, ensuring that the server can immediately adapt to the new hardware layout after the restart, maintaining high performance and stability.

[0173] In the above manner, not only is it ensured that the server can flexibly adjust the link configuration in a variable hardware environment, but also the real-time monitoring and management capabilities of the management engine are enhanced, the risk of system instability caused by hardware changes is reduced, and the response speed and overall performance of the server are improved.

[0174] In an exemplary embodiment, after the target link configuration information is updated to the management engine, the above method further comprises: starting the server by loading the target link configuration information in the management engine.

[0175] That is, in the case where the target hardware configuration information is consistent with the default hardware configuration information, the server can be started by directly loading the default link configuration information.

[0176] Specifically, the system determines whether the hardware configuration of the current server motherboard is consistent with the system default hardware configuration by reading the CPU model information and GPIO state value.

[0177] If they are consistent, the system does not need to go through a complex dynamic configuration search and loading process, but directly reads the pre-stored default link configuration information from the management engine (ME) of the server. This means that if the current hardware layout is consistent with the system preset default hardware layout, no additional calculation and search is needed, and the default link configuration information in the ME can be directly loaded, saving calculation resources and time.

[0178] It is easy to understand that in the case that the hardware configuration of the current server mainboard is consistent with the system default hardware configuration, the method in the above embodiment can also be referred to to find the default link configuration information from the link configuration table set according to the mapping relationship between the mainboard configuration of the current server mainboard and the link configuration table.

[0179] That is, in the case that the default link configuration information corresponding to the default link configuration table is also pre-stored in the link configuration table set, the default link configuration information in the ME can be directly loaded or the default link configuration information can be found from the link configuration table set according to the mainboard configuration.

[0180] For example, for 4NVME configuration, the system will load the corresponding HSIO bus Lane settings, including assigning HSIO[7:0] to PCIe link and controlling through C0 controller, and setting HSIO[13:12] to SATA mode, and the Lane in non-SATA mode is set to non-SATA mode accordingly, ensuring that each Lane is correctly initialized to the predetermined signal type. In addition, the system will also automatically adjust the bandwidth splitting of the PCIe link, the port enable state, and the settings of other hardware interfaces according to the default configuration, and complete the startup preparation of the server.

[0181] By directly obtaining and loading the default link configuration information from the management engine, the startup process of the server is accelerated. Redundant dynamic configuration searching and loading when there is no change in hardware configuration is avoided, and the calculation burden and time delay in the startup stage are reduced.

[0182] In an exemplary embodiment, after starting the server based on the link configuration information in the target link configuration table, the above method further comprises: controlling the server to enter a shutdown state; adjusting the state value of the pin of the general input and output interface to obtain an adjusted pin state value by performing a hat jump operation on the pin of the input and output interface; and updating the mapping relationship between the adjusted pin state value, the mainboard configuration of the server mainboard, and the link configuration table in the link configuration table set.

[0183] In this embodiment, the state value of the configured GPIO pin can but is not limited to adjust the correspondence between the board card identifier and the mainboard configuration of the server mainboard by the hat jump pin method.

[0184] And only after the server enters the shutdown state, the operation and maintenance personnel can adjust the state value of the GPIO pin through the physical hat jump operation, so as to match the new hardware configuration information. The hat jump operation is a simple and effective hardware setting method. By inserting or removing the hat between specific pins, the state of the GPIO pin can be changed, thereby indirectly affecting the link configuration strategy of the server. For example, through the hat jump operation, the combined state of GPIO0 and GPIO1 can be adjusted from 0x00 to 0x01, so as to instruct the server to change Lane12~Lane13 of the HSIO bus from SATA mode to PCIe mode, to adapt to higher performance computing requirements.

[0185] When the server restarts, the BIOS re-reads the modified GPIO state value in the PEI stage, loads the link configuration information matched therewith, and realizes the re-allocation and optimization of hardware resources.

[0186] That is, through the physical adjustment of the state of the GPIO pin in the shutdown state, combined with the automatic loading of the configuration information by the BIOS when the server restarts, a complete hardware configuration dynamic adjustment mechanism is formed, which provides strong support for the server in complex and variable business environments.

[0187] The above processing manner greatly facilitates the on-site maintenance and configuration adjustment of the server. Without complex physical disassembly operation, only through simple hat jump adjustment, the change of the link configuration can be realized, and the flexibility and operation and maintenance efficiency of the server maintenance mode are improved.

[0188] As can be known from the description in the above embodiments, after adjusting the GPIO state through the hat pin, the system automatically updates the mapping relationship between the adjusted pin state value and the server motherboard configuration, and synchronously updates to the link configuration table set, to ensure that all related components can recognize and apply the latest configuration information.

[0189] For example, when the state values of GPIO0 and GPIO1 are changed to 0x11, the system maps the board card identifier 0x11 to the motherboard configuration configured by the GPU+OCP, and updates the allocation of the HSIO bus Lane in the link configuration table, such as adjusting the HSIO[7:0] from the default SATAx4 and PCIEx4 mode to the PCIEx8 mode supporting GPU and OCP, to adapt to the new hardware layout.

[0190] The system automatically detects the change of the GPIO pin state, and updates the mapping relationship between the related motherboard configuration and the link configuration table, to ensure the synchronization of the configuration information.

[0191] When the server restarts, the BIOS loads the updated mapping relationship, initializes the hardware resources according to the latest link configuration information, and optimizes the performance of the server.

[0192] By dynamically adjusting the GPIO pin state value and its mapping relationship with the motherboard configuration and link configuration table, the instant synchronization and optimization of server hardware configuration information are realized. The adaptability of the server to hardware changes is enhanced, the startup delay caused by configuration update is reduced, and the operation and maintenance efficiency is improved.

[0193] At the same time, it ensures that the understanding of hardware resources at the software level is consistent with the actual state, avoids system instability and data transmission abnormalities caused by configuration errors, and improves the overall performance and reliability of the server.

[0194] In an exemplary embodiment, before the basic input / output system of the server is controlled to enter the hardware initialization phase in response to the server startup instruction, the above method further comprises: determining a plurality of motherboard configurations of the motherboard of the server based on the hardware architecture of the server; and creating a set of link configuration tables matched with the plurality of motherboard configurations.

[0195] Server hardware architecture analysis is a basic work. Through the research on the server hardware architecture, a plurality of possible hardware configurations of the motherboard of the server can be identified, and each hardware configuration corresponds to different device layout and HSIO bus Lane usage strategy.

[0196] For example, it is assumed that based on the current server hardware architecture, three different motherboard configurations are allowed: the first configuration emphasizes high-speed data processing and is equipped with more PCIe links and high-end GPU; the second configuration is for storage-intensive applications and has more SATA and NVMe interfaces; the third configuration is cost-effective and focuses on balancing computing and storage resources. Through detailed hardware layout and resource demand analysis, the setting requirements of HSIO bus lane for each hardware layout are determined, which provides a reference basis for the creation of subsequent link configuration tables.

[0197] After determining a plurality of configurations of the motherboard of the server, a dedicated link configuration table can be created for each motherboard configuration, but is not limited to. These configuration tables contain detailed HSIO bus Lane configuration information, including Lane multiplexing signal types (such as PCI, SATA, USB), bandwidth allocation (such as PCIex8, x4x4, x2x2x2x2, etc.), and port enable state.

[0198] For example, for high-speed computing mainboards, the link configuration table will give priority to efficient utilization of PCIe links, and may allocate all HSIO[7:0] to two PCIe x8 link controllers, while storage mainboards may allocate part of the Lane to SATA or NVMe to enhance storage capacity. By constructing such a comprehensive set of link configuration tables, the server can flexibly switch between different mainboard configurations to adapt to diverse business scenarios and performance requirements.

[0199] By analyzing the hardware architecture of the server, multiple configurations of the server mainboard are determined, and a set of link configuration tables matching each configuration are pre-created. This strategy enhances the adaptability of the server to diverse hardware configurations, enabling the server to flexibly adjust the allocation and use of HSIO bus Lane between different mainboard configurations according to their respective characteristics and needs, without the need to recompile the BIOS image. At the same time, by planning the link configuration in advance, the server can quickly load the correct link configuration information at startup, shortening the initialization time and improving system response speed and resource utilization efficiency, ensuring that the server can run stably and efficiently in the face of complex and variable business scenarios.

[0200] In an exemplary embodiment, the above method further comprises, prior to controlling the basic input / output system of the server to enter the hardware initialization phase in response to the startup instruction of the server, pre-setting default link configuration information in the management engine of the server based on the hardware architecture of the server, wherein the default link configuration information includes signal type and bandwidth information of each transmission link.

[0201] In this embodiment, the setting of default link configuration information in the management engine ME can be done before the server starts, but is not limited to the following methods.

[0202] (1) Set the lane link of HSIO according to the hardware design diagram, set the Lane link of HSI0 bus according to the Lane link signal multiplexing design of EE engineers, for example, set HSIO bus Lane0-lane11 as PCI link, Lane12 as SATA link, Lane16 as USB link interface, and other unused Lanes as Unused state, and the unused Lanes of HSIO bus can be pre-planned.

[0203] (2) After the HSIO bus of the SATA link interface is set to the SATA mode, Lane 16 needs to be allocated as the SATA bus, and the HSIO link of the non-SATA bus is allocated as the non-SATA link; meanwhile, Lane 0-lane 15 of the HSIO bus of the PCI link is set according to the bandwidth of the PCI link, Lane 0-lane 7 is the first controller and the bandwidth is x8, that is, RP0 is set to enabled, RP1-RP3 are set to closed, Lane 8-lane 15 is the second controller and needs to be split into x2x2x2x2 or x2x2x4 mode, at this time, the state of RP4-RP7 is RP4, RP5 enabled, RP6, RP7 is set to closed or RP6 is set to closed.

[0204] At this time, the above link configuration information is set in the ME and is determined as a default link configuration information supported by a CPU model.

[0205] It can be known from the description in the above embodiments that the default link configuration information can be but is not limited to directly loading the default link configuration information in the ME for BIOS startup in the case that the hardware configuration of the current server mainboard is determined as the default hardware configuration according to the GPIO pin state.

[0206] By pre-setting the default link configuration information in the management engine, the acceleration of the server startup process and the instant availability of the link configuration are realized. This mechanism allows the server to start initializing the signal type and bandwidth allocation of the HSIO bus Lane before reading the CPU model, reduces the startup delay, and improves the system response speed.

[0207] In an exemplary embodiment, the above method further comprises: in the case that the motherboard configuration of the server mainboard is not identified based on the pin state of the general input and output interface, performing a downtime processing on the server.

[0208] After receiving the server startup instruction, the BIOS reads a set of preset GPIO states in the PEI stage, and the GPIO state values correspond to the motherboard configuration of the server mainboard. For example, the combination of the high and low levels of the GPIO pins determines that the board card identification is 0x00, and the configuration supporting 4 NVMe is preset; in this way, each GPIO state combination corresponds to a specific motherboard configuration, thereby realizing the automatic identification of the server mainboard.

[0209] If the motherboard configuration is supported by the CPU model according to the GPIO pin state, the default link configuration information in the ME is directly loaded or the target link configuration table is searched from the link configuration table set according to the description in each of the above embodiments. If not (e.g., the motherboard configuration is not recognized), the BIOS in the server is subjected to a shutdown process, that is, the server is subjected to a shutdown process.

[0210] If the motherboard configuration corresponding to the GPIO state is not recognized by the BIOS during the server startup process, it means that the motherboard configuration number of the current server motherboard can not be a configuration supported by the CPU, or the hardware configuration is not within the expected range. At this time, the server will immediately perform a shutdown process to terminate the startup process to prevent system instability or security risks that can be caused by subsequent operations.

[0211] The shutdown process is a protective measure that prevents the server from starting in a state where the hardware configuration of the server motherboard is uncertain, ensuring the consistency and security of the server hardware.

[0212] The motherboard configuration recognition based on the GPIO state and the shutdown process mechanism during the server startup phase enhance the hardware security and system stability of the server. The consistency and predictability of the server hardware configuration are ensured, and system failures and potential security risks caused by hardware incompatibility or configuration errors are avoided.

[0213] For ease of understanding, the above server startup method is further described below in conjunction with the overall flowchart shown in Figure 6 .

[0214] S602, in response to a server startup instruction.

[0215] S604, the BIOS system enters the PEI phase.

[0216] That is, the hardware initialization phase is entered.

[0217] S606, the BIOS reads the CPU model and obtains the number of HSIO bus lanes.

[0218] The number of HSIO bus lanes supported by different CPU models can be the same or different.

[0219] S608, whether the number of HSIO bus lanes is consistent with the number of lanes set by the ME for the HSIO bus.

[0220] If consistent, the HSIO bus lane settings in the ME are directly loaded, that is, the default link configuration information in the ME is directly loaded. Otherwise, step S610 is performed.

[0221] It should be noted that before step S602 is performed, the default link configuration information is set in the ME in advance by performing the following steps S601-1 to S601-4.

[0222] S601-1, the HSIO bus multiplex signal sets the actual enable signal, such as SATA, PCI, USB, and the unused PCI link is set to Unused state.

[0223] S601-2, the HSIO bus sets the lane of the SATA interface to be allocated as a SATA lane, and the lane not used for SATA is set to a non-SATA lane.

[0224] S601-3, the 2x8 bandwidth controller of the HSIO bus lane0-lane15 is enabled.

[0225] S601-4, according to the hardware design, the configuration of RP0~RP7 is split according to x8 bandwidth.

[0226] For example, x8x2x2x4, RP0, RP4, RP5, RP6 are enabled, and RP1, RP2, RP3, RP7 are closed.

[0227] S610, BIOS finds and reads the number of HSIO bus lanes corresponding to the CPU model.

[0228] S612, BIOS reads GPIO to confirm whether the motherboard configuration is a known motherboard.

[0229] If yes, step S614 is performed; otherwise, step S624 is performed.

[0230] S614, BIOS reads the configuration GPIO to determine the current hardware configuration information of the server motherboard.

[0231] S616, determine whether the current hardware configuration information determined according to the GPIO pin state is the default hardware configuration information indicated by the board card identification 0x00.

[0232] If yes, step S626 is performed; otherwise, step S618 is performed.

[0233] S618, after confirming the corresponding configuration information, the number of corresponding HSIO bus lanes, bandwidth splitting, HSIO link setting, SATA link setting, bandwidth splitting port enable or close setting, bandwidth length setting, etc.

[0234] Specifically, in the case that the hardware configuration of the current server motherboard is determined to be not the default hardware configuration, a target link configuration table matching the current hardware configuration is found from the link configuration table.

[0235] S620, update the current configuration information to the management engine settings.

[0236] S622, the BIOS system starts according to the confirmed configuration information.

[0237] S624, the BIOS performs a shutdown process.

[0238] S626, if the hardware configuration of the server motherboard is the default hardware configuration, the default link configuration information in the ME is directly executed for BIOS startup.

[0239] As another optional embodiment, in combination with Figure 7 The above server startup method is further explained and described in the swim lane diagram shown. According to the division of the execution subject, the interaction process between each execution subject is described.

[0240] (1) Server

[0241] Server startup: after the server hardware detects the startup signal, the startup process is activated, preparing for the subsequent BIOS and ME interaction.

[0242] (2) Management Engine (ME)

[0243] Load HSIO bus Lane settings in the management engine: ME reads the default HSIO configuration when the server starts, initializes the HSIO bus, including setting the Lane signal multiplexing (such as PCIe, SATA, USB) and the Unused state of the unused Lane.

[0244] HSIO configuration adjustment: according to the dynamic configuration information passed by the BIOS, the ME updates the configuration parameters of the HSIO bus, such as SATA port allocation, PCIe link bandwidth splitting and port enablement, etc.

[0245] (3) BIOS system

[0246] Enter PEI phase: BIOS enters PEI (Pre-Initialization) phase when the server starts, starting preliminary detection of CPU and hardware resources.

[0247] Read CPU model and get HSIO bus Lane number: BIOS reads CPU model and confirms the number of HSIO bus Lanes supported by CPU, which is the basis for PCI link dynamic configuration.

[0248] HSIO quantity consistency verification: BIOS verifies whether the lane quantity of the HSIO bus is consistent with the quantity of the HSIO bus lane in the ME configuration. If consistent, the startup will continue according to the preset configuration; if inconsistent, the BIOS will query the actual HSIO quantity supported by the CPU.

[0249] GPIO reading confirms the motherboard configuration and the configuration: BIOS first confirms whether the motherboard configuration matches the supported configuration by reading the GPIO state, and if matched, continues to read the GPIO to obtain specific hardware configuration information (hardware type and hardware layout); if not matched, performs a shutdown process to ensure hardware safety.

[0250] Dynamic loading of configuration information: BIOS determines the hardware configuration of the current server according to the configuration information read by the GPIO, and if the hardware configuration is not the default hardware configuration, finds and dynamically loads the HSIO bus Lane settings contained in the target link configuration table from the link configuration table set according to the motherboard configuration of the server motherboard, including lane quantity, bandwidth splitting, port enable state, and other dynamic configurations.

[0251] Updating platform startup parameters: BIOS updates the dynamically loaded configuration information to the platform startup parameters to ensure that the server is initialized and started according to the confirmed configuration.

[0252] Configuration information synchronization to ME: BIOS can selectively update the confirmed configuration information to the ME to overwrite the original configuration, achieving dynamic adjustment.

[0253] The core of the technical solution of the application is that: the default hardware configuration and the default link configuration information of the server mainboard are initially configured in the ME configuration file of the BIOS, when the BIOS enters the PEI stage at the server startup, whether the mainboard configuration meets the expectation is confirmed by reading a preset group of GPIO signals. If it does not meet the expectation, the BIOS is executed for downtime processing. At the same time, the number of HSIO bus lanes is confirmed, the actual link configuration information required to support the current server mainboard and CPU model is confirmed by reading another group of GPIO signals, the final target link configuration information is confirmed through the GPIO signal, and different HSIO settings are loaded. The HSIO settings can dynamically adjust the HSIO bus lane multiplexing signal of the CPU, the supported lane, the SATA port, the USB port, the PCI port, the PCI link bandwidth splitting, etc. It is not necessary to configure the configuration information in the ME for each link configuration information corresponding to the diversified hardware configuration, and recompile, burn, etc. action, that is, through the maximum setting, it can be downward compatible with multiple sub-configurations and does not need to update the BIOS image. The HSIO bus lane settings and use can also be dynamically adjusted through the GPIO jump cap method, and the ID of the mainboard can also be verified through the GPIO to ensure the safety, reliability, stability, etc. of the server.

[0254] By adapting the hardware configuration of the server mainboard to the Lane multiplexing signal of the HSIO bus, the settings of the SATA, USB, PCI interfaces, the bandwidth splitting of the PCI port and the port enablement setting according to the maximum of the mainboard, the adaptation results are set in the ME and compiled into the BIOS image. However, when multiple hardware configurations appear, it is necessary to re-adapt the ME configuration and re-compile, which consumes too much time and manpower, material resources. Therefore, by increasing a plurality of configuration tables of the HSIO bus lane multiplexing setting in the code of the BIOS, and then loading different HSIO bus lane settings in a dynamic manner, without modifying the ME configuration and without adjusting the hardware setting of the mainboard, only the confirmation of the current required configuration information through the GPIO method or other methods is needed. Both the number of HSIO bus Lane settings and the multiplexing setting of the HSIO bus lane signal, the splitting of the PCI link bandwidth and the enablement of the port can be adjusted. At the same time, the GPIO is introduced to ensure that the current BIOS image and the mainboard are in a one-to-one supporting relationship, avoiding the technical problem that the subsequent functions cannot be realized due to the server mainboard not being supported. At the same time, the downtime processing is performed for the mainboard configuration which is not adapted, improving the use efficiency of the mainboard.

[0255] The technical scheme has strong replicability and expandability. The actual use of the mainboard hardware HSIO bus is configured in advance in the BIOS ME. When the server starts, the BIOS confirms whether the current mainboard is supported in the PEI stage by combining the mainboard GPIO. If not supported, the server is shut down. If supported, the GPIO signal value corresponding to the hardware configuration of the server mainboard is obtained. The GPIO signal value can be controlled by a physical jump cap. After the BIOS confirms the link configuration information by reading the GPIO setting of the link configuration information, the corresponding HSIO parameter setting is loaded according to the corresponding BIOS link configuration information. At this time, based on the design of the hardware, some ports can be closed or opened. The PCI bandwidth splitting, the PCI port opening or closing setting, the SATA interface opening or closing setting, the USB port opening and closing setting, and the like. At the same time, a BIOS configuration can dynamically support multiple mainboard configuration information without adjusting the mainboard design or disassembling the device. A BIOS image can also support different configurations of different mainboards, which is convenient, fast, and does not require maintenance personnel to disassemble the mainboard of the data center for physical reconfiguration. In summary, the technical scheme can improve the security and reliability of the server mainboard, and improve the use efficiency and cost performance of the CPU.

[0256] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0257] According to another aspect of the embodiments of the present application, a server starting device is also provided. The structural diagram of the system is shown in Figure 8 The server starting device includes the following modules: a control unit 802 configured to control the basic input and output system of the server to enter a hardware initialization stage in response to a starting instruction of the server; a first processing unit 804 configured to determine a target mainboard configuration of the server mainboard based on a pin state of a general input and output interface, wherein the target mainboard configuration includes a type of hardware component, and the type of hardware component includes at least one of a serial interface hard disk, a solid state disk, a graphics processor, and a modular network device; a first searching unit 806 configured to search for a target link configuration table matched with the target mainboard configuration from a link configuration table set, wherein the link configuration table set is used to describe link configuration information matched with different mainboard configurations obtained by signal multiplexing on an actual number of transmission links supported by a central processing unit; and a starting unit 808 configured to start the server based on the link configuration information in the target link configuration table.

[0258] The specific execution steps involved in the various computing processes in the above modules, and the service configuration and abnormality early warning, can refer to the description in the above embodiments, and will not be described here again.

[0259] It is clear that the above server starting apparatus can be used to implement the server starting method provided in the above embodiments, which has been described and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and contemplated.

[0260] It should be noted that the control unit 802 in this embodiment can be used to execute the above step S202, the first processing unit 804 in this embodiment can be used to execute the above step S204, the first lookup unit 806 in this embodiment can be used to execute the above step S206, and the starting unit 808 in this embodiment can be used to execute the above step S208.

[0261] In one exemplary embodiment, the first processing unit 804 described above comprises: a first processing module configured to determine the board card identifier of the server mainboard based on the pin state of the general input and output interface, wherein a mapping relationship exists between the mainboard configuration of the server mainboard, the board card identifier, and the link configuration table in the link configuration table set; and a second processing module configured to determine the target mainboard configuration of the server mainboard based on the board card identifier.

[0262] In one exemplary embodiment, the first processing module described above comprises: a first reading submodule configured to read a first state value of a first pin in the general input and output interface; a second reading submodule configured to read a second state value of a second pin in the general input and output interface; and a first processing submodule configured to determine the board card identifier of the server mainboard based on the first state value and the second state value.

[0263] In one exemplary embodiment, the apparatus described above further comprises: a reading unit configured to read the processor model of the central processing unit before determining the target mainboard configuration of the server mainboard based on the pin state of the general input and output interface; a second processing unit configured to determine the actual number of transmission links of the data transmission bus supported by the central processing unit based on the processor model; and a third processing unit configured to determine the mainboard configuration of the server mainboard based on the pin state of the general input and output interface in the case where the actual number is inconsistent with the preset number of transmission links set in the management engine of the server.

[0264] In an example embodiment, the first searching unit 806 comprises: a comparing module, configured to compare the target hardware configuration information of the target mainboard configuration indication with the default hardware configuration information to obtain a target comparison result; and a first searching module, configured to search the target link configuration table matching the target mainboard configuration from the link configuration table set in a case that the target comparison result indicates that the target hardware configuration information is inconsistent with the default hardware configuration information.

[0265] In an example embodiment, the first searching module comprises: a third reading sub-module, configured to read a third state value of a third pin in a general-purpose input / output interface; a fourth reading sub-module, configured to read a fourth state value of a fourth pin in the general-purpose input / output interface; a second processing sub-module, configured to determine configuration table identifiers of each link configuration table in the link configuration table set based on the third state value and the fourth state value; a third processing sub-module, configured to search a target configuration table identifier consistent with a target board card identifier corresponding to the target mainboard configuration from the configuration table identifiers; and a first searching sub-module, configured to search the target link configuration table from the link configuration table set based on the target configuration table identifier, wherein the target mainboard configuration, the target board card identifier and the link configuration tables in the link configuration table set have a mapping relationship, and the target configuration table identifier and the target link configuration table have a one-to-one correspondence relationship.

[0266] In an example embodiment, the apparatus further comprises: at least one parameter in a plurality of parameters contained in any two link configuration tables in the link configuration table set has different values, including a number of transmission links of a data transmission bus, bandwidth splitting information, configuration information of the transmission link, bandwidth length and state information of a bandwidth splitting port.

[0267] In an example embodiment, the apparatus further comprises: a first configuration unit, configured to configure a first link configuration table matching a first mainboard configuration in the link configuration table set, wherein in the first link configuration table, a first group of links in an actual number of transmission links supported by the central processing unit are set as high-speed serial differential signal links, and a second group of links are set as universal serial bus links; and wherein a first part of links in the first group of links are set as storage device interface links in a link configuration table different from the first link configuration table in the link configuration table set, or a second part of links in the first group of links are set as hard disk drive links in a link configuration table different from the first link configuration table in the link configuration table set.

[0268] In one example embodiment, the apparatus further comprises a second configuration unit configured to configure a second link configuration table in the set of link configuration tables that matches a second motherboard configuration, wherein in the second link configuration table, a first portion of the first set of links in the actual number of transmission links supported by the central processing unit is set as the storage device interface link, and a third portion of the first set of links other than the first portion is set as the high speed serial differential signal link.

[0269] In one example embodiment, the apparatus further comprises a third configuration unit configured to configure a third link configuration table in the set of link configuration tables that matches a third motherboard configuration, wherein in the third link configuration table, a second portion of the first set of links in the actual number of transmission links supported by the central processing unit is set as the hard disk drive link, and a fourth portion of the first set of links other than the second portion is set as the high speed serial differential signal link.

[0270] In one example embodiment, the apparatus further comprises a fourth configuration unit configured to configure a fourth link configuration table in the set of link configuration tables that matches a fourth motherboard configuration, wherein in the fourth link configuration table, the second portion of the first set of links in the actual number of transmission links supported by the central processing unit is set as the hard disk drive link, and a fifth portion of the first set of links other than the second portion is set as the high speed serial differential signal link, at least a portion of the second set of links is set as the storage device interface link, and the target link configuration table is one of the first link configuration table, the second link configuration table, the third link configuration table, and the fourth link configuration table.

[0271] In one example embodiment, the apparatus further comprises a fourth processing unit configured to, after finding the target link configuration table in the set of slave link configuration tables that matches the target motherboard configuration, perform at least one of the following to write back the target link configuration information to a management engine of the server: updating the target link configuration information to the management engine.

[0272] In one example embodiment, the apparatus further comprises a fifth processing unit configured to start the server by loading the target link configuration information in the management engine.

[0273] In an example embodiment, the apparatus further comprises a sixth processing unit configured to control the server to enter a shutdown state; an adjusting unit configured to adjust a state value of a pin of the general input / output interface by performing a hat jump operation on the pin of the input / output interface to obtain an adjusted pin state value; and an updating unit configured to update a mapping relationship between the adjusted pin state value, a motherboard configuration of the server motherboard, and a link configuration table in the set of link configuration tables.

[0274] In an example embodiment, the apparatus further comprises a seventh processing unit configured to, in response to a start instruction of the server, determine a plurality of motherboard configurations of the server motherboard based on a hardware architecture of the server before controlling a basic input / output system of the server to enter a hardware initialization phase, and create the set of link configuration tables matching the plurality of motherboard configurations.

[0275] In an example embodiment, the apparatus further comprises an eighth processing unit configured to, in response to a start instruction of the server, pre-set default link configuration information in a management engine of the server based on a hardware architecture of the server before controlling a basic input / output system of the server to enter a hardware initialization phase, wherein the default link configuration information comprises signal type and bandwidth information of each transmission link.

[0276] In an example embodiment, the apparatus further comprises a ninth processing unit configured to perform a shutdown process on the server in a case where the state of the pin of the general input / output interface is not recognized as the motherboard configuration of the server.

[0277] It should be noted that each of the above modules can be implemented by software or hardware, and for the latter, the following implementation manners can be used, but are not limited thereto: all of the modules are located in the same processor; or each of the modules is located in a different processor in any combination.

[0278] According to still another aspect of the embodiments of the present application, an electronic device is provided, which comprises a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above server start method embodiments.

[0279] According to still another aspect of the embodiments of the present application, a computer readable storage medium is provided, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above server start method embodiments when running.

[0280] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0281] According to still another aspect of the embodiments of the present application, a computer program product is provided, which includes a computer program. The computer program, when executed by a processor, implements the steps in any of the server starting method embodiments described above.

[0282] The embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium. The non-volatile computer readable storage medium stores a computer program. The computer program, when executed by a processor, implements the steps in any of the server starting method embodiments described above.

[0283] The skilled in the art can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0284] The above describes in detail a server starting method provided by the present application. The principles and implementation manners of the present application are described by applying specific examples. The above description of the examples is only applicable to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application. These improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A server startup method, characterized in that, include: In response to the server's startup command, the server's basic input / output system is controlled to enter the hardware initialization phase; Based on the pin states of the general purpose input / output interface, the target motherboard configuration of the server motherboard is determined, wherein the target motherboard configuration includes the type of hardware components, and the type of hardware components includes at least one of serial interface hard disk, solid-state hard disk, graphics processor and modular network device; The target link configuration table that matches the target motherboard configuration is found in the link configuration table set, wherein the link configuration table set is used to describe the link configuration information that matches different motherboard configurations by signal multiplexing of the actual number of transmission links supported by the central processing unit. Start the server based on the link configuration information in the target link configuration table.

2. The method according to claim 1, characterized in that, The determination of the target motherboard configuration of the server motherboard based on the pin states of the general-purpose input / output interface includes: Based on the pin status of the general input / output interface, the board identifier of the server motherboard is determined, wherein there is a mapping relationship between the motherboard configuration of the server motherboard, the board identifier, and the link configuration table in the link configuration table set; Based on the board identifier, the target motherboard configuration of the server motherboard is determined.

3. The method according to claim 2, characterized in that, The process of determining the board identifier of the server motherboard based on the pin states of the general-purpose input / output interface includes: Read the first state value of the first pin in the general-purpose input / output interface; Read the second state value of the second pin in the general-purpose input / output interface; Based on the first status value and the second status value, the board identifier of the server motherboard is determined.

4. The method according to claim 1, characterized in that, Before determining the target motherboard configuration of the server motherboard based on the pin states of the general purpose input / output interface, the method further includes: Read the processor model of the central processing unit; Based on the processor model, determine the actual number of transmission links of the data transmission bus supported by the central processing unit; If the actual number is inconsistent with the preset number of transmission links set in the server's management engine, the motherboard configuration of the server motherboard is determined based on the pin status of the general input / output interface.

5. The method according to claim 1, characterized in that, The step of searching the link configuration table set for the target link configuration that matches the target motherboard configuration includes: Compare the target hardware configuration information indicated by the target motherboard configuration with the default hardware configuration information to obtain the target comparison result; If the target comparison result indicates that the target hardware configuration information is inconsistent with the default hardware configuration information, the target link configuration table that matches the target motherboard configuration is searched from the link configuration table set.

6. The method according to claim 5, characterized in that, The step of searching the link configuration table set for the target link configuration that matches the target motherboard configuration includes: Read the third state value of the third pin in the general purpose input / output interface; Read the fourth state value of the fourth pin in the general-purpose input / output interface; Based on the third state value and the fourth state value, the configuration table identifier of each link configuration table in the link configuration table set is determined; Based on the target board identifier corresponding to the target motherboard configuration, search for the target configuration table identifier that matches the target board identifier from the configuration table identifiers; Based on the target configuration table identifier, the target link configuration table is found from the link configuration table set. There is a mapping relationship between the target motherboard configuration, the target board identifier, and the link configuration tables in the link configuration table set. The target configuration table identifier and the target link configuration table have a one-to-one correspondence.

7. The method according to claim 5, characterized in that, The method further includes: At least one parameter among the multiple parameters contained in any two link configuration tables in the link configuration table set has a different value: the number of transmission links of the data transmission bus, bandwidth splitting information, configuration information of the transmission links, bandwidth length, and status information of the bandwidth splitting port.

8. The method according to claim 1, characterized in that, The method further includes: Configure a first link configuration table in the link configuration table set that matches the first motherboard configuration, wherein, in the first link configuration table, the first group of links in the actual number of transmission links supported by the central processing unit is set as a high-speed serial differential signal link and the second group of links is set as a universal serial bus link. Specifically, the first part of the links in the first group of links is set as a storage device interface link in a link configuration table that is different from the first link configuration table in the link configuration table set; or, the second part of the links in the first group of links is set as a hard disk drive link in a link configuration table that is different from the first link configuration table in the link configuration table set.

9. The method according to claim 8, characterized in that, The method further includes: Configure a second link configuration table in the link configuration table set that matches the second motherboard configuration, wherein, in the second link configuration table, the first part of the first group of links in the actual number of transmission links supported by the central processing unit is set as the storage device interface link, and the third part of the first group of links other than the first part of links is set as the high-speed serial differential signal link.

10. The method according to claim 8, characterized in that, The method further includes: Configure a third link configuration table in the link configuration table set that matches the third motherboard configuration, wherein in the third link configuration table, the second part of the links in the first group of the actual number of transmission links supported by the central processing unit is set as the hard disk drive links, and the fourth part of the links in the first group other than the second part of the links is set as the high-speed serial differential signal links.

11. The method according to claim 8, characterized in that, The method further includes: Configure a fourth link configuration table in the link configuration table set that matches the fourth motherboard configuration. In the fourth link configuration table, the second part of the links in the first group of the actual number of transmission links supported by the central processing unit is set as the hard disk drive links, and the fifth part of the links in the first group other than the second part is set as the high-speed serial differential signal links. At least some of the links in the second group are set as the storage device interface links. The target link configuration table is one of the first link configuration table, the second link configuration table, the third link configuration table, and the fourth link configuration table.

12. The method according to claim 1, characterized in that, After searching the link configuration table set for a target link configuration that matches the target motherboard configuration, the method further includes at least one of the following: Write the target link configuration information back to the management engine of the server; Update the target link configuration information to the management engine.

13. The method according to claim 12, characterized in that, After updating the target link configuration information to the management engine, the method further includes: The server is started by loading the target link configuration information from the management engine.

14. The method according to claim 1, characterized in that, The method further includes: Control the server to enter a shutdown state; By performing a jumper operation on the pins of the input / output interface, the state values ​​of the pins of the general-purpose input / output interface are adjusted to obtain the adjusted pin state values; Update the mapping relationship between the adjusted pin status values, the motherboard configuration of the server motherboard, and the link configuration table in the link configuration table set.

15. The method according to claim 1, characterized in that, Before controlling the server's basic input / output system to enter the hardware initialization phase in response to the server's startup command, the method further includes: Based on the server's hardware architecture, determine multiple motherboard configurations for the server's motherboard; Create a set of link configuration tables that match the multiple motherboard configurations.

16. The method according to claim 1, characterized in that, Before controlling the server's basic input / output system to enter the hardware initialization phase in response to the server's startup command, the method further includes: Based on the server's hardware architecture, default link configuration information is pre-set in the server's management engine, wherein the default link configuration information includes the signal type and bandwidth information of each transmission link.

17. The method according to any one of claims 1 to 16, characterized in that, The method further includes: If the motherboard configuration of the server motherboard is not identified based on the pin status of the general input / output interface, the server shall be shut down.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the server startup method as described in any one of claims 1 to 17.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the server startup method as described in any one of claims 1 to 17.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the server startup method as described in any one of claims 1 to 17.

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