Time synchronization redundancy mistake proofing control method and device, electronic equipment and storage medium

Abstract

The invention discloses a time synchronization redundancy mistake proofing control method and device, electronic equipment and a storage medium, the method and the device are applied to a time synchronization control system, the time synchronization control system comprises an upper computer, a lower computer and a main clock, the upper computer and the lower computer are respectively and automatically subjected to time synchronization with the main clock, and the time synchronization redundancy mistake proofing control method comprises the following steps: acquiring a control instruction issued by the upper computer; the control instruction comprises first time information of an internal clock when the upper computer sends the control instruction; when the lower computer receives the control instruction, second time information in the control instruction is determined; judging whether the deviation between the second time information and the first time information is greater than a preset threshold value; if the deviation is larger than a preset threshold value, the lower computer judges that the control instruction is illegal and refuses execution, and an alarm signal is triggered; if the deviation is not larger than the preset threshold value, the lower computer judges that the control instruction is legal and executes the control instruction, and systematic risks caused by inconsistent time information are reduced through analysis, judgment and processing of the time mark information in the lower computer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a time redundancy fault-tolerant control method and device, electronic equipment and storage medium. BACKGROUND

[0002] The clock system is an important part of the power production system, and establishing a unified clock reference in the system is a necessary condition for centralized process control of equipment, state monitoring and fault analysis. The safety, reliability and accuracy of the clock system directly affect the entire process of power production.

[0003] Establishing a unified clock reference is crucial for centralized control of equipment, state monitoring and fault analysis. A typical clock system uses a series architecture of a primary master clock, a secondary clock and a tertiary clock. The primary master clock usually has dual hot standby, receives Beidou or GPS time signal and distributes it to the lower level. The servers and control PLCs in the system are the main time synchronization users, which are synchronized with the secondary or tertiary clock nearby.

[0004] However, the existing time synchronization mechanism will cause the time scale of the lower PLC and the upper application server to deviate when the master clock function is normal, and the control command of the upper computer will be considered illegal and cannot be executed if the time or time keeping of the upper application server or the lower PLC itself is abnormal. SUMMARY

[0005] In view of the above problems, the present application provides a time redundancy fault-tolerant control method and device, electronic equipment and storage medium to effectively solve the problem of insufficient reliability of the existing system, especially suitable for industrial scenes such as power production which require strict clock accuracy.

[0006] In a first aspect, the present application provides a time redundancy fault-tolerant control method applied to a time control system, the time control system comprising an upper computer, a lower computer and a master clock, the upper computer and the lower computer being automatically time-synchronized with the master clock, the time redundancy fault-tolerant control method comprising: obtaining a control instruction issued by the upper computer, wherein the control instruction comprises first time information of the internal clock when the upper computer sends the control instruction; determining second time information in the control instruction when the lower computer receives the control instruction; judging whether the deviation between the second time information and the first time information is greater than a preset threshold value; if the deviation is greater than the preset threshold value, the lower computer determines that the control instruction is illegal and refuses to execute, and triggers an alarm signal; if the deviation is not greater than the preset threshold value, the lower computer determines that the control instruction is legal and executes the control instruction.

[0007] In some embodiments, the time synchronization redundant error-proof control method further comprises: When the alarm signal is triggered, a manual time synchronization command issued by the upper computer is acquired; When the lower computer receives the manual time synchronization command, automatic time synchronization with the master clock is prohibited, and the internal clock of the lower computer is updated based on the third time information in the manual time synchronization command; In the process of time keeping by the lower computer based on the manual time synchronization command, when a new control instruction sent by the upper computer is received, the deviation is re-judged, and the alarm signal is triggered or the new control instruction is executed.

[0008] In some embodiments, the time synchronization redundant error-proof control method further comprises: When the alarm signal is reset, a cancel manual time synchronization command issued by the upper computer is acquired; When the lower computer receives the cancel manual time synchronization command, automatic time synchronization with the master clock is enabled, and the internal clock of the lower computer is updated based on the time synchronization time mark of the master clock.

[0009] In some embodiments, the judgment of whether the deviation between the second time information and the first time information is greater than a preset threshold value includes: calculating the absolute value of the difference between the second time information T_command and the first time information T_plc, i.e., |T_plc-T_command|; judging whether the absolute value of the difference |T_plc-T_command| is greater than a preset threshold value dt, if |T_plc-T_command|>dt, it is determined that the deviation is greater than the preset threshold value, the lower computer determines that the control instruction is illegal and refuses to execute, and an alarm signal is triggered; if |T_plc-T_command|≤dt, it is determined that the deviation is not greater than the preset threshold value, the lower computer determines that the control instruction is legal and executes the control instruction.

[0010] In some embodiments, when the lower computer receives the manual time synchronization command, the automatic time synchronization with the master clock is prohibited, which includes: After the lower computer receives the manual time synchronization command, the manual time synchronization identifier CommandT is set to 1, and the automatic time synchronization prohibition identifier ForceAuT is set to 1 to prohibit the automatic time synchronization function with the master clock.

[0011] In some embodiments, the updating of the lower-level machine's own internal clock based on the third time information in the manual time synchronization command comprises: The lower-level machine updates the time information T_plc of its own internal clock to the time information T_command in the manual time synchronization command when CommandT=1.

[0012] In some embodiments, the enabling of the automatic time synchronization with the master clock when the lower-level machine receives the cancel manual time synchronization command comprises: The lower-level machine sets the manual time synchronization identifier CommandT to 0 and the automatic time synchronization prohibition identifier ForceAuT to 0 after receiving the cancel manual time synchronization command, so as to enable the automatic time synchronization function with the master clock.

[0013] In a second aspect, an embodiment of the present application provides a time synchronization redundancy fault-tolerant control device, which is applied to a time synchronization control system, the time synchronization control system comprising a host computer, a lower-level machine and a master clock, the host computer and the lower-level machine being automatically time synchronized with the master clock, and the time synchronization redundancy fault-tolerant control device comprising: an acquisition module configured to acquire a control instruction issued by the host computer, wherein the control instruction comprises first time information of an internal clock of the host computer when the host computer sends the control instruction; a determination module configured to determine second time information in the control instruction when the lower-level machine receives the control instruction; a control module configured to judge whether a deviation between the second time information and the first time information is greater than a preset threshold value; if the deviation is greater than the preset threshold value, the lower-level machine determines that the control instruction is illegal and refuses to execute the control instruction, and triggers an alarm signal; if the deviation is not greater than the preset threshold value, the lower-level machine determines that the control instruction is legal and executes the control instruction.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory and a processor, and the memory stores program code which can be run on the processor, and the program code is executed by the processor to implement the time synchronization redundancy fault-tolerant control method as introduced in any one of the embodiments of the first aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a computer storage medium, which stores one or more programs, and the one or more programs can be executed by the electronic device as introduced in the third aspect to implement the time synchronization redundancy fault-tolerant control method as introduced in any one of the embodiments of the first aspect.

[0016] The embodiment of the application provides a time redundancy fault-tolerant control method, device, electronic equipment and storage medium, which is applied to a time control system, the time control system comprises a host computer, a lower computer and a master clock, the host computer and the lower computer are automatically time-synchronized with the master clock, the time redundancy fault-tolerant control method comprises the following steps: obtaining a control instruction issued by the host computer, the control instruction comprises first time information of an internal clock when the host computer sends the control instruction; determining second time information in the control instruction when the lower computer receives the control instruction; judging whether the deviation between the second time information and the first time information is greater than a preset threshold; if the deviation is greater than the preset threshold, the lower computer determines that the control instruction is illegal and refuses to execute, and an alarm signal is triggered; if the deviation is not greater than the preset threshold, the lower computer determines that the control instruction is legal and executes the control instruction, through analysis and judgment of internal time synchronization mark information of the lower computer, an emergency disposal means when the clock system is intervened is provided under the premise that the control command is legal, and systematic risk caused by inconsistent time information is reduced.

[0017] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] The application will be described in more detail below based on embodiments and with reference to the drawings.

[0019] Figure 1 An exemplary time redundancy fault-tolerant control method flow diagram is shown in an embodiment of the application; Figure 2 An exemplary time control system diagram is shown in an embodiment of the application; Figure 3 An exemplary time redundancy fault-tolerant control method flow diagram is shown in an embodiment of the application; Figure 4 A structure block diagram of a time redundancy fault-tolerant control device is shown in an embodiment of the application; Figure 5 A structure block diagram of an electronic device for executing the time redundancy fault-tolerant control method according to the embodiment of the application is shown in the embodiment of the application; Figure 6 A computer readable storage medium for saving or carrying the time redundancy fault-tolerant control method according to the embodiment of the application is shown in the embodiment of the application. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application in combination with embodiments and drawings, the illustrative embodiments and the description thereof are only used to explain the present application, and do not limit the present application.

[0021] At present, a typical clock system is composed of three levels of clocks, namely, a primary clock, a secondary clock and a tertiary clock, which are connected in series. The primary clock of the clock system generally adopts a dual-machine hot backup form, is used for accepting a Beidou or GPS time signal, and sends the received time mark information to the secondary and tertiary clocks of the application level. Users of the clock are basically divided into two categories of servers and control PLCs, which are time-synchronized with the secondary or tertiary clock. The servers and the control PLCs are different in time-synchronization error correction mechanism. Taking a typical NTP time synchronization as an example, when the servers are time-synchronized with the clock system, the servers have a deviation protection mechanism. When the difference between the internal clock of the server and the time mark obtained by the NTP time synchronization is greater than a specific threshold, the server will automatically keep time according to the internal clock. However, the control PLC generally maintains the consistency between the internal clock and the time synchronization signal, even if the time mark of the clock system is abnormal.

[0022] The applicant found that the typical fault phenomenon is as follows. When the time synchronization signal of the primary clock is abnormally issued or the time synchronization signal is abnormally accepted, the incorrect clock signal will be issued to the clocks at all levels and the local PLCs time-synchronized therewith. Since the local PLCs do not have an error correction mechanism for the time synchronization signal, the incorrect clock signal is effective, and thus the time marks of the lower machine PLCs and the upper machine application server are deviated. The control command of the upper machine is considered illegal and cannot be executed. When the primary clock system is abnormal, the time marks of the upper machine and the lower machine are obviously deviated, and the execution of the normal control command can be ensured under human intervention.

[0023] Based on this, when the primary clock is normal, if the time synchronization or time keeping of the upper machine application server or the lower machine PLC is abnormal, the time marks of the lower machine PLC and the upper machine application server will be deviated, and the control command of the upper machine is considered illegal and cannot be executed.

[0024] In view of the above problems, the applicant provides a time synchronization redundancy fault control method, device, electronic equipment and storage medium. Through analysis and judgment of the time mark information in the lower machine, an emergency disposal means for manual intervention of the clock system in an abnormal state is provided under the premise that the control command is legal, and the systematic risk of all control commands being invalid and losing control due to the inconsistency of the time information of the upper and lower machines is greatly reduced.

[0025] The time synchronization redundancy fault control method is described in detail in subsequent embodiments.

[0026] The application scenario of the time redundancy fault-tolerant control method provided in the embodiment of the application is introduced as follows: Please refer to Figure 1 , Figure 1 The flowchart of the time redundancy fault-tolerant control method provided in the embodiment of the application is shown in the figure, in the embodiment, the time redundancy fault-tolerant control method can be applied in the time redundancy fault-tolerant control device 300 shown in Figure 4 and the electronic equipment 200 shown in Figure 5 , the following will be described in detail with respect to the flow shown in Figure 1 , the time redundancy fault-tolerant control method is applied to a time control system, please refer to Figure 2 , the time control system includes a host computer 2, a lower computer 3 and a master clock 1, the host computer 2 and the lower computer 3 are automatically time-synchronized with the master clock 1, the time redundancy fault-tolerant control method can include S110 to S130.

[0027] S110: obtaining a control instruction issued by the host computer, wherein the control instruction includes first time information of an internal clock when the host computer sends the control instruction.

[0028] S120: determining second time information in the control instruction when the lower computer receives the control instruction.

[0029] S130: judging whether the deviation of the second time information and the first time information is greater than a preset threshold value; if the deviation is greater than the preset threshold value, the lower computer determines that the control instruction is illegal and refuses to execute, and triggers an alarm signal; if the deviation is not greater than the preset threshold value, the lower computer determines that the control instruction is legal and executes the control instruction.

[0030] S130 includes S131 to S134, wherein: S131: calculating the absolute value of the difference between the second time information T_command and the first time information T_plc, that is, | T_plc-T_command|.

[0031] S132: judging whether the absolute value of the difference | T_plc-T_command| is greater than a preset threshold value dt.

[0032] S133: if | T_plc-T_command|>dt, it is determined that the deviation is greater than the preset threshold value, the lower computer determines that the control instruction is illegal and refuses to execute, and triggers an alarm signal.

[0033] S134: if | T_plc-T_command|≤dt, it is determined that the deviation is not greater than the preset threshold value, the lower computer determines that the control instruction is legal and executes the control instruction.

[0034] In some embodiments, the time-redundancy fault-tolerant control method further comprises S210 to S230: S210: When the alarm signal is triggered, a manual time-setting command issued by the upper computer is acquired. S220: When the lower computer receives the manual time-setting command, the automatic time-setting with the master clock is prohibited, and the internal clock of the lower computer is updated based on the third time information in the manual time-setting command.

[0035] In the embodiments of the present application, after the lower computer receives the manual time-setting command, the manual time-setting identifier CommandT is set to 1, and the automatic time-setting prohibition identifier ForceAuT is set to 1, so as to prohibit the automatic time-setting function with the master clock. When CommandT = 1, the time information T_plc of the internal clock of the lower computer is updated to the time information T_command in the manual time-setting command.

[0036] S230: In the process of time-keeping of the lower computer based on the manual time-setting command, when a new control instruction sent by the upper computer is received, the deviation is re-judged, and the alarm signal is triggered or the new control instruction is executed.

[0037] In the embodiments of the present application, the emergency disposal means when the clock system is abnormally intervened manually is improved, and the systematic risk that all control commands are invalid and the system is out of control due to the inconsistency of the time information of the upper and lower computers is greatly reduced.

[0038] In some embodiments, the time-redundancy fault-tolerant control method further comprises S240 to S250: S240: When the alarm signal is reset, a cancel manual time-setting command issued by the upper computer is acquired. S250: When the lower computer receives the cancel manual time-setting command, the automatic time-setting with the master clock is enabled, and the internal clock of the lower computer is updated based on the time-keeping time mark of the master clock.

[0039] In the embodiments of the present application, after the lower computer receives the cancel manual time-setting command, the manual time-setting identifier CommandT is set to 0, and the automatic time-setting prohibition identifier ForceAuT is set to 0, so as to enable the automatic time-setting function with the master clock.

[0040] In some embodiments, when the lower computer time-keeps based on the manual time-setting command and receives a new control instruction, if it is judged that the deviation between the time information in the new control instruction and the time information of the internal clock is not greater than a preset threshold, the lower computer executes the new control instruction and resets the alarm signal.

[0041] In specific embodiments, the application scenarios are as follows Figure 2As shown: the lower machine PLC and the upper machine application server are time-synchronized with the primary master clock; the upper machine application server issues a control command to the lower machine PLC, and the control command contains time information of the internal clock when the upper machine issues the command; when the lower machine PLC receives the command from the upper machine application server, it first determines whether there is a large deviation between the time information of the upper machine command and its own internal clock, and if the deviation is greater than a threshold value, the upper machine command is considered illegal and is refused to be executed; when the primary master clock time-synchronization signal is abnormal, for example, after a large jump, the error time-synchronization signal is stably output under the wrong time information, the upper machine application server detects the time-synchronization signal jump, disconnects the automatic time-synchronization mechanism, and keeps time according to the internal clock, the clock of the lower machine PLC is still automatically time-synchronized with the primary master clock, the error clock signal is effective, and thus a large time deviation occurs between the internal time scale of the upper machine application server and the lower machine PLC.

[0042] In the specific working process, for the normal case of time scale deviation between the upper machine application server and the lower machine PLC: Referring to Figure 2 , the primary master clock 1 has normal time-synchronization function, the upper machine 2 and the lower machine PLC 3 are time-synchronized with the primary master clock 1 at the same time, the time-synchronization signals are unified and consistent; the upper machine 2 issues a control command to the lower machine PLC 3, and after the lower machine PLC 3 receives the control command, it first parses the command time scale T_command, and at the same time, acquires its own internal time scale T_plc, the deviation threshold value is dt, if |T_plc-T_command|<=dt, the command is considered legal and is normally executed; if |T_plc-T_command|>dt, the command is considered illegal and is refused to be executed, and an alarm signal Alarm is triggered to 1, generating an alarm event of “time scale deviation between upper and lower machines exceeds threshold value, control command is not executed”.

[0043] For the case of time scale deviation between the upper machine application server and the lower machine PLC exceeding the threshold value: Referring to Figure 3 , the specific implementation steps can include: S1: the upper machine 2 issues a control command to the lower machine PLC 3, and after the lower machine PLC 3 receives the control command, it first parses the command time scale T_command, and at the same time, acquires its own internal time scale T_plc, the deviation threshold value is dt, |T_plc-T_command|>dt, the lower machine PLC determines that the command is illegal and is refused to be executed, an alarm signal Alarm is triggered to 1, generating an alarm event of “time scale deviation between upper and lower machines exceeds threshold value dt, control command is not executed”. If Alarm is 1, S2 is executed.

[0044] S2: when the alarm signal Alarm is 1, the upper computer application service manually issues a time command CommandT, and the lower computer PLC receives the manual time command CommandT, sets CommandT in the lower computer PLC to 1, prohibits the automatic time synchronization function with the master clock, sets ForceAuT to 1, updates the PLC internal time T_plc with the time mark T_command of the time command CommandT, and runs on the basis of the time. At this time, if the upper computer application server issues a new control command, S3 is executed.

[0045] S3: CommandT in the lower computer PLC is 1, the upper computer 2 issues a control command to the lower computer PLC 3, the lower computer PLC 3 receives the control command, first parses the command time mark T_command, and obtains the internal time T_plc of itself, the deviation threshold is dt, if |T_plc-T_command|<=dt, the command is considered to be legal, and normal execution is performed, the alarm signal Alarm is reset to 0, and S4 can be sequentially executed; if |T_plc-T_command|>dt, the command is considered to be illegal, and execution is refused, the alarm signal Alarm is triggered to 1, and an alarm event of "time mark deviation threshold of upper and lower computers is exceeded, and the control command is not executed" is generated, and S2 is executed at this time.

[0046] S4: when the alarm signal Alarm is 0 and CommandT in the lower computer PLC is 1, a manual time command CommandT can be manually issued by the upper computer application service, and the lower computer PLC receives the cancel time command CommandT, sets CommandT in the lower computer PLC to 0, enables the automatic time synchronization function with the master clock, sets ForceAuT to 0, and updates the PLC internal time mark with the time mark obtained from the master clock.

[0047] S5: when the upper computer 2 issues a new control command to the lower computer PLC 3, S1-S4 are cyclically executed.

[0048] In summary, the time synchronization redundancy fault-tolerant control method provided by the application can provide an emergency disposal means for manual intervention in the case of clock system abnormality, and reduce the systematic risk of all control commands being invalid and the system being out of control due to the inconsistency of the time information of the upper and lower computers.

[0049] Please refer to Figure 4 , Figure 4 A structure block diagram of a time synchronization redundancy fault-tolerant control device provided by the application, comprising: an acquisition module 310, a determination module 320 and a control module 330, wherein: The acquisition module 310 is configured to acquire a control instruction issued by the upper computer, wherein the control instruction comprises first time information of an internal clock of the upper computer when the upper computer sends the control instruction. The determination module 320 is configured to determine second time information in the control instruction when the lower computer receives the control instruction. The control module 330 is configured to judge whether a deviation between the second time information and the first time information is greater than a preset threshold value; if the deviation is greater than the preset threshold value, the lower computer determines that the control instruction is illegal and refuses to execute the control instruction, and triggers an alarm signal; if the deviation is not greater than the preset threshold value, the lower computer determines that the control instruction is legal and executes the control instruction.

[0050] It should be noted that the device embodiments in the present application correspond to the foregoing method embodiments, and the specific principles in the device embodiments can be referred to the content in the foregoing method embodiments, which will not be described here.

[0051] In several embodiments provided in the present embodiment, the coupling between the modules can be electrical, mechanical or other forms of coupling.

[0052] In addition, each functional module in each embodiment of the present application can be integrated in one processing module, or each module can exist physically, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0053] Please refer to Figure 5 , Figure 5 A structural block diagram of an electronic device 200 capable of executing the time-redundancy fault-tolerant control method described above is provided for the embodiments of the present application, and the electronic device 200 can be a smart phone, a tablet computer, a computer, a portable computer or the like.

[0054] The electronic device 200 further comprises a processor 202 and a memory 204. The memory 204 stores a program capable of executing the content in the foregoing embodiments, and the processor 202 can execute the program stored in the memory 204.

[0055] The processor 202 can include one or more cores for processing data and a message matrix unit. The processor 202 connects various parts within the entire electronic device 200 by various interfaces and lines, executes various functions of the electronic device 200 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 204, and calling data stored in the memory 204. Alternatively, the processor 202 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA). The processor 202 can be integrated with one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem, etc. Among them, the CPU mainly processes an operating system, a user interface, and an application program, etc.; the GPU is responsible for rendering and drawing display content; and the modem is used for processing wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor, but can be implemented by a separate communication chip.

[0056] The memory 204 can include a random access memory (RAM) and can also include a read-only memory (ROM). The memory 204 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 204 can include a program storage area and a data storage area, wherein the program storage area can store instructions for implementing an operating system, instructions for implementing at least one function (such as instructions for obtaining a random number by a user), instructions for implementing various method embodiments described below, etc. The data storage area can also store data (such as random numbers) created by the terminal in use, etc.

[0057] The electronic device 200 can further include a network module for receiving and sending electromagnetic waves, and a screen for displaying interface content and interacting with data. The network module can include various circuit elements for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor, a cryptographic chip, a subscriber identity module (SIM) card, a memory, and the like. The network module can communicate with various networks, such as the Internet, an intranet, a wireless network, or other devices via the wireless network. The wireless network can include a cellular telephone network, a wireless local area network, or a metropolitan area network. The screen can display interface content and interact with data.

[0058] Reference is made to Figure 6 , Figure 6 A structure block diagram of a computer readable storage medium provided by an embodiment of the present application is shown. The computer readable storage medium 400 stores program code 410, which can be invoked by a processor to execute the methods described in the above method embodiments.

[0059] The computer readable storage medium 400 can be an electronic storage such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer readable storage medium includes a non-transitory computer readable medium. The computer readable storage medium 400 has a storage space for the program code 410 for executing any of the above methods. The program code 410 can be read from or written to one or more computer program products. The program code 410 can be compressed in an appropriate form, for example.

[0060] The embodiments of the present application further provide a computer program product or a computer program, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the error-proof control method for time redundancy described in the various optional implementation manners.

[0061] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art will understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A time-based redundancy error prevention control method, characterized in that, An application is made to a time synchronization control system, which includes a host computer, a slave computer, and a master clock. The host computer and the slave computer automatically synchronize with the master clock. The time synchronization redundancy and error prevention control method includes: Obtain the control command issued by the host computer, wherein the control command includes the first time information of the internal clock when the host computer sends the control command; When the lower-level machine receives the control command, it determines the second time information in the control command; The system determines whether the deviation between the second time information and the first time information is greater than a preset threshold. If the deviation is greater than the preset threshold, the lower-level machine determines that the control instruction is illegal and refuses to execute it, and triggers an alarm signal. If the deviation is not greater than the preset threshold, the lower-level machine determines that the control instruction is legal and executes the control instruction.

2. The time-based redundancy error prevention control method according to claim 1, characterized in that, The time-redundancy error prevention control method further includes: When an alarm signal is triggered, the manual time synchronization command issued by the host computer is obtained; When the lower-level machine receives the manual time synchronization command, it prohibits automatic time synchronization with the master clock and updates its own internal clock based on the third time information in the manual time synchronization command to keep time. During the timekeeping process based on the manual time synchronization command, when the lower-level machine receives a new control command sent by the upper-level machine, it re-executes the judgment deviation and triggers an alarm signal or executes the new control command.

3. The time-synchronization redundancy error prevention control method according to claim 1, characterized in that, The time-redundancy error prevention control method further includes: When the alarm signal is reset, the command to cancel manual time synchronization issued by the host computer is obtained; When the lower-level machine receives the command to cancel manual time synchronization, it enables automatic time synchronization with the master clock and updates its own internal clock based on the master clock's time synchronization time stamp.

4. The time-synchronization redundancy error prevention control method according to claim 2, characterized in that, The system determines whether the deviation between the second time information and the first time information is greater than a preset threshold; if the deviation is greater than the preset threshold, the lower-level machine determines that the control command is illegal and refuses to execute it, and triggers an alarm signal. If the deviation is not greater than the preset threshold, the lower-level machine determines that the control command is valid and executes the control command, including: Calculate the absolute value of the difference between the second time information T_command and the first time information T_plc, |T_plc-T_command|; Determine whether the absolute value of the difference, |T_plc-T_command|, is greater than a preset threshold dt. If |T_plc-T_command|>dt, then the deviation is determined to be greater than the preset threshold. The lower-level machine determines that the control command is illegal and refuses to execute it, and triggers an alarm signal. If |T_plc-T_command|≤dt, then the deviation is determined to be no greater than the preset threshold, and the lower-level machine determines that the control command is valid and executes the control command.

5. The time-synchronization redundancy error prevention control method according to claim 4, characterized in that, When the lower-level machine receives the manual time synchronization command, it prohibits automatic time synchronization with the master clock, including: After receiving the manual time synchronization command, the lower-level machine sets the manual time synchronization flag CommandT to 1 and the automatic time synchronization disable flag ForceAuT to 1 to disable the automatic time synchronization function with the master clock.

6. The time-synchronization redundancy error prevention control method according to claim 4, characterized in that, The step of updating the lower-level machine's internal clock based on the third time information in the manual time synchronization command to maintain time includes: When CommandT=1, the lower-level machine updates its internal clock time information T_plc to the time information T_command in the manual time synchronization command.

7. The time-synchronization redundancy error prevention control method according to claim 3, characterized in that, When the lower-level machine receives the command to cancel manual time synchronization, enabling automatic time synchronization with the master clock includes: After receiving the command to cancel manual time synchronization, the lower-level machine sets the manual time synchronization flag CommandT to 0 and the automatic time synchronization disable flag ForceAuT to 0, so as to enable the automatic time synchronization function with the master clock.

8. A time-redundant error-proofing control device, characterized in that, The device is applied to a time synchronization control system, which includes a host computer, a slave computer, and a master clock. The host computer and the slave computer automatically synchronize with the master clock. The device includes: The acquisition module is used to acquire the control command issued by the host computer, wherein the control command includes the first time information of the internal clock when the host computer sends the control command; The determination module is used to determine the second time information in the control command when the lower-level machine receives the control command; The control module is used to determine whether the deviation between the second time information and the first time information is greater than a preset threshold; if the deviation is greater than the preset threshold, the lower-level machine determines that the control instruction is illegal and refuses to execute it, and triggers an alarm signal; if the deviation is not greater than the preset threshold, the lower-level machine determines that the control instruction is legal and executes the control instruction.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores program code that can run on the processor. When the program code is executed by the processor, it implements the time-redundancy error-proofing control method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program code that can be invoked by one or more processors to execute the time redundancy error prevention control method as described in any one of claims 1-7.

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