Circuit with nonlinear distortion compensation

Abstract

An electronic device may include wireless circuitry. The wireless circuitry may include at least one non-linear distortion compensation circuit including a third transistor having a gate terminal coupled to a gate terminal of the first input transistor, and an amplifier having a first input transistor and a second input transistor, a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor, and a tail current source coupled to a source-drain terminal of the third transistor and to a source-drain terminal of the fourth transistor. The amplifier may be coupled to one or more additional non-linear distortion compensation circuits. The non-linear distortion compensation circuit may be out-of-phase coupled with the amplifier, while the additional non-linear distortion compensation circuit may be in-phase coupled with the amplifier.

Description

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 652,508, filed May 1, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates in general to electronic devices, and more specifically to electronic devices having wireless communication circuitry. Background Technology

[0003] Electronic devices often possess wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuits, which include one or more antennas. The wireless receiver circuit within the wireless communication circuit uses the antennas to transmit and receive radio frequency signals.

[0004] The radio frequency (RF) signal transmitted by the antenna can be fed through a power amplifier configured to amplify the low-power analog signal into a high-power signal more suitable for long-distance transmission over the air. The RF signal received at the antenna can be fed through a low-noise amplifier configured to amplify the low-power analog signal into a high-power signal for processing at the receiver. Designing a satisfactory RF amplifier circuit for electronic devices can be challenging. Summary of the Invention

[0005] One aspect of this disclosure provides a circuit including a first input transistor and a second input transistor, and amplitude modulation to amplitude modulation (AMAM) or amplitude modulation to phase modulation (AMPM) distortion compensation circuitry. The AMAM or AMPM distortion compensation circuitry (sometimes referred to as nonlinear distortion compensation / reduction circuitry) may include a third transistor having a gate terminal coupled to the gate terminal of the first input transistor; a fourth transistor having a gate terminal coupled to the gate terminal of the second input transistor; and a tail current source coupled to the first source-drain terminal of the third transistor and coupled to the first source-drain terminal of the fourth transistor. The circuitry may also include additional AMAM / AMPM distortion compensation circuitry having a fifth transistor having a gate terminal coupled to the gate terminal of the first input transistor; a sixth transistor having a gate terminal coupled to the gate terminal of the second input transistor; and an additional tail current source coupled to the first source-drain terminal of the fifth transistor and coupled to the first source-drain terminal of the sixth transistor.

[0006] One aspect of this disclosure provides a circuit including a differential amplifier having a first input terminal and a second input terminal; and a distortion compensation circuit having input terminals coupled to the first and second input terminals of the differential amplifier. The distortion compensation circuit may further be out-of-phase coupled to the differential amplifier. The distortion compensation circuit may also include a tail current source configured to carry a tail current less than half the output current flowing through the differential amplifier. The circuit may further include an additional distortion compensation circuit having input terminals coupled to the first and second input terminals of the differential amplifier, wherein the additional distortion compensation circuit is in-phase coupled to the differential amplifier. The circuit may further include a first tunable attenuation circuit coupled between the first and second input terminals of the differential amplifier and the distortion compensation circuit; and a second tunable attenuation circuit coupled between the first and second input terminals of the differential amplifier and the additional distortion compensation circuit.

[0007] One aspect of this disclosure provides a circuit comprising: a first input transistor having a gate terminal coupled to a first input terminal, a drain terminal coupled to a first output terminal, and a source terminal coupled to ground; a second input transistor having a gate terminal coupled to a second input terminal, a drain terminal coupled to a second output terminal, and a source terminal coupled to ground; and a third transistor having a gate terminal coupled to the gate terminal of the first input transistor, a source terminal coupled to a first tail current source, and a drain terminal coupled to the second output terminal. Terminals; a fourth transistor having a gate terminal coupled to the gate terminal of the second input transistor, a source terminal coupled to the first tail current source, and a drain terminal coupled to the first output terminal; a fifth transistor having a gate terminal coupled to the gate terminal of the first input transistor, a source terminal coupled to the second tail current source, and a drain terminal coupled to the first output terminal; and a sixth transistor having a gate terminal coupled to the gate terminal of the second input transistor, a source terminal coupled to the second tail current source, and a drain terminal coupled to the second output terminal.

[0008] Other features, nature and various advantages of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0009] Figure 1 This is a diagram of an exemplary electronic device with wireless communication circuitry according to some implementation schemes.

[0010] Figure 2This is a diagram illustrating an exemplary wireless communication circuit with an amplifier circuit according to some implementation schemes.

[0011] Figure 3 This is a circuit diagram of an exemplary amplifier circuit with amplitude modulation to amplitude modulation (AMAM) distortion compensation circuit according to some implementation schemes.

[0012] Figure 4 It is a graph that plots the amplifier output current as a function of the input voltage.

[0013] Figure 5 It is a graph that plots the amplifier's transconductance as a function of the input voltage.

[0014] Figure 6 It is a diagram of the current supplied by the AMAM distortion compensation circuit, drawn according to some implementation schemes.

[0015] Figure 7 This is a diagram illustrating the transconductance of an AMAM distortion compensation circuit based on some implementation schemes.

[0016] Figure 8 The graph shows how the transconductance of the AMAM distortion compensation circuit can be adjusted via different attenuation factors, based on some implementation schemes.

[0017] Figure 9A , Figure 9B and Figure 9C Various specific implementations of signal attenuation circuits according to some schemes are shown.

[0018] Figure 10 The graph illustrates how the range of third-order nonlinear cancellation can be adjusted by selectively activating one or more AMAM distortion compensation circuits, based on some implementation schemes.

[0019] Figure 11 The graph illustrates how amplifier gain can be improved by selectively activating one or more AMAM distortion compensation circuits, based on some implementation schemes.

[0020] Figure 12 The graph illustrates how the third-order intercept point can be improved by selectively activating one or more AMAM distortion compensation circuits, based on some implementation schemes.

[0021] Figure 13 This is a circuit diagram of an exemplary amplifier circuit with an AMAM distortion compensation circuit coupled to the input transformer, according to some implementation schemes.

[0022] Figure 14 This is a circuit diagram of an exemplary amplifier circuit with different types of AMAM distortion compensation circuits according to some implementation schemes. Detailed Implementation

[0023] This invention discloses an electronic device that can provide wireless circuitry. The wireless circuitry may include a radio frequency amplifier and other transmitting or receiving circuitry for processing signals in a transmit or receive path. The amplifier or other components in the transmit or receive path may include one or more input transistors that exhibit nonlinear current behavior. If not carefully managed, such transistor nonlinearity can lead to amplitude modulation to amplitude modulation (AMAM) distortion and / or amplitude modulation to phase modulation (AMPM) distortion, which produces third-order intermodulation distortion. This third-order intermodulation distortion degrades the error vector amplitude (EVM) and worsens the adjacent channel power ratio (ACPR) of the wireless circuitry, which measures the amount of signal interference in the frequency channel adjacent to the channel of interest.

[0024] To compensate for AMAM / AMPM distortion, the amplifier can be coupled in parallel with one or more AMAM or AMPM compensation circuits. The AMAM / AMPM compensation circuit can be a differential circuit biased using a tail current source. The AMAM / AMPM compensation circuit can be biased in a current-limited region to provide a highly compressed transconductance with higher-order nonlinearities. The polarity and amplitude of such higher-order nonlinearities generated by the AMAM / AMPM compensation circuit can be used to cancel the amplifier's third-order intermodulation distortion without affecting the amplifier's gain performance, which technically benefits the improvement of the overall performance of the wireless circuit.

[0025] Figure 1 This is an illustration of an electronic device, such as electronic device 10, which may be equipped with one or more AMAM or AMPM compensation circuits. Electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband device, a headset or handset device, a device embedded in glasses; or other equipment worn on a user's head; or other wearable or micro-devices, televisions, computer monitors without embedded computers, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with a display is installed in a kiosk or car), voice-controlled speakers connected to the wireless Internet, home entertainment devices, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0026] like Figure 1As illustrated in the schematic diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations thereof. In some cases, part or all of housing 12 may be formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0027] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage circuitry 16. Storage circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage devices and / or removable storage media integrated within device 10.

[0028] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0029] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). Protocols for other short-range wireless communication links, such as This protocol may be any of the following: wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G New Radio (NR) protocols, etc.), MIMO protocols, antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols for signals transmitted at millimeter and centimeter wave frequencies, or other desired distance detection protocols), or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0030] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output device 22. Input-output device 22 may be used to allow data to be supplied to device 10 and to allow data to be supplied from device 10 to external devices. Input-output device 22 may include user interface devices, data port devices, and other input-output components. For example, input-output device 22 may include touch sensors, displays, light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice, electronic pens (e.g., styluses), joysticks, and other input-output devices may be coupled to device 10 using wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals of the main processing unit or other parts of device 10 coupled via wired or wireless links).

[0031] Input-output circuitry 20 may include wireless communication circuitry for wirelessly transmitting radio frequency signals, such as wireless communication circuitry 24 (sometimes referred to herein as wireless circuitry 24). Although control circuitry 14 is shown separately from wireless communication circuitry 24 for clarity, wireless communication circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18 and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless communication circuitry 24). For example, control circuitry 14 (e.g., processing circuitry 18) may include baseband processor circuitry or other control components forming part of wireless communication circuitry 24.

[0032] The wireless communication circuit 24 may include a radio frequency (RF) transceiver circuit formed by one or more integrated circuits, a power amplifier circuit configured to amplify uplink RF signals (e.g., RF signals transmitted by device 10 to external devices), a low-noise amplifier configured to amplify downlink RF signals (e.g., RF signals received by device 10 from external devices), passive RF components, one or more antennas, transmission lines, and other circuitry for processing the RF wireless signals. Light (e.g., infrared communication) may also be used to transmit the wireless signals.

[0033] Wireless circuit 24 may include radio frequency transceiver circuitry for transmitting and / or receiving radio frequency signals in various radio frequency communication bands. For example, the radio frequency transceiver circuitry may handle wireless local area network (WLAN) communication bands such as 2.4 GHz and 5 GHz. (IEEE 802.11) bands, Wireless Personal Area Network (WPAN) communication bands such as 2.4 GHz Communication frequency bands, cellular telephone communication frequency bands such as the cellular low frequency band (LB) (e.g., 600MHz to 960MHz), the cellular low intermediate frequency band (LMB) (e.g., 1400MHz to 1550MHz), the cellular intermediate frequency band (MB) (e.g., 1700MHz to 2200MHz), the cellular high frequency band (HB) (e.g., 2300MHz to 2700MHz), the cellular ultra-high frequency band (UHB) (e.g., 3300MHz to 5000MHz), or other cellular communication frequency bands between approximately 600MHz and approximately 5000MHz (e.g., 3G bands, 4G bands). This includes LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands with millimeter and centimeter wavelengths between 20 GHz and 60 GHz, etc., near field communication (NFC) bands (e.g., 13.56 MHz), satellite navigation bands (e.g., the L1 Global Positioning System (GPS) band at 1575 MHz, the L5 GPS band at 1176 MHz, the Global Navigation Satellite System (GLONASS) band, the BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) communication bands supported by the IEEE 802.15.4 protocol and / or other UWB communication protocols (e.g., a first UWB communication band at 6.5 GHz and / or a second UWB communication band at 8.0 GHz), and / or any other desired communication bands. Communication bands processed by such RF transceiver circuits are sometimes referred to herein as frequency bands or simply "bands," and may span corresponding frequency ranges. Generally speaking, the radio frequency transceiver circuit in wireless circuit 24 can cover (process) any desired frequency band.

[0034] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. (Example...) Figure 2 As shown, wireless circuitry 24 may include baseband circuitry 26, such as one or more baseband processors, radio frequency (RF) transceiver circuitry, such as an RF transceiver 28, RF front-end circuitry, such as an RF front-end module (FEM) 40, and an antenna 42. Baseband circuitry 26 may be coupled to transceiver 28 via baseband path 34. Transceiver 28 may be coupled to antenna 42 via RF transmit line path 36. RF front-end module 40 may be disposed on RF transmit line path 36 between transceiver 28 and antenna 42. Figure 2 Any block shown may be provided with one or more AMAM and / or AMPM (distortion) compensation circuits, which are configured to improve the EVM of the entire wireless circuit 24.

[0035] exist Figure 2In the example, for clarity, wireless circuit 24 is shown as including only a single baseband processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of baseband processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each baseband processor 26 may be coupled to one or more transceivers 28 via a corresponding baseband path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmit line path 36. Each RF transmit line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmit line path 36. If desired, one or more RF transmit line paths 36 in wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0036] The RF transmit line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 may have a positive transmit line signal path coupled to the positive antenna feed terminal on the antenna 42. The RF transmit line path 36 may also have a ground transmit line signal path coupled to the ground antenna feed terminal on the antenna 42. This example is merely illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmit line paths 36.

[0037] RF transmission path 36 may include a means for communication with device 10 ( Figure 1 The transmitting lines in device 10 route the radio frequency antenna signals within the device. The transmitting lines in device 10 may include coaxial cables, microstrip transmitting lines, stripline transmitting lines, edge-coupled microstrip transmitting lines, edge-coupled stripline transmitting lines, and transmitting lines formed by combinations of these types of transmitting lines. Transmitting lines in device 10, such as the transmitting lines in radio frequency transmitting line path 36, may be integrated into rigid and / or flexible printed circuit boards.

[0038] During wireless transmission, baseband processor 26 provides baseband signals to transceiver 28 via baseband path 34. Transceiver 28 may also include circuitry for converting the baseband signals received from baseband circuitry 26 into corresponding radio frequency (RF) signals. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the baseband signals to RF before transmission via antenna 42. Transceiver circuitry 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 may transmit RF signals via antenna 42 using transmitter (TX) 30 through RF transmission line path 36 and front-end module 40. Antenna 42 transmits RF signals to external wireless equipment by radiating the RF signals into free space.

[0039] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission path 36 and front-end module 40. Transceiver 28 may include circuitry, such as receiver (RX) 32, for receiving signals from front-end module 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via baseband path 34 to baseband circuitry 26.

[0040] Front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) via radio frequency transmission line path 36. For example, FEM 40 may include front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, antenna common circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifier circuitry 50 and / or one or more low-noise amplifier circuitry 52), impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 with the impedance of radio frequency transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the radio frequency signals transmitted and / or received by antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If needed, the various front-end module components can also be integrated into a single integrated circuit chip.

[0041] Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to regulate the frequency response and wireless performance of antenna 42 over time.

[0042] Transceiver 28 may be separate from front-end module 40. For example, transceiver 28 may be formed on another substrate such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of front-end module 40. Although for clarity, in Figure 1 In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of baseband circuitry 26 and / or transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on baseband circuitry 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) to control the operation of front-end module 40.

[0043] Transceiver circuitry 28 may include processing WLAN communication bands (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz. Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits for processing cellular phone frequency bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); near field communication (NFC) transceiver circuits for processing near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); ultra-wideband (UWB) transceiver circuits for processing communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuits for covering any other desired communication frequency bands of interest.

[0044] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole antenna, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0045] Figure 3 This is a diagram of a differential circuit (such as differential circuit 100, which may be part of wireless circuit 24). Figure 3 The differential circuit 100 can typically represent a power amplifier 50 in the transmit path, a variable gain amplifier (VGA) in the transmit path, a low-noise amplifier 52 in the receive path, a mixer or modulator in the transmit path, a mixer or demodulator in the receive path, some other gain block in the transmit or receive path, some other component in the front-end module 40 or transceiver 28, or other components along the transmit line path 36. The scenario where the differential circuit 100 represents an RF amplifier is sometimes described herein as an example. The differential circuit 100 can therefore sometimes be referred to as an amplifier circuit.

[0046] like Figure 3As shown, amplifier circuit 100 may include a primary differential circuit such as amplifier 102, sometimes referred to as a main amplifier or primary amplifier. Main amplifier 102 may include at least transistors M1 and M2. Transistors M1 and M2 may be n-type (n-channel) transistors, such as n-type metal-oxide-semiconductor (NMOS) devices. Transistor M1 may have a source terminal coupled to ground power line 104 (e.g., a ground line providing ground power voltage Vss), a drain terminal, and a gate terminal coupled to a first input terminal IN1. Transistor M2 may have a source terminal coupled to ground power line 104, a drain terminal, and a gate terminal coupled to a second input terminal IN2. Input terminals IN1 and IN2 together serve as the differential input ports of amplifier 102. Transistors M1 and M2 are therefore sometimes referred to as “input transistors”. The terms “source” and “drain” terminals used to refer to current-carrying terminals in transistors are used interchangeably and are sometimes referred to as “source-drain” terminals. Therefore, the source terminal of transistor M1 can sometimes be referred to as the first source-drain terminal, and the drain terminal of transistor M1 can be referred to as the second source-drain terminal (or vice versa).

[0047] Amplifier 102 may optionally include capacitors C1 and C2. Capacitor C1 may be a first metal-oxide-semiconductor capacitor (MOSCAP) having a gate terminal coupled to a first input terminal IN1 and a body terminal cross-coupled to the drain terminal of a second input transistor M2. Capacitor C2 may be a second MOSCAP having a gate terminal coupled to a second input terminal IN2 and a body terminal cross-coupled to the drain terminal of the first input transistor M1. Configured in this way, the cross-coupled MOS capacitors C1 and C2 can be used to neutralize the gate-to-drain parasitic capacitance of the input transistors M1 and M2, and are therefore sometimes referred to as a parasitic capacitance neutralizing assembly. In other embodiments, the parasitic capacitance neutralizing assembly may be implemented as a cross-coupled transistor, a metal-insulator-metal (MIM) capacitor, a deep trench capacitor, a polysilicon capacitor, or other electronic devices exhibiting capacitance. The use of parasitic capacitance neutralizing capacitors C1 and C2 is optional and may be omitted to save costs.

[0048] The drain terminal of input transistor M1 can be coupled to the first amplifier output terminal OUT1, while the drain terminal of input transistor M2 can be coupled to the second amplifier output terminal OUT2. Output terminals OUT1 and OUT2 can be used together as the differential output port of amplifier 102. A differential output voltage Vout can be provided across output terminals OUT1 and OUT2. Output current Iout can flow through the output port of amplifier 102.

[0049] If desired, amplifier 102 may optionally include a cascode transistor coupled between the input transistor and the amplifier output terminal. For example, a first cascode transistor may be coupled in series between the input transistor M1 and the output terminal OUT1, while a second cascode transistor may be coupled in series between the input transistor M2 and the output terminal OUT2. Such cascode transistors (sometimes referred to as cascode amplifier stages) may be included to increase the output impedance of amplifier 102 and may optionally be used to provide different gain steps (e.g., by selectively adjusting the drive strength of the cascode transistors). Generally, one or more transistors, capacitors, resistors, inductors, transformers, and / or other load components may be coupled to the amplifier output terminals OUT1 and OUT2.

[0050] The performance of a radio frequency (RF) amplifier is sometimes quantified by a parameter called the error vector magnitude (EVM). Ideally, the signal transmitted by an RF amplifier will have a signal modulation constellation point located at some ideal position on the complex plane. However, due to design flaws, distortion, parasitic signals, and / or noise, the actual constellation point usually deviates from these ideal positions. The error vector magnitude is a measure of how far the actual point deviates from the ideal position.

[0051] Generally, amplifiers have linear and nonlinear operating ranges. To avoid signal distortion, amplifiers typically operate within the linear range. When operating in the nonlinear range, the ratio of input power to output power may not be constant. Therefore, as the input signal amplitude increases, the output signal amplitude may increase disproportionately. This unwanted additional amplitude modulation caused by the amplifier's nonlinear characteristics is sometimes called amplitude modulation to amplitude modulation (AMAM) distortion. Similar to the output signal amplitude, the amplifier's output phase can change disproportionately as the input signal amplitude increases. This unwanted additional phase modulation caused by the amplifier's nonlinear characteristics is sometimes called amplitude modulation to phase modulation (AMPM) distortion. Generally, AMAM distortion can arise from undesired gain changes from the amplifier's nonlinear transistor transconductance (sometimes called "Gm") and output resistance (sometimes called "Rout"). AMAM distortion can be more pronounced in amplitude-based modulation schemes such as quadrature amplitude modulation (QAM) schemes.

[0052] Figure 4 This is a graph that plots the amplifier's output current Iout as a function of the input voltage Vin. For example... Figure 4As shown, the Iout curve 200 typically increases with the magnitude of the input voltage Vin. At one end, the output current Iout becomes more positive at a higher +Vin level. At the other end, the output current Iout becomes more negative at a larger -Vin level. The transconductance Gm of an amplifier can be a parameter that measures how much the output current of the device changes in response to a change in the input voltage. In other words, the amplifier transconductance Gm can represent... Figure 4 The first derivative of curve 200 in the figure.

[0053] Figure 5 This is a graph that plots the amplifier's transconductance Gm as a function of the input voltage Vin. For example... Figure 5 As shown, transconductance curve 202 exhibits its maximum level when the input voltage Vin is equal to zero, and decreases to a lower level as the input voltage Vin becomes more positive or more negative. Figure 5 As illustrated by arrow 204, this decrease in amplifier transconductance Gm at larger input voltages can lead to a reduction in amplifier gain at increased input signal amplitude levels, a suboptimal phenomenon sometimes referred to as gain compression. Such gain compression can produce a third-order intermodulation (IM3) product that falls into the target signal band of interest, causing EVM degradation; or it can enter adjacent channel bands, creating sideband spectra that result in enhanced interference.

[0054] To help compensate for or mitigate unwanted AMAM distortion, amplifier 100 may be equipped with AMAM distortion compensation circuitry, such as... Figure 3 AMAM distortion compensation circuits 110-1 and 110-2 are used in the circuit. Although in Figure 3 The example shows at least two AMAM distortion compensation circuits 110, but amplifier 100 typically includes only one compensation circuit 110 or more than two compensation circuits 110 (e.g., three or more compensation circuits 110, four or more compensation circuits 110, five to ten compensation circuits 110, or more than ten compensation circuits 110). Multiple AMAM distortion compensation circuits are sometimes collectively referred to as AMAM distortion compensation or correction circuits.

[0055] Each compensation circuit 110 may be a differential circuit biased with a tail current source and coupled in parallel with the main amplifier 102. The first compensation circuit 110-1 may include transistors M3 and M4 coupled to a first shared tail current source Itail1. Transistor M3 may have a gate terminal coupled to the gate terminal of input transistor M1 via a first attenuation circuit 112-1, a source terminal coupled to tail current source Itail1, and a drain terminal coupled to output terminal OUT2. Transistor M4 may have a gate terminal coupled to the gate terminal of input transistor M2 via a second attenuation circuit 112-1, a source terminal coupled to tail current source Itail1, and a drain terminal coupled to output terminal OUT1. The first tail current source Itail1 may be coupled between a first tail node shorted to the source terminals of transistors M3 and M4 and ground 104. Additionally, transistors M3 and M4 may exhibit parasitic gate-to-drain capacitances at the output terminals OUT1 and OUT2 of the main amplifier 102. Assuming transistors M3 and M4 are cross-coupled to transistors M1 and M2 as shown in cross connection 112, such gate-to-drain capacitances of transistors M3 and M4 can optionally be configured as neutralizing capacitors for amplifier 102, and can help eliminate the need for separate neutralizing capacitors C1 and C2. This can help reduce circuit area and cost.

[0056] Similarly, the second compensation circuit 110-2 may include transistors M5 and M6 coupled to a second shared tail current source Itail2. Transistor M5 may have a gate terminal coupled to the gate terminal of input transistor M1 via a first attenuation circuit 112-2, a source terminal coupled to tail current source Itail2, and a drain terminal coupled to output terminal OUT1. Transistor M6 may have a gate terminal coupled to the gate terminal of input transistor M2 via a second attenuation circuit 112-2, a source terminal coupled to tail current source Itail2, and a drain terminal coupled to output terminal OUT2. The second tail current source Itail2 may be coupled between a second tail node shorted to the source terminals of transistors M5 and M6 and the ground power supply line 104. The differential compensation circuits 110-1 and 110-2 coupled to the main amplifier 102 in this manner are sometimes referred to as “auxiliary” differential pair amplifiers or auxiliary differential circuits.

[0057] The amount of current flowing through the tail current sources of compensation circuit 110 should be constant and substantially less than the amount of output current Iout flowing through main amplifier 102. For example, the tail current flowing through current sources Itail1 and / or Itail2 should be less than half, less than a quarter, less than 1 / 5, less than 1 / 10, less than 1 / 20, less than 1 / 30, less than 1 / 40, less than 1 / 50, less than 1 / 100, or other suitable fraction of the output current Iout flowing through main amplifier 102. Limiting the tail current of auxiliary compensation circuit 110 in this way helps ensure that any current flowing into auxiliary compensation circuit 110 from the main amplifier output path is small and therefore does not affect the fundamental transconductance Gm of main amplifier 102.

[0058] Specifically, the compensation circuit 110 can be biased in a current-limited or saturated region, so that the compensation circuit 110 can generate a highly compressed transconductance with higher order nonlinearity. Figure 6 This is a diagram illustrating the current Iaux that flows through the AMAM distortion compensation circuit 110. (See diagram for example.) Figure 6 As shown, the current distribution 204 can saturate at the positive tail current level Itail for a large +Vin level, and can saturate at the negative tail current level -Itail for a large -Vin level. Figure 7 The corresponding transconductance Gm of the compensation circuit 110 is plotted, which is expressed as a function of the input voltage Vin. Figure 6 The first derivative of curve 204 in the figure. For example... Figure 7 As shown, transconductance curve 206 exhibits a maximum level when the input voltage Vin is equal to zero, and decreases to a lower level as the input voltage Vin becomes more positive or more negative. Specifically, when the input voltage Vin reaches the positive maximum voltage level Vmax, the transconductance Gm is compressed to zero. At the other end, when the input voltage Vin reaches the negative maximum voltage level -Vmax, the transconductance is also compressed to zero. These maximum voltage levels +Vmax and -Vmax correspond to the input voltage levels when the current Iaux saturates at the +Itail and -Itail levels, respectively. Figure 6 As shown in the image.

[0059] The Gm compression exhibited by one or more compensation circuits 110 can generate its own third-order or other higher-order nonlinear products or terms. This higher-order nonlinearity generated from the compensation circuits 110 can be adjusted and applied to amplifier 102 to cancel the third-order nonlinearity of the main amplifier 102 without negatively affecting the signal gain. For example, associated with compensation circuits 110... Figure 7The Gm distribution 206 can be reversed and applied "out of phase" to the main amplifier 102 to help at least partially cancel the third-order nonlinear term of the amplifier 102. This out-of-phase application of Gm can be achieved via a cross-coupling or out-of-phase connection 112 that couples the compensation circuit 110-1 to the amplifier 102.

[0060] exist Figure 3 In the example, compensation circuit 110-2 can be coupled in parallel with amplifier 102 via a “non-inverting” connection, wherein the gate and drain terminals of M5 are coupled to the gate and drain terminals of input transistor M1, respectively, and wherein the gate and drain terminals of M6 are coupled to the gain and drain terminals of input transistor M2, respectively. In contrast to an out-of-phase connection, this non-inverting connection allows the transconductance Gm of compensation circuit 110-2 to be additively applied to the fundamental Gm of amplifier 102. A “non-inverting” connection can therefore refer to, and is defined herein, a connection that allows the current passing through distortion compensation circuit 110 to be subtracted from the output current of main amplifier 102. Conversely, a “non-inverting” connection can refer to, and is defined herein, a connection that allows the current passing through distortion compensation circuit 110 to be added to the output current of main amplifier 102.

[0061] The compensation circuit 110-1 is out-of-phase coupled to the amplifier 102, and the compensation circuit 110-2 is in-phase coupled to the amplifier 102. Figure 3 The examples are illustrative. Generally, amplifier circuit 100 may include one or more compensation circuits, which are at least partially coupled in-phase and out-of-phase to amplifier 102, wholly coupled out-of-phase to amplifier 102, or wholly coupled in-phase to amplifier 102. Compensating for higher-order nonlinear terms in this manner is technically advantageous and beneficial for reducing AMAM distortion.

[0062] This cancellation of the undesirable nonlinear term can be shown in the frequency domain. Consider a two-tone scenario where the input / gate terminals of the transistors in circuit 100 receive a first signal at a first frequency (tone) f1 and a second signal at a second frequency (tone) f2. Figure 3 In the example, input transistors M1 and M2 may be configured to receive input signals [v in0 (f1)+v in0 (f2)] gate terminal. Due to the third-order nonlinearity of input transistors M1 and M2, a generator such as i can be generated at the output terminal of the main amplifier 102. out0 (2*f1-f2) and i out0 The DC current IM3 is (2*f2-f1).

[0063] The transistors M3 and M4 of the auxiliary circuit 110-1 may be configured to receive input signals [v] in1 (f1)+vin1 The gate terminal of (f2)]. An IM2 signal, such as v1(f1-f2), can be generated at the source terminals of transistors M3 and M4 (e.g., at the tail node of circuit 110-1). The mixing of signals at the gate and source terminals of transistors M3 and M4 can generate a corresponding IM3 current i at the drain terminals of M3 and M4. out1 (2*f1-f2) and i out1 (2*f2-f1).

[0064] Similarly, transistors M5 and M6 of auxiliary circuit 110-2 may be configured to receive input signals [v] in2 (f1)+v in2 The gate terminal of (f2)]. An IM2 signal, such as v2(f1-f2), can be generated at the source terminals of transistors M5 and M6 (e.g., at the tail node of circuit 110-2). The mixing of signals at the gate and source terminals of transistors M5 and M6 can generate a corresponding IM3 current i at the drain terminals of M5 and M6. out2 (2*f1-f2) and i out2 (2*f2-f1). IM3 current generated by the auxiliary compensation circuit (e.g., i out1 (2*f1-f2), i out1 (2*f2-f1), i out2 (2*f1-f2) and i out2 (2*f2-f1) can be used in-phase and / or out-of-phase at the output terminal of the main amplifier 102 to cancel the IM3 current i associated with the input transistors M1 and M2. out0 (2*f1-f2) and i out0 (2*f2-f1). Operating circuit 100 in this manner can improve gain performance while reducing nonlinearity.

[0065] Figure 7 The example illustrates a Gm distribution 206 varying between +Vmax and -Vmax, which defines a total gain-compressed voltage range equal to 2*Vmax. According to some embodiments, the gain-compressed voltage range provided by the AMAM distortion compensation circuit 110 can be adjustable. Figure 8 This is a graph illustrating how the transconductance Gm of compensation circuit 110 can be adjusted using different attenuation factors. Different attenuation factors can be provided by tuning or adjusting signal attenuation circuits 112-1 and 112-2. For example, attenuation circuit 112-1 can be adjusted to provide a first attenuation factor for the gain compression voltage range of compensation circuit 110-1, while attenuation circuit 112-2 can be adjusted to provide a second attenuation factor for the gain compression voltage range of compensation circuit 110-2.

[0066] like Figure 8 As shown, the first curve 210 corresponds to the first Gm distribution generated when the attenuation factor is adjusted to a first value k1, the second curve 212 corresponds to the second Gm distribution generated when the attenuation factor is adjusted to a second value k2 different from k1, and the third curve 214 corresponds to the third Gm distribution generated when the attenuation factor is adjusted to a third value k3 different from k1 and k2, and so on. Attenuation factor k2 provides more signal attenuation than k1. Attenuation factor k3 provides more signal attenuation than k2. Generally, the attenuation circuit 112 can be configured to provide signal attenuation of approximately -1dB, -2dB, -3dB, -4dB, -5dB, -5 to -10dB, or other suitable amounts of signal reduction.

[0067] exist Figure 8 In the example, greater signal attenuation will reduce the maximum Gm to zero at Vin, while extending the maximum gain compression voltage range. For example, comparing curves 210 and 212, curve 212, associated with more signal attenuation, has a lower maximum Gm, but extends the positive voltage range from Vmax1 to Vmax2, which is greater than Vmax1. Similarly, comparing curves 212 and 214, curve 214, associated with more signal attenuation, has an even lower maximum Gm, but further extends the positive voltage range from Vmax2 to Vmax3, which is greater than Vmax2. Therefore, the amount of gain compression provided by each AMAM distortion compensation circuit 110 can be adjusted by tuning the attenuation factor of circuit 112, which couples the input of circuit 110 to the gate terminals of the input transistors M1 and M2 in the main amplifier 102.

[0068] The signal attenuation circuit 112 can be implemented in various ways (for example, see...). Figure 9A , Figure 9B and Figure 9C ). Figure 9A A suitable specific implementation of the signal attenuation circuit 112 is shown. For example... Figure 9A As shown, the attenuation circuit 112 may include a series capacitor 304 coupled to the shunt capacitor 306. The series capacitor 304 may have a first terminal coupled to the input terminal 300 and a second terminal coupled to the output terminal 302. The parallel capacitor 306 may have a first terminal coupled to the output terminal 302 and a second terminal coupled to the ground line 104. The input terminal 300 may be coupled to the gate of one of the input transistors M1 or M2 in the main amplifier 102. The output terminal 302 may be coupled to the gate of one of the transistors in the corresponding AMAM distortion compensation circuit 110. The attenuation circuit 112 configured in this way is sometimes referred to as a capacitive voltage divider circuit.

[0069] Figure 9BAnother specific implementation of the signal attenuation circuit 112 is shown. For example... Figure 9B As shown, the attenuation circuit 112 may include a series resistor 310 coupled to the shunt resistor 312. The series resistor 310 may have a first terminal coupled to the input terminal 300 and a second terminal coupled to the output terminal 302. The shunt resistor 312 may have a first terminal coupled to the output terminal 302 and a second terminal coupled to the ground wire 104. The input terminal 300 may be coupled to the gate of one of the input transistors M1 or M2 in the main amplifier 102. The output terminal 302 may be coupled to the gate of one of the transistors in the corresponding AMAM distortion compensation circuit 110. The attenuation circuit 112 configured in this way is sometimes referred to as a resistive voltage divider circuit.

[0070] Figure 9C Another specific implementation of the signal attenuation circuit 112 is shown. For example... Figure 9C As shown, the attenuation circuit 112 may include a primary coil 322 inductively coupled to a secondary coil 324. The primary coil 322 may have opposite terminals coupled to a differential input terminal 300. The secondary coil 324 may have opposite terminals coupled to a differential output terminal 302. The primary coil 322 may have a first number of turns, while the secondary coil 324 may have a second number of turns different from the first number of turns. The ratio of the first number of turns in the primary coil 322 to the second number of turns in the coil 324 may be set to N:1 or another suitable ratio to provide a target attenuation factor. The differential input terminal 300 may be coupled to the gates of input transistors M1 and M2 in the main amplifier 102. The differential output terminal 302 may be coupled to the gates of the differential pair transistors in the corresponding AMAM distortion compensation circuit 110. The coils 322 and 324 arranged in this manner together form a transformer, and are therefore sometimes referred to as a transformer-based attenuation circuit. Figure 9A , Figure 9B and Figure 9C The implementation scheme is exemplary. Generally, other types of signal attenuation circuits 112 may be used within circuit 100 to tune the Gm distribution of one or more AMAM distortion compensation circuits 110.

[0071] Figure 10 This is a graph illustrating how the third-order nonlinearity cancellation range can be adjusted by selectively activating one or more AMAM distortion compensation circuits within amplifier circuit 100. Curve 250 can represent the Gm distribution of circuit 100 when no compensation circuit 110 is activated or switched to use. As shown by curve 250, the total transconductance of amplifier circuit 100 will vary across the entire input voltage range. In contrast, curve 252 can represent the Gm distribution when, for example... Figure 3At least one compensation circuit, such as compensation circuit 110-1, is activated or switched to improve the Gm distribution of circuit 100 when in use. As shown in curve 252, the total transconductance of amplifier circuit 100 can be flattened when the input voltage Vin is within the first voltage range R1. This Gm flattening can be a result of third-order intermodulation distortion cancellation.

[0072] Furthermore, curve 254 can represent another Gm distribution of amplifier circuit 100 when different signal attenuation factors are used to tune compensation circuit 110-1. (As in conjunction with...) Figure 8 The gain compression voltage range can be extended by adjusting or amplifying the attenuation factor k. Curve 254 can therefore correspond to a scenario where the compensation circuit 110-1 has been adjusted to provide more signal attenuation than curve 252. The Gm cancellation contribution from the compensation circuit 110-1 can be adjusted using the attenuation circuit 112-1 (e.g., by tuning the attenuation factor of the tuning circuit 112-1). As shown in curve 254, the total transconductance of the amplifier circuit 100 can be relatively flat when the input voltage Vin is within a second voltage range R2, which is wider than the first voltage range R1 associated with curve 252.

[0073] Furthermore, curve 256 can represent another Gm distribution of amplifier circuit 100 when compensation circuits 110-1 and 110-2 are simultaneously activated or switched on. Compared to curve 254, curve 256 can exhibit an even flatter response over an extended voltage range R2. The use of more than one compensation circuit 110 can therefore help further optimize the Gm distribution (e.g., by selectively applying a cancellation IM3 term via an out-of-phase connection and / or an addition IM3 term via a non-in-phase connection). The Gm cancellation or addition contribution from compensation circuit 110-2 can be adjusted using attenuation circuit 112-2 (e.g., by tuning the attenuation factor of circuit 112-2). In other words, a second or additional auxiliary compensation circuit (e.g., circuit 110-2) can be added to help correct any residual errors from the first auxiliary compensation circuit (e.g., circuit 110-1) to help provide a flatter Gm distribution.

[0074] Figure 11 This is a graph plotting the normalized gain of amplifier circuit 100 as a function of input power Pin. Curve 400 represents the gain of circuit 100 when compensation circuit 110 is not activated or switched to use. Figure 11As shown, curve 400 exhibits gain compression at a relatively low pin level, as illustrated by a relatively early roll-off in the gain. In contrast, curve 402 represents the gain of circuit 100 when at least one compensation circuit, such as circuit 110-1, has been activated or switched to use. Curve 402 introduces the gain roll-off point but experiences a certain amount of gain peaking before the roll-off. Such gain peaking can be attributed to uncancelled residual errors left over from the higher-order nonlinearity associated with the first auxiliary circuit 110-1. Furthermore, curve 404 represents the gain of circuit 100 when both compensation circuits 110-1 and 110-2 have been activated or switched to use. Activation of the second auxiliary compensation circuit 110-2 helps to cancel any remaining residual errors left over from the first auxiliary compensation circuit 110-1, resulting in reduced gain peaking and distortion and thus a flatter gain response.

[0075] Figure 12 This is a graph illustrating how the third-order intercept point can be improved by selectively activating one or more AMAM distortion compensation circuits 110. Specifically, Figure 12 Plot the "Input" third-order intercept, or IIP3, which is a parameter used to characterize the linearity of electronic circuits such as amplifier circuit 100. The input third-order intercept represents the input power level Pin at which the third-order intermodulation product generated by circuit 100 reaches the same level as the desired output signal in a two-tone scenario. Generally, it is desirable to increase IIP3. For example... Figure 12 As shown, curve 450 represents the IIP3 distribution of circuit 100 when no compensation circuit 110 is activated or switched to use.

[0076] In contrast, curve 452 represents the IIP3 distribution of amplifier circuit 100 when at least one compensation circuit, such as compensation circuit 110-1, has been activated or switched to use. Curve 452 exhibits an improved or greater IIP3 level compared to curve 450. Furthermore, curve 454 represents the IIP3 distribution of circuit 100 when multiple compensation circuits, such as compensation circuits 110-1 and 110-2, have been activated or switched to use. Curve 454 exhibits an improved or greater IIP3 level compared to curve 452. Activation of the second auxiliary compensation circuit 110-2 helps to offset any residual error left over from the first auxiliary compensation circuit 110-1, resulting in an improved third-order intercept (IP3) level. Although... Figure 12 The input IP3 is shown, but when plotting the "output" third-order intercept (OIP3) of amplifier circuit 100, a similar improvement can be achieved by selectively activating one or more AMAM distortion compensation circuits 110.

[0077] Figure 3The example is illustrative, in which the gate terminals of input transistors M1 and M2 are directly coupled to input terminals IN1 and IN2. Figure 13 Another embodiment of an amplifier circuit 100 with differential input ports coupled to a transformer 500 is shown. Specifically, the transformer 500 may have a primary coil 501p configured to receive an input voltage signal Vin and secondary coils 501s having opposing terminals coupled to the gate terminals of input transistors M1 and M2. The transformer 500 is therefore sometimes referred to as an input transformer. If desired, the input transistors M1 and M2 may have drain terminals coupled to the amplifier output terminals OUT1 and OUT2 via an additional transformer 502. The transformer 502 coupled to the output terminals OUT1 and OUT2 may be referred to as an output transformer. Other load components may be used if desired.

[0078] like Figure 13 As shown, the AMAM distortion compensation circuit 110 can be coupled to the main amplifier 102 via an optional switching circuit 504. For example, the first compensation circuit 110-1 can be selectively coupled to the drain terminals of input transistors M1 and M2 via the first switching circuit 504-1, while the second compensation circuit 110-2 can be selectively coupled to the drain terminals of input transistors M1 and M2 via the second switching circuit 504-2. The switching circuit 504 can be configured to couple the compensation circuit 110 to the amplifier 102 via a desired switching polarity. For example, the switching circuit 504-1 can be configured to couple the compensation circuit 110-1 to the amplifier 102 via an in-phase (or "positive") connection, an out-of-phase (or "negative") connection, or optionally decouple the compensation circuit 110-1 from the amplifier 102 to disable or deactivate the circuit 110-1. Similarly, switching circuit 504-2 can be configured to couple compensation circuit 110-2 to amplifier 102 via in-phase (or "positive") connection or out-of-phase (or "negative") connection, or optionally decouple compensation circuit 110-2 from amplifier 102 to disable or disable circuit 110-2. Each additional compensation circuit 110 included in amplifier circuit 100 can be selectively coupled to amplifier 102 via a corresponding switching circuit 504.

[0079] The AMAM distortion compensation circuit 110 includes only n-type transistors (see, for example, NMOS transistors M3, M4, M5, and M6). Figure 13 The examples are illustrative. Figure 14 Another embodiment of the amplifier circuit 100 is illustrated, in which different types of transistors can be used to implement the AMAM distortion compensation circuit 110. For example... Figure 14As shown, the first compensation circuit 110-1 may include n-type (n-channel) transistors M3 and M4, which have source terminals coupled to the first tail current source Itail1 and drain terminals coupled to the main amplifier 102 via the first optional switching circuit 504-1.

[0080] On the other hand, the second compensation circuit 110-2 may include p-type (p-channel transistors) P1 and P2. Transistors P1 and P2 may be p-type metal-oxide-semiconductor (PMOS) transistors or other types of p-type switches. Transistors P1 and P2 may have a first source-drain terminal coupled to the tail current source Itail2 and a second source-drain terminal coupled to the main amplifier 102 via the second optional switching circuit 504-2. The tail current source Itail2 may have a first terminal coupled to the first source-drain terminals of transistors P1 and P2 and a second terminal coupled to the power supply line 105 (e.g., a positive power supply line providing a positive power supply voltage thereon). Generally, the amplifier circuit 100 may include one or more AMAM distortion compensation circuits 110, portions of which may include, for example... Figure 14 The examples shown for n-type and p-type transistors may all include only those such as Figure 3 and Figure 13 The example shown may contain only n-type transistors, or may consist entirely of p-type transistors.

[0081] Despite the combination Figures 1 to 14 The described implementation scheme is primarily aimed at compensating for AMAM distortion; however, the techniques described herein can be used additionally or alternatively to compensate for AMPM distortion. For example, the main amplifier may optionally be coupled to one or more auxiliary compensation circuits, at least some of which may be configured with appropriate transistor types, transistor sizes, and / or bias voltages to reduce AMPM distortion or otherwise improve the linearity of the overall circuit. Auxiliary circuits 110-1 and 110-2 may therefore sometimes also be referred to as AMAM and / or AMPM distortion compensation circuits.

[0082] The above combination Figures 1 to 14 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1The storage circuit 16 and / or wireless communication circuit 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of the device 10 (e.g., processing circuitry in wireless communication circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0083] According to the embodiment, a circuit is provided, the circuit including a first input transistor and a second input transistor, and an amplitude modulation to amplitude modulation (AMAM) or amplitude modulation to phase modulation (AMPM) distortion compensation circuit, the AMAM or AMPM distortion compensation circuit including a third transistor having a gate terminal coupled to the gate terminal of the first input transistor; a fourth transistor having a gate terminal coupled to the gate terminal of the second input transistor; and a tail current source coupled to the first source-drain terminal of the third transistor and coupled to the first source-drain terminal of the fourth transistor.

[0084] According to another embodiment, the gate terminal of the first input transistor is optionally coupled to a first input terminal of the circuit, and the first input transistor optionally includes a first source-drain terminal coupled to a power supply line and a second source-drain terminal coupled to a first output terminal of the circuit.

[0085] According to another embodiment, the gate terminal of the second input transistor is optionally coupled to a second input terminal of the circuit, and the second input transistor optionally includes a first source-drain terminal coupled to a power supply line and a second source-drain terminal coupled to a second output terminal of the circuit.

[0086] According to another embodiment, the third transistor optionally includes a second source-drain terminal coupled to the second input transistor, and the fourth transistor optionally includes a second source-drain terminal coupled to the first input transistor.

[0087] According to another embodiment, the circuit optionally includes a switching circuit coupled between the first input transistor and the third transistor and further coupled between the second input transistor and the fourth transistor.

[0088] According to another embodiment, the circuit optionally includes a signal attenuation circuit coupled between the gate terminal of the first input transistor and the gate terminal of the third transistor.

[0089] According to another embodiment, the signal attenuation circuit is optionally configured to provide an adjustable attenuation factor for the gain compression voltage range used to tune the AMAM or AMPM distortion compensation circuit.

[0090] According to another embodiment, the tail current source is optionally configured to transmit a tail current less than one-fifth of the output current flowing through the first input transistor and the second input transistor.

[0091] According to another embodiment, the circuit optionally includes an additional AMAM or AMPM distortion compensation circuit, which includes a fifth transistor having a gate terminal coupled to the gate terminal of a first input transistor; a sixth transistor having a gate terminal coupled to the gate terminal of a second input transistor; and an additional tail current source coupled to the first source-drain terminal of the fifth transistor and coupled to the first source-drain terminal of the sixth transistor.

[0092] According to another embodiment, the third transistor optionally includes a second source-drain terminal coupled to the second input transistor; the fourth transistor optionally includes a second source-drain terminal coupled to the first input transistor; the fifth transistor optionally includes a second source-drain terminal coupled to the first input transistor; and the sixth transistor optionally also includes a second source-drain terminal coupled to the second input transistor.

[0093] According to another embodiment, the circuit optionally includes a first switching circuit coupled between the AMAM or AMPM distortion compensation circuit and the first and second input transistors, and a second switching circuit coupled between an additional AMAM or AMPM distortion compensation circuit and the first and second input transistors.

[0094] According to another embodiment, the circuit optionally includes a first attenuation circuit coupled between the gate terminals of the first and second input transistors and the gate terminals of the third and fourth transistors, and a second attenuation circuit coupled between the gate terminals of the first and second input transistors and the gate terminals of the fifth and sixth transistors.

[0095] According to another embodiment, the third, fourth, fifth, and sixth transistors optionally include n-type transistors.

[0096] According to another embodiment, the third and fourth transistors optionally include n-type transistors, and the fifth and sixth transistors optionally include p-type transistors.

[0097] According to another embodiment, the circuit optionally includes a first transformer coupled to the gate terminals of a first input transistor and a second input transistor; and a second transformer coupled to the source-drain terminals of the first input transistor and the second input transistor.

[0098] According to the implementation scheme, a circuit is provided, the circuit including a differential amplifier having a first input terminal and a second input terminal; and a distortion compensation circuit having input terminals coupled to the first input terminal and the second input terminal of the differential amplifier, wherein the distortion compensation circuit is further out-of-phase coupled to the differential amplifier.

[0099] According to another embodiment, the distortion compensation circuit optionally includes a tail current source configured to deliver a tail current less than half the output current flowing through the differential amplifier.

[0100] According to another embodiment, the circuit optionally includes an additional distortion compensation circuit having input terminals coupled to a first input terminal and a second input terminal of the differential amplifier, wherein the additional distortion compensation circuit is in-phase coupled to the differential amplifier.

[0101] According to another embodiment, the circuit optionally includes a first tunable attenuation circuit coupled between the first and second input terminals of the differential amplifier and the distortion compensation circuit, and further includes a second tunable attenuation circuit coupled between the first and second input terminals of the differential amplifier and the additional distortion compensation circuit.

[0102] According to the embodiment, a circuit is provided, the circuit comprising: a first input transistor having a gate terminal coupled to a first input terminal, a drain terminal coupled to a first output terminal, and a source terminal coupled to ground; a second input transistor having a gate terminal coupled to a second input terminal, a drain terminal coupled to a second output terminal, and a source terminal coupled to ground; and a third transistor having a gate terminal coupled to the gate terminal of the first input transistor, a source terminal coupled to a first tail current source, and a drain terminal coupled to the second output terminal. Terminals; a fourth transistor having a gate terminal coupled to the gate terminal of the second input transistor, a source terminal coupled to the first tail current source, and a drain terminal coupled to the first output terminal; a fifth transistor having a gate terminal coupled to the gate terminal of the first input transistor, a source terminal coupled to the second tail current source, and a drain terminal coupled to the first output terminal; and a sixth transistor having a gate terminal coupled to the gate terminal of the second input transistor, a source terminal coupled to the second tail current source, and a drain terminal coupled to the second output terminal.

[0103] The foregoing is merely illustrative and various modifications can be made to the described implementation. The foregoing implementation can be implemented individually or in any combination.

[0104] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. A circuit, the circuit comprising: First input transistor and second input transistor; as well as An amplitude modulation to amplitude modulation (AMAM) or amplitude modulation to phase modulation (AMPM) distortion compensation circuit, wherein the amplitude modulation to amplitude modulation (AMAM) or amplitude modulation to phase modulation (AMPM) distortion compensation circuit includes: A third transistor having a gate terminal coupled to the gate terminal of the first input transistor; A fourth transistor having a gate terminal coupled to the gate terminal of the second input transistor; and A tail current source, which is coupled to the first source-drain terminal of the third transistor and to the first source-drain terminal of the fourth transistor.

2. The circuit according to claim 1, wherein: The gate terminal of the first input transistor is coupled to the first input terminal of the circuit; and The first input transistor further includes a first source-drain terminal coupled to a power supply line and a second source-drain terminal coupled to a first output terminal of the circuit.

3. The circuit according to claim 2, wherein: The gate terminal of the second input transistor is coupled to the second input terminal of the circuit; and The second input transistor also includes a first source-drain terminal coupled to the power line and a second source-drain terminal coupled to the second output terminal of the circuit.

4. The circuit according to claim 1, wherein: The third transistor further includes a second source-drain terminal coupled to the second input transistor; and The fourth transistor also includes a second source-drain terminal coupled to the first input transistor.

5. The circuit according to claim 4, further comprising: A switching circuit coupled between the first input transistor and the third transistor and further coupled between the second input transistor and the fourth transistor.

6. The circuit according to claim 1, further comprising: A signal attenuation circuit is coupled between the gate terminal of the first input transistor and the gate terminal of the third transistor.

7. The circuit of claim 6, wherein the signal attenuation circuit is configured to provide an adjustable attenuation factor for tuning the gain compression voltage range of the AMAM or AMPM distortion compensation circuit.

8. The circuit of claim 1, wherein the tail current source is configured to transmit a tail current less than one-fifth of the output current flowing through the first input transistor and the second input transistor.

9. The circuit according to claim 1 further includes an additional AMAM or AMPM distortion compensation circuit, said additional AMAM or AMPM distortion compensation circuit having: A fifth transistor having a gate terminal coupled to the gate terminal of the first input transistor; A sixth transistor having a gate terminal coupled to the gate terminal of the second input transistor; as well as An additional tail current source is coupled to the first source-drain terminal of the fifth transistor and to the first source-drain terminal of the sixth transistor.

10. The circuit according to claim 9, wherein: The third transistor further includes a second source-drain terminal coupled to the second input transistor; The fourth transistor further includes a second source-drain terminal coupled to the first input transistor; The fifth transistor further includes a second source-drain terminal coupled to the first input transistor; and The sixth transistor also includes a second source-drain terminal coupled to the second input transistor.

11. The circuit according to claim 10, further comprising: A first switching circuit is coupled between the AMAM or AMPM distortion compensation circuit and the first input transistor and the second input transistor. as well as A second switching circuit is coupled between the additional AMAM or AMPM distortion compensation circuit and the first input transistor and the second input transistor.

12. The circuit according to claim 9, further comprising: A first attenuation circuit is coupled between the gate terminals of the first and second input transistors and the gate terminals of the third and fourth transistors. as well as A second attenuation circuit is coupled between the gate terminals of the first and second input transistors and the gate terminals of the fifth and sixth transistors.

13. The circuit of claim 9, wherein the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprise n-type transistors.

14. The circuit of claim 9, wherein the third transistor and the fourth transistor comprise n-type transistors, and wherein the fifth transistor and the sixth transistor comprise p-type transistors.

15. The circuit according to claim 1, further comprising: A first transformer, the first transformer being coupled to the gate terminals of the first input transistor and the second input transistor; as well as A second transformer is coupled to the source-drain terminals of the first input transistor and the second input transistor.

16. A circuit, the circuit comprising: A differential amplifier having a first input terminal and a second input terminal; as well as A distortion compensation circuit having input terminals coupled to the first input terminal and the second input terminal of the differential amplifier, wherein the distortion compensation circuit is further out-of-phase coupled to the differential amplifier.

17. The circuit of claim 16, wherein the distortion compensation circuit further comprises a tail current source configured to transmit a tail current less than half the output current flowing through the differential amplifier.

18. The circuit according to claim 16, further comprising: An additional distortion compensation circuit has input terminals coupled to the first input terminal and the second input terminal of the differential amplifier, wherein the additional distortion compensation circuit is in-phase coupled to the differential amplifier.

19. The circuit according to claim 18, further comprising: A first tunable attenuation circuit is coupled between the first and second input terminals of the differential amplifier and the distortion compensation circuit. as well as A second tunable attenuation circuit is coupled between the first and second input terminals of the differential amplifier and the additional distortion compensation circuit.

20. A circuit, the circuit comprising: A first input transistor has a gate terminal coupled to a first input terminal, a drain terminal coupled to a first output terminal, and a source terminal coupled to ground. The second input transistor has a gate terminal coupled to a second input terminal, a drain terminal coupled to a second output terminal, and a source terminal coupled to the ground line; A third transistor having a gate terminal coupled to the gate terminal of the first input transistor, a source terminal coupled to the first tail current source, and a drain terminal coupled to the second output terminal; A fourth transistor having a gate terminal coupled to the gate terminal of the second input transistor, a source terminal coupled to the first tail current source, and a drain terminal coupled to the first output terminal; A fifth transistor having a gate terminal coupled to the gate terminal of the first input transistor, a source terminal coupled to the second tail current source, and a drain terminal coupled to the first output terminal; as well as A sixth transistor having a gate terminal coupled to the gate terminal of the second input transistor, a source terminal coupled to the second tail current source, and a drain terminal coupled to the second output terminal.

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