Message uploading method, data processing unit and network processor

Abstract

The invention relates to a message uploading method, a data processing unit and a network processor. The message uploading method comprises the following steps: receiving at least one message of any virtualization queue; obtaining a cache unit length corresponding to the virtualization queue; determining a descriptor reading number according to the length of the at least one message and the length of the cache unit; the descriptors of the number are read through a single PCIE read operation; and writing the at least one message into the cache unit pointed by the corresponding descriptor. According to the message sending method and device, the number of times of reading the descriptor when the message is sent to the Virtio driver can be reduced, the expenditure of PCIe is reduced, and the processing rate of the super-large-frame message is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Virtio, in particular to a message sending method, a data processing unit and a network processor. BACKGROUND

[0002] Virtio is a general-purpose semi-virtualization I / O framework, including Virtio driver, Virtio device and virtualization queue (Virtqueue), and data interaction between the Virtio driver and the Virtio device is implemented through the Virtqueue. Taking SplitVirtqueues as an example, the Virtio driver mainly includes three parts of a descriptor table (Descriptor Ring), an available ring table (AvailableRing) and a used ring table (Used Ring), each descriptor entry (Descriptor Entry) of the descriptor table contains a buffer address (buffer addr), a buffer length (buffer length), a flag and a next hop pointer (next), and the available ring table and the used ring table store pointers (id), which point to a descriptor entry in the descriptor table. The Virtio driver needs to prepare a buffer before receiving a message, and then notifies the Virtio device to start receiving message data. The data processing procedure of the Virtio device is as follows:

[0003] (1) The Virtio device receives an Ethernet message and stores it in the local buffer of the Virtio device;

[0004] (2) The Virtio device initiates a read operation to the available ring table of the Virtio driver to obtain the pointer (id) of the available ring table;

[0005] (3) The descriptor of the descriptor table is read according to the pointer (id) obtained from the available ring table to obtain the buffer address, the buffer length, the flag and the next hop pointer and the like information;

[0006] (4) The Ethernet message is read out from the local buffer of the Virtio device and sent to the buffer unit pointed by the descriptor;

[0007] (5) The used descriptor is updated, that is, the index (index) and the pointer (id) of the used ring table are updated, and the Virtio driver obtains the Ethernet message in the buffer unit through reading the index (index) and the pointer (id) of the used ring table and the like information, and recycles the descriptor entry of the descriptor table for continuous use.

[0008] As Figure 1As shown, the Virtio device reads one descriptor at a time, and the next round of descriptor reading is initiated only after the current descriptor is used up. If the return time of the descriptor is 1us, the message processing performance of one virtualization queue is 1Mpps (packets per second). If the performance of the entire Virtio system is to be improved, multiple virtualization queues have to be enabled to achieve the performance through pipelining, but the number of virtualization queues, the logical resources and area of the Virtio device, etc. limit the performance improvement by merely increasing the number of virtualization queues. SUMMARY

[0009] The present application aims to provide a message uploading method, a data processing unit and a network processor to reduce the number of times of reading descriptors when uploading messages to a virtio driver, reduce the overhead of PCIe, and greatly improve the processing rate of super large frame messages.

[0010] To achieve the above-mentioned purpose, the embodiments of the present application provide a message uploading method, which comprises:

[0011] receiving at least one message of any virtualization queue;

[0012] obtaining the length of the cache unit corresponding to the virtualization queue;

[0013] determining the number of descriptor readings according to the length of the at least one message and the length of the cache unit;

[0014] reading the corresponding descriptors through a single PCIE read operation;

[0015] writing the at least one message into the cache unit pointed by the corresponding descriptors.

[0016] The embodiments of the present application also provide a data processing unit, which comprises a message receiving module, a message uploading module, a cache length obtaining module, a descriptor number determining module and a descriptor reading module.

[0017] The message receiving module is used to receive at least one message of any virtualization queue;

[0018] The cache length obtaining module is used to obtain the length of the cache unit corresponding to the virtualization queue;

[0019] The descriptor number determining module is used to determine the number of descriptor readings according to the length of the at least one message and the length of the cache unit;

[0020] The descriptor reading module is used to read the corresponding descriptors through a single PCIE read operation;

[0021] The message uploading module is configured to write the at least one message into the cache unit pointed by the corresponding descriptor.

[0022] The application further provides a data processing unit, comprising:

[0023] a communication interface configured to communicate with other electronic devices;

[0024] a memory configured to store computer program instructions;

[0025] a processor configured to execute the computer program instructions to support the data processing unit to implement the method.

[0026] The application further provides a network processor comprising a Virtio driver and the data processing unit as described above, wherein the Virtio driver is configured to run on a host side and to generate the descriptors.

[0027] The application further provides a computer program product comprising computer program instructions configured to instruct a computer device to perform operations corresponding to the method.

[0028] The packet uploading method, the data processing unit and the network processor provided by the application have the following advantages

[0029] Advantages:

[0030] The data processing unit communicates with the Virtio driver through at least one Virtqueue, and when receiving at least one message of any Virtqueue, acquires the length of the cache unit corresponding to the Virtqueue. Each Virtqueue has a corresponding cache unit length. According to the length of the at least one message and the length of the cache unit, it can be determined how many cache units are needed to meet the reporting of the at least one message. Each descriptor points to a cache unit, so the number of descriptors to be read can be determined. Then, a corresponding number of descriptors are read in batches at one time, and then the at least one message is uploaded to the cache unit pointed by the corresponding descriptor, thereby reducing the number of times of reading descriptors when uploading messages to the Virtio driver, reducing the overhead of PCIe, and greatly improving the processing rate of super-large frame messages. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0032] Figure 1 A message uploading flowchart disclosed in the background art.

[0033] Figure 2 A message uploading flowchart of an embodiment of the present application.

[0034] Figure 3 An interaction diagram of a data processing unit and a Virtio driver in an embodiment of the present application.

[0035] Figure 4 A principle diagram of message uploading in an embodiment of the present application.

[0036] Figure 5 A structure diagram of a data processing unit in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The detailed description of the drawings is intended as an illustration of the current embodiments of the present application and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be within the spirit and scope of the present application.

[0038] Reference Figures 2-3 One embodiment of the present application provides a message uploading method, which aims to reduce the number of times of reading descriptors when uploading messages to a virtio driver, reduce the overhead of PCIe, and greatly improve the processing rate of super-large frame messages. The method of the embodiment comprises the following steps:

[0039] Step S10, receiving at least one message of any virtual queue;

[0040] Specifically, the Virtio driver needs to prepare a buffer unit before receiving the message, and then notifies a data processing unit (DPU). The data processing unit starts receiving message data and caches it locally. In the data processing unit, the received messages are cached according to the queue.

[0041] Step S20, obtaining the length of the buffer unit corresponding to the virtual queue;

[0042] Specifically, the Virtio driver communicates with the data processing unit through a plurality of virtual queues (Virtqueue). After receiving the message, the data processing unit parses the message to obtain the queue number carried by the message, determines which virtual queue (Virtqueue) the message belongs to according to the queue number, and the length of the buffer unit corresponding to different virtual queues (Virtqueue) may be different because different virtual queues (Virtqueue) may be used for transmission of different types of messages. The length of the buffer unit can be obtained by querying the local data according to the queue number.

[0043] Step S30, determining the number of descriptors to be read according to the length of the at least one packet and the length of the buffer unit;

[0044] Specifically, according to the length of the at least one packet and the length of the buffer, the number of buffers required to meet the reporting of the at least one packet can be determined, i.e. the length of the packet is divided by the length of the descriptor and the integer part is rounded up to obtain the number of descriptors required by one packet, and then the number of packets is multiplied by the number of descriptors required by a single packet to obtain the number of descriptors. Each descriptor points to a buffer, for example, the length of a packet is 9600 Byte and the length of the buffer is 4096 Byte, then 3 buffers are required to store the packet, assuming there are 4 such packets, then 12 buffers are required; therefore, the number of descriptor read operations can be determined to be 12.

[0045] Step S40, reading the number of descriptors by a single PCIE read operation;

[0046] Specifically, taking Split Virtqueues as an example, each Virtqueue includes a descriptor table (Descriptor Ring), an available ring table (Available Ring) and a used ring table (Used Ring), according to the queue number of the Virtqueue, the corresponding available ring table (Available Ring) can be found, then the pointer is read from the available ring table (Available Ring), and the descriptor pointed to by the pointer is read from the descriptor table (Descriptor Ring), and each descriptor contains next field information, according to which the corresponding next descriptor can be found, and the number of descriptors is read by a single PCIE read operation, i.e. 12 descriptors are read by a single PCIE read operation.

[0047] Step S50, writing the at least one packet into the buffer unit pointed to by the corresponding descriptor.

[0048] Specifically, after a certain number of descriptors are read in batches, the packet received in step S10 is written into at least one buffer unit corresponding to the corresponding descriptor, and then the used ring table (Used Ring) of the Virtqueue is updated to notify the Virtio driver.

[0049] As described above, the method in this embodiment reduces the number of times the data processing unit reads the descriptor when sending messages to the Virtio driver, thereby reducing PCIe overhead and greatly improving the processing rate of very large frame messages, providing an effective solution for optimizing the performance of the data processing unit.

[0050] In some embodiments, step S20 includes:

[0051] The descriptor length memory is queried according to the queue number of the virtualization queue to obtain the cache unit length corresponding to the virtualization queue; wherein, the descriptor length memory stores the cache unit length corresponding to each virtualization queue.

[0052] Specifically, the descriptor length memory is a RAM structure, such as... Figure 4 As shown, Figure 4 The image shows a descriptor length RAM, which includes four storage units corresponding to queues 1 to 4, storing the buffer lengths of queues 1 to 4 (for example, the buffer length of queue 4 is 4096 bytes).

[0053] Step S30 includes:

[0054] The number of descriptors to be read for each message is determined based on the length of each message and the length of the buffer unit, and the number of descriptors to be read is obtained based on the number of descriptors to be read for each message.

[0055] Specifically, assuming a message is 9600 bytes long and the buffer is 4096 bytes long, then 3 buffers are needed to store the message. If there are 3 such messages, then 9 buffers are needed. Therefore, it can be determined that the number of descriptor reads is 9.

[0056] In some embodiments, the method further includes:

[0057] After reading the descriptor corresponding to the number of descriptors read in a single PCIe read operation, the cache unit length corresponding to the last descriptor read is obtained, and the cache unit length corresponding to the virtualization queue stored in the descriptor length memory is updated to the cache unit length corresponding to the last descriptor.

[0058] Specifically, such as Figure 4 As shown, Figure 4The descriptor length RAM includes 4 storage units corresponding to queues 1-4, wherein the initial buffer length of queues 1-4 is 4096 bytes, and the last descriptor read by queue 1 after reading the descriptor points to a buffer with a length of 2048 bytes, so the buffer length of queue 1 is updated to 2048 bytes.

[0059] In some embodiments, the step S30 comprises:

[0060] After determining the descriptor read number, the descriptor read number is stored in a descriptor number storage, and the descriptor number storage includes a plurality of storage units corresponding to a plurality of virtualization queues one by one, and each storage unit is used to store the descriptor read number of the corresponding virtualization queue.

[0061] Specifically, the descriptor read number storage is a RAM structure, as shown in Figure 4 , Figure 4 The descriptor read number RAM includes 4 storage units corresponding to queues 1-4, wherein the descriptor read number of the storage unit corresponding to queue 1 is 4, indicating that 4 descriptors corresponding to queue 1 need to be read, and the descriptor read number of the storage unit corresponding to queues 2-4 is 0, indicating that no descriptor needs to be read.

[0062] Whenever a packet is uploaded, the descriptor read number corresponding to the corresponding virtualization queue in the descriptor number storage is updated;

[0063] Specifically, as shown in Figure 4 During the packet uploading process, the descriptor read number of each storage unit of the descriptor read number RAM needs to be updated, for example, the descriptor read number of the storage unit corresponding to queue 1 of the descriptor read number RAM is 12, packet 1 of queue 1 needs to be written into buffers 1-3, and when the uploading of packet 1 is completed, the descriptor read number of the storage unit corresponding to queue 1 of the descriptor read number RAM is updated to 12-3=9.

[0064] In some embodiments, the step S40 comprises:

[0065] Obtaining a packet valid bitmap and a read waiting bitmap, and determining a target virtualization queue to be scheduled according to the packet valid bitmap and the read waiting bitmap;

[0066] Reading the descriptor number corresponding to the target virtualization queue from the descriptor number storage;

[0067] Reading the descriptor corresponding to the descriptor read number through a single PCIE read operation.

[0068] wherein the message valid bitmap and the read waiting bitmap each include a plurality of bits corresponding to a plurality of virtual queues, each bit of the message valid bitmap indicates whether there is a message of the corresponding virtual queue not yet sent up, and each bit of the read waiting bitmap indicates whether a read descriptor has been initiated.

[0069] Specifically, a bitmap includes a plurality of bits, as shown in Figure 4 Figure 4 The message valid bitmap and the read waiting bitmap each include 4 bits corresponding to queues 1-4. Figure 4 The value of the bit corresponding to queue 1 in the message valid bitmap is 1, indicating that the data processing unit has a message of queue 1 not yet sent up, and the values of the bits corresponding to queues 2-4 are 0, indicating that the data processing unit has not received messages of queues 2-4 or the messages of queues 2-4 have all been sent up to the corresponding buffer.

[0070] In some embodiments, the method includes:

[0071] When any message of any virtual queue is received, the message and the number of descriptors to be read are stored in a message storage;

[0072] When the message storage stores at least one message of any virtual queue, the bit of the message valid bitmap corresponding to the virtual queue is set to 1, and when the message storage does not store at least one message of any virtual queue, the bit of the message valid bitmap corresponding to the virtual queue is set to 0.

[0073] Specifically, the message storage is a RAM structure, as shown in Figure 4 Figure 4 The message storage RAM includes a plurality of storage units, each of which is used to store a message and the number of descriptors to be read corresponding to the message. Assuming that the number of descriptors to be read when message 1 is sent up is 3, and the total number of descriptors to be read when messages 1-4 are sent up is 12, after message 1 is sent up to the corresponding buffer, the number of descriptors to be read corresponding to queue 1 in the descriptor read number RAM is updated to 12-3=9 according to the number of descriptors to be read when message 1 is sent up (3) recorded in the message storage RAM. If messages 1-4 have all been sent up to the buffer and there is no message of queue 1 in the message storage RAM, the bit of the message valid bitmap corresponding to queue 1 needs to be set to 0.

[0074] ​​In some embodiments, the step S40 comprises:

[0075] The read descriptor is stored in the descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module;

[0076] Wherein, when the descriptor FIFO module corresponding to any virtualization queue is empty, the bit corresponding to the virtualization queue in the read waiting bitmap is set to 0; when the descriptor FIFO module corresponding to any virtualization queue is not empty, the bit corresponding to the virtualization queue in the read waiting bitmap is set to 1.

[0077] Specifically, as shown in Figure 4 The read waiting bitmap shows four bits corresponding to queues 1-4, and the initial values of the four bits of the read waiting bitmap are all 1, indicating that the descriptor reading is not initiated.

[0078] Queues 1-4 participate in polling scheduling, and the logical AND of the "message valid bitmap" and the "read waiting bitmap" obtains a new bitmap. If the bit0 of the new bitmap is 1, it indicates that queue 1 has a message stored in the RAM and no descriptor reading is initiated to the driver, so queue 1 can participate in subsequent polling scheduling. If queue 1 is selected, the bit0 of the "read waiting bitmap" is set to 0, indicating that the descriptor reading of queue 1 has been initiated and queue 1 no longer participates in polling scheduling.

[0079] Based on Figure 4 Taking an example for illustration, assuming that the VIRTIO negotiates the MERGEABLE feature, the following describes the data processing unit receiving a message and the descriptor reading process in the embodiment method with a Virtqueue (queue 1) as an example:

[0080] ①The data processing unit receives an Ethernet message of queue 1, queries the "descriptor length RAM", and obtains the descriptor buffer length (assuming the initial value is 4096 bytes) of queue 1. Assuming that the message length is 9600 bytes, the message length is divided by the descriptor length and the integer is rounded up, obtaining the number of descriptors required for the current message as 3. Then the message and the number of descriptors required for reading are saved to the "message storage RAM";

[0081] ②The number of descriptors required by all messages of queue 1 is updated to the "descriptor reading number RAM". Assuming that queue 1 receives 4 messages, each message requires 3 descriptors, and the number finally updated to the "descriptor reading number RAM" is 12;

[0082] ③The initial value of "message valid bitmap" is 0, which means no message is stored in RAM. When queue 1 receives a message, bit 0 of "message valid bitmap" is set to 1.

[0083] ④The logical AND of "message valid bitmap" and "read waiting bitmap" results in a new bitmap. If bit 0 of the new bitmap is 1, it means that queue 1 has messages stored in RAM and no descriptor read has been initiated to Virtio driver. Then, queue 1 can participate in the following polling schedule.

[0084] ⑤The initial value of all bits of "read waiting bitmap" is 1, which means no descriptor read has been initiated. The result of step 4 is used in polling schedule. If queue 1 is selected, bit 0 of "read waiting bitmap" is set to 0, which means that descriptor read has been initiated and queue 1 will not participate in polling schedule.

[0085] ⑥Descriptor read of queue 1 is initiated to Virtio driver. The number of descriptors read is 12.

[0086] ⑦Since 12 descriptors are read in step ⑥, 12 descriptors are returned from Virtio driver in succession and stored in "descriptor storage FIFO" of data processing unit. Meanwhile, the value of queue 1 in "descriptor length RAM" is updated to the buffer length (supposed to be 2048 bytes) in the current received descriptor. When queue 1 receives a message again, the number of descriptors required by the message is calculated using the updated buffer length.

[0087] ⑧When the descriptors are stored in FIFO, the message in "message storage RAM", the number of descriptors required by the message and the descriptors in "descriptor storage FIFO" are read, and the message is uploaded to the buffer pointed by the descriptors.

[0088] ⑨When the last descriptor of queue 1 is read from "descriptor storage FIFO", bit 0 of "read waiting bitmap" is set to 1. If the message in "message storage RAM" is not read completely at this time, queue 1 can participate in polling schedule again, and the above steps are repeated.

[0089] ⑩When a message of queue 1 is completely read from "message storage RAM", the value in "descriptor read number RAM" is updated, i.e. the value in "descriptor read number RAM" is subtracted by the number of descriptors required by the current message (the number of descriptors required by the message in step 1 is stored in "message storage RAM" together with the message). When the last message is completely read from "message storage RAM", bit 0 of "message valid bitmap" is set to 0, which means that data processing unit has no message of queue 1.

[0090] Referring to Figure 4 Figure 5 Another embodiment of the present application provides a data processing unit, comprising a packet receiving module 1, a cache length obtaining module 2, a descriptor number determining module 3, a descriptor reading module 4 and a packet uploading module 5.

[0091] The packet receiving module 1 is configured to receive at least one packet of any virtual queue.

[0092] The cache length obtaining module 2 is configured to obtain a cache unit length corresponding to the virtual queue.

[0093] The descriptor number determining module 3 is configured to determine a descriptor reading number according to a length of the at least one packet and the cache unit length.

[0094] The descriptor reading module 4 is configured to read a descriptor corresponding to the descriptor reading number through a single PCIE reading operation.

[0095] The packet uploading module 5 is configured to write the at least one packet into a cache unit pointed by the corresponding descriptor.

[0096] In some embodiments, the cache length obtaining module 2 is configured to query a descriptor length storage according to a queue number of the virtual queue to obtain the cache unit length corresponding to the virtual queue, wherein the descriptor length storage stores cache unit lengths corresponding to respective virtual queues.

[0097] The descriptor number determining module 3 is configured to determine a descriptor number needed to be read for each packet according to a length of each packet and the cache unit length, and obtain the descriptor reading number according to the descriptor number needed to be read for each packet.

[0098] In some embodiments, the data processing unit further comprises a cache length updating module, which is configured to, after reading the descriptor corresponding to the descriptor reading number through the single PCIE reading operation, obtain a cache unit length corresponding to a last read descriptor, and update the cache unit length corresponding to the virtual queue stored in the descriptor length storage as the cache unit length corresponding to the last descriptor.

[0099] In some embodiments, the method further comprises a descriptor number storage module configured to store the descriptor read number into a descriptor number storage after determining the descriptor read number; the descriptor number storage comprises a plurality of storage units corresponding to the plurality of virtualization queues, each storage unit is configured to store the descriptor read number of a corresponding virtualization queue; and the descriptor number storage is configured to update the descriptor read number of a corresponding virtualization queue in the descriptor number storage whenever a packet is uploaded.

[0100] In some embodiments, the descriptor read module 4 is configured to obtain a packet valid bitmap and a read waiting bitmap, determine a target virtualization queue to be dispatched according to the packet valid bitmap and the read waiting bitmap; read the descriptor number of the target virtualization queue from the descriptor number storage; and read the descriptors corresponding to the descriptor read number through a single PCIE read operation; wherein the packet valid bitmap and the read waiting bitmap each comprises a plurality of bits corresponding to the plurality of virtualization queues, each bit of the packet valid bitmap indicates whether there is a packet of a corresponding virtualization queue that has not been uploaded, and each bit of the read waiting bitmap indicates whether a descriptor has been initiated to be read.

[0101] In some embodiments, the packet receiving module 1 is configured to store any packet of any virtualization queue and the descriptor number to be read of the packet into a packet storage when receiving the packet;

[0102] The data processing unit further comprises a bitmap management module configured to set a bit corresponding to any virtualization queue in the packet valid bitmap to 1 when there is at least one packet of the virtualization queue stored in the packet storage, and set the bit corresponding to the virtualization queue in the packet valid bitmap to 0 when there is no at least one packet of the virtualization queue stored in the packet storage.

[0103] In some embodiments, the descriptor read module 4 is further configured to store the read descriptors into a descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module;

[0104] The bitmap management module is further configured to set a bit corresponding to any virtualization queue in the read waiting bitmap to 0 when the descriptor FIFO module corresponding to the virtualization queue is empty, and set the bit corresponding to the virtualization queue in the read waiting bitmap to 1 when the descriptor FIFO module corresponding to the virtualization queue is not empty.

[0105] It should be noted that the data processing unit of the embodiment corresponds to the method of the above embodiment, and the content not described in detail in the data processing unit of the embodiment can be obtained by referring to the content of the method of the embodiment, and the data processing unit of the embodiment will not be described again.

[0106] Another embodiment of the application provides a data processing unit, comprising:

[0107] a communication interface configured to communicate with other electronic devices;

[0108] a memory configured to store computer program instructions;

[0109] a processor configured to execute the computer program instructions to support the data processing unit to implement the method according to the above embodiment.

[0110] In the embodiment, the memory mainly includes a program storage area and a data storage area, wherein the program storage area can store application programs required by at least one function of the operating device, and the data storage area can store related data. In addition, the memory can be a high-speed random access memory, and can also be a non-volatile memory such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc., or the memory can also be other volatile solid-state storage devices.

[0111] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor can also be any conventional processor. The processor is the control center of the data processing unit, and connects various parts of the data processing unit through various interfaces and lines.

[0112] Another embodiment of the application provides a network processor, characterized in that comprising a Virtio driver and the data processing unit of the above embodiment, the Virtio driver runs on the host side, and the Virtio driver is at least used to generate the descriptor.

[0113] Another embodiment of the present application provides a computer program product comprising computer program instructions instructing a computer device to perform operations corresponding to the packet uploading method as described in the above embodiments.

[0114] In particular, the computer program product comprises a series of computer program instructions, which are codes written in a computer program and define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and guide the device to perform specific operations, which are steps in the packet uploading method as described in the above embodiments. In this way, the computer program product of the present embodiment provides a complete software solution, which can be run on various computer devices to implement the packet uploading method of the above embodiments.

[0115] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A message uploading method, characterized in that, The method includes: Receive at least one message from any virtualization queue; Obtain the length of the cache unit corresponding to the virtualization queue; The number of descriptors to be read is determined based on the length of the at least one message and the length of the buffer unit; The number of descriptors read is obtained by a single PCIe read operation; Write the at least one message into the cache unit pointed to by the corresponding descriptor.

2. The method according to claim 1, characterized in that, The step of obtaining the cache unit length corresponding to the virtualization queue includes: The descriptor length memory is queried according to the queue number of the virtualization queue to obtain the cache unit length corresponding to the virtualization queue; wherein, the descriptor length memory stores the cache unit length corresponding to each virtualization queue; Determining the number of descriptor reads based on the length of the at least one message and the length of the buffer unit includes: The number of descriptors to be read for each message is determined based on the length of each message and the length of the buffer unit, and the number of descriptors to be read is obtained based on the number of descriptors to be read for each message.

3. The method according to claim 2, characterized in that, The method further includes: After reading the descriptor corresponding to the number of descriptors read in a single PCIe read operation, the cache unit length corresponding to the last descriptor read is obtained, and the cache unit length corresponding to the virtualization queue stored in the descriptor length memory is updated to the cache unit length corresponding to the last descriptor.

4. The method according to claim 1, characterized in that, The method further includes: After determining the number of descriptor reads, the number of descriptor reads is stored in the descriptor number memory; the descriptor number memory includes multiple storage units corresponding one-to-one with multiple virtualization queues, and each storage unit is used to store the number of descriptor reads for the corresponding virtualization queue; After each message is sent, the number of descriptors read from the corresponding virtualization queue in the descriptor count memory is updated.

5. The method according to claim 4, characterized in that, The step of reading the descriptor corresponding to the number of descriptors read in a single PCIe read operation includes: Obtain the valid bitmap of the message and the waiting bitmap, and determine the target virtualization queue to be scheduled based on the valid bitmap of the message and the waiting bitmap. Read the number of descriptors corresponding to the target virtualization queue from the descriptor number memory; The number of descriptors read is obtained by a single PCIe read operation; The message valid bitmap and the read wait bitmap each include multiple bits corresponding to multiple virtualization queues. Each bit of the message valid bitmap indicates whether a message corresponding to a virtualization queue has not been sent, and each bit of the read wait bitmap indicates whether a read descriptor has been initiated.

6. The method according to claim 5, characterized in that, The method includes: When any message is received from any virtualization queue, the message and the number of descriptors to be read are stored in the message memory. When the message memory stores at least one message of any virtualization queue, the bit corresponding to the virtualization queue in the message validity bitmap is set to 1; when the message memory does not store at least one message of any virtualization queue, the bit corresponding to the virtualization queue in the message validity bitmap is set to 0.

7. The method according to claim 5, characterized in that, The method further includes: The read descriptors are stored in the descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module; Specifically, when the FIFO descriptor module corresponding to any virtualization queue is empty, the bit corresponding to that virtualization queue in the read wait bitmap is set to 0; when the FIFO descriptor module corresponding to any virtualization queue is not empty, the bit corresponding to that virtualization queue in the read wait bitmap is set to 1.

8. A data processing unit, characterized in that, It includes a message receiving module, a message uploading module, a buffer length acquisition module, a descriptor number determination module, and a descriptor reading module; The message receiving module is used to receive at least one message from any virtualization queue; The cache length acquisition module is used to obtain the cache unit length corresponding to the virtualization queue; The descriptor number determination module is used to determine the number of descriptors to be read based on the length of the at least one message and the length of the buffer unit; The descriptor reading module is used to read the descriptor corresponding to the number of descriptors read in a single PCIe read operation; The message uploading module is used to write the at least one message into the cache unit pointed to by the corresponding descriptor.

9. The data processing unit according to claim 8, characterized in that, The cache length acquisition module is used to query the descriptor length memory according to the queue number of the virtualization queue to obtain the cache unit length corresponding to the virtualization queue; wherein, the descriptor length memory stores the cache unit length corresponding to each virtualization queue; The descriptor number determination module is used to determine the number of descriptors that need to be read for each message based on the length of each message and the length of the buffer unit, and to obtain the descriptor read count based on the number of descriptors that need to be read for each message.

10. The data processing unit according to claim 8, characterized in that, The descriptor reading module is used to obtain the valid bitmap of the message and the read waiting bitmap, and to determine the target virtualization queue to be scheduled based on the valid bitmap of the message and the read waiting bitmap. The number of descriptors corresponding to the target virtualization queue is read from the descriptor number memory; the descriptor corresponding to the number of descriptors read is read through a single PCIe read operation; wherein, the packet valid bitmap and the read wait bitmap each include multiple bits corresponding one-to-one with multiple virtualization queues, each bit of the packet valid bitmap indicates whether a packet corresponding to a virtualization queue has not been sent, and each bit of the read wait bitmap indicates whether a descriptor read has been initiated.

11. The data processing unit according to claim 10, characterized in that, The message receiving module is used to store any message and the number of descriptors to be read into the message storage when receiving any message from any virtualization queue. The data processing unit further includes a bitmap management module, which is used to set the bit corresponding to the virtualization queue in the valid bitmap of the message to 1 when the message memory stores at least one message of any virtualization queue, and to set the bit corresponding to the virtualization queue in the valid bitmap of the message to 0 when the message memory does not store at least one message of any virtualization queue.

12. The data processing unit according to claim 10, characterized in that, The descriptor reading module is also used to store the read descriptors into the descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module; The bitmap management module is further configured to set the bit corresponding to the virtualization queue in the read wait bitmap to 0 when the descriptor FIFO module corresponding to any virtualization queue is empty, and to set the bit corresponding to the virtualization queue in the read wait bitmap to 1 when the descriptor FIFO module corresponding to any virtualization queue is not empty.

13. A data processing unit, characterized in that, include: A communication interface used for communicating with other electronic devices; Memory is used to store computer program instructions; A processor for executing the computer program instructions to support the data processing unit in implementing the method of any one of claims 1 to 7.

14. A network processor, characterized in that, The device includes a Virtio driver and a data processing unit as described in any one of claims 9 to 12, wherein the Virtio driver runs on the host side and is used at least to generate the descriptor.

15. A computer program product, characterized in that, It includes computer program instructions that instruct a computer device to perform an operation corresponding to the method as described in any one of claims 1 to 7.

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