Apparatus and system for ESD protection

Abstract

A circuit for electrostatic discharge (ESD) protection may protect a sensitive circuit in the presence of both a positive ESD event and a negative ESD event. A protection transistor may be coupled to the pad, and a protection clamp may be coupled to the protection transistor. A protection transistor may be located in the isolated n-well, and a current limiting resistor may be coupled from the pad to the isolated n-well. In operation, the current limiting resistor may limit current during a negative ESD event.

Description

[0001] Priority

[0002] This application claims priority to commonly owned U.S. Patent Application No. 63 / 460,687, filed April 20, 2023, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD

[0003] The present disclosure relates to apparatuses and methods for protecting electronic circuits from damage due to electrostatic discharge (ESD). BACKGROUND

[0004] Electronic circuits can be exposed to very high voltages during handling, assembly, and operation. As one of various examples, a technician handling a semiconductor device can discharge static electricity from their body to the semiconductor device. These discharge events can expose the semiconductor device to voltages exceeding 1000V. These discharge events are referred to as electrostatic discharge (ESD) events. The voltages applied during ESD events can be positive voltages above ground or negative voltages below ground.

[0005] ESD events can cause permanent damage to a semiconductor device, and for this reason, significant design and verification effort is spent to design special protection circuits to protect internal circuits within the semiconductor device from excess voltages and currents during ESD events.

[0006] ESD protection circuits in semiconductor devices can consist of clamps from a pin to ground, from a pin to a supply voltage. In one of various examples, the clamps can be diodes. When an excess positive voltage is applied to a pin, the diode can be reverse biased, and when the reverse breakdown voltage of the diode is reached, the diode can provide a low impedance discharge path for current to flow to ground. This low impedance discharge path can prevent the excess voltage from reaching sensitive circuits inside the semiconductor device.

[0007] In the case of an excess negative voltage applied to a pin, the diode can be forward biased and allow current to flow from a ground connection within the semiconductor device through the diode and out of the semiconductor device. This forward biased operation can introduce large currents and large negative voltages that can damage internal circuits.

[0008] There is a need for ESD protection circuits that protect internal circuits from both large positive input voltages and large negative input voltages, and limit the current from such ESD events. SUMMARY

[0009] Examples herein implement a circuit that can protect an electronic circuit from damage due to positive ESD events and negative ESD events.

[0010] According to an aspect, an apparatus includes a current limiting resistor having a first node coupled to a pad and a second node coupled to an isolated n-well. The apparatus includes a protection transistor located inside the isolated n-well and a protection clamp located outside the isolated n-well. The protection clamp has a cathode coupled to a drain node of the protection transistor and an anode coupled to a fixed voltage. The protection transistor can be located inside the isolated n-well and can include a source node coupled to the pad, a gate node coupled to the pad, and a body node coupled to the pad.

[0011] According to an aspect, a system includes a pad, a current limiting resistor having a first node coupled to the pad and a second node coupled to an isolated n-well. The system includes a protection transistor located inside the isolated n-well and a protection clamp located outside the isolated n-well. The protection clamp includes a cathode coupled to a drain node of the protection transistor and an anode coupled to a fixed voltage. The protection transistor can be located inside the isolated n-well and can include a source node coupled to the pad, a gate node coupled to the pad, and a body node coupled to the pad. In addition, one or more circuits can be coupled to the pad.

[0012] According to an aspect, the example implementations herein implement a method that includes detecting a voltage at a pad, activating a discharge path based on the detected voltage exceeding a predetermined range of allowable voltages, the discharge path based on at least a polarity of the voltage at the pad, and limiting a current in the discharge path to a level below a predetermined current threshold. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings illustrate examples of apparatuses, systems, and methods for protecting electronic circuits from damage due to ESD events.

[0014] Figure 1 One of the various examples of a cross-section of an ESD protection circuit during a positive ESD event is illustrated.

[0015] Figure 2 One of the various examples of a cross-section of an ESD protection circuit during a positive ESD event is illustrated.

[0016] Figure 3 One of the various examples of a cross-section of an ESD protection circuit during a positive ESD event is illustrated.

[0017] Figure 4 One of the various examples of a cross-section of an ESD protection circuit during a positive ESD event is illustrated.

[0018] Figure 5One of the various examples of current versus voltage performance of the ESD protection circuit during a positive ESD event is illustrated.

[0019] Figure 6 One of the various examples of current versus voltage performance of the ESD protection circuit during a negative ESD event is illustrated.

[0020] Figure 7 One of the various examples of the ESD protection circuit is illustrated. DETAILED DESCRIPTION

[0021] Figure 1 One of the various examples of the ESD protection circuit 100 is illustrated. The pad 110 can be a pad on a semiconductor device 115. The ESD protection circuit 100 can protect internal circuitry 180 within the semiconductor device 115 from negative ESD events and positive ESD events. A negative ESD event can be an ESD event in which the voltage at the pad 110 is below ground. A positive ESD event can be an ESD event in which the voltage at the pad 110 is above ground. The term ground as used herein is not meant to be limited to earth ground and can include any common potential. The semiconductor device 115 can be a semiconductor device in a package including, but not limited to, a DIP (dual in-line package), a SOP (small outline package), a QFP (quad flat package), a TSOP (thin small outline package), a PLCC (plastic leaded chip carrier), a BGA (ball grid array), a WLP (wafer level package), or another package type.

[0022] The pad 110 can be coupled to a protection transistor 135. The protection transistor 135 can be a negative protection circuit for protecting the internal circuitry 180 from negative ESD events at the pad 110. The pad 110 can be coupled to a gate node of the protection transistor 135. The pad 110 can be coupled to a source node of the protection transistor 135. The pad 110 can be coupled to a body node of the protection transistor 135. The protection transistor 135 can be placed in an isolation n-well 130. The isolation n-well 130 can be an n-type doped semiconductor material. The pad 110 can be coupled to the internal circuitry 180 via a path 170. The internal circuitry 180 can be one or more transistors, one or more passive components, or another circuit. A protection clamp 150 can be a positive protection circuit for protecting the internal circuitry 180 from positive ESD events. A cathode of the protection clamp 150 can be coupled to a drain of the protection transistor 135. The protection clamp 150 can be a PNP diode or an NPN diode, or can be another device for clamping current. An anode of the protection clamp 150 can be coupled to ground.

[0023] A current limiting resistor 120 can be coupled between the isolation n-well 130 and the pad 110. The current limiting resistor 120 can limit current flowing to the pad 110 during a negative ESD event.

[0024] The protection transistor 135 and the protection clamp 150 can be designed with a particular breakdown voltage such that when the voltage at the pad 110 exceeds a predetermined threshold, the discharge path can be activated and the voltage on the pad 110 can be limited.

[0025] Figure 2 One of the various examples of a cross-section of the ESD protection circuit 200 during a positive ESD event is illustrated.

[0026] The pad 210 can be a pad on the semiconductor device 215. The pad 210 can be coupled to a first node of a current limiting resistor 220. A second node of the current limiting resistor 220 can be coupled to an isolation n-well 230 at a well band 241. The isolation n-well 230 can be an n-type doped semiconductor material. The well band 241 can be a higher doping density than the isolation n-well 230. The well band 241 can provide an ohmic contact between the second end of the current limiting resistor 220 and the isolation n-well 230.

[0027] The pad 210 can be coupled to a source node 243 of a protection transistor 235. The source node 243 can be an n-type doped semiconductor material. The pad 210 can be coupled to a body node 242 of the protection transistor 235. The body node 242 can be a p-type doped semiconductor material. The body node 242 can provide an ohmic contact between the pad 210 and a p-well 237. The p-well 237 is formed within the isolation n-well 230.

[0028] A diode 246 can be formed between the p-type doped semiconductor material of the body node 242 and the n-type doped semiconductor material of the drain node 244.

[0029] The protection transistor 235 can be one of the various examples of the protection transistor 135 as described and illustrated with reference to Figure 1 The pad 210 can be coupled to a gate node 245 of the protection transistor 235. The protection transistor 235 is formed within the p-well 237.

[0030] The drain node 244 of the protection transistor 235 can be coupled to a protection clamp 250. The protection clamp 250 is illustrated as a diode-connected PNP transistor, but this is not intended to be limiting. The protection clamp 250 can be another clamp or diode structure as not illustrated in Figure 2

[0031] ​The drain node 244 of the protection transistor 235 can be coupled to a first base node 251 and a second base node 255 of the protection clamp 250. The first base node 251 can be an n-type doped semiconductor material. The first base node 251 can provide an ohmic contact between the drain node 244 of the protection transistor 235 and the n-well 260. The second base node 255 can be an n-type doped semiconductor material. The second base node 255 can provide an ohmic contact between the drain node 244 of the protection transistor 235 and the n-well 260.

[0032] Figure 2 Examples of the protection clamp 250 are illustrated with two base nodes, the first base node 251 and the second base node 255, but this is not intended to be limiting. The protection clamp 250 can include a single base node connection, or can include more than two base node connections.

[0033] The drain node 244 of the protection transistor 235 can be coupled to an emitter node 253 of the protection clamp 250. The emitter node 253 can be a p-type doped semiconductor material. The emitter node 253 and the n-well 260 can form a PN junction.

[0034] A first collector node 252 of the protection clamp 250 can be coupled to ground 290. A second collector node 254 of the protection clamp 250 can be coupled to ground 290. The first collector node 252 can be a p-type doped semiconductor material. The first collector node 252 and the n-well 260 can form a PN junction. The second collector node 254 can be a p-type doped semiconductor material. The second collector node 254 and the n-well 260 can form a PN junction diode 256, where the cathode of the PN junction diode 256 is formed by a portion of the n-well 260.

[0035] A parasitic bipolar device 257 can be formed by the second collector node 254, the base node 251, and the emitter node 253. The parasitic bipolar device 257 can enter a snapback mode when sufficient current flows between the second collector node 254 and the base node 251. The snapback mode can provide an additional discharge path, and can limit the voltage on the pad 210.

[0036] An additional bipolar device can be formed by the first collector node 252, the base node 251, and the emitter node 253, but this additional bipolar device is not shown to improve readability of the figure. Figure 2

[0037] Other parasitic junctions and transistors can be present in the ESD protection circuit 200, but these parasitic junctions and transistors are not illustrated to improve readability of the figure. This is not intended to be limiting.

[0038] ​During operation, during a positive ESD event, the voltage on pad 210 can increase to a higher voltage than ground 290. The voltage can rise high at body node 242, and diode 246 can be forward biased. Under the forward bias condition of diode 246, current can flow from body node 242 to drain node 244, as illustrated by arrow 291. Current can flow out of drain node 244, as illustrated by arrow 292.

[0039] Current can flow to the first base node 251, thereby increasing the voltage at the first base node 251. The increased voltage at the first base node 251 reverse-biases the PN junction diode 256. As the reverse bias increases, the PN junction diode 256 can reach its breakdown voltage, and current can flow from the cathode to the anode of the PN junction diode 256, as illustrated by path 293. Due to the resistance of the n-well 260, the current from the first base node 251 to the base connection at the parasitic bipolar device 257 can create a voltage difference between the first base node 251 and the base connection at the parasitic bipolar device 257. The voltage at the base connection of the bipolar device can drop below the voltage at the emitter node 253, and the base-emitter junction can be forward-biased. The parasitic bipolar device 257 can enter a quick-return mode and can conduct current from the emitter node 253 to the second collector node 254 and then to ground 290, as illustrated by path 294. An additional bipolar device may be formed between the first collector node 252, base node 251, and emitter node 253, and may operate in a manner similar to the parasitic bipolar device 257. In this manner, a discharge path may be activated between pad 210 and ground loop 290, and the voltage on pad 210 may be limited to the reverse bias breakdown voltage of PN junction diode 256 plus the forward bias voltage of PN junction diode 246.

[0040] The protection transistor 235 can be designed with a specific breakdown voltage so that when the voltage at pad 210 exceeds a predetermined threshold, the discharge path can be activated and the voltage on pad 210 can be limited. The current-limiting resistor 220 can be designed with a specific resistance value to limit the current through pad 210 to below a predetermined threshold.

[0041] Figure 3 This is one example of various examples of the cross-section of the ESD protection circuit 300 during a negative ESD event. Figure 2 and Figure 3 Elements labeled with the same last two numbers can represent the same structure.

[0042] Pad 310 can be a pad on semiconductor device 315. Semiconductor device 315 can be fabricated on a p-type substrate (not shown). Pad 310 can be coupled to a first node of current limiting resistor 320. A second node of current limiting resistor 320 can be coupled to isolation n-well 330 at well band 341. Isolation n-well 330 can be an n-type doped semiconductor material. Well band 341 can be an n-type doped semiconductor material. Well band 341 can provide an ohmic contact between current limiting resistor 320 and isolation n-well 330. Diode 331 can be a diode between isolation n-well 330 and a p-type substrate of semiconductor device 315 that is coupled to ground 390.

[0043] In operation, when diode 331 is forward biased, current limiting resistor 320 can limit current to pad 310 during a negative ESD event.

[0044] Pad 310 can be coupled to source node 343 of protection transistor 335. Source node 343 can be an n-type doped semiconductor material. Pad 310 can be coupled to body node 342 of protection transistor 335. Body node 342 can be a p-type doped semiconductor material. Body node 342 can provide an ohmic contact between pad 310 and p-well 337. P-well 337 is formed within isolation n-well 330.

[0045] Diode 346 can be formed between the p-type doped semiconductor material of body node 342 and the n-type doped semiconductor material of drain node 344.

[0046] Parasitic bipolar device 347 can be formed from drain node 344, body node 342, and source node 343. Parasitic bipolar device 347 can enter snapback mode when sufficient current flows from drain node 344 to body node 342. Snapback mode can provide an additional discharge path and can limit voltage on pad 310.

[0047] Protection transistor 335 can be one of the various examples of protection transistor 135 as described and illustrated with reference to Figure 1 Pad 310 can be coupled to gate node 345 of protection transistor 335. Protection transistor 335 is formed within p-well 337.

[0048] Drain node 344 of protection transistor 335 can be coupled to protection clamer 350. Protection clamer 350 is illustrated as a diode-connected PNP transistor, but this is not intended to be limiting. Protection clamer 350 can be another clamper or diode structure not illustrated in Figure 3

[0049] ​The first base node 351 can be an n-type doped semiconductor material. The first base node 351 can provide an ohmic contact between the drain node 344 of the protection transistor 335 and the n-well 360. The second base node 355 can be an n-type doped semiconductor material. The second base node 355 can provide an ohmic contact between the drain node 344 of the protection transistor 335 and the n-well 360.

[0050] Figure 3 Examples of the protection clamer 350 are illustrated with two base nodes, the first base node 351 and the second base node 355, but this is not intended to be limiting. The protection clamer 350 can include a single base node connection, or can include more than two base node connections.

[0051] The drain node 344 of the protection transistor 335 can be coupled to an emitter node 353 of the protection clamer 350. The emitter node 353 can be a p-type doped semiconductor material. The emitter node 353 and the n-well 360 can form a PN junction.

[0052] A first collector node 352 of the protection clamer 350 can be coupled to ground 390. A second collector node 354 of the protection clamer 350 can be coupled to ground 390. The first collector node 352 can be a p-type doped semiconductor material. The first collector node 352 and the n-well 360 can form a PN junction. The second collector node 354 can be a p-type doped semiconductor material. The second collector node 354 and the n-well 360 can form a PN junction diode 356.

[0053] Other parasitic junctions and transistors can exist in the ESD protection circuit 300, but these parasitic junctions and transistors are not illustrated to improve readability of the figures. This is not intended to be limiting.

[0054] In operation, during a negative ESD event, the voltage on the pad 310 can decrease below the voltage of the ground 390. The voltage can drop on the body node 342, and the diode 346 can be reverse biased. As the voltage on the body node 342 continues to drop, the diode 346 can reach a breakdown voltage, and current can flow through the diode 346, as illustrated by the arrow 391. Due to the resistance of the p-well 337, the current from the base connection of the parasitic bipolar device 347 to the body node 342 can create a voltage difference between the base connection of the parasitic bipolar device 347 and the body node 342. The voltage at the base connection of the parasitic bipolar device 347 can rise above the voltage at the body node 342, and the base-emitter junction can be forward biased, and the parasitic bipolar device 347 can enter snapback mode and can conduct current from the drain node 344 to the source node 343.

[0055] Current along path 391 can create a voltage difference between the base of parasitic bipolar device 347 connected to body node 342 and the emitter of parasitic bipolar device 347 connected to source node 343. The voltage difference can forward bias the base-emitter junction in parasitic bipolar device 347, and parasitic bipolar device 347 can enter snapback mode and conduct current. Current can flow through parasitic bipolar device 347 from drain node 344 to source node 343.

[0056] Current can flow from protection clamp 350 to protection transistor 335, as indicated by arrow 392. The voltage at first base node 351 can decrease, and PN junction diode 356 can be forward biased, and current can flow as illustrated by arrow 393. In this way, current can flow from ground 390 through PN junction diode 356, through parasitic bipolar device 347, and to pad 310. The voltage on pad 310 can be limited by the reverse breakdown voltage of diode 346 plus the forward bias voltage of PN junction diode 356.

[0057] Figure 4 One of various examples of input leakage current in an ESD protection circuit is illustrated. Graph 400 illustrates input current during a negative bias voltage on pad 180 in one of various examples of ESD protection circuit 100 as described with reference to Figure 1

[0058] Figure 4 An example of input current versus a negative bias voltage scan on pad 180 as described with reference to Figure 1 Graph 400 illustrates input current versus a negative bias voltage on pad 180 in one of various examples of ESD protection circuit 100 as described with reference to Figure 1

[0059] As illustrated by trace 430 in Figure 4 As the voltage at the pad increases on the negative potential (moving from right to left on graph 400), the absolute value of the current increases along the y-axis. At a pad voltage of -10 V, the current in this example does not exceed -1.5 mA.

[0060] Figure 5 One of various examples of a graph 500 illustrating current versus voltage performance of an ESD protection circuit during a positive ESD event is illustrated. Graph 500 illustrates current versus voltage performance of one of various examples of ESD protection circuit 100 as described with reference to Figure 1

[0061] The voltage at the pad is illustrated on the x-axis, and the current through the pad is illustrated on the y-axis. As Figure 5 ​​​As illustrated, at position 510, the diode conduction path can begin conducting current. Reference is made to Figure 2 As illustrated and described in the example, the diode conduction path can be from the pad 210 through the diode 246 and the diode 256 and to the ground 290. As Figure 5 As illustrated, at position 530, the ESD protection circuit can enter a snapback mode for limiting voltage to prevent damage.

[0062] Figure 5 The particular voltages shown in the examples are not intended to be limiting. In other examples, the diodes can conduct current at voltages different from Figure 5 the voltages illustrated. Other examples can enter a snapback mode at voltages different from Figure 5 the voltages illustrated.

[0063] Figure 6 One of the various examples of a plot 600 of current versus voltage performance of an ESD protection circuit during a negative ESD event is illustrated. The plot 600 illustrates the current versus voltage performance of one of the various examples of the ESD protection circuit 100 as described with reference to Figure 1

[0064] The voltage at the pad is illustrated on the x-axis and the current through the pad is illustrated on the y-axis. As Figure 6 As illustrated, at position 630, the ESD protection circuit can enter a snapback mode for limiting voltage to prevent damage.

[0065] Figure 6 The particular voltages shown in the examples are not intended to be limiting. In other examples, the diodes can conduct current at voltages different from Figure 6 the voltages illustrated. Other examples can enter a snapback mode at voltages different from Figure 6 the voltages illustrated.

[0066] Figure 7 One of the various examples of an ESD protection circuit is illustrated.

[0067] Figure 7 A pad 710, a current limiting circuit 720, a negative protection circuit 730, and a positive protection circuit 750 are illustrated. The current limiting circuit 720 is illustrated as a resistor, but this is not intended to be limiting. The current limiting circuit 720 can be another circuit capable of limiting current.

[0068] The pad 710 can be coupled to the current limiting circuit 720 and the negative protection circuit 730. The negative protection circuit 730 can be coupled to the pad 710, the current limiting circuit 720, and the positive protection circuit 750. The positive protection circuit 750 can be coupled to the negative protection circuit 730 and a ground node 790.

[0069] ​The positive protection circuit 750 can be a diode, a bipolar transistor, a metal oxide semiconductor field effect transistor, or can be another type of protection circuit. The negative protection circuit 730 can be a diode, a bipolar transistor, a metal oxide semiconductor field effect transistor, or can be another type of protection circuit.

[0070] In operation, for a positive voltage at the pad 710 above a predetermined threshold, current can flow from the pad 710 through the negative protection circuit 730, through the positive protection circuit 750, and to the ground node 790.

[0071] In operation, for a negative voltage at the pad 710 below a predetermined threshold, current can flow from the ground node 790 through the positive protection circuit 750, through the negative protection circuit 730, and to the pad 710, the current being limited by the current limiting circuit 720.

Claims

1. A device for ESD protection, the device comprising: A current-limiting resistor having a first node coupled to a pad and a second node coupled to an isolated n-well; A protection transistor, located in a p-well inside the isolated n-well, the protection transistor comprising: Source node, the source node being coupled to the pad; Gate node, the gate node being coupled to the pad; and A body node, the body node being coupled to the pad; A protection clamp is located outside the isolation n-well, the protection clamp having a cathode coupled to the drain node of the protection transistor and an anode coupled to ground.

2. The apparatus of claim 1, wherein the protection clamp comprises a diode-connected PNP transistor.

3. The apparatus of claim 1, wherein the protection clamp comprises a diode-connected NPN transistor.

4. The apparatus according to any one of claims 1 to 3, wherein for a positive voltage exceeding a predetermined threshold at the pad, the protection clamp causes current to flow from the input pad through the protection transistor, through the protection clamp, and to the ground.

5. The apparatus according to any one of claims 1 to 4, wherein for a negative voltage below a predetermined threshold at the pad, the protection clamp causes current to flow from the ground loop through the protection clamp, through the protection transistor, and to the pad.

6. A system comprising: solder pads; A current-limiting resistor having a first node coupled to the pad and a second node coupled to an isolated n-well; A protection transistor is formed in a p-well, the p-well being located inside the isolated n-well, the protection transistor comprising: Source node, the source node being coupled to the pad; Gate node, the gate node being coupled to the pad; and A body node, the body node being coupled to the pad; A protection clamp, located outside the isolated n-well, has a cathode coupled to the drain node of the protection transistor and an anode coupled to a fixed voltage. The protection transistor is located within the isolated n-well and has a source node coupled to the pad, a gate node coupled to the pad, and a body node coupled to the pad. One or more circuits coupled to the pads.

7. The system of claim 6, wherein the protection clamp comprises a diode-connected PNP transistor.

8. The system of claim 6, wherein the protection clamp comprises a diode-connected NPN transistor.

9. The system according to any one of claims 6 to 8, wherein the fixed voltage includes ground.

10. The system according to any one of claims 6 to 9, wherein for a positive voltage exceeding a predetermined threshold at the pad, the protection clamp causes current to flow from the input pad through the protection transistor, through the protection clamp, and to the ground loop.

11. The system according to any one of claims 6 to 10, wherein for a negative voltage below a predetermined threshold at the pad, the protection clamp causes current to flow from the ground loop through the protection clamp, through the protection transistor, and to the pad.

12. The system according to any one of claims 6 to 11, wherein the protection clamp, the protection diode, and the current-limiting resistor are used to limit the voltage at one or more of the circuits.

13. An apparatus comprising: solder pads; Negative protection circuit; Positive protection circuit; Current limiting circuit; in: The negative protection circuit includes a first node connected to the pad. The second node is connected to the positive protection circuit and the third node is connected to the current limiting circuit; The positive protection circuit includes a first node connected to the negative protection circuit and a second node connected to ground; The current limiting circuit includes a first node connected to the negative protection circuit and a second node connected to the pad; For a positive voltage exceeding a predetermined threshold at the pad, current flows from the pad through the negative protection circuit, through the positive protection circuit, and to ground. For a negative voltage below a predetermined threshold at the pad, current flows from ground through the positive protection circuit, through the negative protection circuit, and to the pad, and the current is limited by the current limiting circuit.

14. The apparatus of claim 13, wherein the negative protection circuit comprises a metal-oxide-semiconductor field-effect transistor (MOSFET).

15. The apparatus according to any one of claims 13 to 14, wherein the positive protection circuit comprises a diode.

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