Direct-current weak voltage signal acquisition system and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the technical field of typical weak signal detection, and particularly relates to a direct-current weak voltage signal acquisition system and method based on an FPGA, and the system comprises a pre-amplification module, a chopper module, a differential amplification module, the FPGA, a band-pass filtering module, and an ADC module. A multi-stage signal conditioning framework is adopted, and the problems that a direct-current weak signal is prone to noise interference, the dynamic range is limited, the system response speed is low, and the direct-current signal monitoring adaptability is poor are effectively solved. The system introduces an ultra-low noise precision operational amplifier to pre-amplify an input signal of the sensor, so that the problem of signal processing caused by too small amplitude in a signal monitoring process is avoided. In order to eliminate common-mode interference and low-frequency noise, a chopping modulation circuit is innovatively introduced. Aiming at the difference of output amplitudes of different sensors, the system is integrated with a gain attenuation module.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of typical weak signal detection, and particularly relates to a direct-current weak voltage signal acquisition system and method based on FPGA. BACKGROUND

[0002] At present, a typical weak signal detection system generally adopts a phase-locked amplification technology to realize small signal extraction under a strong noise background. The technology is based on the difference in spectral characteristics between a target signal and background noise: the noise is distributed in a wide frequency band, while the target signal has a narrowband characteristic, and the noise energy in the same frequency band is significantly lower than that of the signal component. A detection system performs cross-correlation processing on the target signal and a same-frequency reference signal through a phase-sensitive detector, generates sum frequency and difference frequency components containing signal characteristics by using a mixing effect. After high-frequency components are filtered out by a low-pass filter, the final signal output is positively correlated with the amplitude and phase of the target signal, so that signal-to-noise ratio is improved and signal characteristics are reconstructed. The core advantage of the technology is reflected in the extraction ability of weak signals under a strong noise background. When the sensor background noise is lower than the threshold value of the technology design, the applicability of the method is reduced, and the signal processing ability is decreased. In addition, in a sensing signal monitoring scene, the sensor output is mostly weak direct-current or low-frequency voltage / current signals. Since the working principle of the phase-locked amplification technology depends on synchronous extraction of a reference frequency to extract a specific frequency component, the output result is the amplitude and phase of the signal on the reference frequency component, so the direct-current signal that is not synchronized with the reference signal cannot be effectively processed, which greatly limits the applicability of the phase-locked amplification technology in sensing detection.

[0003] In engineering practice, a multi-level anti-interference protection system needs to be constructed for a signal transmission link, and sensing signals are not necessarily in a strong noise environment. Anti-interference of a signal link is an important means to ensure effective transmission of signals, and therefore, it is necessary to develop a weak voltage signal acquisition technology with adaptive noise suppression function. SUMMARY

[0004] The application aims to overcome the above-mentioned shortcomings of the prior art, and proposes a direct-current weak voltage signal acquisition system and method based on FPGA. The direct-current voltage signal output by sensing is pre-amplified to enhance the signal amplitude, and the signal is chopped. Low-noise differential amplification is used to effectively condition the signal, avoid the limitations of traditional lock-in amplification technology in low-frequency direct-current signal detection, and realize effective monitoring of the direct-current voltage sensing signal. The technical scheme is as follows:

[0005] A DC weak voltage signal acquisition system based on FPGA includes a pre-amplification module, a chopper module, a differential amplifier module, an FPGA, a bandpass filter module, and an ADC module. The two outputs of the pre-amplification module enter the differential amplifier module through the chopper module. The output of the differential amplifier module is connected to the filter module. The output signal of the bandpass filter module passes sequentially through a range selection module, a low-noise amplifier module, and the ADC module before entering the FPGA. The FPGA is connected to a host computer, the chopper module, and the range selection module.

[0006] Preferably, the pre-amplification module includes two identical amplification units, each including an operational amplifier U1, a capacitor C3, and resistors R1 and R2. The input terminal of the operational amplifier U1 is connected to the sensor, and the other input terminal is connected to resistors R1 and R2 and capacitor C3 respectively. Resistor R1 is grounded. Resistor R2 and capacitor C3 are connected in parallel to the output terminal of operational amplifier U1, and the output terminal of operational amplifier U1 is connected to a chopper module.

[0007] Preferably, the chopper module includes a multiplexer U4 and a selection switch U3. The two outputs of the pre-amplifier module are respectively connected to the two terminals of the selection switch U3. The IN1, IN2, IN3, and IN4 terminals of the selection switch U3 are all connected to the multiplexer U4. Inverters are provided on the IN2 and IN3 terminals of the selection switch U3. The FPGA output control signal CHOP_CTL controls the output of the multiplexer U4 to continuously switch between 0V and +5V, generating a square wave signal. The two signal output terminals of the selection switch U3 are respectively connected to the differential amplifier module.

[0008] Preferably, the differential amplifier module includes amplifiers U5, U6, and U7; amplifiers U5 and U6 are preamplifiers providing differential amplification, and amplifier U7 is a differential amplifier for eliminating common-mode voltage; the output terminals node1 and node2 of amplifiers U5 and U6 are connected through resistor R. 11 R 12 R 13 Series connection; the output node1 of amplifier U5 is connected to R through resistor R9. 10 And the positive input terminal of amplifier U7, the R 10 Connect the output terminal of amplifier U7; the output terminal node2 of amplifier U6 is connected to resistor R. 14 Connect R 15 And the inverting input terminal of amplifier U7, R 15 Connect to reference power supply V ref .

[0009] Preferably, the range selection module includes a chip U 12 The output signal of the bandpass filter module passes through resistor R. 24 R26 Enter chip U 12 Two input terminals, resistor R 24 With resistance R 27 Connection, resistor R 27 Grounding;

[0010] The FPGA is connected to the temperature compensation module, which includes a chip U. 16 Resistance R 41 R 42 R 43 C 44 The resistor R 41 One end is connected to the power supply, and the other end is connected to resistor R. 42 R 43 Connection, resistor R 42 Connect to chip U respectively 16 Capacitor C 44 resistance R 43 With capacitor C 44 Parallel connection, capacitor C 44 Both ends are connected to chip U 16 The two endpoints.

[0011] A method for acquiring weak DC voltage signals based on FPGA: after the sensor completes the pseudo-differential DC voltage signal conversion of the target physical quantity, the signal enters the pre-amplification module for primary gain adjustment;

[0012] The signal input chopper module converts low-frequency or DC signals into AC square waves using chopper modulation technology. The chopped AC signal is processed by a differential amplifier module, then enters an active bandpass filter. The filtered signal enters a range selection module, which dynamically switches the gain level according to the signal amplitude to ensure that the signal amplitude is within the ADC input range, achieving wide dynamic range acquisition. Subsequently, a low-noise amplifier module performs a final stage of amplification to improve the signal-to-noise ratio. The amplified analog signal is then sent to a high-resolution ADC module for analog-to-digital conversion. The resulting digital signal is processed in real time by an FPGA. The FPGA acquires temperature compensation information and dynamically corrects the sensing signal to achieve adaptive compensation for ambient temperature.

[0013] Preferably, the FPGA uses a square wave signal to further control the selection switch U3. When the output of the multiplexer U4 is high, the selector switch U3's C... out+ Output C in1 The voltage at point C out- Output C in2 The voltage at the point, conversely, when the output of multiplexer U4 is low, selector switch U3's C... out+ Output C in2 The voltage at point C out- Output C in1The voltage at the input of the amplifier, C out+ And C out- The output amplitude of the square wave signal is equal, and the phase difference is 180°. Thus, the chopping modulation of the input DC signal is realized, and the frequency of the square wave signal output by U3 is the same as that of the chopping control signal, providing a synchronous reference for subsequent demodulation, which facilitates accurate restoration of the reference signal.

[0014] Preferably, in the differential amplification module, the gain G is calculated as follows:

[0015] When R 10 = R 15 , R9 = R 14 , R 11 = R 13 , V ref = 0,

[0016]

[0017] The positive input terminal of amplifier U5 is connected to the input voltage V in1 , and the positive input terminal of amplifier U6 is connected to the input voltage V in2 .

[0018] Preferably, the range selection module avoids saturation by pre-attenuating large signals, and further amplifies small signals in the subsequent amplification circuit;

[0019] The range selection module distinguishes between high and low ranges of signals, and there is a 6dB overlap between the high and low ranges. The high and low ranges are continuous, and the high and low ranges are controlled by FPGA. The final measurement result is obtained by appropriate weighting to ensure smooth transition between the high and low ranges. The signal strength attenuation value G d of the high range part in the range selection circuit is:

[0020]

[0021] Preferably, the temperature compensation method is as follows:

[0022] V AIN0 is the ADC input voltage, V REF is the input reference voltage, Gain is the ADC gain, R REF is the value of the reference resistor R 41 , Code is the value of the temperature ADC after analog-to-digital conversion, and R Thermistor is the value of the thermistor R 43 ;

[0023]

[0024] The reference resistor and the thermistor should satisfy the following formula:

[0025] RREF 2 = R Thermistor_Max · R Thermistor_Min

[0026] wherein R Thermistor_Max is the maximum value of the thermistor, and R Thermistor_Min is the minimum value of the thermistor.

[0027] Compared with the prior art, the application has the following advantages:

[0028] (1) The system has self-adaptive noise suppression capability and is designed for high-precision acquisition and processing of weak voltage signals. The system constructs an efficient signal processing link with chopper technology, differential amplification and multi-stage filtering as the core, which can effectively suppress low-frequency noise and drift, realize stable and high-resolution measurement of sub-microvolt-level direct-current weak voltage signals. In terms of dynamic range expansion, the system combines real-time measurement results with weighted algorithms to intelligently control the seamless switching between high and low ranges, ensuring smooth signal transition and avoiding distortion, thereby not only significantly improving the applicable measurement range of the system, but also further enhancing the overall measurement accuracy and stability.

[0029] (2) A weak signal processing scheme suitable for non-strong noise environment is proposed according to the actual needs of sensor signal detection. This scheme focuses more on the optimization of the signal link itself, especially in suppressing additional noise introduction. Through reasonable circuit structure design, noise control strategy and temperature compensation scheme, the system signal-to-noise ratio and monitoring stability are effectively improved. The proposed scheme provides strong support for high-precision, low-noise sensor signal acquisition. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is the principle framework diagram of the application;

[0031] Figure 2 is the pre-amplification module circuit diagram;

[0032] Figure 3 is the chopper module circuit diagram;

[0033] Figure 4 is the differential amplification module circuit diagram;

[0034] Figure 5 is the band-pass filter module circuit diagram;

[0035] Figure 6 is the range selection module circuit diagram;

[0036] Figure 7 is the low-noise amplification module circuit diagram;

[0037] Figure 8 is the ADC module driving circuit;

[0038] Figure 9 This is the temperature compensation module circuit. Detailed Implementation

[0039] The technical solution of this application will be described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of this application, rather than limitations thereof. Specific technical features can be combined with each other.

[0040] Figure 1 A DC weak voltage signal acquisition system based on FPGA includes a pre-amplification module, a chopper module, a differential amplifier module, an FPGA, a bandpass filter module, and an ADC module. The two outputs of the pre-amplification module enter the differential amplifier module through the chopper module. The output of the differential amplifier module is connected to the filter module. The output signal of the bandpass filter module passes sequentially through a range selection module, a low-noise amplifier module, and the ADC module before entering the FPGA. The FPGA is connected to a host computer, the chopper module, and a temperature compensation module.

[0041] Figure 2 The pre-amplification module includes two identical amplification units. Each amplification unit includes an operational amplifier U1, a capacitor C3, and resistors R1 and R2. The input terminal of the operational amplifier U1 is connected to the sensor, and the other input terminal is connected to resistors R1 and R2 and capacitor C3 respectively. Resistor R1 is grounded. Resistor R2 and capacitor C3 are connected in parallel to the output terminal of operational amplifier U1, and the output terminal of operational amplifier U1 is connected to a chopper module.

[0042] Figure 3 The chopper module includes a multiplexer U4 and a selection switch U3. The two outputs of the pre-amplifier module are connected to the four terminals (D1, D2, D3, D4) of the selection switch U3. The IN1, IN2, IN3, and IN4 terminals of the selection switch U3 are all connected to the multiplexer U4. Inverters are provided on the IN2 and IN3 terminals of the selection switch U3. The VDD terminal of the selection switch U3 is connected to +5V and capacitor C7, and capacitor C7 is grounded. The VSS terminal is connected to -5V, capacitor C8, and capacitor C8 is grounded and connected to the GND terminal of the selection switch U3.

[0043] The A terminal of multiplexer U4 is connected to the IN1, IN2, IN3, and IN4 terminals of selector switch U3, respectively; the VCC terminal of multiplexer U4 is connected to resistor R5 and capacitor C9, with resistor R5 connected to +5V; the S terminal of multiplexer U4 is connected in series with resistors R6 and R7, and resistors R6 and R7 are connected in parallel with capacitor C9 and then grounded; the B terminal of multiplexer U4 is connected to R8 and C9, respectively. 10 C 11 Capacitor C 10 C11 Parallel ground, R8 +5V.

[0044] FPGA output control signal CHOP_CTL control multiplexer U4 output between 0V and +5V constantly switching, generating square wave signal; the selection switch U3 two signal output terminals are connected respectively differential amplifier module.

[0045] Figure 4 , the differential amplifier module includes amplifier U5, amplifier U6 and amplifier U7; amplifier U5, amplifier U6 for providing differential preamplifier, amplifier U7 for eliminating common mode voltage differential amplifier; amplifier U5, amplifier U6 output node1, node2 through resistance R 11 , R 12 , R 13 Series; amplifier U5 output node1 through resistance R9 connection R 10 and amplifier U7 positive input end, the R 10 connected to the amplifier U7 output; the amplifier U6 output node2 through resistance R 14 connection R 15 and amplifier U7 negative input end, R 15 connect the reference power V ref .

[0046] Figure 5 , in order to realize high selectivity and low pass band ripple frequency screening, the system uses eight order Butterworth structure design band pass filter, its band in amplitude response flat, suitable for 1kHz square wave signal effective extraction, while suppressing out of band interference. Band pass filter module includes in series U8, U9, U 10 and U 11 .

[0047] Figure 6 For range selection module includes chip U 12 , the output signal of the band pass filter module through resistance R 24 , R 26 into the chip U 12 two input terminals, resistance R 24 and resistance R 27 , resistance R 27 connect the ground.

[0048] Figure 7 For low noise amplifier module, including operational amplifier U 13， positive input end V in , the reverse end is connected to resistance R 30 , R 31 , C 39 , resistance R30 Grounding; R 31 C 39 Parallel connection followed by operational amplifier U 13 The output terminal.

[0049] Figure 8 This is the driver circuit for the ADC module, including the arithmetic unit U. 14 U 15 The analog-to-digital converter (ADC) module employs a 24-bit Σ-Δ ADC, offering advantages such as wide input bandwidth and high-speed sampling. At a sampling rate of 2.5 MSPS, the device achieves a signal-to-noise ratio (SNR) of 100 dB. Internally, the chip utilizes oversampling technology, significantly increasing the modulator's sampling frequency to extend quantization noise over a wider frequency range (0 Hz to 20 MHz), thereby significantly reducing noise power within the target signal band and improving the SNR. To further enhance the extraction of effective signals, the chip integrates a three-stage FIR digital filter architecture. The modulator output data is first input to the first-stage FIR filter at a rate of 20 MHz. This filter effectively suppresses out-of-band quantization noise while simultaneously processing the data. Extraction effectively reduces the load on the backend processing. The subsequent second-stage FIR filter continues to use... The decimation ratio of the pre-processed output gradually compresses the data bandwidth while retaining effective information within the signal frequency band, ultimately forming a high-quality, low-distortion digital output signal. After cascaded filter processing, the system can achieve an effective output rate of 1.25MHz, meeting the requirements of high-speed, high-precision data acquisition. In terms of the analog front-end, the chip integrates a differential amplifier and supports anti-aliasing filter configuration. To ensure rated performance in normal system mode, the analog signal needs to be converted from single-ended to differential drive via an operational amplifier, forming a differential input drive structure that matches the analog-to-digital converter module. The circuit implementation is as follows: Figure 8 .

[0050] Figure 9 The FPGA is connected to a temperature compensation module, which includes a chip U. 16 Resistance R 41 R 42 R 43 C 44 The resistor R 41 One end is connected to the power supply, and the other end is connected to resistor R. 42 R 43 Connection, resistor R 42 Connect to chip U respectively 16 Capacitor C 44 resistance R 43 With capacitor C 44 Parallel connection, capacitor C 44 Both ends are connected to chip U 16 The two endpoints.

[0051] This invention addresses the problems of slow response and poor adaptability to low-frequency DC signal detection in traditional weak signal detection processes by proposing a weak voltage signal acquisition method with adaptive noise suppression function.

[0052] After the sensor completes the pseudo-differential DC voltage signal conversion of the target physical quantity, it enters the primary gain adjustment circuit to enhance the signal amplitude. Subsequently, the signal is input to the chopper circuit, where chopper modulation technology converts the low-frequency or DC signal into a 1kHz AC square wave, effectively suppressing low-frequency drift and... Noise. The chopped AC signal is processed by a differential amplifier to further improve the common-mode rejection ratio and achieve high-precision differential amplification. The signal then enters an active bandpass filter to accurately filter out interference noise outside the target frequency band, retaining effective frequency components. The filtered signal enters the range selection module, which dynamically switches the gain level according to the signal amplitude to ensure the signal amplitude is within the ADC input range, achieving high-precision acquisition over a wide dynamic range. Subsequently, a low-noise amplifier performs a final stage of amplification to further improve the signal-to-noise ratio. The amplified analog signal is then sent to a high-resolution ADC for analog-to-digital conversion. The resulting digital signal is processed in real-time by the FPGA, including digital filtering, averaging, and error compensation. Finally, the data is visualized, recorded, and analyzed via host computer software. To enhance the system's stability under different environmental conditions, a temperature compensation circuit is integrated into the design. This circuit collects ambient temperature information in real time and dynamically corrects the sensor signal, achieving adaptive compensation for ambient temperature and effectively improving the overall measurement accuracy and reliability of the system. The block diagram of the DC weak voltage signal acquisition system is shown below. Figure 1 As shown, the system, when paired with sensors, can effectively measure voltage signals as low as 0.22μV to 70mV.

[0053] To amplify the weak voltage signal output by the sensor with high fidelity, the pre-amplifier signal conditioning circuit uses the AD797BR ultra-low noise operational amplifier from Analog Devices. This chip features extremely low input voltage noise density and harmonic distortion, making it ideal for precision analog front-end design. The voltage signal output by the sensor is a pseudo-differential DC signal, with its effective signal characterized by the differential voltage between the two output terminals. The voltages to ground at the two output terminals are not symmetrical, resulting in a common-mode component. However, the overall signal is a stable DC signal. The pre-amplifier circuit employs a non-inverting amplification structure to achieve a 10x gain, ensuring that the total system noise is below a certain threshold while amplifying the signal. This design can provide a high signal-to-noise ratio output in the frequency range of DC to 100kHz, effectively suppressing the accumulation of errors in the subsequent amplifier circuit and ADC acquisition process.

[0054] To improve the flatness of the frequency response and enhance the stability of the system in the high-frequency range, a 5.0pF compensation capacitor is connected in parallel with the feedback resistor. This compensation network optimizes the phase margin of the system, enabling the entire amplifier circuit to have better dynamic performance and phase characteristics over a wide bandwidth, and improving the system's anti-interference capability.

[0055] After the amplification process, the voltage signal output by the sensor showed a certain increase in amplitude. However, during subsequent amplification, the operational amplifier and other components exhibited significant performance degradation at low frequencies (<10Hz). Noise is prevalent, and the lower the frequency, the greater the noise. Weak DC signals are easily masked in this frequency band. When an amplifier amplifies a signal, DC drift and zero-point drift are also amplified. To reduce noise during signal processing... To reduce noise and DC drift, and improve the measurement accuracy of small DC or low-frequency signals, the pre-amplified DC signal is chopped to avoid drift and noise effects from the subsequent operational amplifier at low frequencies, thereby improving the sensor's dynamic range and measurement accuracy. The FPGA output control signal CHOP_CTL controls the output of multiplexer U4 to continuously switch between 0V and +5V, generating a 1kHz square wave signal. This signal is used to further control U3. When the output of U4 is high, C... out+ Output C in1 The voltage at point C out- Output C in2 The voltage at the point, conversely, when the output of U4 is low, C out+ Output C in2 The voltage at point C out- Output C in1 The voltage at point C out+ and C out- The output square wave signal has the same amplitude and a phase difference of 180°, thus realizing the chopping modulation of the input DC signal. The frequency of the square wave signal output by U3 is the same as that of the chopping control signal, providing a synchronous reference for subsequent demodulation and facilitating accurate restoration of the reference signal.

[0056] The differential amplifier module employs a traditional three-op-amp topology, consisting of two stages: a preamplifier providing differential amplification and a differential amplifier eliminating common-mode voltage. The differential signal applied to the input is copied to R... 12 At both ends, flowing through R 12 The current also flows through R. 11 and R 13 A differential voltage with amplified gain is established between node1 and node2. The amplified differential and common-mode signals are input to the differential amplifier. The common-mode voltage is suppressed, while the differential voltage is retained. This circuit can achieve extremely low output error.

[0057] In this circuit configuration, the two signal input terminals are connected to the non-inverting input terminal of the corresponding operational amplifier. The input impedance of the non-inverting input terminal is very high. Since the two operational amplifiers use the same manufacturing process, the input impedances of the two input terminals are also approximately equal. When R 10 =R 15 R9 = R 14 R 11 =R 13 V ref =0

[0058]

[0059]

[0060] To match the subsequent low-noise amplifier, range selection circuit, and ADC signal detection range, and considering the amplitude of the sensor output voltage, the gain is appropriately set here. 11 For a fixed 15kΩ, R 12 With an impedance of 10kΩ, the amplifier circuit achieves a gain of G = 4. At this point, the voltage range of the low-range portion in the subsequent range selection circuit is 28μV to 112mV, and the voltage range of the high-range portion is 28mV to 2.8V. Furthermore, the voltage amplitude after the output of the subsequent low-noise amplifier meets the detection range of the ADC input signal and satisfies the signal processing requirements of the subsequent circuit.

[0061] To achieve high selectivity and low passband ripple in frequency filtering, this system employs an eighth-order Butterworth structure to design a bandpass filter. Its in-band amplitude response is flat, making it suitable for the effective extraction of 1kHz square wave signals while suppressing out-of-band interference. Theoretically, an ideal square wave signal can be decomposed into a fundamental wave and all its odd harmonics (such as 3f, 5f, 7f, etc.), with amplitudes calculated as follows: The Fourier series expansion of the superposition of attenuated sine waves is shown in equation (3):

[0062]

[0063] To ensure the square wave signal remains undistorted, at least the high-frequency components between 1kHz and 9kHz must be preserved. Therefore, the designed bandpass filter has a passband setting of 800Hz to 10kHz, which can effectively filter out low-frequency drift and DC components, suppress high-frequency noise, and retain the key signal characteristics of the square wave signal, thereby improving the accuracy of subsequent signal processing.

[0064] If the voltage signal output by the band-pass filter circuit is directly input to the ADC, the measurement accuracy of the small signal part will be limited by the quantization resolution. In order to improve the ability of the sensor in small signal detection, the system introduces a range selection circuit, which pre-attenuates the large signal to avoid saturation, and further amplifies the small signal in the subsequent amplifier circuit, thereby effectively improving the overall measurement sensitivity and accuracy. In the present scheme, a range switching circuit is used to distinguish between high and low ranges of the signal, and there is a 6dB overlap between the high and low ranges, which are continuous. The high and low ranges are controlled by the FPGA, and the final measurement result is obtained by appropriate weighting to ensure smooth transition between the high and low ranges. The signal strength attenuation value of the high range part in the range selection circuit is R 27 / (R 24 +R 27 )=1 / 25, the maximum voltage amplitude of the high and low ranges after attenuation by the resistance attenuation network is 112mV, to ensure that the voltage amplitude in the entire range is within the sampling range of the ADC after further amplification, the range control circuit is as follows Figure 6 .

[0065] The maximum value of the high and low range signals selected by the range control circuit is 112mV, and the output signal is further amplified in the same direction, with an amplification factor of 29. The maximum amplitude of the circuit output under high and low range conditions is 3.248V after amplification, which meets the voltage input range of the ADC. The low-noise amplifier circuit is implemented as Figure 7 .

[0066] The analog-to-digital conversion module uses a 24-bit sigma-delta analog-to-digital converter, which has the advantages of wide input bandwidth and high-speed sampling. At a sampling rate of 2.5MSPS, the device can achieve a signal-to-noise ratio of 100dB. Inside the chip, oversampling technology is used to significantly reduce the noise power in the target signal frequency band and improve the signal-to-noise ratio by significantly increasing the sampling frequency of the modulator and spreading the quantization noise to a wider frequency range (0Hz-20MHz). To further enhance the ability to extract effective signals, a three-stage FIR digital filter architecture is integrated into the chip. The data output by the modulator is first input to the first-stage FIR filter at a rate of 20MHz, which suppresses the out-of-band quantization noise while decimating the data to effectively reduce the load of the backend processing. The second-stage FIR filter continues to decimate the data at a rate of The extraction ratio of the extraction is higher than the processing front stage output, the data bandwidth is gradually compressed and the effective information in the signal frequency band is reserved, and finally a high-quality, low-distortion digital output signal is formed, after the filter cascade processing, the system can realize 1.25MHz effective output rate, meet the demand of high-speed high-precision data acquisition. In the analog front end, the chip built-in differential amplifier supports the anti-aliasing filter configuration, in order to ensure that the system reaches the rated performance in the normal mode, the analog signal needs to be driven by the operational amplifier to realize single-ended to differential, form the differential input drive structure matching the analog-digital conversion module, the circuit implementation is as follows Figure 8 The differential input voltage is limited by the reference voltage V ref , which should not exceed 80% of V ref , and in this design, V ref is 4.096V, so the input differential signal range is ±3.275V, which can well match the output range of the front-stage signal conditioning circuit and realize efficient connection between systems.

[0067] In the actual test environment of the sensor, the test result is easily affected by the change of environmental temperature, thereby introducing measurement error, in order to improve the accuracy of the test data, the temperature compensation circuit is combined to adaptively correct the change of environmental temperature and related noise, and effective inhibition of temperature drift is realized. The temperature compensation circuit is as follows Figure 9 A 10kΩ thermistor is used for temperature measurement, and +3.3VDD is used as the excitation voltage of the thermistor. By measuring the voltage distribution in the R 41 and R 43 voltage division network, it is converted into a corresponding digital code to realize accurate measurement of the temperature ADC.

[0068] The relationship between the temperature ADC and the resistance value of the thermistor is as formula 6, wherein

[0069] V AIN0 is the ADC input voltage, V REF is the input reference voltage, Gain is the ADC gain, R REF is the value of the reference resistance R 41 , Code is the value of the temperature ADC after analog-digital conversion, and R Thermistor is the value of the thermistor R 43 .

[0070]

[0071]

[0072] In the thermistor temperature compensation system, the measurement accuracy is independent of the excitation voltage, but depends on the accuracy of the reference resistance R REF . Since the thermistor and the reference resistance R REFThe reference resistance and the thermistor constitute a voltage division relationship, and the error of the reference resistance will directly affect the linearity and accuracy of the temperature measurement result. Therefore, a precision resistance with high precision and low drift characteristics needs to be selected as R REF . To achieve the best performance of the system, the reference resistance and the thermistor should satisfy formula (7), wherein R Thermistor_Max is the maximum value of the thermistor, and R Thermistor_Min is the minimum value of the thermistor.

[0073] R REF 2 = R Thermistor_Max · R Thermistor_Min (7)

[0074] In the circuit implementation process, NCP15XH103J03RC is selected as the thermistor, the resistance value is 195.652kΩ at-40℃, the resistance value is 0.531kΩ at 125℃, and the resistance value of the reference resistance is 10.2kΩ. The voltage input range of the ADC is 0.16V to 3.14V, which meets the voltage input range requirement of the temperature ADC.

[0075] Compared with the prior art, the application is more focused on sensing signal monitoring and processing in application, and the collected signal form is a direct current weak signal, which is suitable for effective monitoring and processing of sub-microvolt level weak signals output by a sensor. In the signal processing process, the system flexibly introduces chopper and differential amplification technology, effectively suppresses common mode interference, and improves the anti-interference ability and measurement precision of the signal link. The application aims to convert the original sensing signal into a stable and directly collectable direct current voltage signal, form a clear and clean output, and facilitate subsequent data acquisition and analysis. The overall design focuses on the protection and amplification of weak signals, emphasizes anti-interference performance and high-fidelity output capability, and can more efficiently and reliably realize real-time and high-precision detection of sensor signals.

[0076] The above only describes the preferred embodiments of the application, and it should be noted that for ordinary skilled persons in the technical field, several improvements and modifications can be made without departing from the technical principles of the application, and these improvements and modifications should be considered as the protection scope of the application.

Claims

1. An FPGA-based direct current weak voltage signal acquisition system, characterized in that, It comprises a pre-amplification module, a chopping module, a differential amplification module, an FPGA, a band-pass filter module and an ADC module; two-way output of the pre-amplification module enters the differential amplification module through the chopping module, the output of the differential amplification module is connected with the filter module, the output signal of the band-pass filter module sequentially passes through a range selection module, a low-noise amplification module and an ADC module to enter the FPGA; the FPGA is connected with an upper computer and the chopping module respectively.

2. The FPGA-based direct current weak voltage signal acquisition system according to claim 1, characterized in that, The pre-amplification module comprises two amplification units with the same structure, each of which comprises an operational amplifier U1, a capacitor C3 and resistors R1 and R2; the input end of the operational amplifier U1 is connected with a sensor, the other input end is connected with the resistor R1, the resistor R2 and the capacitor C3 respectively, and the resistor R1 is grounded; the resistor R2 and the capacitor C3 are connected in parallel and then connected with the output end of the operational amplifier U1, and the output end of the operational amplifier U1 is connected with the chopping module.

3. The FPGA-based direct current weak voltage signal acquisition system according to claim 1, characterized in that, The chopping module comprises a multiplexer U4 and a selection switch U3, two-way output of the pre-amplification module is connected with four end points of the selection switch U3 respectively, the IN1, IN2, IN3 and IN4 end points on the selection switch U3 are connected with the multiplexer U4, and an inverter is arranged on the IN2 and IN3 end points of the selection switch U3; the FPGA outputs a control signal CHOP_CTL to control the output of the multiplexer U4 to be switched between 0V and +5V constantly to generate a square wave signal; and two signal output ends of the selection switch U3 are connected with the differential amplification module respectively.

4. The FPGA-based direct current weak voltage signal acquisition system according to claim 1, characterized in that, The differential amplification module comprises an amplifier U5, an amplifier U6 and an amplifier U7; the amplifier U5 and the amplifier U6 are preamplifiers for providing differential amplification, and the amplifier U7 is a differential amplifier for eliminating common-mode voltage; the output ends node1 and node2 of the amplifier U5 and the amplifier U6 are connected in series through resistors R 11 , 12 , 13 ; the output end node1 of the amplifier U5 is connected with the positive input end of the amplifier U7 through a resistor R 10 , and the output end of the amplifier U7 is connected with a resistor R 10 ; the output end node2 of the amplifier U6 is connected with the negative input end of the amplifier U7 through a resistor R 14 , and the resistor R 15 is connected with a reference power supply V 15 . ref ​ 5. The FPGA-based direct current weak voltage signal acquisition system according to claim 1, characterized in that, The range selection module includes chip U 12 The output signal of the band-pass filter module passes through resistors R 24 , R 26 into two input terminals of chip U 12 Resistor R 24 is connected with resistor R 27 , and resistor R 27 is grounded. The FPGA is connected with a temperature compensation module, the temperature compensation module includes a chip U 16 , a resistor R 41 , R 42 , R 43 , C 44 ; one end of the resistor R 41 is connected with a power supply, and the other end is connected with resistors R 42 , R 43 respectively, the resistor R 42 is connected with the chip U 16 and the capacitor C 44 respectively, the resistor R 43 is connected with the capacitor C 44 in parallel, and the capacitor C 44 is connected with two end points of the chip U 16 respectively.

6. A method for collecting weak DC voltage signal based on FPGA, applicable to the system as claimed in any one of claims 4-5, characterized in that, After the sensor completes the conversion of the pseudo-differential direct current voltage signal of the target physical quantity, the signal enters the pre-amplification module for primary gain adjustment. The signal enters the chopping module to convert the low-frequency or direct current signal into an alternating square wave through chopping modulation technology; the chopped alternating signal is processed by the differential amplification module, then the signal enters an active band-pass filter, the filtered signal enters a range selection module, the gain level is dynamically switched according to the signal amplitude to ensure that the signal amplitude is within the input range of the ADC, and the signal is collected in a wide dynamic range; subsequently, the low-noise amplification module performs the last-stage amplification on the signal to improve the signal-to-noise ratio, the analog signal after the amplification processing is sent to the high-resolution ADC module for analog-digital conversion, the obtained digital signal is processed in real time by the FPGA, the FPGA acquires temperature compensation information and dynamically corrects the sensing signal to realize the self-adaptive compensation of the ambient temperature.

7. The FPGA-based direct-current weak voltage signal acquisition method according to claim 6, characterized in that, FPGA utilizes square wave signal to make further control to selection switch U3, when multi-channel selector U4 outputs high level, voltage at C out+ output of selection switch U3, otherwise when multi-channel selector U4 outputs low level, voltage at C in1 output of selection switch U3 out- . in2 output of selection switch U3 out+ . in2 output of selection switch U3 out- . in1 output of selection switch U3 out+ and C out- output amplitude equal square wave signal with phase difference 180°, thus realizes chopping modulation of input DC signal, frequency of square wave signal output by U3 is same as that of chopping control signal, provides synchronous reference for subsequent demodulation, and facilitates restoration of reference signal.

8. The FPGA-based direct-current weak voltage signal acquisition method according to claim 6, characterized in that, In the differential amplification module, the gain G is calculated as follows: when R 10 = R 15 , R9= R 14 , R 11 = R 13 , V ref = 0, The positive input of amplifier U5 is connected to the input voltage V in1 The positive input of amplifier U6 is connected to the input voltage V in2 .

9. The FPGA-based direct-current weak voltage signal acquisition method according to claim 6, characterized in that, The range selection module pre-attenuates the large signal to avoid saturation and further amplifies the small signal in the subsequent amplification circuit; The range selection module distinguishes the high and low ranges of the signal, and there is a 6dB overlap between the high and low ranges. The high and low ranges are continuous, and the high and low ranges are controlled by the FPGA. The final measurement result is obtained by appropriate weighting, ensuring smooth transition between the high and low ranges. In the range selection circuit, the signal strength attenuation value G of the high range part is d :

10. The FPGA-based direct-current weak voltage signal acquisition method according to claim 6, characterized in that, The temperature compensation method is as follows: V AIN0 is the input voltage of the ADC, V REF is the input reference voltage, Gain is the ADC gain, R REF is the value of the reference resistor R 41 is the value of the thermistor R Thermistor ; Code is the value of the ADC corresponding to the temperature after analog-to-digital conversion, R 43 ; The reference resistor and the thermistor should satisfy the following formula: R REF 2 = R Thermistor_Max • R Thermistor_Min where R Thermistor_Max is the maximum value of the thermistor, and R Thermistor_Min is the minimum value of the thermistor.

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