Electrostatic discharge test structure, test method and chip

Abstract

The invention provides an electrostatic discharge test structure, a test method and a chip, the test structure comprises an electrostatic discharge protection device and a protected device, the positive electrode of the electrostatic discharge protection device and the positive electrode of the protected device are jointly connected with a second test pad, and the negative electrode of the electrostatic discharge protection device is connected with a first test pad. And the cathode of the protected device is connected with the third test pad. The test pads are coupled, the typesetting layout area of the electrostatic discharge test structure is reduced, meanwhile, the first test pad, the second test pad and the third test pad are adopted to carry out TLP characteristic test on the electrostatic discharge test structure, the effective pulse current in the effective window of the electrostatic discharge protection device can be accurately measured, and the test accuracy is improved. The method does not excessively depend on test hardware, makes up for the defects of test in the industry, is not affected by parasitic internal resistance of a machine and the like, and does not need calculation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to an electrostatic discharge test structure, test method, and chip. Background Technology

[0002] In the development and design of electrostatic discharge (ESD) devices, semiconductor manufacturing fab process platforms require the design of ESD test structures and their testing, evaluation, and verification. The circuit design of conventional ESD test structures must meet the requirements of the ESD Design Window (or ESD Effective Window).

[0003] Figure 1 This is a schematic diagram illustrating the effective electrostatic discharge window range of an electrostatic discharge protection device. Please refer to it. Figure 1 As shown, the lower limit (LSL) of the effective electrostatic discharge (ESD) window is determined by the operating voltage (Vop) of the protected device. The trigger voltage (Vtrigger) of the ESD protection device must be greater than the operating voltage of the protected device, i.e., Vtrigger > Vop, to ensure that the ESD protection device is in the off state during normal operation and does not affect the operation of the normal circuit. The upper limit (USL) is determined by the breakdown voltage (BV) of the protected device. The trigger voltage (Vtrigger) of the ESD protection device must be less than the breakdown voltage of the protected device, i.e., Vtrigger < BV, to ensure that the ESD protection device can be turned on in time when an ESD event occurs, discharging the large ESD current and preventing the protected device from being burned out.

[0004] Figure 2 This is a schematic diagram of the TLP (Transmission Line Pulse) IV (current-voltage) curve when the electrostatic discharge protection device is a high-voltage electrostatic discharge PNP device. Please refer to it. Figure 2As shown, ① is a trigger point, which is the opening point of the electrostatic discharge protection device, the turning point from high resistance state to low resistance state, the corresponding pulse voltage (Pulse V) is called Vtrigger, and the corresponding pulse current (Pulse I) is called Itrigger. ② is the dynamic resistance of the electrostatic discharge protection device in the triggered conduction state, which is the conduction resistance (Ron) and determines the voltage drop generated by the device when discharging the current. ③ is a second breakdown point (2nd breakdown), which is the point at which the electrostatic discharge protection device fails due to heat caused by thermal breakdown. The corresponding pulse current is called the second breakdown current It2, and the corresponding pulse voltage is called the second breakdown voltage Vt2. At this time, the electrostatic discharge protection device is thermally damaged and permanently damaged. ④ is the intersection of the USL and the TLPIV curve, which corresponds to the effective pulse current It2. The effective electrostatic discharge window is the effective electrostatic discharge performance, and at this time the electrostatic discharge protection device is not failed and damaged. However, outside the window, the protected device will be turned on, which has the risk of being burned out. The electrostatic discharge protection device also does not have a protective effect, i.e. invalid protection capability.

[0005] The on-resistance of the electrostatic discharge protection device with a protective capability is usually small (for example, within 10Ω, or even less than 1Ω), but due to the existence of machine parasitic resistance, test system lead resistance, test table parasitic resistance, etc., the test accuracy of the on-resistance is greatly reduced, thereby causing the accuracy of the effective pulse current It2 to be not high and being underestimated. SUMMARY

[0006] The purpose of the present application is to provide an electrostatic discharge test structure, a test method and a chip, which can reduce the layout area of the electrostatic discharge test structure and accurately measure the effective pulse current It2 in the effective window of the electrostatic discharge protection device.

[0007] To solve the above technical problems, the present application provides an electrostatic discharge test structure, comprising: an electrostatic discharge protection device and a protected device, the positive electrode of the electrostatic discharge protection device and the positive electrode of the protected device are commonly connected to a second test pad, the negative electrode of the electrostatic discharge protection device is connected to a first test pad, and the negative electrode of the protected device is connected to a third test pad.

[0008] Optionally, the high potential end of the electrostatic discharge protection device and the protected device is the positive electrode, and the low potential end is the negative electrode.

[0009] Optionally, the electrostatic discharge protection device comprises a bipolar junction transistor or a metal oxide semiconductor field effect transistor, and the protected device comprises a metal oxide semiconductor field effect transistor.

[0010] Optionally, the collector of the PNP bipolar junction transistor is negative, the base and the emitter are positive, the collector of the NPN bipolar junction transistor is positive, the base and the emitter are negative; the drain of the N-type metal oxide semiconductor field effect transistor is positive, the source, the gate and the body are negative, the drain of the P-type metal oxide semiconductor field effect transistor is negative, the source, the gate and the body are positive.

[0011] Optionally, the Psub substrate end of the electrostatic discharge protection device is connected with the Psub substrate end of the protected device to the fourth test pad.

[0012] Correspondingly, the application further provides a chip comprising the electrostatic discharge test structure.

[0013] Correspondingly, the application further provides an electrostatic discharge test method for testing the electrostatic discharge test structure.

[0014] The first test pad, the second test pad and the third test pad are used to test the TLP characteristics of the electrostatic discharge test structure.

[0015] Optionally, when the TLP characteristics are tested, the second test pad is connected with a TLP pulse probe, the first test pad is connected with a TLP grounding probe, and the third test pad is connected with a TLP direct current bias probe and the voltage is 0V.

[0016] Optionally, the method further comprises using the first test pad, the second test pad and the third test pad to test the DC electrical characteristics of the electrostatic discharge test structure; when the DC electrical characteristics are tested, the second test pad applies a voltage or a voltage scan, the first test pad applies a 0V voltage, and the third test pad applies a 0V voltage.

[0017] Optionally, the method further comprises using the first test pad, the second test pad and the third test pad to test the package HBM of the electrostatic discharge test structure; when the package HBM is tested, the second test pad is connected with an HBM pulse, and the first test pad and the third test pad are grounded.

[0018] In summary, in the electrostatic discharge test structure, the test method and the chip provided by the application, the electrostatic discharge test structure comprises an electrostatic discharge protection device and a protected device, a positive electrode of the electrostatic discharge protection device and a positive electrode of the protected device are connected to a second test pad, a negative electrode of the electrostatic discharge protection device is connected to a first test pad, and a negative electrode of the protected device is connected to a third test pad. The positive electrode of the electrostatic discharge protection device and the positive electrode of the protected device share a test pad, and the test pad is coupled, so that the layout area of the electrostatic discharge test structure is reduced. Meanwhile, the first test pad, the second test pad and the third test pad are used to perform TLP test on the electrostatic discharge test structure, so that the effective pulse current It2 in the effective window of the electrostatic discharge protection device can be accurately measured, the test hardware is not excessively dependent, the defects in the prior art are compensated, the influence of the parasitic internal resistance of a machine table and the like is avoided, and calculation is not required.

[0019] Further, the packaged electrostatic discharge test structure can be directly verified for the electrostatic discharge performance in the effective window by using an HBM machine table.

[0020] In addition, compared with the conventional test structure, the electrostatic discharge test structure of the application is matched with the protection device and the protected device for verification, is closer to the actual application scene, can predict and verify part of the application risk in advance, and reduces the risk of the electrostatic discharge protection device (especially the high-voltage electrostatic discharge protection device) in product application. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a schematic diagram of an electrostatic discharge effective window range of an electrostatic discharge protection device.

[0022] Figure 2 is a schematic diagram of a TLP IV curve when the electrostatic discharge protection device is a high-voltage electrostatic discharge PNP device.

[0023] Figure 3 is a schematic diagram of a measured TLP IV curve and a theoretical TLP IV curve of a high-voltage electrostatic discharge PNP device.

[0024] Figure 4 is an equivalent circuit schematic diagram of the electrostatic discharge test structure provided by an embodiment of the application.

[0025] Figure 5 is a layout schematic diagram of the electrostatic discharge test structure provided by an embodiment of the application.

[0026] Figure 6 is a layout schematic diagram of the electrostatic discharge test structure provided by another embodiment of the application.

[0027] Figure 7is a TLP IV curve provided by an embodiment of the present application when testing the electrostatic discharge protection device alone.

[0028] Figure 8 is a TLP IV curve provided by an embodiment of the present application when testing the protected device alone.

[0029] Figure 9 is a TLP IV curve provided by an embodiment of the present application when testing the electrostatic discharge test structure.

[0030] BRIEF DESCRIPTION OF DRAWINGS

[0031] 10 - electrostatic discharge protection device; 20 - protected device; 31 - first test pad; 32 - second test pad; 33 - third test pad. DETAILED DESCRIPTION

[0032] As shown in the background, due to the existence of machine parasitic resistance, test system lead resistance, test original table parasitic resistance and other resistances, the test accuracy of the on-resistance of the electrostatic discharge protection device is greatly reduced, resulting in low accuracy of the effective pulse current It2.

[0033] Figure 3 is a schematic diagram of the actual TLP IV curve of the high-voltage electrostatic discharge PNP device and the theoretical TLP IV curve. Please refer to Figure 3 As shown, the dashed line is the theoretical curve, and the actual curve is realized. As can be seen, due to the existence of parasitic resistance and other resistances, the effective pulse current It2 will be underestimated (as shown by the one-way arrow in Figure 3 ).

[0034] The machine parasitic resistance, test system lead resistance, test original table parasitic resistance and other resistances in series on the electrostatic protection device will cause the following problems: the on-resistance Ron of the electrostatic protection device is overestimated, the voltage division of the parasitic resistance leads to the overestimation of the secondary breakdown voltage Vt2, the large on-resistance Ron leads to the underestimation of the effective pulse current It2, the electrostatic discharge protection device is broken due to thermal failure, and the current resistance of the electrostatic discharge protection device is not affected by the series parasitic resistance, so the secondary breakdown current It2 is not affected.

[0035] The industry's solution to this mainly includes two methods, the first method is to add a check compensation function to the TLP machine, and the test result is deducted by the parasitic resistance of the machine through the check compensation, but this method only solves the influence of the parasitic resistance of the machine. The second method is to add a TLP 4-end-Kelvin test system to the TLP machine hardware, which can greatly improve the test accuracy of the on-resistance compared to the traditional 2-end test system. However, this method has high requirements for the pin holder and pin card, on the one hand, it is expensive (for example, 10 to 100 times more than the traditional 2-end test system), on the other hand, it is not convenient to operate and the test efficiency is low (for example, the test efficiency is reduced by 2 to 5 times), in addition, the amount of consumables of the pin card is large, and the cost of consumables and maintenance is high (for example, the cost of a single pin card is more than 100 to 1,000 times that of an ordinary pin card, and the amount of consumables is 5 to 10 times that of an ordinary pin card).

[0036] In addition, another existing problem is that the electrostatic discharge performance (ESD performance) within the effective window of the electrostatic discharge device cannot be directly verified by the industry's general HBM machine. The TLP (Transmission Line Pulse) test machine is a core device for evaluating the dynamic performance of electrostatic discharge protection devices, which can simulate real electrostatic discharge events and test the clamping voltage, dynamic resistance and failure threshold of the device. However, TLP testing is an analysis tool for in-depth understanding of the physical properties of electrostatic discharge devices, suitable for the research and development stage. The HBM (Human Body Model) test machine is a standard device for evaluating the anti-electrostatic discharge capability of electronic components, which simulates the discharge process when a person with static electricity touches the pins of a device. Its test results directly affect the electrostatic discharge protection level certification of the chip, and HBM is a certification tool for verifying whether the product meets industry standards, suitable for the measurement stage. The equivalent relationship between TLP test results and HBM is: TLP It2*1500Ω (human body equivalent resistance) is equivalent to HBM level, which is only an approximate HBM result, and the quantitative accurate result needs to be tested and verified by HBM test machine and certified. The secondary breakdown current It2 of the electrostatic discharge protection device can be directly verified by the HBM test result, but the effective current pulse It2 cannot be directly verified by the HBM machine because the device is not damaged.

[0037] The existing solution is to verify through the product circuit framework, but the product application and circuit framework are complex and diverse, only individual cases can be verified, and cannot be verified in all aspects, and the verification requires more resources and a large amount of work, which is not realistic for Fab platform, in addition, it is difficult and complex to debug when the product is verified to find problems, and it is too late to find and solve problems, which is not realistic for Fab platform development progress.

[0038] In order to solve the above problems, the application provides a static discharge test structure, comprising: a static discharge protection device and a protected device, a positive electrode of the static discharge protection device and a positive electrode of the protected device are connected to a second test pad, a negative electrode of the static discharge protection device is connected to a first test pad, and a negative electrode of the protected device is connected to a third test pad.

[0039] The TLP test is performed on the static discharge test structure, and the effective pulse current in the effective window of the static discharge protection device can be directly measured.

[0040] Correspondingly, the application also provides a chip comprising the static discharge test structure.

[0041] Correspondingly, the application also provides a static discharge test method for testing the static discharge test structure, and the test method comprises: performing TLP characteristic test on the static discharge test structure by using the first test pad, the second test pad and the third test pad.

[0042] The static discharge test structure, the test method and the chip provided by the application have the following advantages: the positive electrode of the static discharge protection device and the positive electrode of the protected device share one test pad, the test pad is coupled, and thus the layout area of the static discharge test structure is reduced. Meanwhile, the TLP characteristic test is performed on the static discharge test structure by using the first test pad, the second test pad and the third test pad, the effective pulse current It2 in the effective window of the static discharge protection device can be accurately measured, the test hardware is not excessively relied on, the defects in the industry are compensated, the influence of the parasitic resistance of a machine or the like is avoided, and calculation is not needed.

[0043] Further, the static discharge test structure after packaging can be directly verified for the static discharge performance in the effective window by using an HBM machine.

[0044] In order to make the purpose, advantages and characteristics of the application more clear, the application is further described in detail below in combination with the drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn according to scale, and are only used to facilitate and clearly assist the purpose of describing the embodiments of the application. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0045] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. As used in the present application, the term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. As used in the present application, the term "several" is generally employed in its sense of "at least one" unless the content clearly dictates otherwise. As used in the present application, the term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," are used merely for descriptive purposes and are not understood to indicate or imply relative importance or a quantity of the indicated technical features. Thus, features defined with "first," "second," "third" can explicitly or implicitly include one or at least two of the features.

[0046] Figure 4 is an equivalent circuit schematic diagram of the electrostatic discharge test structure provided by an embodiment of the present application, Figure 5 is a layout schematic diagram of the electrostatic discharge test structure provided by an embodiment of the present application. Please refer to Figure 4 and Figure 5 As shown in the figures, the electrostatic discharge test structure provided by the embodiment includes an electrostatic discharge protection device 10 and a protected device 20. The anode A1 of the electrostatic discharge protection device 10 is connected to the anode A2 of the protected device 20, and the cathode C1 of the electrostatic discharge protection device 10 is connected to the first test pad 31, and the cathode C2 of the protected device 20 is connected to the third test pad 33.

[0047] In an embodiment of the present application, the anode and the cathode of the electrostatic discharge protection device 10 and the protected device 20 are defined as follows: the high potential end of the device in the conventional application is the anode, and the low potential end is the cathode.

[0048] The protected device 20 includes a device that needs to be protected from electrostatic discharge, and the electrostatic discharge protection device 10 includes a device that can prevent the protected device 20 from being damaged by electrostatic discharge. In an embodiment of the present application, the electrostatic discharge protection device 10 includes but is not limited to a bipolar junction transistor or a metal oxide semiconductor field effect transistor. In the subsequent description, the most typical PNP type bipolar junction transistor is taken as an example for introduction. The protected device 20 includes but is not limited to a metal oxide semiconductor field effect transistor. In the subsequent description, the typical N-type metal oxide semiconductor field effect transistor is taken as an example for introduction.

[0049] For the bipolar junction transistor, the collector of PNP type bipolar junction transistor is negative, the base and the emitter are connected as positive, for NPN type bipolar junction transistor, the collector is positive, the base and the emitter are connected as negative. For the metal oxide semiconductor field effect transistor, the drain of N type metal oxide semiconductor field effect transistor is positive, the source, the gate and the body are connected as negative, for P type metal oxide semiconductor field effect transistor, the drain is negative, the source, the gate and the body are connected as positive.

[0050] In the following embodiment, the electrostatic discharge protection device 10 is PNP (PNP type bipolar junction transistor), the protected device 20 is DMOS (N type metal oxide semiconductor field effect transistor), which is taken as an example for description, other types of devices are similar, which will not be described one by one in the embodiment. Please refer to Figure 4 As shown, the base B of the electrostatic discharge protection device 10 is connected with the emitter E as positive A1, which is connected with the second test pad 32, the collector C of the electrostatic discharge protection device 10 is connected as negative C1, which is connected with the first test pad 31. The drain D of the protected device 20 is positive A2, which is connected with the second test pad 32, the source S of the protected device 20 is connected with the gate G as negative C2, which is connected with the third test pad 33.

[0051] Please refer to Figure 5 As shown, the first connection pad 31 is connected with the negative C1 of the electrostatic discharge protection device 10 through a metal wire, the positive A1 of the electrostatic discharge protection device 10 is connected with the second connection pad 32 through a metal wire, the second connection pad 32 is connected with the positive A2 of the protected device 20 through a metal wire, the negative C2 of the protected device 20 is connected with the third connection pad 33 through a metal wire.

[0052] In another embodiment of the present application, the electrostatic discharge test structure can further comprise a fourth connection pad, the substrate end of the electrostatic discharge protection device 10 and the substrate end of the protected device 20 are connected with the fourth test pad. Figure 6 It is the layout of the electrostatic discharge test structure provided by another embodiment of the present application. Please refer to Figure 6As shown, the collector C of the electrostatic discharge protection device 10 is connected to the first test pad 31, the base B and the emitter E of the electrostatic discharge protection device 10 are connected together and connected to the second test pad 32, the drain D of the protected device 20 is connected to the second test pad 32, the gate G, the source S and the bulk B of the protected device 20 are connected together and connected to the third test pad 33, the substrate Psub of the electrostatic discharge protection device 10 is connected to the fourth test pad 34, and the substrate Psub of the protected device 20 is also connected to the fourth test pad 34. The test pads and the devices are connected by metal wires. Of course, in other embodiments, the electrostatic discharge test structure can further include a fifth connection pad or more connection pads to connect other ports of the electrostatic discharge protection device 10 and the protected device 20.

[0053] The electrostatic discharge test structure provided by the embodiment can realize DC electrical test and TLP test of the electrostatic discharge protection device 10 through the first test pad 31 and the second test pad 32, realize DC electrical test and TLP test of the protected device 20 through the third test pad 33 and the second test pad 32, and realize DC electrical test and TLP test of the electrostatic discharge device 10 (i.e. the electrostatic discharge test structure) with the protected device 20 through the first test pad 31, the second test pad 32 and the third test pad 33.

[0054] Table 1 is a comparison between the conventional electrostatic discharge test structure and the electrostatic discharge test structure provided by the embodiment.

[0055] Table 1

[0056]

[0057]

[0058] In Table 1, TLP Pulse is a TLP pulse probe, TLP Pulse:PAD2 indicates that the TLP pulse probe is connected to the second test pad, TLP GND is a TLP ground probe, TLP GND:PAD1 indicates that the TLP ground probe is connected to the first test pad, TLP Bias is a direct current bias probe, and TLP Bias:PAD3, 0V indicates that the TLP direct current bias probe is connected to the third test pad and the voltage is 0V.

[0059] As shown in Table 1, the layout area of the electrostatic discharge test structure of at least one embodiment provided by the present application can be reduced by more than 25%, the test accuracy of the effective pulse current It2 in the effective window is high, and the test results can be directly verified by the HBM machine, thereby reducing the risk of electrostatic discharge protection devices in product application.

[0060] In the electrostatic discharge test structure provided by the embodiment of the present application, the anode A1 of the electrostatic discharge protection device 10 shares a test pad (i.e., the second test pad 32) with the anode A2 of the protected device 20, and the test pads of the electrostatic discharge protection device 10 and the protected device 20 are coupled, thereby reducing the layout area of the electrostatic discharge test structure.

[0061] Meanwhile, the first test pad 31, the second test pad 32, and the third test pad 33 can be used to perform DC electrical test and TLP characteristic test on the electrostatic discharge test structure, which can accurately measure the effective pulse current It2 in the effective window of the electrostatic discharge protection device, without over-reliance on test hardware, thereby making up for the deficiency of the industry test. Moreover, the electrostatic discharge test structure can be directly verified for electrostatic discharge performance in the effective window by the HBM machine after packaging.

[0062] In addition, compared with the conventional test structure, the electrostatic discharge test structure of the present application is matched and verified with the electrostatic discharge protection device 10 and the protected device 20, which is closer to the actual application scenario, can predict and verify part of the application risk in advance, and reduces the risk of electrostatic discharge protection devices (especially high-voltage electrostatic discharge protection devices) in product application.

[0063] Correspondingly, the present application also provides a chip comprising the electrostatic discharge test structure as described above.

[0064] Correspondingly, the present application also provides an electrostatic discharge test method for testing the electrostatic discharge test structure as described above, please refer to Figure 4 and Figure 5 As shown in Table 1, the layout area of the electrostatic discharge test structure of at least one embodiment provided by the present application can be reduced by more than 25%, the test accuracy of the effective pulse current It2 in the effective window is high, and the test results can be directly verified by the HBM machine, thereby reducing the risk of electrostatic discharge protection devices in product application.

[0065] In an embodiment of the present application, when performing TLP characteristic test, the second test pad 32 is connected to a TLP pulse (TLPPulse) probe, the first test pad 31 is connected to a TLP ground (TLP GND) probe, and the third test pad 33 is connected to a TLP direct current bias probe with a voltage of 0V (TLP Bias=0V).

[0066] In an embodiment of the present application, the electrostatic discharge test structure is also subjected to DC electrical property test by the first test pad 31, the second test pad 32 and the third test pad 33. In the DC electrical property test, the second test pad 32 applies a voltage or a voltage sweep, the first test pad 31 applies a 0V voltage, and the third test pad 33 applies a 0V voltage. The DC electrical property test includes a DC leakage test and a breakdown voltage (BV) test.

[0067] In an embodiment of the present application, the electrostatic discharge test structure is also subjected to package HBM test by the first test pad 31, the second test pad 32 and the third test pad 33. That is, a chip containing the electrostatic discharge test structure is subjected to HBM test. In the package HBM test, the second test pad 32 is connected to an HBM pulse, and the first test pad 31 and the third test pad 33 are grounded, i.e., a voltage of 0V.

[0068] In the electrostatic discharge test method provided by the present application, the electrostatic discharge test structure is subjected to TLP property test by the first test pad 31, the second test pad 32 and the third test pad 33, so that the effective pulse current It2 within the effective window of the electrostatic discharge protection device can be accurately measured, the test hardware is not excessively relied on, the shortcomings in the industry are made up, the influence of the parasitic internal resistance of a machine or the like is avoided, and calculation is not needed.

[0069] Further, the packaged electrostatic discharge test structure can be directly verified for electrostatic discharge performance within the effective window by using an HBM machine.

[0070] In the present embodiment, the first test pad 31 and the second test pad 32 are used to perform TLP test on the electrostatic discharge protection device 10, and the electrostatic discharge protection device 10 is, for example, a 12V ESD PNP. Figure 7 FIG. 2 is a TLP IV curve diagram of the electrostatic discharge protection device 10 in the present embodiment. In the present test, the TLP property reflects the characteristics of the 12V ESD PNP, and the TLP failure object is the breakdown failure of the 12V ESD PNP.

[0071] The third test pad 33 and the second test pad 32 are used to perform TLP test on the protected device 20, and the protected device 20 is, for example, a 12V NLDMOS. Figure 8 FIG. 3 is a TLP IV curve diagram of the protected device 20 in the present embodiment. In the present test, the TLP property reflects the characteristics of the 12V NLDMOS, and the TLP failure object is the breakdown failure of the 12V NLDMOS.

[0072] The TLP test is performed on the electrostatic discharge device 10 (i.e. electrostatic discharge test structure) such as 12V ESD PNP and the protected device 20 such as 12V NLDMOS by the first test pad 31, the second test pad 32 and the third test pad 33. Figure 9 The TLP IV curve is provided when the electrostatic discharge test structure is tested. In this test, the TLP characteristic represents the characteristic of the 12V ESD PNP, and the TLP failure object is the breakdown failure of the 12V NLDMOS. Figure 9 At the intersection of the two curves in the figure (indicated by the box), the protected device is burned out, and the corresponding pulse current at this point is the effective pulse current It2.

[0073] Comparison Figures 7 to 9 It can be seen that the test on the electrostatic discharge protection device 10 alone can obtain the characteristic and secondary breakdown current It2 of the ESD PNP, the effective pulse current It2 is obtained by estimation, the test on the protected device alone can obtain the characteristic and secondary breakdown current It2 of the NLDMOS. The test on the electrostatic discharge test structure can obtain the characteristic and secondary breakdown current It2 of the ESD PNP, and the effective pulse current It2 is obtained by actual measurement.

[0074] In summary, in the electrostatic discharge test structure, test method and chip provided by the present application, the electrostatic discharge test structure includes an electrostatic discharge protection device and a protected device, the positive electrode of the electrostatic discharge protection device and the positive electrode of the protected device are commonly connected to the second test pad, the negative electrode of the electrostatic discharge protection device is connected to the first test pad, and the negative electrode of the protected device is connected to the third test pad. The positive electrode of the electrostatic discharge protection device and the positive electrode of the protected device share a test pad, which is coupled to the test pad, thereby reducing the layout area of the electrostatic discharge test structure. At the same time, the first test pad, the second test pad and the third test pad are used to perform TLP characteristic test on the electrostatic discharge test structure, which can accurately measure the effective pulse current It2 within the effective window of the electrostatic discharge protection device, without over-reliance on test hardware, making up for the shortcomings of the industry, and not being affected by the parasitic resistance of the machine and other devices, and not needing to be calculated.

[0075] Further, the packaged electrostatic discharge test structure can directly verify the electrostatic discharge performance within the effective window by using the HBM machine.

[0076] In addition, compared with the conventional test structure, the electrostatic discharge test structure of the present application is matched with the protection device and the protected device, is closer to the actual application scene, can predict and verify the application risk in advance, and reduces the risk of the electrostatic discharge protection device (especially the high-voltage electrostatic discharge protection device) in the product application.

[0077] It can be understood that, generally, the secondary breakdown voltage Vt2 of the electrostatic discharge protection device is outside the electrostatic discharge effective window (i.e., Vt2>USL), but there is also a case that the secondary breakdown voltage Vt2 is within the electrostatic discharge effective window (i.e., Vt2≤USL). The present application mainly aims at the case that the secondary breakdown voltage Vt2 of the electrostatic discharge protection device is outside the electrostatic discharge effective window (i.e., Vt2>USL).

[0078] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. An electrostatic discharge test structure, characterized by, The electrostatic discharge protection device and the protected device, the positive electrode of the electrostatic discharge protection device and the positive electrode of the protected device are connected to a second test pad, the negative electrode of the electrostatic discharge protection device is connected to a first test pad, and the negative electrode of the protected device is connected to a third test pad. The high potential end of the electrostatic discharge protection device and the protected device is the positive electrode, and the low potential end is the negative electrode.

2. The electrostatic discharge test structure of claim 1, wherein, The electrostatic discharge protection device includes a bipolar junction transistor or a metal oxide semiconductor field effect transistor, and the protected device includes a metal oxide semiconductor field effect transistor.

3. The electrostatic discharge test structure of claim 1, wherein, The collector of the PNP bipolar junction transistor is the negative electrode, and the base and the emitter are the positive electrodes. The collector of the NPN bipolar junction transistor is the positive electrode, and the base and the emitter are the negative electrodes. The drain of the N-type metal oxide semiconductor field effect transistor is the positive electrode, and the source, the gate, and the body are the negative electrodes. The drain of the P-type metal oxide semiconductor field effect transistor is the negative electrode, and the source, the gate, and the body are the positive electrodes.

4. The electrostatic discharge test structure of claim 3, wherein, The Psub substrate end of the electrostatic discharge protection device and the Psub substrate end of the protected device are connected to a fourth test pad.

5. The electrostatic discharge test structure of claim 4, wherein, The electrostatic discharge test structure according to any one of claims 1 to 5.

6. A chip, characterized by The electrostatic discharge test structure according to any one of claims 1 to 5 is tested, and the testing method comprises:

7. An electrostatic discharge test method, characterized by, The first test pad, the second test pad, and the third test pad are used to perform TLP characteristic testing on the electrostatic discharge test structure. During the TLP characteristic testing, the second test pad is connected to a TLP pulse probe, the first test pad is connected to a TLP ground probe, and the third test pad is connected to a TLP DC bias probe with a voltage of 0 V.

8. The electrostatic discharge test method according to claim 7, wherein The first test pad, the second test pad, and the third test pad are also used to perform DC electrical testing on the electrostatic discharge test structure. During the DC electrical testing, the second test pad applies a voltage or a voltage scan, the first test pad applies a voltage of 0 V, and the third test pad applies a voltage of 0 V.

9. The electrostatic discharge test method according to claim 7, wherein The first test pad, the second test pad, and the third test pad are also used to perform package HBM testing on the electrostatic discharge test structure. During the package HBM testing, the second test pad is connected to an HBM pulse, and the first test pad and the third test pad are grounded.

10. The electrostatic discharge test method of claim 7, wherein, ​

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