Flash memory control method, equipment and medium
By setting a preset storage space shared by multiple channels and a timing control arbitration module in the NAND Flash controller, the problems of increased timing control complexity and storage requirements in SCA mode are solved, and the efficiency of read and write operations is improved.
Patent Information
- Application Number
- CN202511076873.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2025-11-07
AI Technical Summary
The separation of command and address transmission in SCA mode increases the complexity of timing control, leading to a sharp increase in the storage requirements of individual modules.
A preset storage space shared by multiple channels is set in the NAND Flash controller to maintain the timing control script cache for all channels. The target timing instruction request is arbitrated through the multi-channel timing control arbitration module, avoiding the storage of timing instructions in each channel and realizing read and write operations.
This reduces the hardware overhead of independently configuring storage units for each channel, improves the response speed of read and write commands, and makes SCA mode more efficient.
Smart Images
Figure CN120909520A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of storage, in particular to a flash memory control method, device and medium. BACKGROUND
[0002] With the progress of NAND Flash technology, its traditional structure and Input / Output (IO) interface gradually become the bottleneck of improving IO utilization. To cope with this challenge, the Separate Command and Address (SCA) mode emerges as the times require.
[0003] However, the uniqueness of this new mode of command and address separation transmission makes the traditional timing control script extremely complex. In order to meet the precise timing requirements, each timing control module needs to store a large number of detailed instructions, resulting in a sharp increase in the storage demand of a single module.
[0004] In view of the above, how to solve the problem that the command and address separation transmission of the SCA mode increases the complexity of timing control and improves the storage demand of a single module is a problem that technicians in this field need to solve urgently. SUMMARY
[0005] The present application provides a flash memory control method, device and medium to at least solve the problem that the command and address separation transmission of the SCA mode increases the complexity of timing control and improves the storage demand of a single module.
[0006] The present application provides a flash memory control method applied to a target channel of a flash memory controller; wherein the flash memory controller comprises a plurality of channels, each channel having a corresponding flash memory; the target channel corresponds to a target flash memory; the method comprises:
[0007] When a read-write command sent by firmware is received through a read-write command interface, the read-write command is parsed and a corresponding target timing instruction request is generated;
[0008] The target timing instruction request is sent to a multi-channel timing control arbitration module, so that the multi-channel timing control arbitration module arbitrates and responds to the timing instruction request of each channel;
[0009] When the target timing instruction request is responded by arbitration, the target timing instruction corresponding to the read-write command in the preset storage space is obtained according to the target timing instruction request; wherein the preset storage space contains the timing control script cache corresponding to each channel;
[0010] According to the target timing instruction, the read-write operation on the target flash memory is performed.
[0011] The application further provides an electronic device, comprising a memory for storing a computer program and a processor for executing the computer program to implement the steps of any of the flash memory control methods.
[0012] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of any of the flash memory control methods.
[0013] The application has the advantages that a plurality of preset storage spaces shared by the channels are arranged outside the channels in the NAND flash controller, which are used to maintain the timing control script cache of all the channels, thereby avoiding the storage of the timing instructions in the timing control modules in the channels and greatly relieving the storage pressure of the channels; when a target channel receives a read / write command, the read / write command is analyzed and the corresponding target timing instruction request is generated, after the target timing instruction request is responded through arbitration, the corresponding target timing instruction is obtained in the preset storage space according to the target timing instruction request, and the read / write operation on the target flash memory is performed based on the instruction, which not only reduces the hardware overhead caused by the independent configuration of the storage units of the channels, but also improves the response speed of the read / write command, so that the SCA mode has higher operation efficiency.
[0014] In addition, the application further provides a flash memory control device and medium, which have the same effects. BRIEF DESCRIPTION OF DRAWINGS
[0015] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.
[0016] Figure 1 The figure shows the interface between the flash controller in the traditional mode and the NAND flash memory provided by the embodiments of the application.
[0017] Figure 2 The figure shows the interface between the flash controller in the SCA mode and the NAND flash memory provided by the embodiments of the application.
[0018] Figure 3 The figure shows a NAND flash controller shared by multiple channels provided by the embodiments of the application.
[0019] Figure 4 The figure shows a flowchart of a flash memory control method provided by the embodiments of the application.
[0020] Figure 5 A schematic diagram of a timing control module based on an SCA mode is provided for an embodiment of the present application.
[0021] Figure 6 A schematic diagram of a flash control device is provided for an embodiment of the present application. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0023] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.
[0024] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.
[0025] As a kind of large capacity, non-volatile memory, NAND Flash memory is gradually replacing traditional magnetic disk, and becomes the preferred solution of high-performance storage environment such as data center, with its high-speed read-write characteristics. The structure of NAND Flash memory is composed of multiple levels: logical unit number (LUN) is the basic unit of independent execution command, each LUN contains multiple planes (Plane);Block (Block) is the basic unit of erase operation, each Plane contains multiple Blocks;And page (Page) is the basic unit of read-write operation, each Block is divided into multiple Pages.
[0026] Figure 1 The interface schematic diagram of the flash controller and the NAND Flash memory in the traditional mode is provided for an embodiment of the present application. As shown in FIG. 1, the flash controller is connected with the NAND Flash memory through the interface, and the interface is composed of the following parts: command interface, data interface, address interface and control interface. Figure 1As shown, the traditional NAND Flash IO interface usually includes the following signals: ChipEnable Not (CE_N), Command Latch Enable (CLE), Address Latch Enable (ALE), Write Enable Not (WE_N), Read Enable Not (RE_N), Data Strobe Signal (DQS), Data Bus (DQ) and Write Protect (WP). In the traditional mode, both the Command and the Address are transmitted through the DQ bus. However, with the development of NAND Flash technology, this way gradually becomes a bottleneck for improving the IO utilization. To solve this problem, the SCA mode emerges as the times require.
[0027] Figure 2 The Flash controller and the NAND Flash memory interface in the SCA mode provided by the embodiment of the present application are shown in the following figure. Figure 2 As shown, in the SCA mode, the ALE and CLE signals are redefined as the command / address line 0 (CA[0]) and the command / address line 1 (CA[1]), which together constitute the Command Address (CA) bus, which is specially used for the transmission of the command. The WP signal is converted into the clock signal (CLK), which is used as the clock signal of the CA bus, to ensure the synchronization and accuracy of the command transmission. The transmission of the read / write data is still performed through the DQ bus.
[0028] However, the uniqueness of the new mode of the SCA mode, which separates the transmission of the command and the address, makes the traditional timing control script extremely complex. Each timing control module needs to store a large number of detailed instructions to meet the precise timing requirements, resulting in a sharp increase in the storage demand of a single module. Therefore, in order to solve the above problems, the present application provides a flash control method. It should be noted that the method provided by the present application is applied to a target channel in a multi-channel shared NAND Flash controller. It can be understood that the target channel is any one of all channels.
[0029] Figure 3 The schematic diagram of a multi-channel shared NAND Flash controller provided by the embodiment of the present application is shown in the following figure. Figure 3As shown in the figure, the flash controller includes multiple channels, each of which has a corresponding flash memory; the target channel corresponds to the target flash memory. Meanwhile, the controller also includes a timing instruction cache control module and a multi-channel timing control arbitration module, and each channel includes a corresponding command data processing module and a timing control module. The operation mode of each module will be described in detail below in combination with the flash control method.
[0030] Figure 4 A flow chart of a flash control method provided by an embodiment of the present application is shown in the figure. As shown in the figure, the method includes the following steps. Figure 4
[0031] S10: When a read-write command sent by the firmware is received through the read-write command interface, the read-write command is parsed and a corresponding target timing instruction request is generated.
[0032] First, for the target channel, the read-write command sent by the processor firmware is received through the corresponding read-write command interface. It can be understood that the read-write command can be a read command or a write command. The type of firmware and the type of read-write command are not limited in this embodiment.
[0033] When the read-write command sent by the firmware is received, the read-write command is parsed and a corresponding target timing instruction request is generated to request the corresponding timing for executing the read-write command. It should be noted that the specific process of parsing the read-write command and generating the corresponding target timing instruction request is not limited in this embodiment, but is determined according to the specific implementation.
[0034] S11: The target timing instruction request is sent to the multi-channel timing control arbitration module, so that the multi-channel timing control arbitration module arbitrates and responds to the timing instruction request of each channel.
[0035] The multi-channel timing control arbitration module is an arbitrator shared by each channel in the NAND Flash controller, which is used to determine which channel's request to respond by polling arbitration. It should be noted that each channel in the NAND Flash controller has a corresponding priority; after arbitration is completed, the priority of each channel will not change.
[0036] It should be noted that the polling arbitration process of the multi-channel timing control arbitration module can adopt the following two ways: one is to strictly arbitrate according to the channel priority order, when a channel completes arbitration response, if the channel arbitrated has no new request, the next channel can be polled; if the channel arbitrated has a new request, the channel is continued to be responded to, to ensure the continuity of the command of each channel. Two is to take the priority order as the initial order arbitration, when a channel completes arbitration, it is placed at the last position of all channels, and the next channel is arbitrated and responded to, so that the command of each channel can be executed. It should be noted that the arbitration response mode adopted by the multi-channel timing control arbitration module in the embodiment is not limited, and is determined according to the specific implementation.
[0037] Therefore, in the embodiment, after obtaining the target timing instruction request, the target timing instruction request needs to be sent to the multi-channel timing control arbitration module, and the timing instruction request of each channel is arbitrated and responded to by the multi-channel timing control arbitration module.
[0038] S12: When the target timing instruction request is arbitrated and responded to, the target timing instruction corresponding to the read-write command in the preset storage space is obtained according to the target timing instruction request.
[0039] The preset storage space includes the timing control script cache corresponding to each channel.
[0040] When the target timing instruction request is arbitrated and responded to, it means that the number of times can process the read-write instruction of the target channel. The target timing instruction corresponding to the read-write command in the preset storage space is obtained according to the target timing instruction request.
[0041] It should be noted that the preset storage space is a storage space in the timing instruction cache control module, which stores instructions for implementing SCA mode timing and commands (i.e. timing control script cache corresponding to each channel). The instructions can be generated by python script or other ways, which are not limited in the embodiment. At the same time, the timing instruction cache control module is provided with an instruction loading interface, and the firmware loads the generated instructions for implementing SCA mode timing and commands into the module through the interface during the initialization process. The specific process of obtaining the target timing instruction corresponding to the read-write command in the preset storage space according to the target timing instruction request is not limited in the embodiment, and is determined according to the specific implementation.
[0042] S13: The read-write operation of the target flash memory is performed according to the target timing instruction.
[0043] Finally, after obtaining the target timing instruction corresponding to the read-write command, the read-write operation on the target flash memory is performed according to the target timing instruction, the read-write operation instruction is converted and sent by the interface conversion module through the physical layer (PHY), and the NAND IO timing and command are converted from the Data Flow Interface (DFI) signal instruction, so as to ensure the effective communication between the system and the NAND flash memory. It should be noted that the specific process of performing the read-write operation is not limited in the embodiment.
[0044] In the embodiment, a plurality of preset storage spaces shared by the channels are set outside each channel in the NAND Flash controller, which are used to maintain the timing control script cache of all channels, thereby avoiding storing the timing instructions in the timing control module in each channel, greatly relieving the storage pressure of each channel; when the target channel receives the read-write command, the read-write command is parsed and the corresponding target timing instruction request is generated, after the target timing instruction request is responded through arbitration, the corresponding target timing instruction is only obtained in the preset storage space according to the target timing instruction request, and the read-write operation on the target flash memory can be performed based on the instruction, which not only reduces the hardware overhead caused by the independent configuration of the storage unit of each channel, but also improves the response speed of the read-write command, so that the SCA mode has higher running efficiency.
[0045] On the basis of the above embodiment, in some embodiments, when the read-write command sent by the firmware is received through the read-write command interface, before the read-write command is parsed and the corresponding target timing instruction request is generated, the following steps are further included:
[0046] S101: It is judged whether the read-write command does not exist in the read-write data stage or the corresponding execution time is less than a preset time value; if yes, step S102 is entered; if no, step S103 is entered.
[0047] S102: The read-write command is stored in the first priority queue.
[0048] S103: The read-write command is stored in the second priority queue.
[0049] The priority of the first priority queue is higher than the priority of the second priority queue.
[0050] In order to store the read-write command for parsing, the read-write command is stored by the command data processing module. As shown in Figure 3 It is judged whether the read-write command does not exist in the read-write data stage or the corresponding execution time is less than a preset time value. It should be noted that the size of the preset time value is not limited in the embodiment, which is determined according to the specific implementation condition.
[0051] If it is confirmed that the read-write command does not have a read-write data stage, or the corresponding execution time is less than the preset time value, the read-write command is stored in the first priority queue; if it is confirmed that the read-write command has a read-write data stage, and the corresponding execution time is less than the preset time value, the read-write command is stored in the second priority queue. It should be noted that the priority of the first priority queue is higher than the priority of the second priority queue, so that the subsequent module processes the command according to the priority order. After the read-write command is classified by the command data processing module, the read-write command is transmitted to the timing control module. It can be understood that the first priority queue and the second priority queue are both first in, first out (FIFO) queues.
[0052] In the embodiment, the read-write command is classified and stored by the command data processing module, so that the subsequent module processes the command according to the priority order, and the processing efficiency is improved.
[0053] Figure 5 A schematic diagram of a timing control module based on an SCA mode is provided for the embodiment of the application. As shown in the figure, the timing control parameter configuration module can provide flexible configuration functions for the timing control module through an advanced peripheral bus (APB) interface, and support key parameter configuration of the SCA mode. Figure 5
[0054] At the same time, the prefetch control module is a module responsible for prefetching timing instructions in the SCA mode, and can extract read-write commands from the first priority queue or the second priority queue according to the LUN address and the command type of the command being executed fed back by the instruction execution module, optimize the instruction prefetching process, and improve the running efficiency of the system in the SCA mode.
[0055] It should be further noted that in the SCA mode, the NAND Flash is divided into a CA bus and a DQ bus, so that the timing instructions of a command are cached in different queues of the instruction execution module according to different situations. When the instruction execution module detects that the corresponding queue is not empty, the execution process of the timing instructions will be started immediately; when the instructions of a new command are started to be executed, the instruction execution module will immediately pull up the prefetch request signal pre_cmd_req, and at the same time, update the LUN address of the command currently using the DQ bus to transmit data in real time, and feed back to the prefetch control module.
[0056] Therefore, on the basis of the above-mentioned embodiments, in some embodiments, the read-write command is parsed and the corresponding target timing instruction request is generated, which comprises:
[0057] S111: Determine whether there is a timing instruction being executed in the current channel. If not, go to step S112; if yes, go to step S113.
[0058] S112: Obtain and parse the read-write command in the first priority queue to generate a corresponding target timing instruction request.
[0059] S113: Obtain the first logical unit number address of the timing instruction being executed, and obtain the second logical unit number address and command type of the command in the first priority queue.
[0060] S114: According to the first logical unit number address, the second logical unit number address and the command type, obtain the read-write command in the first priority queue or the second priority queue, and generate a corresponding target timing instruction request.
[0061] In order to accurately generate the target timing instruction request corresponding to the read-write command, in the specific implementation, the prefetch control module determines whether there is a timing instruction being executed in the current channel. If it is confirmed that there is no timing instruction being executed in the current channel, it means that the current read-write command is the only command that needs to be processed at present, and the read-write command will only be stored in the first priority queue. Therefore, the read-write command in the first priority queue is obtained and parsed, and a corresponding target timing instruction request is generated.
[0062] If it is confirmed that there is a timing instruction being executed in the current channel, it means that the current read-write command is not the only command that needs to be processed at present; as known from the above embodiment, the current read-write command may be stored in the first priority queue or the second priority queue. Therefore, the first logical unit number address of the timing instruction being executed is obtained, and the second logical unit number address and the command type of the command in the first priority queue are obtained. According to the first logical unit number address, the second logical unit number address and the command type, the read-write command in the first priority queue or the second priority queue is obtained, and a corresponding target timing instruction request is generated.
[0063] In this way, the prefetch control module realizes the advance preprocessing of the read-write command, and tries to ensure that the CA BUS and the DQBus can be processed in parallel.
[0064] The specific process of obtaining the read-write command in the first priority queue or the second priority queue according to the first logical unit number address, the second logical unit number address and the command type will be described in detail below:
[0065] In some embodiments, obtaining the read-write command in the first priority queue or the second priority queue according to the first logical unit number address, the second logical unit number address and the command type includes:
[0066] S121: judging whether the first logical unit number address is same as the second logical unit number address. If not, entering step S122; if yes, entering step S123.
[0067] S122: obtaining the read-write command from the first priority queue.
[0068] S123: judging whether the command type is Non-DQ type. If yes, entering step S124; if not, entering step S125.
[0069] S124: obtaining the read-write command from the first priority queue.
[0070] S125: obtaining the read-write command from the second priority queue.
[0071] Specifically, the prefetch control module first judges whether the first logical unit number address of the time sequence instruction being executed is same as the second logical unit number address of the command in the first priority queue. If it is confirmed that the two logical unit number addresses are not same, the read-write command is obtained from the first priority queue. If it is confirmed that the two logical unit number addresses are same, it is judged whether the command type is Non-DQ type. It should be noted that Non-DQ refers to that while one LUN uses DQ bus for data transmission, some commands of the same LUN CA bus are allowed to be executed in parallel, and the Non-DQ type command is determined by the NAND Flash manufacturer.
[0072] If it is confirmed that the command type of the command in the first priority queue is Non-DQ type, the read-write command is obtained from the first priority queue. If it is confirmed that the command type of the command in the first priority queue is not Non-DQ type, the read-write command is obtained from the second priority queue. In this way, the accurate obtaining of the read-write module from the first priority queue or the second priority queue is realized.
[0073] It should be further noted that after the read-write command is obtained, the prefetch control module needs to feed back the prefetch response signal pre_cmd_ack to the instruction execution module; after the target time sequence instruction request is generated, the step of sending the target time sequence instruction request to the multi-channel time sequence control arbitration module is entered. At the same time, after the prefetch response signal pre_cmd_ack is fed back, the instruction execution module will pull down the prefetch request signal pre_cmd_req, ending the present prefetch request.
[0074] On the basis of the above embodiment, in some embodiments, obtaining the target time sequence instruction corresponding to the read-write command in the preset storage space according to the target time sequence instruction request comprises:
[0075] S131: The timing instruction cache control module acquires the initial timing instruction corresponding to the read-write command in the preset storage space according to the start address in the target timing instruction request.
[0076] S132: The start flag and the end flag are added to the initial timing instruction to generate the target timing instruction.
[0077] S133: The target timing instruction is written into the prefetch storage queue.
[0078] To acquire the target timing instruction corresponding to the read-write command, in the specific implementation, the timing instruction cache control module acquires the initial timing instruction corresponding to the read-write command in the preset storage space according to the start address in the target timing instruction request. It should be noted that the specific type of the preset storage space is not limited in this embodiment, for example, it can be a static random access memory (SRAM). Then, the timing instruction cache control module adds the start flag (start) and the end flag (end) to the initial timing instruction to generate the target timing instruction. Finally, the prefetch control module writes the target timing instruction into the prefetch storage queue, and when the last instruction of the instruction is cached (i.e., the instruction with the end flag), the arbitration request arb_req is pulled down, and the sending of the target timing instruction request to the multi-channel timing control arbitration module is stopped. It can be understood that the prefetch storage queue is also a FIFO queue.
[0079] In this way, the preset storage space in the timing instruction cache control module is used as the timing control script cache shared by each channel, which greatly reduces the hardware overhead caused by the independent storage unit of each channel, and realizes accurate reading of the timing instruction corresponding to each channel.
[0080] On the basis of the above embodiment, in some embodiments, the read-write operation on the target flash memory according to the target timing instruction includes:
[0081] S141: The target timing instruction is transferred from the prefetch storage queue to the first execution queue or the second execution queue of the instruction execution module.
[0082] S142: The instruction execution module reads the target timing instruction from the first execution queue or the second execution queue, and performs the read-write operation on the target flash memory until the end flag is read.
[0083] As Figure 5As shown, the instruction execution module has a corresponding first execution queue and a second execution queue, and the instruction execution module is configured to process the time sequence instructions in the two queues. Therefore, in order to perform the read / write operation on the target flash memory according to the target time sequence instruction, the target time sequence instruction needs to be first transferred from the prefetch storage queue to the first execution queue or the second execution queue of the instruction execution module in the embodiment, so as to realize the transfer of the target time sequence instruction from the prefetch cache area to the execution cache area and to prepare for the execution of the target time sequence instruction. It can be understood that the first execution queue and the second execution queue are both first-in-first-out queues. It should be noted that the specific process of transferring the target time sequence instruction from the prefetch storage queue to the first execution queue or the second execution queue of the instruction execution module is not limited in the embodiment and is determined according to the specific implementation.
[0084] It should be further pointed out that the instruction execution module continuously detects the time sequence instructions stored in the first execution queue and the second execution queue. When the end flag end is 1 (indicating that the current command is the last instruction) or one of the execution queues is full, the instruction execution module will pull down the ready signal micro_data_rdy, indicating that the current time sequence instruction cannot be received. Thus, the loss of the time sequence instruction and the invalidation of the read / write operation are avoided.
[0085] Further, the target time sequence instruction is read from the first execution queue or the second execution queue by the instruction execution module, and the read / write operation on the target flash memory is performed. In the execution process, the instruction execution module analyzes the target time sequence instruction in detail, and accurately controls the time sequence and data transmission operation of the NAND Flash according to the analysis result, so as to ensure that the NAND Flash can complete the read, write, erase and other operations according to the requirements of the instruction. Specifically, if the first execution queue is not empty, the instruction execution module will read the target time sequence instruction from the first execution queue and analyze it, and perform the corresponding operation according to the analysis result. If the target time sequence instruction being executed is to transmit data by the DQ bus, when the second execution queue is not empty, the instruction execution module will read the time sequence instruction from the second execution queue in parallel and analyze it, and perform the corresponding operation according to the analysis result until the end flag end is read. In this way, the requirement of parallel transmission of the CA Bus and the DQ bus in the SCA protocol is realized.
[0086] Correspondingly, on the basis of the above embodiment, in some embodiments, transferring the target time sequence instruction from the prefetch storage queue to the first execution queue or the second execution queue of the instruction execution module comprises:
[0087] S151: determining whether the ready signal is high; wherein the ready signal being high indicates that the current time sequence instruction is allowed to be received. If not, the transfer process is ended; if yes, step S152 is entered.
[0088] S152: determine whether the current instruction execution module is executing a timing instruction using the data bus; if not, proceed to step S156; if yes, proceed to step S153.
[0089] S153: determine the command type corresponding to the target timing instruction.
[0090] S154: when the command type corresponding to the target timing instruction is a non-data bus type, store the target timing instruction in the second execution queue.
[0091] S155: when the command type corresponding to the target timing instruction is a data bus type, determine whether the logical unit number address of the timing instruction currently being executed using the data bus is the same as the logical unit number address corresponding to the target timing instruction; if yes, proceed to step S156; if not, proceed to step S157.
[0092] S156: store the target timing instruction in the first execution queue.
[0093] S157: store the timing instruction related to the data bus in the target timing instruction in the first execution queue, and store the timing instruction related to the command address bus in the target timing instruction in the second execution queue.
[0094] Specifically, in order to realize the transfer of the target timing instruction from the prefetch buffer area to the execution buffer area, in the specific implementation, first determine whether the ready signal is high. It should be noted that the ready signal micro_data_rdy represents that the current new timing instruction is allowed to be received. If it is confirmed that the ready signal is not high, it means that the current new timing instruction cannot be received, and the storage process is ended. If it is confirmed that the ready signal is high, it is determined whether the current instruction execution module is executing a timing instruction using the data bus DQ bus.
[0095] If it is confirmed that the instruction execution module is not currently executing a timing instruction using the data bus DQ bus, the target timing instruction is directly stored in the first execution queue. If it is confirmed that the instruction execution module is currently executing a timing instruction using the data bus DQ bus, the command type corresponding to the target timing instruction is determined.
[0096] When the command type corresponding to the target timing instruction is a non-data bus type, i.e. Non-DQ, the target timing instruction is stored in the second execution queue. At the same time, when the first execution queue is empty, the ready signal micro_data_rdy can be pulled high. When the command type corresponding to the target timing instruction is a data bus type, it is determined whether the logical unit number address of the timing instruction currently being executed using the data bus is the same as the logical unit number address corresponding to the target timing instruction.
[0097] If it is confirmed that the logical unit number address of the timing instruction currently being executed using the data bus DQ bus is the same as the logical unit number address corresponding to the target timing instruction, the target timing instruction is stored in the first execution queue; thus, the timing instructions in the first execution queue are processed in order of storage, and the ready signal micro_data_rdy is pulled high after the currently executing timing instruction is completed.
[0098] If it is confirmed that the logical unit number address of the timing instruction currently being executed using the data bus DQ bus is not the same as the logical unit number address corresponding to the target timing instruction, the timing instruction related to the data bus DQ bus in the target timing instruction is stored in the first execution queue, and the timing instruction related to the command address bus CA bus in the target timing instruction is stored in the second execution queue. At this time, the ready signal micro_data_rdy can be pulled high only after the timing instruction related to the data bus DQ bus in the target timing instruction is completely executed and the second execution queue is empty.
[0099] In the embodiment, by classifying the timing instructions that can be executed in parallel in advance and placing them in the first execution queue and the second execution queue, and by sequentially executing the timing instructions that cannot be executed in parallel in the first execution queue, the basic condition for meeting the parallel transmission requirement of the CA Bus and the DQ Bus in the SCA protocol is met.
[0100] In specific implementation, each channel can receive read-write commands directly through a read-write command interface and can also receive data operation commands through a corresponding data operation interface. The data operation command is a simple command, such as a setfeature, a get feature, and an initialization command. The timing control parameter configuration module is configured to issue short commands. For example, in the NAND Flash initialization process, the address, data, and other information related to the command are directly configured through the APB interface, and then executed through the command control and instruction execution module, thereby simplifying the data operation command issuing process.
[0101] Therefore, on the basis of the above embodiment, in some embodiments, the method further includes:
[0102] S161: When it is detected that the prefetch request signal is high and the prefetch storage queue is empty, it is determined whether a data operation command is received through a data operation interface; wherein the high level of the prefetch request signal indicates that a new command is started to be executed. If yes, step S162 is entered; if no, the process is ended.
[0103] S162: The data operation command is sent to the multi-channel timing control arbitration module for arbitration response.
[0104] Specifically, when the pre-fetch control module detects that the pre-fetch request signal pre_cmd_req is high, and the pre-fetch storage queue is empty, it is determined whether a data operation command is received through the data operation interface. It can be understood that the pre-fetch request signal is high, which represents the start of a new command.
[0105] If yes, the pre-fetch response signal pre_cmd_ack is fed back to the instruction execution module, indicating that the pre-fetch request has been responded. At the same time, according to the data operation command, an arbitration request is sent to the multi-channel timing control arbitration module to request the timing instruction corresponding to the command. The subsequent process is the same as the content type in the above embodiment, which will not be described in this embodiment. In this way, the priority processing of the data operation command is realized, and the operation efficiency is improved.
[0106] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.
[0107] Figure 6 A schematic diagram of a flash memory control device provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the device is applied to a target channel of a flash memory controller; wherein the flash memory controller includes a plurality of channels, and each channel has a corresponding flash memory; the target channel corresponds to a target flash memory; and the device includes: Figure 6
[0108] The analysis module 10 is configured to analyze the read-write command and generate a corresponding target timing instruction request when the read-write command sent by the firmware is received through the read-write command interface;
[0109] The sending module 11 is configured to send the target timing instruction request to the multi-channel timing control arbitration module, so that the multi-channel timing control arbitration module arbitrates and responds to the timing instruction request of each channel;
[0110] The obtaining module 12 is configured to obtain the target timing instruction corresponding to the read-write command in the preset storage space according to the target timing instruction request when the target timing instruction request is responded by arbitration; wherein the preset storage space includes a timing control script cache corresponding to each channel;
[0111] The execution module 13 is configured to execute the read-write operation on the target flash memory according to the target timing instruction.
[0112] In some embodiments, the device further includes:
[0113] The first cache module is configured to determine whether the read-write command does not exist a read-write data stage or a corresponding execution time is less than a preset time value; if yes, the read-write command is stored in the first priority queue; if no, the read-write command is stored in the second priority queue; wherein the priority of the first priority queue is higher than the priority of the second priority queue.
[0114] In some embodiments, the parsing module 10 comprises:
[0115] The first determination module is configured to determine whether there is an executing timing instruction in the current channel; if no, the read-write command in the first priority queue is acquired and parsed to generate the corresponding target timing instruction request; if yes, a first logical unit number address of the executing timing instruction is acquired, and a second logical unit number address and a command type of the command in the first priority queue are acquired;
[0116] The read-write command acquisition module is configured to acquire the read-write command in the first priority queue or the second priority queue according to the first logical unit number address, the second logical unit number address and the command type, and generate the corresponding target timing instruction request.
[0117] In some embodiments, the read-write command acquisition module comprises:
[0118] The first read-write command acquisition submodule is configured to determine whether the first logical unit number address and the second logical unit number address are the same; if the logical unit number addresses are different, the read-write command is acquired from the first priority queue; if the logical unit number addresses are the same, the second read-write command acquisition submodule is triggered;
[0119] The second read-write command acquisition submodule is configured to determine whether the command type is a non-data bus type; if it is confirmed to be a non-data bus type, the read-write command is acquired from the first priority queue; if it is confirmed to be not a non-data bus type, the read-write command is acquired from the second priority queue.
[0120] In some embodiments, the acquisition module 12 comprises:
[0121] The initial timing instruction acquisition module is configured to acquire, by the timing instruction cache control module, an initial timing instruction corresponding to the read-write command in the preset storage space according to a start address in the target timing instruction request;
[0122] The adding module is configured to add a start flag bit and an end flag bit to the initial timing instruction to generate the target timing instruction.
[0123] a second cache module, configured to write the target timing instruction into a prefetch storage queue.
[0124] In some embodiments, the execution module 13 comprises:
[0125] a staging module, configured to stage the target timing instruction from the prefetch storage queue into the first execution queue or the second execution queue of the instruction execution module;
[0126] a read-write operation execution module, configured to read the target timing instruction from the first execution queue or the second execution queue by the instruction execution module, and execute the read-write operation on the target flash memory until an end flag is read;
[0127] wherein, when the first execution queue is not empty, the target timing instruction is read from the first execution queue by the instruction execution module to execute the read-write operation on the target flash memory; when the target timing instruction being executed represents data transmission through a data bus, and the second execution queue is not empty, the timing instruction is read from the second execution queue by the instruction execution module in parallel to execute the read-write operation on the target flash memory.
[0128] In some embodiments, the staging module comprises:
[0129] a second judging module, configured to judge whether a ready signal is high; wherein, when the ready signal is high, it represents that a new timing instruction is currently allowed to be received; if it is confirmed that the ready signal is not high, the staging process is ended; if it is confirmed that the ready signal is high, a third judging module is triggered;
[0130] the third judging module, configured to judge whether the instruction execution module is currently using a data bus to execute a timing instruction; if it is confirmed that the data bus is not used to execute the timing instruction, the target timing instruction is directly staged into the first execution queue; if it is confirmed that the data bus is used to execute the timing instruction, a command type corresponding to the target timing instruction is determined;
[0131] a first staging submodule, configured to stage the target timing instruction into the second execution queue when the command type corresponding to the target timing instruction is a non-data bus type;
[0132] The fourth judging module is configured to, when the command type corresponding to the target timing instruction is a data bus type, judge whether the logical unit number address of the timing instruction currently being executed by the data bus is the same as the logical unit number address corresponding to the target timing instruction; if it is confirmed that they are the same, the target timing instruction is stored in the first execution queue; if it is confirmed that they are different, the timing instruction related to the data bus in the target timing instruction is stored in the first execution queue, and the timing instruction related to the command address bus in the target timing instruction is stored in the second execution queue.
[0133] In some embodiments, further comprising:
[0134] The fifth judging module is configured to, when it is detected that the pre-fetch request signal is high and the pre-fetch storage queue is empty, judge whether a data operation command is received through a data operation interface; wherein the high pre-fetch request signal represents that a new command is started to be executed; if yes, the data operation command is sent to the multi-channel timing control arbitration module for arbitration response.
[0135] The features of the embodiments of the flash memory control device can be referred to the related descriptions of the embodiments of the flash memory control method, which will not be repeated here.
[0136] The embodiments of the present application also provide an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned flash memory control method embodiments.
[0137] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above-mentioned flash memory control method embodiments when running.
[0138] In an exemplary embodiment, the above-mentioned computer readable storage medium can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.
[0139] The embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned flash memory control method embodiments.
[0140] The embodiment of the present application further provides another computer program product, comprising a nonvolatile computer readable storage medium, the nonvolatile computer readable storage medium stores a computer program, the computer program is executed by a processor to implement the steps in any of the above flash memory control method embodiments.
[0141] Those skilled in the art will further appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, various examples have been described generally in terms of their functionality, without limitation to the corresponding description in the accompanying drawings. The description of the various examples has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the examples described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the present application. The scope of the application should be determined from the appended claims and their legal equivalents, rather than from the above description, which is given for none other than to provide a summary of the exemplary embodiments.
[0142] The above has introduced in detail the flash memory control method, device and medium provided by the present application. The principle and implementation mode of the present application are described by applying specific examples in the present text, and the above embodiment description is only for helping to understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principle of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.
Claims
1. A flash memory control method, characterized by, The application is applied to a target channel of a flash memory controller; wherein the flash memory controller comprises a plurality of channels, each channel having a corresponding flash memory; the target channel corresponds to a target flash memory; the method comprises: When a read-write command sent by firmware is received through a read-write command interface, the read-write command is parsed and a corresponding target timing instruction request is generated; The target timing instruction request is sent to a multi-channel timing control arbitration module, so that the multi-channel timing control arbitration module arbitrates and responds to the timing instruction request of each channel; When the target timing instruction request is arbitrated and responded, the target timing instruction corresponding to the read-write command in a preset storage space is obtained according to the target timing instruction request; wherein the preset storage space comprises a timing control script cache corresponding to each channel; The read-write operation on the target flash memory is performed according to the target timing instruction.
2. The flash memory control method of claim 1, wherein, When a read-write command sent by firmware is received through a read-write command interface, before the read-write command is parsed and a corresponding target timing instruction request is generated, it further comprises: Determine whether the read-write command does not exist in the read-write data stage, or the corresponding execution time is less than the preset time value; If yes, the read-write command is stored in the first priority queue; If not, the read-write command is stored in the second priority queue; Wherein, the priority of the first priority queue is higher than the priority of the second priority queue.
3. The flash memory control method of claim 2, wherein, Parsing the read-write command and generating a corresponding target timing instruction request comprises: Determine whether there is an executing timing instruction in the current channel; If not, the read-write command in the first priority queue is obtained and parsed to generate the target timing instruction request corresponding thereto; If yes, the first logical unit number address of the executing timing instruction is obtained, and the second logical unit number address and the command type of the command in the first priority queue are obtained; According to the first logical unit number address, the second logical unit number address and the command type, the read-write command is obtained in the first priority queue or the second priority queue, and the target timing instruction request corresponding thereto is generated.
4. The flash memory control method of claim 3, wherein, According to the first logical unit number address, the second logical unit number address and the command type, the read-write command is obtained in the first priority queue or the second priority queue, comprising: Determine whether the first logical unit number address and the second logical unit number address are the same; If the logical unit number addresses are different, the read-write command is obtained from the first priority queue; If the logical unit number addresses are the same, it is determined whether the command type is a non-data bus type; If it is confirmed to be a non-data bus type, the read-write command is obtained from the first priority queue; If it is confirmed to be not a non-data bus type, the read-write command is obtained from the second priority queue.
5. The flash memory control method of claim 1, wherein, According to the target timing instruction request, the target timing instruction corresponding to the read-write command in the preset storage space is obtained, comprising: The time sequence instruction cache control module acquires the initial time sequence instruction corresponding to the read-write command in the preset storage space according to the start address in the target time sequence instruction request; Start and end flag bits are added to the initial time sequence instruction to generate the target time sequence instruction; The target time sequence instruction is written into a prefetch storage queue.
6. The flash memory control method of claim 1, wherein, The read-write operation on the target flash memory is performed according to the target time sequence instruction, including: The target time sequence instruction is transferred from the prefetch storage queue to the first execution queue or the second execution queue of the instruction execution module; The instruction execution module reads the target time sequence instruction from the first execution queue or the second execution queue to perform the read-write operation on the target flash memory until the end flag bit is read; When the first execution queue is not empty, the instruction execution module reads the target time sequence instruction from the first execution queue to perform the read-write operation on the target flash memory; when the target time sequence instruction being executed represents that data is transmitted through a data bus, and the second execution queue is not empty, the instruction execution module reads the time sequence instruction from the second execution queue in parallel to perform the read-write operation on the target flash memory.
7. The flash memory control method of claim 6, wherein, The target time sequence instruction is transferred from the prefetch storage queue to the first execution queue or the second execution queue of the instruction execution module, including: It is judged whether the ready signal is high; wherein the ready signal being high represents that a new time sequence instruction is currently allowed to be received; If it is confirmed that the ready signal is not high, the transfer process is ended; If it is confirmed that the ready signal is high, it is judged whether the instruction execution module is currently using the data bus to execute the time sequence instruction; If it is confirmed that the data bus is not used to execute the time sequence instruction, the target time sequence instruction is directly transferred to the first execution queue; If it is confirmed that the data bus is used to execute the time sequence instruction, the command type corresponding to the target time sequence instruction is determined; When the command type corresponding to the target time sequence instruction is a non-data bus type, the target time sequence instruction is transferred to the second execution queue; When the command type corresponding to the target time sequence instruction is a data bus type, it is judged whether the logical unit number address of the time sequence instruction currently being executed using the data bus is the same as the logical unit number address corresponding to the target time sequence instruction; If it is confirmed that they are the same, the target time sequence instruction is transferred to the first execution queue; If it is confirmed that they are different, the time sequence instruction related to the data bus in the target time sequence instruction is transferred to the first execution queue, and the time sequence instruction related to the command address bus in the target time sequence instruction is transferred to the second execution queue.
8. The flash memory control method according to any one of claims 1 to 7, characterized by, Further comprising: When it is detected that the prefetch request signal is high and the prefetch storage queue is empty, it is judged whether a data operation command is received through a data operation interface; wherein the prefetch request signal being high represents that a new command is started to be executed; If yes, the data operation command is sent to the multi-channel time sequence control arbitration module for arbitration response.
9. An electronic device, comprising: It includes: A memory for storing a computer program; A processor for implementing the steps of the flash memory control method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, A computer readable storage medium having stored therein a computer program, wherein the computer program, when executed by a processor, implements the steps of the flash memory control method according to any one of claims 1 to 7.