Task scheduling method, system and device of data stream processor and storage medium

Abstract

The application relates to the technical field of task scheduling, and discloses a task scheduling method, system and device of a data flow processor and a storage medium. A host end uses a heterogeneous computing framework, and the total amount of computing resources of a device end does not need to be considered during compilation. Resource allocation is automatically allocated by a flow control core of the data flow processor, and the scale of a computing task is not restricted by the resource configuration of hardware. The C flow control core can analyze a DAG task graph and time-divisionally distribute the computing task to a computing node. The DAG task graph can simultaneously process multiple computing tasks, improve the parallel execution capability of the data flow processor, and further improve the processing efficiency of the data flow processor, thereby solving the problem of low overall computing resource utilization of the data flow processor in the existing task scheduling scheme of the data flow processor.

Description

Technical Field

[0001] This application relates to the field of task scheduling technology, such as a task scheduling method, system, device, and storage medium for a data stream processor. Background Technology

[0002] A dataflow processor is a processor designed with a dataflow architecture. Unlike processors based on the von Neumann architecture, dataflow processors drive the computation process through the flow of data, rather than the conventional flow of instructions.

[0003] When a processor employs a dataflow architecture to execute computational tasks, the computation order is dynamically driven by data dependencies. Each computational unit executes its task immediately after the input data is ready, without the need for central controller scheduling. This architecture connects computational modules through dedicated data channels, achieving "overlapping computation and data transmission" and reducing idle waiting time. Example: After the computational unit executing the Step 1 computational task completes its execution, its output data flows directly into the dedicated computational unit for the Step 2 computational task.

[0004] Existing problems: Current dataflow processors require the compiler to determine which processing node each computation task will run on during the compilation phase, and the driver program to distribute tasks to the corresponding processing nodes. The drawback is that within a single task cycle, a computation node can only run one dataflow computation task at a time. The computation node cannot be released until the entire computation task has finished executing. The binding relationship between computation tasks and computation nodes is determined during the compilation phase and cannot be changed during the execution of the dataflow processor program.

[0005] A complex computational task may have a long Directed Acyclic Graph (DAG). While earlier nodes are executing, later processing cores remain idle, resulting in low core utilization. When multiple tasks concurrently request the use of a stream processor in the operating system, they can only be executed sequentially, one by one. The host uses a task queue to sequentially utilize the stream processor, waiting for the preceding tasks to complete before issuing the next computational task. This leads to low overall computational resource utilization of the stream processor.

[0006] In summary, existing task scheduling schemes for data stream processors suffer from low overall utilization of computing resources.

[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application. Summary of the Invention

[0008] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0009] The task scheduling method, system, device, and storage medium for data stream processors provided in this disclosure can solve the problem of low overall computing resource utilization in existing task scheduling schemes for data stream processors.

[0010] This disclosure provides a task scheduling method for a data stream processor, the method comprising:

[0011] During the programming phase of the computation task, the computation task is separated from the node coordinates, and the node coordinates are configured as execution parameters.

[0012] During the compilation phase, the compiler analyzes the dependencies and data flow relationships of each computation task, generates a DAG task scheduling graph, and each task node corresponds to an execution node in a data stream processor, and generates the virtual coordinates of the node.

[0013] During the execution phase, the host writes the kernel function bin instructions of each computing node into the data stream processor memory, writes the data structure of the DAG task scheduling graph into the data stream processor memory, and releases the PCIe bus so that other applications can concurrently write tasks to the data stream processor.

[0014] The C-flow control core of the data stream processor reads the DAG task scheduling graph in the data stream processor's memory;

[0015] The C-flow control core creates a task scheduler for each DAG task scheduling graph, and sequentially sends firmware and kernel function bin instructions to the actual computing core according to the coordinate mapping relationship of the grouped DAG task scheduling graph output by the corresponding parser.

[0016] When a computing node completes the first segment of the first group of computing tasks, it sends a completion signal to the C-flow control core. The parsing program then allocates computing cores to the second group of tasks in the DAG task scheduling graph, establishing a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the second group of tasks in the DAG task scheduling graph. The C-flow core scheduler then distributes the corresponding second group of computing tasks in the DAG task scheduling graph to the actual computing cores. The node that has completed its computing task promptly releases its resources and enters the idle node resource pool. This process continues until all computing tasks in the entire DAG task scheduling graph are completed.

[0017] This disclosure provides a task scheduling system for a data stream processor, the system comprising:

[0018] The separation module is used to separate the computation task from the node coordinates during the programming phase of the computation task, and to configure the node coordinates as execution parameters.

[0019] The compiler is used during the compilation phase to analyze the dependencies and data flow relationships of various computing tasks, generate a DAG task scheduling graph, where each task node corresponds to an execution node in a data stream processor, and generates virtual coordinates for the node.

[0020] The host is used during the execution phase to write the kernel function bin instructions of each computing node into the data stream processor memory, write the data structure of the DAG task scheduling graph into the data stream processor memory, and release the PCIe bus so that other applications can concurrently write tasks to the data stream processor.

[0021] A data stream processor is used to read the DAG task scheduling graph in the data stream processor's memory, based on the C-flow control core.

[0022] The data stream processor is also used to create a task scheduler for each DAG task scheduling graph based on the C-flow control core, and to send the corresponding grouped DAG task scheduling graph output by the parser to the actual computing core in sequence according to the coordinate mapping relationship.

[0023] The data stream processor is also used to send a completion signal to the C-flow control core when a computing node completes the first segment of the first group of computing tasks. The parser allocates computing cores to the second group of tasks in the DAG task scheduling graph and establishes a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the second group of tasks in the DAG task scheduling graph. The C-flow core scheduler sends the corresponding second group of computing tasks in the DAG task scheduling graph to the actual computing cores. The node that has completed the computing task releases its resources in a timely manner and enters the idle node resource pool. This process continues until all computing tasks in the entire DAG task scheduling graph are completed.

[0024] This disclosure provides an electronic device that includes at least one processor;

[0025] and memory that is communicatively connected to at least one processor;

[0026] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the task scheduling method of the data stream processor described above.

[0027] This disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the task scheduling method of the data stream processor described above.

[0028] The task scheduling method, system, device, and storage medium for the data stream processor provided in this disclosure can achieve the following technical effects:

[0029] In this disclosure, a heterogeneous computing framework is used on the host side. During compilation, the total computing resources on the device do not need to be considered; resource allocation is automatically handled by the flow control core of the dataflow processor. Hardware resource configuration no longer restricts the scale of computing tasks. The C flow control core can parse the DAG task graph and distribute computing tasks to computing nodes in a time-sharing manner. It can process DAG task graphs of multiple computing tasks simultaneously, improving the parallel execution capability of the dataflow processor and increasing its processing efficiency. Computational tasks are not executed sequentially; multiple computing tasks can be written to the dataflow processor concurrently, and the dataflow processor automatically allocates resources to each computing task, improving parallelism. Computation node coordinates are used as execution parameters and are not compiled as static coordinates. The binding relationship between computing tasks and computing nodes is no longer mandatory; the flow control core performs the mapping from virtual coordinates to physical coordinates, increasing the flexibility of program design. This solves the problem of low overall computing resource utilization in existing dataflow processor task scheduling schemes.

[0030] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0031] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0032] Figure 1 This is a flowchart illustrating a task scheduling method for a data stream processor provided in an embodiment of this disclosure;

[0033] Figure 2 This is a flowchart illustrating another task scheduling method for a data stream processor provided in this embodiment of the present disclosure;

[0034] Figure 3 This is a schematic diagram illustrating the specific interaction of a task scheduling method for a data stream processor provided in an embodiment of this disclosure;

[0035] Figure 4 This is a schematic diagram of a process for cyclically executing a task calculation in a DAG task scheduling graph, provided by an embodiment of this disclosure.

[0036] Figure 5 This is a schematic diagram of the architecture of a task scheduling system for a data stream processor provided in an embodiment of this disclosure;

[0037] Figure 6 This is a schematic diagram of the architecture of another data stream processor task scheduling system provided in this embodiment of the disclosure;

[0038] Figure 7 This is a schematic diagram of the structure of a task scheduling device for a data stream processor provided in an embodiment of this disclosure. Detailed Implementation

[0039] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0040] The terms "first," "second," etc., used in the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0041] Unless otherwise stated, the term "multiple" means two or more.

[0042] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0043] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0044] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0045] To address the aforementioned issues, this disclosure provides a task scheduling method, system, device, and storage medium for a data stream processor.

[0046] The task scheduling method, system, device, and storage medium of the data stream processor provided in the embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0047] Figure 1 This is a flowchart illustrating a task scheduling method for a data stream processor provided in an embodiment of this disclosure.

[0048] Combination Figure 1 As shown, the task scheduling method of the data stream processor may include:

[0049] S101, in the programming phase of the computation task, the computation task is separated from the node coordinates, and the node coordinates are configured as execution parameters.

[0050] S102, during the compilation phase, the compiler analyzes the dependencies and data flow relationships of each computation task, generates a Directed Acyclic Graph (DAG) task scheduling graph, where each task node corresponds to an execution node in a data stream processor, and generates the virtual coordinates of the node;

[0051] S103, during the execution phase, the host writes the kernel function bin instructions of each computing node into the data stream processor memory, and writes the data structure of the DAG task scheduling graph into the data stream processor memory, and releases the PCIe bus so that other applications can concurrently write tasks to the data stream processor.

[0052] S104, the C-flow control core of the data stream processor, reads the DAG task scheduling graph in the data stream processor's memory;

[0053] S105, the C-flow control core creates a task scheduler for each DAG task scheduling graph, and sends the corresponding grouped DAG task scheduling graph output by the parser to the actual computing core in sequence according to the coordinate mapping relationship;

[0054] S106: When a computing node completes the first segment of the first group of computing tasks, it sends a completion signal to the C-flow control core. The parsing program allocates computing cores to the second group of tasks in the DAG task scheduling graph and establishes a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the second group of tasks in the DAG task scheduling graph. The C-flow core scheduler sends the corresponding second group of computing tasks in the DAG task scheduling graph to the actual computing cores. The node that has completed the computing task releases its resources in a timely manner and enters the idle node resource pool. This process continues until all computing tasks in the entire DAG task scheduling graph are completed.

[0055] In some embodiments, after reading the DAG task scheduling graph in the data stream processor's memory from the C-flow control core of the data stream processor... Figure 1 The methods may also include:

[0056] A parser is assigned to each DAG task. Based on the computational data volume and complexity of the task, the parser estimates the ratio of computation time to transmission time and then segments and groups the DAG task scheduling graph according to this ratio. Each group consists of two task segments, where the ratio of estimated computation time to transmission time satisfies the formula... , computational load wi Determined by the complexity of the task. P k For the processing capacity of the target computing node, DataSize(e ij ) is edge e ij The amount of data transmitted; BandWidth is the network bandwidth between nodes (NOC).

[0057] Establish a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and allocate actual computing cores to computing tasks.

[0058] In some embodiments, the threshold determination rule can be: CTR>10: computationally intensive tasks → priority independent grouping;

[0059] CTR < 0.1: Communication-intensive tasks → Force them to be grouped with dependent tasks;

[0060] 0.1≤CTR≤10: Balanced tasks → dynamically grouped based on global dependencies.

[0061] In some embodiments, when there are three computing tasks TASK1, TASK2 and TASK3 requests on the current host, corresponding to three different DAG task scheduling graphs, the C flow control core creates a parser including DAG parser 1, DAG parser 2 and DAG parser 3.

[0062] The DAG parsing program analyzes the computational complexity, computational data volume, and data transmission time between child nodes and adjacent nodes in the DAG task scheduling graph, estimates the computation time and transmission time of each child node, and groups the DAG task scheduling graph.

[0063] In some embodiments, the mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, as described above, for allocating actual computing cores to computing tasks, includes:

[0064] The flow control core searches for computing cores in the current idle resource pool and allocates actual computing cores to the computing subtasks corresponding to the virtual coordinates. When searching for computing cores in the current idle resource pool, the flow control core considers the physical topology distance between the location of idle nodes in the pool and the computing node where the parent task resides, as well as the available bandwidth of the node's NOC network path, and defines the node matching degree Affinity(n). k ,v i ), Dist(n k parent i ) is node n k With the parent task i Physical distance of the computing node, BW avail Given the available network bandwidth, α and β are weighting factors. Then, the idle node with the highest matching degree is selected, and the physical coordinates of the idle node are mapped to the virtual coordinates of the corresponding node in the DAG task graph.

[0065] In some embodiments, the above-mentioned kernel function bin instruction is a computation instruction that the computing node in the data stream processor needs to execute, and different computing nodes correspond to different computation subtasks;

[0066] The data structure of the DAG task scheduling graph includes the virtual coordinate information of each sub-task node, the input and output data information of the sub-node, the data dependency information of each node in the DAG task scheduling graph, and the location information of the kernel function bin instruction corresponding to the sub-task in DDR memory.

[0067] Figure 2 This is a flowchart illustrating another task scheduling method for a data stream processor provided in this embodiment of the present disclosure. Figure 3 This is a schematic diagram illustrating the specific interaction of a task scheduling method for a data stream processor provided in an embodiment of this disclosure. Figure 4 This is a schematic diagram of a process for cyclically executing a computational task in a DAG task scheduling graph, provided by an embodiment of this disclosure. Figures 2 to 4 ,right Figure 1 The task scheduling method of the data stream processor in the paper will be further described.

[0068] like Figure 3 As shown, the host has three computing tasks, TASK1, TASK2, and TASK3, which require calling the data stream processor. For this scenario, the implementation of this invention includes the following steps:

[0069] Step 1: In the programming phase of the computation task, separate the computation task from the node coordinates and configure the node coordinates as execution parameters.

[0070] Step 2: During the compilation phase, the compiler analyzes the dependencies and data flow relationships of each computational task to generate a Directed Acyclic Graph (DAG). For example... Figure 3 As shown, the three computational tasks TASK1, TASK2, and TASK3 correspond to different DAG task graphs. Each subtask node in the graph corresponds to an execution node in a data stream processor, and the compiler generates virtual node coordinates for it.

[0071] Step 3: During the execution phase, the CPU host communicates with the P-core via the PCIe bus, writing the kernel function bin instructions of each computing node into the data stream processor's memory, and writing the DAG task scheduling graph data structure into the data stream processor's memory. The PCIe bus is then immediately released so that other applications can concurrently write tasks to the data stream processor.

[0072] The kernel function bin instruction is the computation instruction that the computing nodes in the data stream processor need to execute. Different computing nodes correspond to different computational subtasks. The data structure of the DAG task graph includes: virtual coordinate information of each subtask node, input and output data information of the sub-nodes, data dependency information of each node in the DAG task graph, and the location information of the kernel function bin instruction corresponding to the subtask in DDR memory.

[0073] Step 4: The C-flow control core of the data stream processor reads the DAG task graph data from the data stream processor's memory. A parser is assigned to each DAG task. The parser estimates the computation and transmission times based on the amount of computational data and computational complexity of the task, and segments and groups the DAG task graph into two segments per group (this can be adjusted). A mapping relationship is established between the actual physical coordinates of idle nodes and the virtual coordinates of the first group of tasks in the DAG graph, allocating actual computational cores to the computational subtasks.

[0074] For example, if there are three computational tasks TASK1, TASK2, and TASK3 on the host, corresponding to three different DAG task graphs, the C flow control core will create three different parsers: DAG parser 1, DAG parser 2, and DAG parser 3.

[0075] The DAG parsing program analyzes information such as the computational complexity, computational data volume, and data transmission time between child nodes and adjacent nodes in the DAG task graph, estimates the computation time and transmission time of each child node, and groups the DAG task graph as shown in Tables 1 to 3.

[0076] Table 1

[0077]

[0078] Table 2

[0079]

[0080] Table 3

[0081]

[0082] Establishing the mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the first group of tasks in the DAG graph is the process by which the flow control kernel searches for computing cores in the current idle resource pool and allocates actual computing cores to the computing subtasks corresponding to the virtual coordinates, as shown in Tables 4 to 6.

[0083] Table 4

[0084]

[0085] Table 5

[0086]

[0087] Table 6

[0088]

[0089] Step 5: The C-flow control core creates a task scheduler for each DAG task graph, and sequentially sends firmware and kernel function bin instructions to the actual computing core according to the coordinate mapping relationship of the grouped DAG task graphs output by each parser.

[0090] As described in step 4, the current host has three computing task requests, TASK1, TASK2, and TASK3, corresponding to three different DAG task graphs. The C-flow control core will create three different schedulers: DAG scheduler 1, DAG scheduler 2, and DAG scheduler 3.

[0091] Based on the mapping relationship between the virtual coordinates of the first set of task nodes and the actual computing core coordinates determined in step 4, the DAG scheduler sends the firmware of the computing core and the bin instructions of the kernel function to the actual computing core.

[0092] Step 6: As Figure 4 As shown, when a computing node completes the first segment of the first group of computational tasks, it sends a completion signal to the C-flow control core. The parsing program then allocates computing cores to the second group of tasks in the DAG graph, establishing a mapping between the actual physical coordinates of idle nodes and the virtual coordinates of the second group of tasks in the DAG graph. The C-core scheduler then distributes the corresponding second group of computational tasks in the DAG graph to the actual computing cores. Nodes that have completed their computational tasks promptly release their resources and enter the idle node resource pool. This process continues until all computational tasks in the entire DAG graph are completed.

[0093] The task scheduling method of the dataflow processor disclosed herein uses a heterogeneous computing framework on the host side. During compilation, the total amount of computing resources on the device side does not need to be considered; resource allocation is automatically handled by the flow control core of the dataflow processor. Hardware resource configuration no longer restricts the scale of computing tasks. The C flow control core can parse the DAG task graph and distribute computing tasks to computing nodes in a time-sharing manner. It can process DAG task graphs of multiple computing tasks simultaneously, improving the parallel execution capability of the dataflow processor and thus its processing efficiency. Computational tasks are not executed sequentially; multiple computing tasks can be written to the dataflow processor concurrently, and the dataflow processor automatically allocates resources to each computing task, improving parallelism. Computational node coordinates are used as execution parameters and are not compiled as static coordinates. The binding relationship between computing tasks and computing nodes is no longer mandatory; the flow control core performs the mapping from virtual coordinates to physical coordinates, increasing the flexibility of program design.

[0094] Figure 5 This is a schematic diagram of the architecture of a task scheduling system for a data stream processor provided in an embodiment of this disclosure. Figure 5 As shown, the system mainly includes a host-side CPU, a device-side data stream processor, and a device-side DDR memory.

[0095] The processing cores of a data stream processor are divided into several types based on their functions, including flow control cores, computation cores, memory access cores, and host communication cores.

[0096] Computational kernel (T): Its function is to perform specific computational tasks.

[0097] Flow Control Core (C): Its function is to monitor the status of the computing cores through the on-chip NoC network of the dataflow processor, identify and parse the DAG task graph in DDR, and issue the corresponding bin instructions for each task to the idle nodes. It is responsible for the management and allocation of idle nodes.

[0098] Memory access core (M): Its function is to receive memory access requests from other cores in the NoC network and perform read and write access to DDR memory.

[0099] Host Communication Core (P): Its function is to communicate with the host through the PCIe bus, parse the data read and write requests from the host, and forward them to the corresponding nodes in the NoC network.

[0100] and Figure 1 Corresponding to the flowchart of the task scheduling method for a data stream processor, this disclosure also provides a task scheduling system for a data stream processor, combined with... Figure 5 ,right Figure 6 Further describing the system shown, the task scheduling system of the data stream processor may include:

[0101] Separation module 601 is used to separate the computation task from the node coordinates during the programming phase of the computation task, and to configure the node coordinates as execution parameters.

[0102] Compiler 602 is used to analyze the dependencies and data flow relationships of various computing tasks during the compilation phase, generate a DAG task scheduling graph, with each task node corresponding to an execution node in a data stream processor, and generate virtual coordinates of the nodes;

[0103] The host 603 is used to write the kernel function bin instructions of each computing node into the memory of the data stream processor during the execution phase, and to write the data structure of the DAG task scheduling graph into the memory of the data stream processor, and to release the PCIe bus so that other applications can concurrently write tasks to the data stream processor.

[0104] The data stream processor 604 is used to read the DAG task scheduling graph in the memory of the data stream processor based on the C-flow control core.

[0105] The data stream processor 604 is also used to create a task scheduler for each DAG task scheduling graph based on the C-flow control core, and to send the firmware and kernel function bin instructions to the actual computing core in sequence according to the coordinate mapping relationship of the grouped DAG task scheduling graph output by the corresponding parser.

[0106] The data stream processor 604 is also used to send a completion signal to the C-flow control core when the computing node completes the first segment of the first group of computing tasks. The parser allocates computing cores to the second group of tasks in the DAG task scheduling graph and establishes a mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the second group of tasks in the DAG task scheduling graph. The C-flow core scheduler sends the corresponding second group of computing tasks in the DAG task scheduling graph to the actual computing cores. The node that has completed the computing task releases its resources in a timely manner and enters the idle node resource pool. This process continues until all computing tasks in the entire DAG task scheduling graph are completed.

[0107] In some embodiments, the data stream processor 604 is further configured to, after reading the DAG task scheduling graph in the data stream processor memory, allocate a parser to each DAG task. The parser estimates the ratio of computation time to transmission time based on the computational data volume and computational complexity of the task, and segments and groups the DAG task scheduling graph according to the ratio, with each group consisting of two task segments. The ratio of the estimated computation time to transmission time satisfies the formula... , computational load wi Determined by the complexity of the task. P k For the processing capacity of the target computing node, DataSize(eij ) is edge e ij The amount of data transmitted; BandWidth is the network bandwidth between nodes (NOC).

[0108] Establish a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and allocate actual computing cores to computing tasks.

[0109] In some embodiments, when there are three computing tasks TASK1, TASK2, and TASK3 requests on the current host, corresponding to three different DAG task scheduling graphs, the C-flow control core will create three different parsers: DAG parser 1, DAG parser 2, and DAG parser 3.

[0110] The DAG parser analyzes information such as the computational complexity, computational data volume, and data transmission time between child nodes and adjacent nodes in the DAG task graph, estimates the computation time and transmission time of each child node, and groups the DAG task scheduling graph.

[0111] In some embodiments, the mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, as described above, for allocating actual computing cores to computing tasks, includes:

[0112] The flow control core searches for computing cores in the current idle resource pool and allocates actual computing cores to the computing subtasks corresponding to the virtual coordinates. When searching for computing cores in the current idle resource pool, the flow control core considers the physical topology distance between the location of idle nodes in the pool and the computing node where the parent task resides, as well as the available bandwidth of the node's NOC network path, and defines the node matching degree Affinity(n). k ,v i ), Dist(n k parent i ) is node n k With the parent task i Physical distance of the computing node, BW avail Given the available network bandwidth, α and β are weighting factors. Then, the idle node with the highest matching degree is selected, and the physical coordinates of the idle node are mapped to the virtual coordinates of the corresponding node in the DAG task graph.

[0113] In some embodiments, the above-mentioned kernel function bin instruction is a computation instruction that the computing node in the data stream processor needs to execute, and different computing nodes correspond to different computation subtasks;

[0114] The data structure of the DAG task scheduling graph includes the virtual coordinate information of each sub-task node, the input and output data information of the sub-node, the data dependency information of each node in the DAG task scheduling graph, and the location information of the kernel function bin instruction corresponding to the sub-task in DDR memory.

[0115] Combination Figure 7 As shown in the illustration, this disclosure also provides a task scheduling device 700 for a data stream processor, including a processor 704 and a memory 701. Optionally, the system may further include a communication interface 702 and a bus 703. The processor 704, communication interface 702, and memory 701 can communicate with each other via the bus 703. The communication interface 702 can be used for information transmission. The processor 704 can call logical instructions in the memory 701 to execute the task scheduling method of the data stream processor described in the above embodiment.

[0116] Furthermore, the logic instructions in the aforementioned memory 701 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0117] The memory 701, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 704 executes functional applications and data processing by running the program instructions / modules stored in the memory 701, that is, it implements the task scheduling method of the data stream processor in the above embodiments.

[0118] The memory 701 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 701 may include high-speed random access memory and may also include non-volatile memory.

[0119] This disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured as a task scheduling method for a data stream processor.

[0120] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0121] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0122] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes the element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0123] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0124] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0126] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0127] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0128] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0129] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0130] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0131] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0132] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0133] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A task scheduling method for a data stream processor, characterized in that, The method includes; During the programming phase of the computation task, the computation task is separated from the node coordinates, and the node coordinates are configured as execution parameters. During the compilation phase, the compiler analyzes the dependencies and data flow relationships of each computation task, generates a DAG task scheduling graph, and each task node corresponds to an execution node in a data stream processor, and generates the virtual coordinates of the node. During the execution phase, the host writes the kernel function bin instructions of each computing node into the data stream processor memory, writes the data structure of the DAG task scheduling graph into the data stream processor memory, and releases the PCIe bus so that other applications can concurrently write tasks to the data stream processor. The C-flow control core of the data stream processor reads the DAG task scheduling graph in the data stream processor's memory; The C-flow control core creates a task scheduler for each DAG task scheduling graph, and sequentially sends firmware and kernel function bin instructions to the actual computing core according to the coordinate mapping relationship of the grouped DAG task scheduling graph output by the corresponding parser. When the computing node completes the first segment of the computing task in the first group, it sends a completion signal to the C-flow control core. The parsing program allocates computing cores to the second group of tasks in the DAG task scheduling graph and establishes a mapping relationship between the actual physical coordinates of the idle node and the virtual coordinates of the second group of tasks in the DAG task scheduling graph. The C-flow core scheduler distributes the second group of computation tasks in the corresponding DAG task scheduling graph to the actual computation core; the node that has completed the computation task releases its resources in a timely manner and enters the idle node resource pool, and so on, until all computation tasks in the entire DAG task scheduling graph are completed.

2. The method according to claim 1, characterized in that, After reading the DAG task scheduling graph in the data stream processor's memory within the C-flow control core of the data stream processor, the method further includes: A parser is assigned to each DAG task. Based on the computational data volume and complexity of the task, the parser estimates the ratio of computation time to transmission time. Then, based on this ratio, the DAG task scheduling graph is segmented and grouped into two task segments per group. The ratio of the estimated computation time to transmission time satisfies the formula... , computational load wi Determined by the complexity of the task. P k For the processing capacity of the target computing node, DataSize(e ij ) is edge e ij The amount of data transmitted; BandWidth is the network bandwidth between nodes (NOC). Establish a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and allocate actual computing cores to computing tasks.

3. The method according to claim 2, characterized in that, When there are three computing tasks TASK1, TASK2 and TASK3 requests on the current host, corresponding to three different DAG task scheduling graphs, the C flow control core creates parsers including DAG parser 1, DAG parser 2 and DAG parser 3. The DAG parsing program analyzes the computational complexity, computational data volume, and data transmission time between child nodes and adjacent nodes in the DAG task scheduling graph, estimates the computation time and transmission time of each child node, and groups the DAG task scheduling graph.

4. The method according to claim 2, characterized in that, The establishment of the mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and the allocation of actual computing cores for computing tasks, includes: The flow control core searches for computing cores in the current idle resource pool and allocates actual computing cores to the computing subtasks corresponding to the virtual coordinates. When searching for computing cores in the current idle resource pool, the flow control core considers the physical topology distance between the location of idle nodes in the pool and the computing node where the parent task resides, as well as the available bandwidth of the node's NOC network path, and defines the node matching degree Affinity(n). k ,v i ), Dist(n k parent i ) is node n k With the parent task i Physical distance of the computing node, BW avail Given the available network bandwidth, α and β are weighting factors. Then, the idle node with the highest matching degree is selected, and the physical coordinates of the idle node are mapped to the virtual coordinates of the corresponding node in the DAG task graph.

5. The method according to claim 1, characterized in that, The kernel function bin instruction is the computation instruction that the computing nodes in the data stream processor need to execute. Different computing nodes correspond to different computation subtasks. The data structure of the DAG task scheduling graph includes the virtual coordinate information of each sub-task node, the input and output data information of the sub-node, the data dependency information of each node in the DAG task scheduling graph, and the location information of the kernel function bin instruction corresponding to the sub-task in DDR memory.

6. A task scheduling system for a data stream processor, characterized in that, The system includes; The separation module is used to separate the computation task from the node coordinates during the programming phase of the computation task, and to configure the node coordinates as execution parameters. The compiler is used during the compilation phase to analyze the dependencies and data flow relationships of various computing tasks, generate a DAG task scheduling graph, where each task node corresponds to an execution node in a data stream processor, and generates virtual coordinates for the node. The host is used during the execution phase to write the kernel function bin instructions of each computing node into the data stream processor memory, write the data structure of the DAG task scheduling graph into the data stream processor memory, and release the PCIe bus so that other applications can concurrently write tasks to the data stream processor. A data stream processor is used to read the DAG task scheduling graph in the data stream processor's memory, based on the C-flow control core. The data stream processor is also used to create a task scheduler for each DAG task scheduling graph based on the C-flow control core, and to send the firmware and kernel function bin instructions to the actual computing core in sequence according to the coordinate mapping relationship of the grouped DAG task scheduling graph output by the corresponding parser. The data stream processor is also used to send a completion signal to the C-flow control core when the computing node completes the first segment of the computing task in the first group, and to allocate computing cores to the second group of tasks in the DAG task scheduling graph by the parsing program, and to establish a mapping relationship between the actual physical coordinates of the idle node and the virtual coordinates of the second group of tasks in the DAG task scheduling graph. The C-flow core scheduler distributes the second group of computation tasks in the corresponding DAG task scheduling graph to the actual computation core; the node that has completed the computation task releases its resources in a timely manner and enters the idle node resource pool, and so on, until all computation tasks in the entire DAG task scheduling graph are completed.

7. The system according to claim 6, characterized in that, The data stream processor is further configured to, after reading the DAG task scheduling graph in the data stream processor's memory, allocate a parsing program to each DAG task. The parsing program estimates the ratio of computation time to transmission time based on the computational data volume and computational complexity of the task, and segments and groups the DAG task scheduling graph according to this ratio, with each group consisting of two task segments. The ratio of the estimated computation time to transmission time satisfies the formula... , computational load wi Determined by the complexity of the task. P k For the processing capacity of the target computing node, DataSize(e ij ) is edge e ij The amount of data transmitted; BandWidth is the network bandwidth between nodes (NOC). Establish a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and allocate actual computing cores to computing tasks.

8. The system according to claim 7, characterized in that, When there are three computing tasks TASK1, TASK2, and TASK3 requests on the current host, corresponding to three different DAG task scheduling graphs, the C flow control core will create three different parsers: DAG parser 1, DAG parser 2, and DAG parser 3. The DAG parser analyzes the computational complexity, computational data volume, and data transmission time between child nodes and adjacent nodes in the DAG task graph, estimates the computation time and transmission time of each child node, and groups the DAG task scheduling graph.

9. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

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