Modular electrical fault diagnosis method based on redundancy feature suppression

Abstract

The invention relates to the technical field of analog current fault diagnosis, in particular to an analog current fault diagnosis method based on redundancy feature suppression, which comprises the following steps: acquiring voltage and current data of a circuit output position according to a circuit simulation model, and constructing a circuit fault state data set according to the voltage and current data; performing time-frequency analysis on the circuit fault state data set through discrete wavelet transform; performing redundant feature suppression processing on the hierarchical frequency domain component set to obtain a circuit fault state data feature set; a DCNN-BiLSTM model is constructed, the DCNN-BiLSTM model is trained according to the circuit fault state data feature set, and the DCNN-BiLSTM model meeting a preset fault diagnosis correct rate is output as an analog power fault diagnosis model; and obtaining target to-be-detected voltage and current data, and performing analog current fault diagnosis on the target to-be-detected voltage and current data according to the analog current fault diagnosis model to obtain a corresponding fault type classification result. According to the invention, redundant features can be effectively suppressed, and the accuracy of analog power supply fault diagnosis is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog circuit fault diagnosis, and in particular to an analog circuit fault diagnosis method based on redundant feature suppression. BACKGROUND

[0002] Electronic circuits have now been deeply integrated into various industries and have become a key technology to ensure the normal operation of life and production activities. With the rapid progress of electronic circuit technology, its size is constantly reduced, its function is continuously expanded, and its system complexity is increasingly improved, which has led to a significant increase in failure rate. Electronic circuit failure not only causes safety risks, but also causes huge economic losses. Therefore, effective fault diagnosis of the circuit is extremely critical.

[0003] However, due to the diversity of circuit excitation signals, the uncertainty of fault component position, the complexity of fault type, and the complexity of analog circuit system, the difficulty of analog circuit fault diagnosis is increasing. In fault diagnosis, fault component position positioning and fault type distinction are two core elements, which are related to fault elimination efficiency and system reliability and stability. The fault type of analog circuit components is mainly divided into soft fault and hard fault, and hard fault shows that the component parameter completely fails (such as open circuit, short circuit), if soft fault is misjudged as hard fault, unnecessary maintenance or replacement of equipment may be caused, which affects production efficiency; soft fault refers to the partial deviation of the parameter from the rated value, if hard fault is misjudged as soft fault, the fault may exist continuously, which threatens the safety and stability of the system, especially in critical fields such as aviation, aerospace and medical treatment.

[0004] Traditional circuit fault diagnosis relies on the experience of engineers and point-by-point testing, which is time-consuming and difficult to adapt to the rapid development of integrated circuit technology. In recent years, data-driven methods have been widely used in complex electronic circuit system fault diagnosis because they do not rely on accurate mathematical models of the system. Data-driven methods mainly include two stages of feature extraction and fault pattern classification, and the current research focus is on how to remove noise interference from complex signals and extract key fault feature information. At the same time, deep learning has developed rapidly in the field of circuit fault diagnosis with the advantages of directly capturing data features from signals and not requiring prior domain knowledge, and has become an important means to improve the accuracy and efficiency of diagnosis. However, existing technologies only consider voltage changes when diagnosing circuit faults, and the diagnosis results only locate the fault component position without distinguishing the fault type.

[0005] Chinese patent publication No. CN107490758A discloses a modular BP neural network circuit fault diagnosis method based on fault propagation, which includes determining the test nodes of each sub-circuit based on circuit module division, and taking the feature parameter data of the test nodes as the data source of fault diagnosis; a modular anomaly detection model is established based on the data source of circuit simulation, fault propagation is analyzed, and a modular BP neural network model is established; when an actual circuit fails, the modular anomaly detection model is used for primary positioning to determine the fault sub-circuit, and then the BP neural network model of the target sub-circuit is used for secondary positioning to identify the fault mode. Although this scheme can realize two-stage positioning diagnosis of circuit faults by combining modular BP neural network with fault propagation analysis, it cannot effectively suppress redundant features, it is difficult to accurately mine effective information in the data, and the accuracy of modular electric fault diagnosis is reduced. SUMMARY

[0006] To this end, the present application provides a modular electric fault diagnosis method based on redundant feature suppression to overcome the problem that the prior art cannot effectively suppress redundant features, it is difficult to accurately mine effective information in the data, and the accuracy of modular electric fault diagnosis is low.

[0007] To achieve the above-mentioned purpose, the present application provides a modular electric fault diagnosis method based on redundant feature suppression, comprising the following steps: S1, based on the preset modular electric fault diagnosis requirement information, constructing a circuit simulation model in simulation software, and collecting voltage and current data at the circuit output position according to the circuit simulation model, and constructing a circuit fault state data set according to the voltage and current data; S2, using discrete wavelet transform to convert the voltage and current data in the circuit fault state data set to the frequency domain for time-frequency analysis, and decomposing the voltage and current data in the circuit fault state data set into sub-bands of different hierarchical frequency domain components to obtain a hierarchical frequency domain component set; S3, determining the redundant feature amplitude threshold value of the corresponding level based on the hierarchical frequency domain component set, and using a first preset fixed-length sub-window to analyze the hierarchical frequency domain component set, filling the frequency domain components that meet the redundant feature amplitude threshold value of the corresponding level into the sub-window in ascending order to obtain the processed sub-window data of each level, and constructing a circuit fault state data feature set based on the processed sub-window data of each level; S4, a DCNN-BiLSTM model is constructed, the DCNN-BiLSTM model is trained according to the circuit fault state data feature set, and the DCNN-BiLSTM model meeting the preset fault diagnosis accuracy is output as a model electric fault diagnosis model, the DCNN-BiLSTM model is used to save the voltage and current data of the corresponding frequency in the circuit fault state data feature set as a two-dimensional matrix as the input information of the DCNN module, and the input information of the DCNN module is subjected to spatial feature extraction and local pattern mining to obtain high-dimensional features, and the high-dimensional features are input into the BiLSTM module to analyze the time dynamic characteristics of the voltage and current data, and obtain the time sequence characteristics associated with the circuit fault; S5, obtaining target voltage and current data to be tested, and performing model electric fault diagnosis on the target voltage and current data to be tested according to the model electric fault diagnosis model to obtain a fault type classification result.

[0008] Compared with the prior art, the beneficial effects of the present application are: By using the discrete wavelet transform to convert the voltage and current data in the circuit fault state data set to the frequency domain for time-frequency analysis, and decomposing into subbands of different hierarchical frequency domain components to obtain a hierarchical frequency domain component set, and then determining the corresponding hierarchical redundant feature amplitude threshold, the redundant features in the data can be effectively identified and screened out, the hierarchical frequency domain component set is analyzed by using a first preset fixed-length sub-window, the frequency domain components meeting the redundant feature amplitude threshold are filled in ascending order to obtain the processed sub-window data of each hierarchical level, and then the circuit fault state data feature set is constructed, a large amount of redundant information is removed, and the data features that are really useful for fault diagnosis are retained, the problem that the model input contains a large amount of noise or redundant information due to the fact that the features are not subjected to time-frequency domain analysis and redundancy suppression in the prior art is solved, and finally, when the DCNN-BiLSTM model is constructed, the noise interference and redundant components of the input data are significantly reduced, so that the model can more efficiently learn the deep rules of the fault mode, thereby improving the diagnosis accuracy.

[0009] By constructing the DCNN-BiLSTM model, the DCNN-BiLSTM model saves the voltage and current data of the corresponding frequency in the circuit fault state data feature set as a two-dimensional matrix as the input information of the DCNN module, the DCNN module can mine the spatial features and local patterns of the input information, obtain high-dimensional features, and effectively extract the key features of the data in the spatial dimension. Then the high-dimensional features are input into the BiLSTM module, the BiLSTM module analyzes the time dynamic characteristics of the voltage and current data, and obtains the time sequence features associated with the circuit fault. By combining the model structure of DCNN and BiLSTM, the advantages of both in spatial feature mining and time sequence analysis are fully utilized. Compared with the situation that a single model in the prior art is difficult to comprehensively and accurately mine effective information of data, the analog and electric fault diagnosis model of the present application can more deeply and comprehensively mine effective information in data, and then more accurately judge the circuit fault type, thereby improving the accuracy of analog and electric fault diagnosis.

[0010] Further, the S1 comprises the following steps: S11, inputting circuit element parameters and circuit element topology structure in the simulation software according to preset analog and electric diagnosis requirements, and constructing a circuit simulation model; S12, setting faults of circuit element parameters in the circuit simulation model based on circuit tolerance theory, and obtaining a fault working condition simulation model of multiple fault states; S13, determining a corresponding circuit fault test scheme based on preset simulation conditions, and inputting excitation source parameters and measurement nodes in the fault working condition simulation model according to the circuit fault test scheme, and collecting voltage and current data of circuit output positions; S14, standardizing the voltage and current data to obtain standardized voltage and current data, and labeling the standardized voltage and current data to obtain a corresponding circuit fault state data set.

[0011] In the scheme, the preset analog circuit diagnosis requirement refers to the target and requirement for diagnosing the fault of the analog circuit, such as diagnosing the short circuit, open circuit fault or parameter drift fault of the resistor, capacitor and other elements in the circuit, the circuit tolerance theory refers to considering the allowable deviation range of the circuit element parameters, and the actual value of the element is within the range, the circuit can still work normally, the preset simulation condition refers to the environmental condition for simulating the circuit, such as temperature, power voltage fluctuation range, etc., the circuit fault test scheme refers to the scheme for determining how to input the excitation and select the measurement node to detect the fault for the fault working condition simulation model, for example, in a certain filter circuit, a sinusoidal excitation is used, and the input and output ends are selected as the measurement nodes, the excitation source parameter refers to the relevant parameter of the excitation source input into the circuit simulation model, such as the frequency and amplitude of the sinusoidal excitation, and the voltage and current data refer to the original values of the voltage and current at the circuit output position collected according to the circuit fault test scheme in the fault working condition simulation model.

[0012] By constructing the circuit simulation model according to the preset analog circuit diagnosis requirement, the actual diagnosis target can be accurately matched, the fault is set by using the circuit tolerance theory, the model is closer to the actual element parameter fluctuation, the simulation process is standardized by presetting the simulation condition and determining the circuit fault test scheme, the excitation source parameter and the measurement node are reasonably set, the voltage and current data can be accurately collected, the circuit fault state data set is obtained after standardization processing and fault labeling, comprehensive, accurate and actual data support is provided for subsequent analog circuit fault diagnosis, and the accuracy and reliability of the diagnosis are improved.

[0013] Further, the S2 includes the following steps: S21, determining a matched wavelet base function according to the circuit fault state data set, and determining a decomposition layer number of the discrete wavelet transform according to a sampling frequency of the circuit fault state data set, wherein a mathematical expression of the discrete wavelet transform is: , wherein, indicates a result of the discrete wavelet transform, j indicates a scaling parameter, and k indicates a translation parameter, indicates a normalization factor, indicates an input function, indicates a wavelet base function, indicates a complex conjugate function of the wavelet base function, and t indicates an integral variable; S22, substituting the wavelet base function, the decomposition layer number and the voltage and current data in the circuit fault state data set into the discrete wavelet transform to perform decomposition, to obtain a time-frequency domain decomposition result containing an approximation coefficient and a detail coefficient; S23, decomposing the time-frequency domain decomposition result into subbands of different level frequency domain components through a multi-level decomposition mechanism of the discrete wavelet transform, and integrating the subbands of different level frequency domain components according to a level relationship, to obtain a level frequency domain component set.

[0014] In the scheme, the approximation coefficient refers to a coefficient reflecting the characteristics of the low-frequency part of the signal, embodying the overall trend and general outline of the signal, the detail coefficient refers to a coefficient reflecting the characteristics of the high-frequency part of the signal, capturing the mutation and detail information of the signal, and the multi-level decomposition mechanism refers to a mechanism for repeatedly decomposing the signal to further decompose the approximation coefficient of the previous level to obtain multi-level approximation coefficients and detail coefficients.

[0015] By determining the wavelet basis function and the number of decomposition levels according to the circuit fault data, and then performing discrete wavelet transform and multi-level decomposition, the different frequency domain sub-band information of the circuit fault signal can be accurately obtained, the approximation and detail characteristics can be effectively separated, the circuit fault state can be more comprehensively and accurately analyzed, and the accuracy of fault diagnosis can be improved.

[0016] Further, the S3 comprises the following steps: S31, determining the redundant feature amplitude threshold of the corresponding level based on the maximum value of the redundant feature amplitude of the frequency signal under each level frequency domain component, and combining the amplitude range and the noise range of the frequency signal; S32, analyzing each level frequency domain component in the set of level frequency domain components using a first preset fixed length sub-window, determining the level frequency domain component that meets the redundant feature amplitude threshold of the corresponding level as the corresponding effective feature amplitude, filling the effective feature amplitude to the sub-window in ascending order of frequency, deleting the level frequency domain component that does not meet the redundant feature amplitude threshold of the corresponding level, and performing zero padding to the last position of the sub-window that is not filled, to obtain the processed sub-window data of each level; S33, concatenating and splicing the processed sub-window data of each level and the low-frequency part data in the order of the decomposition levels to form a second preset fixed length total window data sequence, and constructing a circuit fault state data feature set through the total window data sequence.

[0017] In the scheme, the redundant feature amplitude threshold refers to the maximum value of the redundant feature amplitude of the frequency signal under each level frequency domain component, which is determined in combination with the amplitude range and the noise range, and is used to screen the effective feature amplitude, for example, the maximum value of the redundant feature amplitude of a certain level is 10, the amplitude range is 0-15, and the noise range is 0-2, the threshold is determined as 8, and the value greater than 8 is effective, the first preset fixed length refers to the fixed length of the sub-window when analyzing the level frequency domain component, for example, 100 data points are set as the length to analyze the component, and the second preset fixed length refers to the fixed length of the total window data sequence after concatenation and splicing, for example, the processed data of each level is spliced into a total sequence of 500 data points.

[0018] The effective amplitude is screened by determining a threshold value based on the maximum value of the redundant feature amplitude, the data is processed by a fixed length sub-window and zero padding, and then concatenated and spliced into a fixed length total sequence to construct a circuit fault state data feature set, which can accurately extract circuit fault features, reduce noise interference, enhance feature stability and consistency, and improve the reliability and accuracy of fault diagnosis.

[0019] Further, the S4 comprises the following steps: S41, converting the circuit fault state data feature set into a spatial feature input matrix conforming to DCNN processing, constructing a DCNN module, and extracting spatial features of the spatial feature input matrix through a plurality of convolution kernels in the DCNN module to obtain a local spatial feature tensor containing voltage and current signals; S42, constructing a BiLSTM module at the output end of the DCNN module, and processing the local spatial feature tensor through a forward LSTM unit and a reverse LSTM unit in the BiLSTM module to obtain a global time sequence feature vector; S43, performing dimension matching and feature integration on the local spatial feature tensor of the DCNN module and the global time sequence feature vector of the BiLSTM module through a full connection layer to obtain an end-to-end DCNN-BiLSTM model; S44, dividing the circuit fault state data feature set into a 70% data training set and a 30% data validation set; S45, inputting the data training set into the DCNN-BiLSTM model for iterative training, calculating the error between the prediction result of the DCNN-BiLSTM model and the real fault label by using a cross-entropy loss function, and optimizing the model parameters of the DCNN-BiLSTM model through a back propagation algorithm; S46, inputting the data validation set into the trained DCNN-BiLSTM model for verification, stopping the iterative training when the accuracy of the trained DCNN-BiLSTM model on the data validation set reaches a preset accuracy threshold, and obtaining a verified DCNN-BiLSTM model; S47, obtaining a data test set according to a circuit simulation model, inputting the data test set into the verified DCNN-BiLSTM model for testing, and outputting a module electrical fault diagnosis model when the fault diagnosis accuracy of the verified DCNN-BiLSTM model on the data test set reaches a preset fault diagnosis accuracy threshold.

[0020] In the scheme, the DCNN (Deep Convolutional Neural, deep convolutional neural network) refers to a deep learning network specially used for processing data with network structure (such as time series, images, etc.), the BiLSTM (Bidirectional Long Short-Term Memory, bidirectional long short-term memory network) refers to a deep learning module combining bidirectional information processing and long short-term memory (LSTM) capability, the preset accuracy threshold refers to a standard accuracy value preset for measuring the performance of the DCNN-BiLSTM model on the data validation set, for example, if the accuracy of the model on the data validation set is 92%, the requirement is met, the fault diagnosis accuracy refers to the proportion of the number of correctly diagnosed samples to the total number of samples when the DCNN-BiLSTM model diagnoses the circuit fault state data in the data test set, for example, if there are 100 samples in the data test set and the model correctly diagnoses 95 samples, the fault diagnosis accuracy is 95%, and the preset fault diagnosis accuracy threshold refers to the preset fault diagnosis accuracy standard that the DCNN-BiLSTM model needs to achieve on the data test set, for example, if the preset fault diagnosis accuracy threshold is 93% and the model test accuracy is 94%, the model is qualified.

[0021] By converting the circuit fault state data feature set into a spatial feature input matrix, using the DCNN module to extract local spatial feature tensors, the local spatial information of the voltage and current signals can be captured, the BiLSTM module is used to process the local spatial feature tensors, the global time sequence feature vector can be obtained, the time sequence information is fused, the DCNN-BiLSTM model is obtained through the full connection layer integration, the advantages of spatial and time sequence features are combined, the data set is divided and iteratively trained, the parameters are optimized using the cross-entropy loss function and the back propagation algorithm, the model performance can be improved, the preset accuracy threshold and the preset fault diagnosis accuracy threshold are set, and the model can achieve high accuracy in the verification and test stages, so as to output an accurate and reliable analog circuit fault diagnosis model, improve the accuracy and stability of fault diagnosis.

[0022] Further, the S5 comprises the following steps: S51, acquiring original analog signals through a circuit simulation model, and performing data conversion on the original analog signals to obtain target voltage and current data to be measured; S52, performing time-frequency analysis on the target voltage and current data to be measured by using discrete wavelet transform to obtain a set of measured hierarchical frequency domain components, determining the corresponding hierarchical measured redundant feature amplitude threshold value based on the set of measured hierarchical frequency domain components, and using a first preset fixed-length sub-window to analyze the set of measured hierarchical frequency domain components, and filling the frequency domain components meeting the corresponding hierarchical measured redundant feature amplitude threshold value in ascending order to obtain a measured circuit feature vector sequence; S53, input the to-be-tested circuit feature vector sequence into the analog circuit fault diagnosis model, acquire multi-scale local features through a deep feature extraction layer of a DCNN module, and output a time sequence confidence distribution sequence of each fault type through a time sequence feature fusion layer of a BiLSTM module; S54, analyze the time sequence confidence distribution sequence based on a maximum a posteriori probability criterion to obtain a corresponding fault type classification result.

[0023] In this scheme, the multi-scale local features refer to local features of voltage and current signals extracted from multiple scales through a deep feature extraction layer of a DCNN module by performing convolution operations on the input to-be-tested circuit feature vector sequence through different scale convolution kernels, for example, large-scale convolution kernels can capture overall trend features of signals, and small-scale convolution kernels can acquire detailed features; the time sequence confidence distribution sequence refers to a probability distribution sequence for each fault type output by a time sequence feature fusion layer of a BiLSTM module by performing time sequence information processing on the multi-scale local features; the to-be-tested hierarchical frequency domain component set based on the frequency signal refers to a threshold value determined in combination with a redundant feature amplitude and a noise range of the frequency signal, which is used to filter effective frequency domain components, for example, the maximum redundant feature amplitude of a to-be-tested hierarchical component is 12, the amplitude range is 0-18, the noise range is 0-3, and the threshold value is determined as 10; and the maximum a posteriori probability criterion refers to a criterion for selecting a fault type with the maximum a posteriori probability as a classification result under the condition of the time sequence confidence distribution sequence.

[0024] By collecting original analog signals and converting to obtain target to-be-tested voltage and current data, performing the same processing as the circuit fault state data set, ensuring data consistency, acquiring multi-scale local features through a DCNN module, comprehensively extracting signal local features, outputting a time sequence confidence distribution sequence through a BiLSTM module, fusing time sequence and spatial information, analyzing the time sequence confidence distribution sequence based on a maximum a posteriori probability criterion, and accurately obtaining a fault type classification result, the accuracy of analog circuit fault diagnosis is improved.

[0025] Further, the S53 includes the following steps: S531, input the to-be-tested circuit feature vector sequence into a deep feature extraction layer of a DCNN module, analyze through multi-layer convolution operations, and generate multi-scale local features containing fault mode spatial distribution features through nonlinear activation and pooling operations; S532, input the multi-scale local features into a time sequence feature fusion layer of a BiLSTM module, analyze the time sequence evolution characteristics of the multi-scale local features, and obtain a time sequence confidence distribution sequence of each fault type.

[0026] In the scheme, the fault mode space distribution feature refers to the characteristic distribution of different fault types in the circuit space, the time sequence evolution characteristic of the multi-scale local feature refers to the law of the multi-scale local feature changing with time, and the time sequence confidence distribution sequence refers to a sequence of probability judgments of the model on the occurrence of each fault type at different times.

[0027] The multi-scale local feature containing the fault mode space distribution feature is extracted through the DCNN module, which can accurately capture the feature performance of the fault in the circuit space, the time sequence evolution characteristic of the multi-scale local feature is analyzed, the time sequence information is comprehensively obtained, and then the time sequence confidence distribution sequence of each fault type is obtained, and the fault type is accurately judged.

[0028] Further, the S54 comprises the following steps: S541, based on the maximum posterior probability criterion, the Bayesian posterior probability of the fault type of each time step in the time sequence confidence distribution sequence is calculated, and the posterior probability value corresponding to each time step is obtained; S542, the fault type corresponding to the maximum posterior probability value in each time step is taken as a candidate fault type, and the candidate fault type is time sequence weighted fusion, and a fault type classification result is obtained.

[0029] In the scheme, the posterior probability value is calculated based on the maximum posterior probability criterion, and the fault type classification result is obtained by weighted fusion, which can improve the accuracy of fault type judgment and improve the practicability and efficiency of the analog and electric fault diagnosis. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 It is a flowchart of the analog and electric fault diagnosis method based on redundant feature suppression of the embodiment of the application; Figure 2 It is a schematic diagram of the Sallen-Key band-pass filter circuit of the embodiment of the application; Figure 3 It is a schematic diagram of the four-OAMP high-pass filter circuit of the embodiment of the application; Figure 4 It is a first four-OAMP high-pass filter circuit diagnosis result diagram of the embodiment of the application; Figure 5 It is a second four-OAMP high-pass filter circuit diagnosis result diagram of the embodiment of the application; Figure 6 It is a first one-way LSTM fault diagnosis result diagram of the embodiment of the application; Figure 7 It is a second one-way LSTM fault diagnosis result diagram of the embodiment of the application; Figure 8 It is a first BiLSTM fault diagnosis result diagram of the embodiment of the application; Figure 9 FIG. 2 is a BiLSTM fault diagnosis result diagram of an embodiment of the present application; Figure 10 FIG. 3 is a first BiLSTM-DCNN fault diagnosis result diagram of an embodiment of the present application; Figure 11 FIG. 4 is a second BiLSTM-DCNN fault diagnosis result diagram of an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following is further described in detail through specific embodiments: Referring to FIG. 1, Figure 1 As shown in FIG. 1, which is a flowchart of a method for analog and electrical fault diagnosis based on redundant feature suppression according to an embodiment of the present application, the method comprises the following steps: S1, constructing a circuit simulation model in simulation software based on preset analog and electrical fault diagnosis requirement information, collecting voltage and current data at a circuit output position according to the circuit simulation model, and constructing a circuit fault state data set according to the voltage and current data; S2, converting the voltage and current data in the circuit fault state data set to the frequency domain for time-frequency analysis by using discrete wavelet transform, and decomposing the voltage and current data in the circuit fault state data set into subbands of different hierarchical frequency domain components to obtain a hierarchical frequency domain component set; S3, determining a redundant feature amplitude threshold value corresponding to a hierarchical level based on the hierarchical frequency domain component set, and analyzing the hierarchical frequency domain component set using a first preset fixed-length sub-window, filling the frequency domain components that meet the redundant feature amplitude threshold value corresponding to the hierarchical level into the sub-window in ascending order to obtain processed sub-window data of each hierarchical level, and constructing a circuit fault state data feature set based on the processed sub-window data of each hierarchical level; S4, constructing a DCNN-BiLSTM model, training the DCNN-BiLSTM model according to the circuit fault state data feature set, and outputting the DCNN-BiLSTM model that meets the preset fault diagnosis accuracy as an analog and electrical fault diagnosis model, wherein the DCNN-BiLSTM model is used to save the voltage and current data at a corresponding frequency in the circuit fault state data feature set as a two-dimensional matrix as input information of a DCNN module, and to perform spatial feature extraction and local pattern mining on the input information of the DCNN module to obtain high-dimensional features, and input the high-dimensional features into a BiLSTM module to analyze the time dynamic characteristics of the voltage and current data to obtain time sequence features associated with circuit faults; S5, obtaining target voltage and current data to be measured, and performing analog and electrical fault diagnosis on the target voltage and current data to be measured according to the analog and electrical fault diagnosis model to obtain a fault type classification result.

[0032] Specifically, S1 comprises the following steps: S11, inputting circuit element parameters and circuit element topology structure in the simulation software according to preset mode electrical diagnosis requirements, and constructing a circuit simulation model; S12, setting faults of circuit element parameters in the circuit simulation model based on circuit tolerance theory, and obtaining a fault working condition simulation model of multiple fault states; S13, determining a corresponding circuit fault test scheme based on preset simulation conditions, inputting excitation source parameters and measurement nodes in the fault working condition simulation model according to the circuit fault test scheme, and collecting voltage and current data of circuit output positions; S14, standardizing the voltage and current data to obtain standardized voltage and current data, and marking faults of the standardized voltage and current data to obtain corresponding circuit fault state data sets.

[0033] In this embodiment, setting faults of circuit element parameters in the circuit simulation model based on circuit tolerance theory includes: setting the tolerance range of the resistor and the capacitor to 10% respectively, and referring to existing research regulations, when the parameter value of an element exceeds 50% of its rated value (regardless of its tolerance range), the circuit enters a fault state; when the element parameter value exceeds 10%-50% of the rated value, it is considered that the circuit has a soft fault. This application only considers single fault conditions, that is, only one element parameter value deviates from its tolerance range. When setting faults, a key element is selected, and the parameters of other components are fixed at their nominal values. Hard fault setting: for the selected key element, set its parameter value to exceed 50% of the rated value, for example, the resistance rated value is 100Ω, set it to short circuit (resistance value is 0Ω) or open circuit (resistance value is infinite, which can be set to a maximum value in simulation), simulate the major damage of the circuit element in the hard fault state and the complete change of the internal structure and connection. Soft fault setting: set the parameter value of the selected key element to be in the range of 10%-50% of the rated value, for example, the resistance rated value is 100Ω, set its resistance value to be between 110Ω and 150Ω, simulate the case that the circuit element deviates from the initial nominal value when working in the actual environment. Through such setting, a fault working condition simulation model of multiple fault states is obtained, and each model corresponds to a specific element fault setting condition.

[0034] The fault labeling of the standardized voltage and current information includes the classification and judgment standard of the circuit fault, that is, the element parameter value exceeding 50% of the rated value is a hard fault, the parameter value exceeding 10%-50% of the rated value is a soft fault, and only a single fault condition is considered. In the fault working condition simulation model, when a certain element is set as a hard fault (such as a short circuit or an open circuit, the parameter value exceeds 50% of the rated value), the standardized voltage and current data collected under the fault model are labeled as a hard fault state. For example, in a circuit containing resistors and capacitors, the resistor is set as a short circuit fault, and the voltage and current data collected under this model are labeled as “resistor short circuit hard fault”. If a certain element is set as a soft fault (the parameter value exceeds 10%-50% of the rated value), the standardized voltage and current data collected under the corresponding fault model are labeled as a soft fault state. For example, the parameter value of the capacitor is set to exceed 20% of the rated value, and the voltage and current data collected under this model are labeled as “capacitor soft fault (parameter deviation 20%)”. Through such a labeling method, the corresponding circuit fault state data set is obtained, in which each data sample is clearly labeled with the fault type and related information, facilitating subsequent analysis and diagnosis of the circuit fault.

[0035] Specifically, S2 includes the following steps: S21, determining a matching wavelet basis function according to the circuit fault state data set, and determining the decomposition level of the discrete wavelet transform according to the sampling frequency of the circuit fault state data set, wherein the mathematical expression of the discrete wavelet transform is: , wherein, represents the result of the discrete wavelet transform, j represents a scaling parameter, k represents a translation parameter, represents a normalization factor, represents an input function, represents a wavelet basis function, represents a complex conjugate function of the wavelet basis function, and t represents an integral variable; S22, substituting the wavelet basis function, the decomposition level and the voltage and current data in the circuit fault state data set into the discrete wavelet transform to perform decomposition, to obtain a time-frequency domain decomposition result containing approximation coefficients and detail coefficients; S23, decomposing the time-frequency domain decomposition result into subbands of different level frequency domain components through the multi-level decomposition mechanism of the discrete wavelet transform, and integrating the subbands of different level frequency domain components according to the level relationship to obtain a level frequency domain component set.

[0036] In this embodiment, a suitable wavelet basis function is selected according to the transient characteristics of the signals in the circuit fault condition dataset. For example, if the signal has sharp transient changes, a wavelet basis with good time-domain locality, such as the Daubechies series wavelet, can be selected; if the signal frequency characteristics are complex, a wavelet basis with good frequency-domain locality, such as the Morlet wavelet, can be selected. The number of decomposition layers of the discrete wavelet transform is determined according to the sampling frequency of the circuit fault condition dataset. The fault characteristic frequencies (such as harmonic, transient oscillation frequency) are analyzed, and it is assumed that the sampling frequency is , according to the Nyquist theorem, the upper limit of the effective frequency is , each layer of decomposition frequency is halved, and the number of decomposition layers N satisfies , where represents the lowest frequency of the fault characteristic, for example, the sampling frequency is 1 kHz, the lowest frequency of the fault characteristic is in the range of 15.6-31.2 Hz, and is calculated, and N is 3, that is, 3 layers of decomposition are obtained. If the low-frequency subband still contains redundant information after decomposition, the number of layers can be reduced, or if the high-frequency noise interferes with the characteristics, the number of layers can be increased or combined with threshold denoising. Using the selected wavelet basis function and the number of decomposition layers, the discrete wavelet transform is performed on each sample signal in the circuit fault condition dataset. First, the signal is convolved with the wavelet basis function to obtain the approximation coefficients and the detail coefficients at different scales. Specifically, by adjusting the scaling parameter and the translation parameter, the inner product of the input function and the wavelet basis function and its complex conjugate function is calculated to obtain the result of the discrete wavelet transform. This process is repeated for multi-scale decomposition of the signal, and each layer of decomposition obtains a set of approximation coefficients and detail coefficients. The approximation coefficients reflect the low-frequency part of the signal, and the detail coefficients reflect the high-frequency part of the signal.

[0037] The subband of the time-frequency domain decomposition result decomposed into different levels of frequency domain components through the multi-level decomposition mechanism includes: the input signal is high-pass filtered to obtain high-frequency detail coefficients (D1), which reflect the local abrupt change of the signal; low-pass filtered to obtain low-frequency approximation coefficients (A1), which retain the main characteristics of the signal. A1 is further decomposed to generate higher-level detail coefficients (D2, D3, etc.) and approximation coefficients (A2, A3, etc.). Each layer of detail coefficients corresponds to a subband of different frequency bands (such as D1 for high frequency, D2 for high frequency), and the approximation coefficients approach the low-frequency component of the signal layer by layer. The frequency band covered by each layer of detail coefficients is determined by the sampling frequency and the number of decomposition layers, for example, 3 layers of decomposition can divide the signal into 4 frequency bands (A3, D3, D2, D1).

[0038] The subbands of different hierarchical frequency domain components are integrated into a hierarchical frequency domain component set according to the hierarchical relationship, including: arranging the detail coefficients (D1, D2, …) and the final approximation coefficient (An) according to the decomposition order to form a frequency domain component set. For example, the 3-layer decomposition result is [A3, D3, D2, D1]. It is ensured that the frequency bands corresponding to each subband do not overlap and cover the full frequency spectrum, and the high-frequency subband (such as D1) is located at the front end of the set, and the low-frequency subband (such as A3) is located at the end. If a specific frequency band needs to be analyzed, the subband can be extracted alone; if the signal needs to be reconstructed, the detail coefficients are added layer by layer from An to the inverse transform. The integrated component set can be used for fault feature extraction or classification.

[0039] Specifically, S3 includes the following steps: S31, determining the redundant feature amplitude threshold value of the corresponding hierarchical level based on the maximum value of the redundant feature amplitude of the frequency signal under each hierarchical frequency domain component, and combining the amplitude range and noise range of the frequency signal; S32, analyzing each hierarchical frequency domain component in the hierarchical frequency domain component set using a first preset fixed-length sub-window, determining the hierarchical frequency domain component that meets the redundant feature amplitude threshold value of the corresponding hierarchical level as the corresponding effective feature amplitude, and filling the effective feature amplitude into the sub-window in ascending order of frequency, deleting the hierarchical frequency domain component that does not meet the redundant feature amplitude threshold value of the corresponding hierarchical level, and performing zero padding processing on the last position of the sub-window that is not filled, to obtain the processed sub-window data of each hierarchical level; S33, concatenating and splicing the processed sub-window data of each hierarchical level and the low-frequency part data in the order of the decomposition hierarchical level to form a second preset fixed-length total window data sequence, and constructing a circuit fault state data feature set through the total window data sequence.

[0040] In this embodiment, filling the effective feature amplitude into the sub-window in ascending order of frequency includes: traversing the frequency domain components of each hierarchical level, and screening out the components that meet the redundant feature amplitude threshold value of the corresponding hierarchical level. The amplitudes of these components are the effective feature amplitudes. Then, the components are sorted in ascending order according to their frequency values to ensure that the frequencies are arranged from low to high. Next, the effective feature amplitudes are filled into the preset first fixed-length sub-window in order. Each position of the sub-window corresponds to a fixed frequency interval, and the amplitude needs to be ensured to correspond to the frequency interval during filling. If the number of effective feature amplitudes is less than the length of the sub-window, zero padding processing will be performed in the subsequent steps.

[0041] The zero padding of the last position of the unfilled sub-window includes: after the filling of the valid feature amplitudes is completed, it is checked whether the sub-window has been filled (i.e., whether the first preset fixed length is reached). If not, zero values are sequentially filled from the last position of the sub-window until the length of the sub-window reaches the preset value. The zero padding operation is only for positions not occupied by valid feature amplitudes, and the zero padding does not affect the order and values of the filled valid feature amplitudes. The length of the sub-window after zero padding is consistent with the preset value, ensuring the uniformity of the data structure for subsequent processing.

[0042] The concatenation of the sub-window data processed by each level and the low-frequency part data includes: arranging the sub-window data processed by each level in order according to the level order of frequency domain decomposition (e.g., from high frequency to low frequency or vice versa). The low-frequency part data is usually the lowest frequency component reserved after the original signal is decomposed and needs to be processed separately. The low-frequency part data is taken as the last level and is spliced with the sub-window data of other levels in order. When splicing, the sub-window data is directly connected end to end to form a continuous data sequence. The length of the finally generated sequence is the second preset fixed length (i.e., the sum of the lengths of all sub-windows), ensuring the integrity of the data structure.

[0043] The construction of the circuit fault state data feature set through the total window data sequence includes: extracting statistical features (such as mean, variance) or time-frequency features (such as energy distribution) from the total window data sequence. According to the actual fault state of the circuit (such as normal, short circuit, open circuit), a label is added to the feature set. The feature values are normalized to eliminate dimensional differences. The processed features are stored in correspondence with the labels to form a structured feature set for subsequent fault classification or diagnosis model training.

[0044] Specifically, S4 includes the following steps: S41, converting the circuit fault state data feature set into a spatial feature input matrix conforming to DCNN processing, constructing a DCNN module, and performing spatial feature extraction on the spatial feature input matrix through multiple convolution kernels in the DCNN module to obtain a local spatial feature tensor containing voltage and current signals; S42, constructing a BiLSTM module at the output end of the DCNN module, and processing the local spatial feature tensor through a forward LSTM unit and a reverse LSTM unit in the BiLSTM module to obtain a global time sequence feature vector; S43, performing dimension matching and feature integration on the local spatial feature tensor of the DCNN module and the global time sequence feature vector of the BiLSTM module through a full connection layer to obtain an end-to-end DCNN-BiLSTM model; S44, dividing the circuit fault state data feature set into a 70% data training set and a 30% data validation set; S45, input the data training set into the DCNN-BiLSTM model for iterative training, calculate the error between the prediction result of the DCNN-BiLSTM model and the real fault label by using the cross-entropy loss function, and optimize the model parameters of the DCNN-BiLSTM model by the back propagation algorithm; S46, input the data verification set into the trained DCNN-BiLSTM model for verification, when the accuracy of the trained DCNN-BiLSTM model on the data verification set reaches the preset accuracy threshold, stop iterative training, and obtain the verified DCNN-BiLSTM model; S47, obtain the data test set according to the circuit simulation model, and input the data test set into the verified DCNN-BiLSTM model for testing, when the fault diagnosis accuracy of the verified DCNN-BiLSTM model on the data test set reaches the preset fault diagnosis accuracy threshold, output the module electrical fault diagnosis model.

[0045] In this embodiment, converting the circuit fault state data feature set into a spatial feature input matrix conforming to DCNN processing includes: analyzing the dimensions and structures of each feature in the circuit fault state data feature set. It is assumed that the feature set contains multiple feature channels, each channel records information about signals in different aspects, such as different frequency components of voltage and current, etc. The width and height of the input matrix are determined, the width can correspond to the time sequence length of the signal, and the height can correspond to the number of feature channels. If the signal time sequence lengths are inconsistent, the shorter sequence is padded to reach a uniform length; if the signal time sequence is too long, it is truncated according to a preset window size to ensure that all samples have the same time dimension. At the same time, the data of each feature channel is aligned and integrated to ensure the corresponding relationship of the data in the feature dimension. The processed data is arranged according to the determined dimensions to construct a three-dimensional matrix. The three dimensions of the matrix represent the number of samples, the length of the time sequence and the number of feature channels respectively, this structure meets the requirements of deep convolutional neural network (DCNN) for input data, and can effectively extract spatial features.

[0046] The forward LSTM unit processes the local spatial feature tensor in time sequence from front to back. At each time step, it receives the input feature of the current time step and the hidden state of the previous time step, and controls the flow of information through the gating mechanism (input gate, forget gate, and output gate). The input gate determines how much new information is added to the cell state, the forget gate determines how much cell state information of the previous moment is retained, and the output gate determines the output of the current moment. The forward LSTM unit can capture the time sequence dependency from the past to the current moment and extract the forward time sequence feature in the sequence. The backward LSTM unit processes the local spatial feature tensor in time sequence from back to front. Similar to the forward LSTM unit, it also has its own gating mechanism. The backward LSTM unit can capture the time sequence dependency from the future to the current moment and extract the backward time sequence feature in the sequence. The outputs of the forward LSTM unit and the backward LSTM unit at each time step are spliced or weighted and fused to obtain a global time sequence feature vector containing bidirectional time sequence information. This fusion method enables the model to consider past and future context information at the same time and more comprehensively understand the time sequence features of the sequence.

[0047] The dimensions of the local spatial feature tensor output by the DCNN module and the global time sequence feature vector output by the BiLSTM module are analyzed. If the dimensions are inconsistent, a fully connected layer can be used to transform the dimension of the local spatial feature tensor so that it matches the dimension of the global time sequence feature vector. The fully connected layer maps the input data to a new feature space through linear transformation, changing the dimension of the data. The local spatial feature tensor and the global time sequence feature vector after dimension matching are spliced in the feature dimension. The splicing operation combines two different types of features together to form a new feature vector that contains both spatial features and time sequence features of the signal. In order to further integrate the spliced features, a fully connected layer can be used again to perform nonlinear transformation on the spliced feature vector. The fully connected layer introduces a nonlinear factor through the activation function, enabling the model to learn more complex feature combinations and relationships, thereby obtaining an end-to-end DCNN-BiLSTM model. This model can fully utilize local spatial features and global time sequence features to improve the diagnosis performance of circuit faults.

[0048] Specifically, S5 includes the following steps: S51, acquiring an original analog signal through a circuit simulation model, and performing data conversion on the original analog signal to obtain target voltage and current data to be measured; S52, time-frequency analysis is performed on the target voltage and current data to be measured by using discrete wavelet transform to obtain a set of frequency domain components to be measured at a level, and a redundant feature amplitude threshold to be measured at the level is determined based on the set of frequency domain components to be measured at the level, and a first preset fixed-length sub-window is used to analyze the set of frequency domain components to be measured at the level, and the frequency domain components satisfying the redundant feature amplitude threshold to be measured at the corresponding level are filled in ascending order to obtain a circuit feature vector sequence to be measured; S53, the circuit feature vector sequence to be measured is input into a DC fault diagnosis model, multi-scale local features are obtained through a deep feature extraction layer of a DCNN module, and a time sequence confidence distribution sequence of each fault type is output through a time sequence feature fusion layer of a BiLSTM module; S54, the time sequence confidence distribution sequence is analyzed based on a maximum a posteriori probability criterion to obtain a corresponding fault type classification result.

[0049] Specifically, S53 includes the following steps: S531, input the circuit feature vector sequence to be measured into a deep feature extraction layer of a DCNN module, analyze through multi-layer convolution operation, and generate multi-scale local features containing fault mode space distribution features through nonlinear activation and pooling operation; S532, input the multi-scale local features into a time sequence feature fusion layer of a BiLSTM module, analyze the time sequence evolution characteristics of the multi-scale local features, and obtain a time sequence confidence distribution sequence of each fault type.

[0050] Specifically, S54 includes the following steps: S541, Bayesian posterior probability calculation is performed on the fault type of each time step in the time sequence confidence distribution sequence based on the maximum a posteriori probability criterion to obtain a posterior probability value corresponding to each time step; S542, the fault type corresponding to the maximum posterior probability value in each time step is taken as a candidate fault type, and the candidate fault type is time sequence weighted fused to obtain a fault type classification result.

[0051] In this embodiment, generating multi-scale local features through nonlinear activation and pooling operations includes: inputting the feature vector sequence of the circuit under test into the deep feature extraction layer of the DCNN module. First, multi-scale local features are extracted through multi-layer convolution operation. The size and step of the convolution kernel are set according to the requirements. A smaller convolution kernel can capture detailed features, and a larger convolution kernel can obtain more extensive context information. After convolution operation, a nonlinear activation function (such as ReLU) is introduced to enhance the nonlinear expression ability of the model, so that the model can learn complex features. Then, the pooling operation (such as max pooling or average pooling) is performed to reduce the spatial size of the feature map, reduce the calculation amount, and retain important features. Through the alternation of multi-layer convolution, nonlinear activation and pooling, multi-scale local features containing spatial distribution characteristics of fault modes are gradually extracted.

[0052] Analyzing the time evolution characteristics of the multi-scale local features includes: inputting the generated multi-scale local features into the time sequence feature fusion layer of the BiLSTM module. BiLSTM (Bidirectional Long Short-Term Memory Network) is composed of a forward LSTM unit and a reverse LSTM unit, which can process past and future information at the same time. In the time sequence feature fusion layer, the multi-scale local features are input into the BiLSTM according to the time steps. The forward LSTM unit processes the feature sequence from front to back to capture historical information; the reverse LSTM unit processes the feature sequence from back to front to capture future information. Through the gating mechanism (input gate, forget gate, and output gate), BiLSTM can effectively handle long sequence dependency problems and learn the evolution characteristics of features over time. Finally, the time sequence confidence distribution sequence of each fault type is output.

[0053] Determining the physical location coordinates of the fault element in the circuit topology through the coordinate backstepping algorithm: input the spatial positioning parameters of the fault element into the preset circuit topology mapping model. The preset circuit topology mapping model establishes the mapping relationship between the position of the circuit element in the topology structure and the spatial positioning parameters. The coordinate backstepping algorithm first searches and matches in the circuit topology model according to the spatial positioning parameters. By calculating the distance or similarity between the spatial positioning parameters and the positions of the elements in the circuit topology, the most matched element position is found. Specific implementation can use the nearest neighbor search algorithm or optimization algorithms such as gradient descent method, which continuously adjusts the position parameters to minimize the error between the calculated position and the spatial positioning parameters, thereby determining the physical location coordinates of the fault element in the circuit topology. Match the fault type classification result with the physical location coordinates to determine the physical location corresponding to each fault type. Then, according to the circuit topology structure and the element identifier, the correspondence between the fault element identifier and the physical location coordinates is established. Through correlation analysis, it can be clearly known which element at which position has what type of fault. For example, the fault type "resistor open circuit" is associated with the physical location coordinates (x, y), and the element identifier at this position is determined as The circuit fault information is "component A resistance open circuit fault occurs at position (x, y)".

[0054] Experimental analysis is performed according to the above content: In circuit design, the filter is one of the most common circuits in analog circuits. Since the filtering principle of the filter circuit is basically unified, the commonly used filter circuit is basically composed of capacitors, resistors and the like of different types and different parameters. A classical Sallen-Key band-pass filter in an analog circuit is selected as a fault object, and a Sallen-Key band-pass filter circuit schematic diagram is shown in Figure 2 The circuit model of Sallen-Key is constructed. Since a pulse signal can usually provide a high signal-to-noise ratio and the transience of the pulse signal makes it easier to be identified and analyzed in a noisy environment. Considering that the input time-domain voltage signal is a pulse voltage U(t), the mathematical expression of the pulse voltage U(t) is: In the formula, V1 represents the initial value; V2 represents the pulse value; PW represents the pulse width; t represents time; TD represents the delay time; TR represents the rise time; and TF represents the fall time. The related parameters of the pulse voltage signal source are shown in Table 1.

[0055] Table 1: Pulse voltage signal related parameter table

[0056] Based on the above concept of circuit tolerance, the faults of electronic components are divided into soft faults and hard faults, and the identifiers of different components and different fault types are set. By comparing the circuit schematic diagram and the circuit fault type table, the fault component position and fault type can be distinguished. Each component and its different fault types have and only have a unique identifier to represent them. Taking the Sallen-Key band-pass filter circuit as an example, the circuit fault types are shown in Table 2.

[0057] Table 2: Sallen-Key band-pass filter circuit fault type table

[0058] Based on the simulation of 1175 groups of fault data of different fault types based on the Sallen-Key circuit model, the corresponding fault data set is established. And through the 70%-30% proportion split into training data set and test data set. Based on the established data set, compared with other classic methods, the classic methods selected in this application include CNN (Convolutional Neural Network), SWT-DCNN-ELM (Stationary Wavelet Transform-Deep Convolutional Neural Network-Extreme Learning Machine), LSTM (Long Short-Term Memory) and BiLSTM. And the diagnostic results obtained in this application and the results of other classic methods are compared. The comparison results are shown in Table 3.

[0059] Table 3 Comparison results of different diagnostic methods

[0060] In order to further verify the circuit fault diagnosis method proposed in this application, the present application selects a more complex circuit for experimental analysis to cope with more components and higher diagnostic difficulty. By comparing the fault diagnosis results under different circuit conditions, the accuracy and applicability of the method can be more comprehensively evaluated. The second circuit is a four operational amplifier high pass filter circuit, and its circuit schematic diagram is shown in Figure 3

[0061] Based on the above tolerance concept and the concept of soft and hard faults of circuit components, the circuit faults are divided into 24 different fault types, and the fault types of the four OAMP high pass filter circuit are shown in Table 4.

[0062] Table 4 Fault type table of four OAMP high pass filter circuit

[0063] For the four OAMP high pass filter circuit, 4350 groups of fault data of different fault types are simulated by using circuit simulation software, and are split into training data set and test data set by 70%-30% proportion, in this application, train represents training set, and val represents validation set. According to Figure 4 、 Figure 5 ​As shown in Table 4, the method proposed in the present application still has a high fault diagnosis accuracy rate when facing complex circuits and multi-element circuits. With the increase of the number of iterations, the training accuracy gradually increases and tends to be stable, and finally approaches 1. The verification accuracy fluctuates at the beginning, but as the training progresses, the fluctuation gradually decreases, and the final accuracy reaches more than 90%. The verification accuracy is slightly lower than the training accuracy, which to some extent indicates that the generalization ability of the model is still good, indicating that the model performs well on the training set and can accurately identify the faults of the circuit elements.

[0064] To verify the effectiveness of the method proposed in the present application in specific tasks, the present application conducts a number of ablation experiments. By gradually removing or replacing certain components in the model, the contribution of each part to the overall performance is evaluated. Based on the 1175 group data set, the voltage data and current data are uniformly converted into time-frequency by DWT, and then the feature extraction method designed in this paper is used for feature extraction, and then the model is used for fault diagnosis. Accuracy, model loss, convergence speed, and robustness are used as main evaluation indicators. All experiments are carried out under the same hyperparameter settings to ensure the comparability of the results.

[0065] Experiment 1: Unidirectional LSTM To investigate the effect of unidirectional LSTM, the BiLSTM in the model is replaced by unidirectional LSTM. The experimental results are shown in Figure 6 and Figure 7 In the accuracy graph on the left, the training set accuracy gradually increases and finally approaches 0.9, indicating that the model has good learning effect in the training process. The verification set accuracy increases slowly and finally stabilizes at about 0.8, indicating that the model does not achieve the same performance on the verification set and there is a certain overfitting phenomenon. The loss value graph on the right shows a clear downward trend. The training set loss decreases rapidly and finally remains at a low level, indicating that the model effectively captures the features of the training data. However, the validation set loss also shows a downward trend, but its value is significantly higher and more volatile than the training set loss, indicating that the LSTM model lacks generalization ability and may need further optimization. At the same time, the robustness of the model on the verification set shows that the loss value fluctuates greatly, indicating that the model is not stable when facing unseen data and is sensitive to certain input data. The convergence speed of the model is fast, and the training and validation losses decrease rapidly within the first few epochs, but the convergence of the validation set is slower than that of the training set.

[0066] Experiment 2: BiLSTM From Figure 8 and Figure 9As shown in the accuracy plot of BiLSTM, both the training set and the validation set show relatively stable and high accuracy. The training set accuracy continues to approach 1, indicating that the model has learned quite fully on the training data. In contrast, the validation set accuracy reaches about 89%, and the gap between the training set is significantly smaller than the LSTM model, which shows that the BiLSTM model has improved in generalization ability. In the loss value plot, the training set and validation set loss of the BiLSTM model both show a smooth downward trend. Especially the validation set loss gradually decreases to close to 0.5, which shows that when testing unseen data, the model performs more stably and effectively. While the validation loss of the LSTM model fluctuates over time, indicating that BiLSTM significantly reduces the overfitting phenomenon during training. Compared with the LSTM model, BiLSTM shows stronger robustness. The stability and smaller fluctuation range of the validation set loss show that the model can better handle unseen data and has stronger adaptability. The convergence speed of the BiLSTM model is faster, especially in the early iterations, such as the change of loss value and accuracy, which shows faster decline and rise, which benefits from the characteristics of bidirectional information processing, which helps to capture more rich context information in time series.

[0067] Experiment Three: BiLSTM-DCNN From Figure 10 and Figure 11In the DCNN-BiLSTM accuracy graph proposed in this application, the accuracy of the training set and the validation set is quite high and tends to be saturated, with the training set accuracy close to 1 and the validation set accuracy stable at about 94.33%. This shows that the model has solved the problem of diagnosing analog circuit component faults at a high level. Compared with the LSTM and BiLSTM models, the validation set accuracy of the latter two is significantly different, and the validation set performance of BiLSTM is significantly better than that of LSTM, but still not as good as the method proposed in this paper, showing that the feature extraction capability of DCNN-BiLSTM is more superior. In the loss value graph, the training and validation loss of DCNN-BiLSTM decreases rapidly and remains at a low level, and the validation loss is even close to 0, showing excellent learning ability and generalization ability. In contrast, the validation loss of the LSTM model fluctuates and is significantly higher than that of DCNN-BiLSTM, while the validation loss of BiLSTM is lower than that of LSTM but still higher than that of DCNN-BiLSTM. This shows that the proposed model has stronger anti-interference ability and lower overfitting risk when processing data. DCNN-BiLSTM shows good robustness, and the stable performance of the validation loss shows that it has strong generalization ability for unseen data. In contrast, the validation loss of LSTM fluctuates greatly, and although BiLSTM is relatively stable, it is still not as good as DCNN-BiLSTM. When faced with variable data, CNN-BiLSTM may be more adaptable. At the same time, DCNN-BiLSTM converges quickly, and the training loss and validation loss decrease rapidly in the early iterations, especially after the first few iterations, showing excellent performance. While the convergence speed of LSTM and BiLSTM is also fast, but before the accuracy stabilizes, it goes through a period of fluctuation, indicating that DCNN-BiLSTM can quickly extract features and learn effectively. DCNN, as a feature extraction network, can effectively capture spatial features, and combined with BiLSTM, it improves the modeling ability of sequence information. This fusion enables DCNN-BiLSTM to better handle the potential patterns and complexities in sequence data, and the independent LSTM and BiLSTM models perform worse in feature extraction.

[0068] Through the above ablation experiments, the effectiveness of each part of the model is verified. Overall, DCNN-BiLSTM performs better than traditional LSTM and BiLSTM models in terms of accuracy, loss value, robustness, and convergence speed. This shows that the combination of convolutional neural network and bidirectional long short-term memory neural network has significant advantages and stronger adaptability when dealing with complex sequence tasks, greatly improving the performance of the model. The synergy between bidirectional long short-term memory network and convolutional layer significantly improves the overall performance of the model.

[0069] The above is only an embodiment of the present application, and the common knowledge of specific structures and characteristics in the scheme is not described in detail, and the ordinary skilled person in the art knows all the ordinary technical knowledge in the technical field of the present application before the application date or the priority date, can know all the prior art in the field, and has the ability to apply conventional experimental means before that date, and the ordinary skilled person in the art can improve and implement the present scheme under the guidance of the present application, and some typical known structures or known methods should not be an obstacle for the ordinary skilled person in the art to implement the present application. It should be pointed out that for those skilled in the art, without departing from the structure of the present application, a number of modifications and improvements can be made, which should also be considered as the protection scope of the present application, which will not affect the effect and practicality of the patent. The protection scope of the present application should be subject to the content of its claims, and the specific implementation mode and the like in the specification can be used to explain the content of the claims.

Claims

1. A method for analog electrical fault diagnosis based on redundancy feature suppression, characterized in that: Comprise the following steps: S1, based on the preset module electric fault diagnosis demand information in the simulation software constructs the circuit simulation model, and according to the circuit simulation model gathers the voltage and current data of circuit output position, and according to the voltage and current data constructs circuit fault state data set; S2, the voltage and current data in the circuit fault state data set is converted to frequency domain for time-frequency analysis by using discrete wavelet transform, and the voltage and current data in the circuit fault state data set is decomposed into subbands of different hierarchical frequency domain components, to obtain hierarchical frequency domain component set; S3, based on the hierarchical frequency domain component set, determine the corresponding level of redundant feature amplitude threshold, and use the first preset fixed length sub-window to analyze the hierarchical frequency domain component set, fill the frequency domain components that meet the corresponding level of redundant feature amplitude threshold into the sub-window in ascending order, obtain the processed sub-window data of each level, and construct the circuit fault state data feature set based on the processed sub-window data of each level; S4, construct DCNN-BiLSTM model, and train DCNN-BiLSTM model according to circuit fault state data feature set, and output DCNN-BiLSTM model that meets the preset fault diagnosis accuracy as module electric fault diagnosis model, the DCNN-BiLSTM model is used to save the voltage and current data under corresponding frequency in the circuit fault state data feature set as two-dimensional matrix as the input information of DCNN module, and the input information of DCNN module is subjected to spatial feature extraction and local pattern mining, to obtain high-dimensional features, and the high-dimensional features are input into BiLSTM module, to analyze the time dynamic characteristics of voltage and current data, to obtain the time sequence features associated with circuit fault; S5, obtain target voltage and current data to be measured, and perform module electric fault diagnosis on target voltage and current data to be measured according to module electric fault diagnosis model, to obtain fault type classification result.

2. The method according to claim 1, wherein: The S1 comprises the following steps: S11, input circuit element parameters and circuit element topology structure in simulation software according to preset module electric diagnosis demand, to construct circuit simulation model; S12, based on circuit tolerance theory, set fault to circuit element parameters in circuit simulation model, to obtain fault working condition simulation model of multiple fault states; S13, determine the corresponding circuit fault test scheme based on the preset simulation condition, and input the excitation source parameters and measurement nodes in the fault working condition simulation model according to the circuit fault test scheme, to collect the voltage and current data of circuit output position; S14, standardize the voltage and current data to obtain standardized voltage and current data, and label the standardized voltage and current data to obtain the corresponding circuit fault state data set.

3. The method of claim 1, wherein: The S2 comprises the following steps: S21, determining a matching wavelet base function according to the circuit fault state data set, and determining a decomposition layer number of the discrete wavelet transform according to a sampling frequency of the circuit fault state data set, wherein a mathematical expression of the discrete wavelet transform is: , wherein, indicates a result of the discrete wavelet transform, j indicates a scaling parameter, and k indicates a translation parameter, indicates a normalization factor, indicates an input function, indicates a wavelet base function, indicates a complex conjugate function of the wavelet base function, and t indicates an integral variable; S22, wavelet basis function, decomposition level and voltage and current data in the circuit fault state data set are substituted into discrete wavelet transform for decomposition, to obtain time-frequency domain decomposition result containing approximation coefficient and detail coefficient; S23, decompose the time-frequency domain decomposition result into subbands of different level frequency domain components through a multi-level decomposition mechanism of discrete wavelet transform, and integrate the subbands of different level frequency domain components according to the level relationship to obtain a set of level frequency domain components.

4. The method of claim 1, wherein: The S3 comprises the following steps: S31, determine the maximum value of the redundant feature amplitude of the frequency signal based on each level frequency domain component, and determine the redundant feature amplitude threshold value of the corresponding level in combination with the amplitude range and noise range of the frequency signal; S32, analyze each level frequency domain component in the set of level frequency domain components using a first preset fixed-length sub-window, determine the level frequency domain component that meets the redundant feature amplitude threshold value of the corresponding level as the corresponding effective feature amplitude, fill the effective feature amplitude into the sub-window in ascending order of frequency, delete the level frequency domain component that does not meet the redundant feature amplitude threshold value of the corresponding level, and perform zero padding on the last position of the sub-window that is not filled, to obtain processed sub-window data of each level; S33, cascade and splice the processed sub-window data of each level and the low-frequency part data in the order of the decomposition level to form a second preset fixed-length total window data sequence, and construct a circuit fault state data feature set through the total window data sequence.

5. The method of claim 1, wherein: The S4 comprises the following steps: S41, convert the circuit fault state data feature set into a spatial feature input matrix conforming to the DCNN processing, construct a DCNN module, and extract spatial features from the spatial feature input matrix through multiple convolution kernels in the DCNN module to obtain a local spatial feature tensor containing voltage and current signals; S42, construct a BiLSTM module at the output end of the DCNN module, and process the local spatial feature tensor through the forward LSTM unit and the backward LSTM unit in the BiLSTM module to obtain a global time sequence feature vector; S43, perform dimension matching and feature integration on the local spatial feature tensor of the DCNN module and the global time sequence feature vector of the BiLSTM module through a fully connected layer to obtain an end-to-end DCNN-BiLSTM model; S44, divide the circuit fault state data feature set into a 70% data training set and a 30% data validation set; S45, input the data training set into the DCNN-BiLSTM model for iterative training, calculate the error between the prediction result of the DCNN-BiLSTM model and the true fault label using a cross-entropy loss function, and optimize the model parameters of the DCNN-BiLSTM model through a backpropagation algorithm; S46, input the data validation set into the trained DCNN-BiLSTM model for verification, and stop iterative training when the accuracy of the trained DCNN-BiLSTM model on the data validation set reaches a preset accuracy threshold to obtain a verified DCNN-BiLSTM model; S47, acquire a data test set according to the circuit simulation model, input the data test set into the verified DCNN-BiLSTM model for testing, and output the module electrical fault diagnosis model when the fault diagnosis accuracy of the verified DCNN-BiLSTM model on the data test set reaches a preset fault diagnosis accuracy threshold.

6. The method of claim 5, wherein: The S5 comprises the following steps: S51, acquire an original analog signal through the circuit simulation model, and perform data conversion on the original analog signal to obtain target voltage and current data to be measured; S52, perform time-frequency analysis on the target voltage and current data to be measured by using discrete wavelet transform to obtain a set of frequency domain components to be measured at a level, determine a redundant feature amplitude threshold value to be measured at the corresponding level based on the set of frequency domain components to be measured at the level, and analyze the set of frequency domain components to be measured at the level by using a first preset fixed-length sub-window, and fill the frequency domain components satisfying the redundant feature amplitude threshold value to be measured at the corresponding level in ascending order to obtain a circuit feature vector sequence to be measured; S53, input the circuit feature vector sequence to be measured into the module electrical fault diagnosis model, acquire multi-scale local features through a deep feature extraction layer of a DCNN module, and output a time sequence confidence distribution sequence of each fault type through a time sequence feature fusion layer of a BiLSTM module; S54, analyze the time sequence confidence distribution sequence based on a maximum a posteriori probability criterion to obtain a corresponding fault type classification result.

7. The method according to claim 6, wherein: The S53 comprises the following steps: S531, input the circuit feature vector sequence to be measured into a deep feature extraction layer of a DCNN module, analyze by multi-layer convolution operation, and generate multi-scale local features containing fault mode space distribution features through nonlinear activation and pooling operation; S532, input the multi-scale local features into a time sequence feature fusion layer of a BiLSTM module, analyze the time sequence evolution characteristics of the multi-scale local features, and obtain a time sequence confidence distribution sequence of each fault type.

8. The method of claim 6, wherein: The S54 comprises the following steps: S541, perform Bayesian posterior probability calculation on the fault type of each time step in the time sequence confidence distribution sequence based on the maximum a posteriori probability criterion to obtain a posterior probability value corresponding to each time step; S542, take the fault type corresponding to the maximum posterior probability value in each time step as a candidate fault type, and perform time sequence weighted fusion on the candidate fault type to obtain a fault type classification result.

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