Shifting register and control method thereof, scanning driving circuit, display panel and electronic equipment

Abstract

The invention provides a shift register and a control method thereof, a scanning driving circuit, a display panel and electronic equipment, relates to the technical field of electronic equipment, and is used for improving the stability and reliability of sub-pixel control by the scanning driving circuit. The shift register comprises a first output circuit, a second output circuit and a first control circuit. The first output circuit is configured to write a first voltage signal provided by a first voltage end into the output end of the shift register under the control of the voltage of the first node. And the second output circuit is configured to write a second voltage signal provided by a second voltage end into the output end of the shift register under the control of the voltage of the second node. The first control circuit is configured to pull down the voltage of the second node in the process that the output end outputs the first voltage signal to output the second voltage signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronic device, and in particular, to a shift register and a control method thereof, a scan driving circuit, a display panel and an electronic device. BACKGROUND

[0002] Electronic devices with display functions such as mobile phones and tablets are ubiquitous in people's daily work and life. Among them, the display function is realized by relying on a display panel. Specifically, the display panel is provided with a plurality of sub-pixels for emitting light, and each sub-pixel can be controlled to emit light by a scan driving circuit and a source integrated circuit (Source IC), and a plurality of sub-pixels collectively emit light to realize the display of a picture.

[0003] At present, the signals emitted by the scan driving circuit have steps, and the stability and reliability of the control of the sub-pixels are low. SUMMARY

[0004] Embodiments of the present application provide a shift register and a control method thereof, a scan driving circuit, a display panel and an electronic device, which are used to improve the stability and reliability of the control of the sub-pixels by the scan driving circuit.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a shift register is provided. The shift register includes a first node, a second node, a first voltage terminal, a second voltage terminal, an output terminal, a first output circuit, a second output circuit and a first control circuit. The first output circuit is coupled with the first node, the first voltage terminal and the output terminal. The first output circuit is configured to write a first voltage signal provided by the first voltage terminal to the output terminal under the control of the voltage of the first node. The second output circuit is coupled with the second node, the second voltage terminal and the output terminal. The second output circuit is configured to write a second voltage signal provided by the second voltage terminal to the output terminal under the control of the voltage of the second node; the voltage value of the second voltage signal is less than the voltage value of the first voltage signal. The first control circuit is configured to pull down the voltage of the second node in the process of switching from outputting the first voltage signal to outputting the second voltage signal at the output terminal.

[0007] The first control circuit further pulls down the voltage of the second node when the voltage of the second node is switched from the high voltage to the low voltage. Thus, the conduction degree of the second output circuit when the second output circuit connects the second voltage output end and the output end is increased, the transmission loss of the second voltage signal provided by the second voltage output end transmitted by the second output circuit is reduced or even eliminated, and the second output circuit can directly output the second voltage signal. The signal output by the output end of the actual shift register is the second voltage signal output by the second output circuit. Therefore, the output end of the shift register can directly output the second voltage signal (low voltage signal) provided by the second voltage end.

[0008] In this way, in the case that the output end of the shift register switches the output signal from the high voltage to the low voltage, there is no step problem, thereby improving the stability and reliability of the shift register (scan driving circuit) in controlling the pixel circuit.

[0009] In some possible implementation manners, the shift register further includes an input signal end, a first control source, a second control source, and a third control source. The first control circuit can include an input sub-circuit and a pull-down sub-circuit. The input sub-circuit is coupled with the input signal end, the third control source, and the second node. The input sub-circuit is configured to transmit, under control of a third control signal provided by the third control source, an input signal provided by the input signal end to the second node. The pull-down sub-circuit is coupled with the first control source, the second control source, the first voltage end, and the second node. The pull-down sub-circuit is configured to pull down the voltage of the second node in a process in which the input sub-circuit writes the input signal to the second node.

[0010] By pulling down the voltage of the second node written by the input sub-circuit through the pull-down sub-circuit, the voltage of the second node can be further reduced when the second node is switched from the high voltage to the low voltage, thereby reducing or even eliminating the transmission loss of the second voltage signal provided by the second voltage end transmitted by the second output circuit. The second output circuit can directly output the second voltage signal. In this way, the output end of the shift register can also directly output the second voltage signal (low voltage signal) provided by the second voltage end.

[0011] In some possible implementation manners, the shift register further includes a third node. The pull-down sub-circuit can include a first voltage regulating unit, a second voltage regulating unit and a pull-down unit. The first voltage regulating unit is coupled with the first voltage terminal, the third node and a first control source. The first voltage regulating unit is configured to write, under control of a first control signal provided by the first control source, a first voltage signal provided by the first voltage terminal to the third node. The second voltage regulating unit is coupled with the second control source, the third node and a second node. The second voltage regulating unit is configured to write, under control of a voltage of the second node, a second control signal provided by the second control source to the third node. The pull-down unit is coupled with the third node and the second node. The pull-down unit is configured to pull down the voltage of the second node in a case where the voltage of the third node drops.

[0012] The first voltage regulating unit can write the first voltage signal (high voltage signal) to the third node before the first output circuit switches from providing the first voltage signal to the output terminal to the second output circuit providing the second voltage signal to the output terminal. The second voltage regulating unit can write the second voltage signal (low voltage signal) to the third node in a case where the first output circuit switches from providing the first voltage signal to the output terminal to the second output circuit providing the second voltage signal to the output terminal. At this time, the voltage of the third node drops.

[0013] The pull-down unit is connected to the third node side, and the voltage of the second node side connected to the pull-down unit is pulled down synchronously, so as to pull down the voltage of the second node. In this way, the second output circuit can directly output the second voltage signal, and the output terminal of the shift register can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal. The process of switching the signal output by the output terminal of the shift register from the high voltage signal to the low voltage signal does not have a step problem, thereby improving the stability and reliability of the shift register (scanning driving circuit) in controlling the pixel circuit.

[0014] In some possible implementation manners, the first voltage regulating unit includes a first control transistor. The first control transistor is coupled with the first voltage terminal at a first electrode, coupled with the third node at a second electrode, and coupled with the first control source at a control electrode. The first control transistor is configured to write, under control of the first control signal provided by the first control source, the first voltage signal provided by the first voltage terminal to the third node.

[0015] The first control transistor writes the first voltage signal (high voltage signal) to the third node when in the on state, and the first control transistor does not lower the voltage of the third node when in the off state. Therefore, the first control transistor only functions to pull up or maintain the high voltage of the third node.

[0016] In some possible implementations, the second voltage regulating unit includes a second control transistor. A first electrode of the second control transistor is coupled with the second control source, a second electrode of the second control transistor is coupled with the third node, and a control electrode of the second control transistor is coupled with the second node. The second control transistor is configured to write the second control signal provided by the second control source to the third node under control of the voltage of the second node.

[0017] The second control transistor writes the second control signal to the third node when in the on state. The second control signal can be a high voltage signal or a low voltage signal. Therefore, the second control transistor can maintain a high voltage or pull down to a low voltage for the voltage of the third node.

[0018] In some possible implementations, the pull-down unit includes a capacitor. A first plate of the capacitor is coupled with the third node, and a second plate of the capacitor is coupled with the second node. The capacitor is configured to pull down the voltage of the second node in the case that the voltage of the third node drops.

[0019] The capacitor can change (drop) the voltage of the other plate synchronously when the voltage of any plate changes (drops). Therefore, the capacitor can pull down the voltage of the second node synchronously in the case that the second control transistor pulls down the voltage of the third node.

[0020] In some possible implementations, the input sub-circuit includes a first input transistor. A first electrode of the first input transistor is coupled with the input signal terminal, a second electrode of the first input transistor is coupled with the second node, and a control electrode of the first input transistor is coupled with the third control source. The first input transistor is configured to write the input signal provided by the input signal terminal to the second node under control of the third control signal provided by the third control source.

[0021] In some possible implementations, the input sub-circuit includes a first input transistor and a second input transistor. A first electrode of the first input transistor is coupled with the input signal terminal, a second electrode of the first input transistor is coupled with a first electrode of the second input transistor, a control electrode of the first input transistor is coupled with the third control source, a second electrode of the second input transistor is coupled with the second node, and a control electrode of the second input transistor is coupled with the second electrode of the first input transistor. The first input transistor and the second input transistor are both in the on state to write the input signal provided by the input signal terminal to the second node under control of the third control signal provided by the third control source and the input signal provided by the input signal terminal.

[0022] In some possible implementations, the shift register further includes a first clock signal terminal and a first input circuit. The first input circuit is coupled with the first clock signal terminal, the input signal terminal and the second node. The first input circuit is configured to write, under control of a first clock signal provided by the first clock signal terminal, an input signal provided by the input signal terminal to the second node.

[0023] The first input circuit can adjust the voltage of the second node under control of the first clock signal.

[0024] In some possible implementations, the first input circuit includes a second input transistor. A first electrode of the second input transistor is coupled with the input signal terminal, a second electrode of the second input transistor is coupled with the second node, and a control electrode of the second input transistor is coupled with the first clock signal terminal. The second input transistor is configured to write, under control of a first clock signal provided by the first clock signal terminal, an input signal provided by the input signal terminal to the second node.

[0025] In some possible implementations, the shift register further includes a third clock signal terminal and a fourth clock signal terminal. The first control source includes the first clock signal terminal, the second control source includes the fourth clock signal terminal, and the third control source includes the third clock signal terminal.

[0026] The first control circuit can be coupled with the first clock signal terminal, the first voltage terminal, the third clock signal terminal, the fourth clock signal terminal, the second node and the input signal terminal respectively. The first control circuit is configured to pull down the voltage of the second node under control of a first clock signal provided by the first clock signal terminal and a third clock signal provided by the third clock signal terminal. Illustratively, the first control circuit pulls down the voltage of the second node in a case where a waveform output by the output terminal of the shift register switches from a high voltage to a low voltage.

[0027] In some examples, the first control circuit includes an input sub-circuit and a pull-down sub-circuit. The input sub-circuit and the pull-down sub-circuit are both coupled with the second node. The pull-down sub-circuit is coupled with the first clock signal terminal, the second node, the first voltage terminal and the fourth clock signal terminal respectively. The pull-down sub-circuit is configured to pull down the voltage of the second node under control of a first clock signal provided by the first clock signal terminal and the voltage of the second node.

[0028] The first voltage regulating unit in the pull-down sub-circuit is coupled with the first clock signal terminal, the first voltage terminal and the third node respectively. The first voltage regulating unit is configured to write the first voltage signal provided by the first voltage terminal to the third node under the control of the first clock signal provided by the first clock signal terminal. Illustratively, before the waveform output by the output terminal of the shift register switches from high voltage to low voltage, the first voltage regulating unit writes the first voltage signal provided by the first voltage terminal to the third node under the control of the first clock signal provided by the first clock signal terminal.

[0029] In some possible implementation manners, the shift register further includes a fourth node, a second clock signal terminal, a second input circuit, a second control circuit and a third control circuit. The second input circuit is coupled with the second voltage terminal, the first clock signal terminal and the fourth node. The second input circuit is configured to write the second voltage signal provided by the second voltage terminal to the fourth node under the control of the first clock signal provided by the first clock signal terminal. The second control circuit is coupled with the fourth node, the second clock signal terminal and the first node. The second control circuit is configured to write the second clock signal provided by the second clock signal terminal to the first node under the control of the voltage of the fourth node and the second clock signal provided by the second clock signal terminal. The third control circuit is coupled with the second node, the first voltage terminal and the first node. The third control circuit is configured to write the first voltage signal provided by the first voltage terminal to the first node under the control of the voltage of the second node.

[0030] The second input circuit, the second control circuit and the third control circuit can adjust the voltage of the first node under the control of the voltage of the second node and the second clock signal provided by the second clock signal terminal.

[0031] In some possible implementation manners, the shift register further includes a third clock signal terminal and a fourth clock signal terminal. The first control source includes the second clock signal terminal, the second control source includes the fourth clock signal terminal, and the third control source includes the third clock signal terminal.

[0032] The first control circuit can be coupled with the second clock signal terminal, the first voltage terminal, the third clock signal terminal, the fourth clock signal terminal, the second node and the input signal terminal respectively. The first control circuit is configured to pull down the voltage of the second node under the control of the second clock signal provided by the second clock signal terminal and the third clock signal provided by the third clock signal terminal. Illustratively, in the case where the waveform output by the output terminal of the shift register switches from high voltage to low voltage, the first control circuit pulls down the voltage of the second node.

[0033] In some examples, the first control circuit includes an input sub-circuit and a pull-down sub-circuit. The input sub-circuit and the pull-down sub-circuit are coupled with the second node. The pull-down sub-circuit is coupled with the second clock signal terminal, the second node, the first voltage terminal and the fourth clock signal terminal respectively. The pull-down sub-circuit is configured to pull down the voltage of the second node under the control of the second clock signal provided by the second clock signal terminal and the voltage of the second node.

[0034] The pull-down sub-circuit can include a first voltage regulating unit, a second voltage regulating unit and a first pull-down unit. The first voltage regulating unit is coupled with the second clock signal terminal, the first voltage terminal and the third node respectively. The first voltage regulating unit is configured to write the first voltage signal provided by the first voltage terminal to the third node under the control of the second clock signal provided by the second clock signal terminal. Illustratively, before the waveform output by the output terminal of the shift register switches from the high voltage to the low voltage, the first voltage regulating unit writes the first voltage signal provided by the first voltage terminal to the third node under the control of the second clock signal provided by the second clock signal terminal.

[0035] In some possible implementations, the first control source includes the second clock signal terminal, the second control source includes the first clock signal terminal, and the third control source includes the first clock signal terminal.

[0036] The first control circuit can be coupled with the second clock signal terminal, the first voltage terminal, the first clock signal terminal, the second node and the input signal terminal respectively. The first control circuit is configured to pull down the voltage of the second node under the control of the second clock signal provided by the second clock signal terminal and the first clock signal provided by the first clock signal terminal. Illustratively, in the case that the waveform output by the output terminal of the shift register switches from the high voltage to the low voltage, the first control circuit pulls down the voltage of the second node.

[0037] The first control circuit includes an input sub-circuit and a pull-down sub-circuit. The input sub-circuit and the pull-down sub-circuit are coupled with the second node. The input sub-circuit is coupled with the first clock signal terminal, the input signal terminal and the second node respectively. The input sub-circuit is configured to write the input signal provided by the input signal terminal to the second node under the control of the first clock signal provided by the first clock signal terminal. The pull-down sub-circuit is coupled with the second clock signal terminal, the second node, the first voltage terminal and the first clock signal terminal respectively. The pull-down sub-circuit is configured to pull down the voltage of the second node under the control of the second clock signal provided by the second clock signal terminal and the voltage of the second node.

[0038] In some examples, the pull-down sub-circuit includes a first voltage regulating unit, a second voltage regulating unit and a first pull-down unit. The first voltage regulating unit is coupled with the second clock signal terminal, the first voltage terminal and the third node respectively. The first voltage regulating unit is configured to write the first voltage signal provided by the first voltage terminal to the third node under control of the second clock signal provided by the second clock signal terminal. The second voltage regulating unit is coupled with the first clock signal terminal, the third node and the second node respectively. The second voltage regulating unit is configured to write the first clock signal provided by the first clock signal terminal to the third node under control of the voltage of the second node. The first pull-down unit is coupled with the third node and the second node respectively. The first pull-down unit is configured to pull down the voltage of the second node in case that the voltage of the third node drops.

[0039] In some possible implementation manners, the shift register further includes a third clock signal terminal and a fourth clock signal terminal. The first control source includes a fourth node, the second control source includes the fourth clock signal terminal, and the third control source includes the third clock signal terminal.

[0040] The input sub-circuit is coupled with the third clock signal terminal, the input signal terminal and the second node. The input sub-circuit is configured to write the input signal provided by the input signal terminal to the second node under control of the third clock signal provided by the third clock signal terminal.

[0041] The pull-down sub-circuit is coupled with the fourth node, the first voltage terminal, the fourth clock signal terminal and the second node respectively. The pull-down sub-circuit is configured to pull down the voltage of the second node in case that the first output circuit provides the first voltage signal to the output terminal switches to the second output circuit providing the second voltage signal to the output terminal under control of the voltage of the fourth node and the voltage of the second node.

[0042] In some examples, the pull-down sub-circuit includes a first voltage regulating unit, a second voltage regulating unit and a first pull-down unit. The first voltage regulating unit is coupled with the fourth node, the first voltage terminal and the third node respectively. The first voltage regulating unit is configured to write the first voltage signal provided by the first voltage terminal to the third node under control of the voltage of the fourth node. The second voltage regulating unit is coupled with the fourth clock signal terminal, the third node and the second node respectively. The second voltage regulating unit is configured to write the fourth clock signal provided by the fourth clock signal terminal to the third node under control of the voltage of the second node. The first pull-down unit is coupled with the third node and the second node respectively. The first pull-down unit is configured to pull down the voltage of the second node in case that the voltage of the third node drops.

[0043] In some possible implementation manners, the second input circuit includes a third input transistor. A first electrode of the third input transistor is coupled with the second voltage terminal, a second electrode of the third input transistor is coupled with the fourth node, and a control electrode of the third input transistor is coupled with the first clock signal terminal. The third input transistor is configured to write, under control of a first clock signal provided by the first clock signal terminal, the second voltage signal provided by the second voltage terminal to the fourth node.

[0044] In some possible implementation manners, the shift register further includes a protection circuit and a sixth node. The protection circuit is connected in series between the second input circuit and the second control circuit. The protection circuit is coupled with the fourth node, the sixth node, and the second voltage terminal; the second control circuit is directly coupled with the sixth node and indirectly coupled with the fourth node. The protection circuit is configured to write, under control of the second voltage signal provided by the second voltage terminal, the voltage of the fourth node to the sixth node.

[0045] In some possible implementation manners, the shift register further includes a third clock signal terminal and a fourth clock signal terminal. The first control source includes the sixth node, the second control source includes the fourth clock signal terminal, and the third control source includes the third clock signal terminal.

[0046] Since the protection circuit writes the voltage of the fourth node to the sixth node for a long time, the case that the first control source includes the sixth node is consistent with the case that the first control source includes the fourth node, which will not be described here.

[0047] In some possible implementation manners, the signal provided by the second control source is the same as the signal provided by the third control source.

[0048] Exemplarily, in the case that the second control source includes the fourth clock signal terminal and the third control source includes the third clock signal terminal, the third clock signal terminal can be reset by the fourth clock signal terminal. Understandably, the second control signal provided by the second control source and the third control signal provided by the third control source are both the third clock signal provided by the third clock signal terminal.

[0049] In a second aspect, a control method of a shift register is provided. The shift register includes any of the shift registers in the first aspect. The method includes: in a process in which the first voltage signal output by the output terminal is switched to the second voltage signal, the first control circuit pulls down the voltage of the second node.

[0050] In some possible implementation manners, the pull-down sub-circuit can include a first voltage regulating unit, a second voltage regulating unit and a pull-down unit. The first voltage regulating unit is coupled with the first voltage terminal, the third node and a first control source. The first voltage regulating unit is configured to write, under control of a first control signal provided by the first control source, a first voltage signal provided by the first voltage terminal to the third node. The second voltage regulating unit is coupled with the second control source, the third node and a second node. The second voltage regulating unit is configured to write, under control of a voltage of the second node, a second control signal provided by the second control source to the third node. The pull-down unit is coupled with the third node and the second node. The pull-down unit is configured to pull down the voltage of the second node in a case where the voltage of the third node drops.

[0051] Before the output terminal outputs the first voltage signal switching to the second voltage signal, the method further includes: the first voltage regulating unit writes a high voltage signal to the third node. The first control circuit pulling down the voltage of the second node includes: the second voltage regulating unit writes a low voltage signal to the third node, and the input sub-circuit writes a low voltage signal to the second node, and the pull-down unit pulls down the voltage of the second node in a case where the voltage of the third node drops.

[0052] In a third aspect, a scan driving circuit is provided. The scan driving circuit includes a plurality of shift registers cascaded with each other. At least one of the shift registers is the shift register of any one of the first aspect.

[0053] In a fourth aspect, a display panel is provided. The display panel includes a plurality of sub-pixels and a scan driving circuit. The plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns. The scan driving circuit is coupled with the plurality of sub-pixels through a plurality of scan signal lines. Each scan signal line is coupled with a plurality of sub-pixels located in a same row. At least one of the scan driving circuits includes the scan driving circuit of the third aspect.

[0054] In a fifth aspect, an electronic device is provided. The electronic device includes a display panel and a processor. The display panel includes the display panel of the fourth aspect. The processor provides display data to the display panel.

[0055] It can be understood that the beneficial effects of the shift register control method of the second aspect, the scan driving circuit of the third aspect, the display panel of the fourth aspect, and the electronic device of the fifth aspect can refer to the beneficial effects of the first aspect and any one of the shift registers, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 FIG. 1 is a structural schematic diagram of a display panel;

[0057] Figure 2 FIG. 2 is a structural schematic diagram of a shift register; Figure 1Circuit structure diagram of one sub-pixel in middle AA region;

[0058] Figure 3 For Figure 2 Timing diagram of multiple signals of the sub-pixel shown in middle AA region under normal refresh in one frame refresh period;

[0059] Figure 4 Two waveform diagrams of the scan control signal which is the output of the shift register;

[0060] Figure 5 Structure schematic diagram of the scan driving circuit provided in some embodiments of the present application;

[0061] Figure 6 For Figure 5 Structure schematic diagram of the shift register shown in middle AA region;

[0062] Figure 7 For Figure 6 Structure schematic diagram of the shift register shown in middle AA region;

[0063] Figure 8 For Figure 6 Another structure schematic diagram of the shift register shown in middle AA region;

[0064] Figure 9 For Figure 8 Structure schematic diagram of the shift register shown in middle AA region;

[0065] Figure 10 For Figure 9 Timing diagram of multiple signal terminals and circuit nodes corresponding to the shift register shown in middle AA region;

[0066] Figure 11 For Figure 9 Working schematic diagram of the shift register shown in middle AA region in the first stage or the fourth stage;

[0067] Figure 12 For Figure 9 Working schematic diagram of the shift register shown in middle AA region in the second stage;

[0068] Figure 13 For Figure 9 Working schematic diagram of the shift register shown in middle AA region in the third stage;

[0069] Figure 14 For Figure 9 Working schematic diagram of the shift register shown in middle AA region in the fifth stage;

[0070] Figure 15 For Figure 9 Working schematic diagram of the shift register shown in middle AA region in the sixth stage;

[0071] Figure 16 for Figure 9 The diagram shown illustrates the operation of the shift register in its seventh stage.

[0072] Figure 17 for Figure 9 The diagram shown illustrates the operation of the shift register in its eighth stage.

[0073] Figure 18 for Figure 9 The diagram shown illustrates the operation of the shift register in its ninth stage.

[0074] Figure 19 for Figure 8 The diagram shows another possible structure of the shift register.

[0075] Figure 20 for Figure 8 The diagram shows another possible structure of the shift register.

[0076] Figure 21 for Figure 20 The diagram shown illustrates the operation of the shift register in its seventh stage.

[0077] Figure 22 for Figure 20 The diagram shown illustrates the operation of the shift register in its eighth stage.

[0078] Figure 23 for Figure 8 The diagram shows another possible structure of the shift register.

[0079] Figure 24 for Figure 23 The diagram shown illustrates the operation of the shift register in its seventh stage.

[0080] Figure 25 for Figure 23 The diagram shown illustrates the operation of the shift register in its eighth stage.

[0081] Figure 26 for Figure 8 The diagram shows another possible structure of the shift register.

[0082] Figure 27 for Figure 26 The diagram shown illustrates the operation of the shift register in its seventh stage.

[0083] Figure 28 for Figure 26 The diagram shown illustrates the operation of the shift register in its eighth stage.

[0084] Figure 29 for Figure 26 The diagram shown illustrates the operation of the shift register in its ninth stage.

[0085] Figure 30 for Figure 8 a working schematic diagram of the shift register shown in

[0086] Figure 31 for Figure 30 a working schematic diagram of the shift register shown in

[0087] Figure 32 for Figure 30 a working schematic diagram of the shift register shown in

[0088] Figure 33 for

[0089] Figure 34 for Figure 9 a working schematic diagram of the shift register shown in

[0090] Figure 35 for

[0091] Figure 36 for

[0092] Figure 37 for Figure 5 a working schematic diagram of the shift register shown in

[0093] Figure 38 for

[0094] Figure 39 for

[0095] Figure 40 for Figure 39 a working schematic diagram of the shift register shown in DETAILED DESCRIPTION

[0096] In the following, the technical solutions in the embodiments of the present application will be described with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments provided in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0097] Hereinafter, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0098] In addition, in the present application, the orientation terms such as "upper", "lower", "left", "right" and the like can include but not limited to the orientation defined by the relative position of the components shown in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the position of the components shown in the drawings.

[0099] In describing some embodiments, "connection", "connected" and their derivatives can be used. For example, the term "connected" can be used to describe some embodiments to indicate that two or more components have direct or indirect physical contact with each other. For example, A and B are connected, which can mean that A and B are connected, or A and B are connected through other components. In addition, the term "coupled" can be an electrical connection mode for realizing signal transmission, and the coupling can mean direct coupling or indirect coupling.

[0100] "A, B and C at least one of them" has the same meaning as "at least one of A, B or C", which includes the following combinations of A, B and C: only A, only B, only C, combination of A and B, combination of A and C, combination of B and C, and combination of A, B and C.

[0101] "A and / or B" includes the following three combinations: only A, only B, and combination of A and B.

[0102] As used herein, "about", "approximately" or "nearly" includes the stated value and the average value within an acceptable deviation range of the specific value, wherein the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e. the limitation of the measurement system).

[0103] The transistor mentioned in the present document can be a thin film transistor (TFT), a triode, a metal-oxide-semiconductor field-effect transistor (MOSFET, referred to as MOS tube), etc., which is not limited herein. In the case of TFT, the transistor can be a low temperature poly-silicon (LTPS) TFT.

[0104] In addition, the high voltage signal and the low voltage signal mentioned in the present document are only a relative concept of high and low. The high voltage signal can be a signal greater than 0V or a signal less than 0V; similarly, the low voltage signal can be a signal greater than 0V or a signal less than 0V.

[0105] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all.

[0106] The current electronic device generally includes a display panel. The display panel can be used to display images, text, videos and other information, thereby realizing information interaction between the electronic device and the user.

[0107] The display panel described above can be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel, etc., which is not limited in the present disclosure.

[0108] For ease of understanding, the structure of the display panel will be introduced below by taking the display panel described above as an OLED display panel.

[0109] Figure 1 A structural schematic diagram of a display panel is shown. The display panel PNL includes a display area (active area, AA; referred to as AA area; also referred to as effective display area) and a peripheral area SA located at least one side (such as left side, right side or around) of the AA area.

[0110] The aforementioned display panel PNL includes multiple color sub-pixels in the AA area. These multiple color sub-pixels include at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color, the second color, and the third color can be three primary colors (e.g., red, green, and blue).

[0111] For ease of explanation, the above-mentioned multiple sub-pixels P are illustrated using a matrix arrangement as an example. In this case, sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row; sub-pixels P arranged in a row along the vertical direction Y are called sub-pixels in the same column.

[0112] The AA area may also include multiple scan signal lines connected to the sub-pixels of the multiple rows respectively. For example, the multiple scan signal lines include multiple enable signal lines L-EM connected to the sub-pixels of the multiple rows respectively, multiple first reset signal lines L-ResetN connected to the sub-pixels of the multiple rows respectively, multiple second reset signal lines L-ResetP connected to the sub-pixels of the multiple rows respectively, multiple first gate lines L-GateP connected to the sub-pixels of the multiple rows respectively, and multiple second gate lines L-GateN connected to the sub-pixels of the multiple rows respectively.

[0113] Any one of the enable signal line L-EM, the first reset signal line L-ResetN, the second reset signal line L-ResetP, the first gate line L-GateP, and the second gate line L-GateN extends along the first direction X, and multiple lines are arranged side by side along the second direction Y.

[0114] The AA area may also include multiple data signal lines L-Data that are connected to multiple columns of sub-pixels respectively.

[0115] Each sub-pixel may include pixel circuits and light-emitting elements with circuit structures such as 7T1C (where T represents a transistor and C represents a capacitor), 7T2C, 8T1C, 8T2C or 4T1C, which are available in the art.

[0116] in addition, Figure 1 The example described uses the first direction X and the second direction Y as being perpendicular to each other. In other examples, the first direction X and the second direction Y may also be an angle forming 80°, 75° or other angles, which is not limited here.

[0117] like Figure 1 As shown, the surrounding area SA may include a first scan driving circuit 21, a second scan driving circuit 22, a third scan driving circuit 23, a fourth scan driving circuit 24, and a fifth scan driving circuit 25.

[0118] In some examples, the first scan driving circuit 21 can be connected with a plurality of enable signal lines L-EM to provide enable signals to a plurality of rows of sub-pixels respectively. Since the first scan driving circuit 21 is used to drive the enable sub-circuit of the sub-pixel, the first scan driving circuit 21 can also be referred to as an emission gate driver on array (EM GOA).

[0119] In some examples, the second scan driving circuit 22 can be located at a side of the first scan driving circuit 21 close to the display area AA and connected with a plurality of reset signal lines L-ResetN to provide first reset signals to a plurality of rows of sub-pixels respectively. The second scan driving circuit 22 is used to drive the N-type thin film transistor (TFT) in the sub-pixel, and therefore, the second scan driving circuit 22 can also be referred to as an N-type reset scan driving circuit Reset-N GOA.

[0120] In some examples, the third scan driving circuit 23 can be located at a side of the second scan driving circuit 22 close to the display area AA and connected with a plurality of first gate lines L-GateP to provide first gate signals to a plurality of rows of sub-pixels respectively. For example, the third scan driving circuit 23 provides the first gate signal for the P-type transistor in the sub-pixel, and therefore, the third scan driving circuit 23 can also be referred to as a P-type gate scan driving circuit Gate-P GOA.

[0121] In some examples, the peripheral area SA can further include a fourth scan driving circuit 24. The fourth scan driving circuit 24 is located at a side of the display area AA away from the first scan driving circuit 21. The fourth scan driving circuit 24 can be connected with a plurality of second reset signal lines L-ResetP to provide second reset signals to a plurality of rows of sub-pixels respectively. The fourth scan driving circuit 24 is used to drive the P-type thin film transistor in the sub-pixel, and therefore, the fourth scan driving circuit 24 can also be referred to as a P-type reset scan driving circuit Reset-P GOA.

[0122] In some examples, the peripheral area SA can further include a fifth scan driving circuit 25. The fifth scan driving circuit 25 is located at a side of the fourth scan driving circuit 24 close to the display area AA and connected with a plurality of second gate lines L-GateN to provide second gate signals to a plurality of rows of sub-pixels respectively. For example, the fifth scan driving circuit 25 provides the second gate signal for the N-type transistor in the sub-pixel, and therefore, the fifth scan driving circuit 25 can also be referred to as an N-type gate scan driving circuit Gate-N GOA.

[0123] As Figure 1As shown, in some examples, the third scan driving circuit 23 can also be partially located between the first scan driving circuit 21 and the display region AA, and partially located between the fourth scan driving circuit 24 and the display region AA.

[0124] It should be noted that the embodiments of the present application do not limit the mutual positions of the first scan driving circuit 21, the second scan driving circuit 22, the third scan driving circuit 23, the fourth scan driving circuit 24 and the fifth scan driving circuit 25, and it should be understood that Figure 1 This is only a schematic of one arrangement position of the five scan driving circuits. In other embodiments of the present application, the first scan driving circuit 21, the second scan driving circuit 22, the third scan driving circuit 23, the fourth scan driving circuit 24 and the fifth scan driving circuit 25 can also have other positional relationships.

[0125] As Figure 1 shown, the non-display region SA can also include a source driving circuit (source integrated circuit, referred to as Source IC) 26. The source driving circuit 26 is coupled with the data line L-Data passing through the AA region along the second direction Y, and provides a data signal to the plurality of sub-pixels in the AA region through the data line L-Data. One data line L-Data provides a data signal for a column of sub-pixels arranged in an array, and a plurality of data lines L-Data provide data signals for different columns of sub-pixels. For example, the pixel circuit in the sub-pixel works under the control of the data signal transmitted through the data line and the gate signal and the enable signal transmitted through the scan signal line, to drive the light emitting element to emit light to realize display and other operations. The light emitting element can be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), and the embodiments of the present application do not limit this.

[0126] Figure 2 For Figure 1 a circuit structure diagram of a sub-pixel in the AA region. As Figure 2 shown, the sub-pixel P includes a light emitting element E and a pixel circuit M for driving the light emitting element E to emit light, and the pixel circuit M includes a driving sub-circuit 71, a data writing sub-circuit 72, a compensation sub-circuit 73, a reset sub-circuit 74, an enable sub-circuit 75 and a storage capacitor Cst.

[0127] The reset sub-circuit 74 includes a first reset sub-circuit 741, and the first reset sub-circuit 741 includes a first reset transistor BT1. The compensation sub-circuit 73 includes a compensation transistor BT2. The driving sub-circuit 71 includes a driving transistor BT3. The data writing sub-circuit 72 includes a data writing transistor BT4. The enable sub-circuit 75 includes a first enable sub-circuit 751 and a second enable sub-circuit 752, where the first enable sub-circuit 751 includes a first enable transistor BT5, and the second enable sub-circuit 752 includes a second enable transistor BT6. The reset sub-circuit 74 can further include a second reset sub-circuit 742, and the second reset sub-circuit 742 includes a second reset transistor BT7. The reset sub-circuit 74 can further include a third reset sub-circuit 743, and the third reset sub-circuit 743 includes a third reset transistor BT8.

[0128] Since the low temperature polycrystalline oxide (LTPO) has better anti-leakage performance than the low temperature poly silicon (LTPS) commonly used at present, the use of the LTPS transistor in the pixel circuit can enable the pixel circuit to more accurately control the light-emitting device to emit light. However, the LTPO transistor is an N-type transistor. Therefore, in the embodiments of the present application, at least one of the above-mentioned plurality of transistors (BT1, BT2, …, BT8) can adopt an LTPO transistor (hereinafter referred to as an N-type transistor). For example, the first reset transistor BT1 and the compensation transistor BT2 are N-type transistors.

[0129] It should be noted that the connection relationship and working principle of the pixel unit in the embodiments of the present disclosure are only examples, and the pixel unit can also adopt other structures according to needs, which is not limited in the present disclosure.

[0130] As shown in FIG. 1, in some embodiments, the pixel circuit M is described as a whole: Figure 2

[0131] The control electrode of the first reset transistor BT1 is coupled with the reset signal line L-ResetN, and the first electrode of the first reset transistor BT1 is coupled with the first initial signal line L-Vinit1. The first reset transistor BT1 is configured to transmit the first initial signal provided by the first initial signal line L-Vinit1 to the first node N1 under the control of the first reset signal provided by the reset signal line L-ResetN.

[0132] ​A control electrode of the compensation transistor BT2 is coupled with the second gate line L-GateN, a first electrode of the compensation transistor BT2 is coupled with the third node N3, and a second electrode of the compensation transistor BT2 is coupled with the first node N1. The compensation transistor BT2 is configured to form a path between the first node N1 and the third node N3 under control of a second gate signal provided by the second gate line L-GateN.

[0133] A control electrode of the driving transistor BT3 is coupled with the first node N1, a first electrode of the driving transistor BT3 is coupled with the second node N2, and a second electrode of the driving transistor BT3 is coupled with the third node N3. The driving transistor BT3 is configured to form a path between the second node N2 and the third node N3 under control of a voltage of the first node N1.

[0134] A control electrode of the data write transistor BT4 is coupled with the first gate line L-GateP, a first electrode of the data write transistor BT4 is coupled with the data line L-Data, and a second electrode of the data write transistor BT4 is coupled with the second node N2. The data write transistor BT4 is configured to transmit a data signal provided by the data line L-Data to the second node N2 under control of a first gate signal provided by the first gate line L-GateP.

[0135] A control electrode of the first enable transistor BT5 is coupled with the enable signal line L-EM, a first electrode of the first enable transistor BT5 is coupled with the first power supply line L-VDD, and a second electrode of the first enable transistor BT5 is coupled with the second node N2. The first enable transistor BT5 is configured to transmit a first power signal provided by the first power supply line L-VDD to the second node N2 under control of an enable signal provided by the enable signal line L-EM.

[0136] A control electrode of the second enable transistor BT6 is coupled with the enable signal line L-EM, a first electrode of the second enable transistor BT6 is coupled with the third node N3, and a second electrode of the second enable transistor BT6 is coupled with the fourth node N4. The second enable transistor BT6 is configured to form a path between the third node N3 and the fourth node N4 under control of an enable signal provided by the enable signal line L-EM.

[0137] A control electrode of the second reset transistor BT7 is coupled with the second reset signal line L-ResetP, a first electrode of the second reset transistor BT7 is coupled with the second initial signal line L-Vinit2, and a second electrode of the second reset transistor BT7 is coupled with the fourth node N4. The second reset transistor BT7 is configured to transmit a second initial signal provided by the second initial signal line L-Vinit2 to the fourth node N4 under control of a second reset signal provided by the second reset signal line L-ResetP.

[0138] The control electrode of the third reset transistor BT8 is coupled to the second reset signal line L-ResetP, the first electrode of the third reset transistor BT8 is coupled to the third initial signal line L-Vinit3, and the second electrode of the third reset transistor BT8 is coupled to the second node N2. The third reset transistor BT8 is configured to transmit the third initial signal provided by the third initial signal line L-Vinit3 to the fourth node N2 under the control of the second reset signal provided by the second reset signal line L-ResetP.

[0139] In some embodiments, any scan driving circuit includes a plurality of cascaded shift registers, each shift register being used to drive one or more rows of subpixels. This application embodiment illustrates this by using each shift register to drive one row of subpixels, but this disclosure is not intended to limit the scope of the embodiments.

[0140] For example, the surrounding area may also include a first voltage signal line ( Figure 2 (not shown) and second voltage signal line ( Figure 2 (Not shown), a first voltage signal line is configured to provide a first voltage signal, and a second voltage signal line is configured to provide a second voltage signal. The voltage value of the first voltage signal is greater than the voltage value of the second voltage signal. A first scan drive circuit 21 is coupled to the first voltage signal line to output the first voltage signal as the first part of an enable signal EM. For example, the first voltage signal line is connected to multiple first shift registers in the first scan drive circuit 21. The first part of the enable signal is, for example, a high-voltage portion of the enable signal. For example, this high-voltage portion of the enable signal can cause the first enable transistor BT5 and the second enable transistor BT6 to be in a cut-off state during the light-emitting phase. The first scan drive circuit 21 is also coupled to the second voltage signal line to output the second voltage signal as the second part of the enable signal. For example, the second voltage signal line is coupled to multiple first shift registers in the first scan drive circuit 21. The second part of the enable signal is, for example, a low-voltage portion of the enable signal. For example, this low-voltage portion of the enable signal can cause the first enable transistor BT5 and the second enable transistor BT6 to be in a conduction state during the light-emitting phase. For ease of explanation, the first voltage signal will be referred to as the high voltage signal and the second voltage signal as the low voltage signal in this article.

[0141] Figure 3 It shows Figure 2 The diagram shown illustrates the timing of multiple signals for a sub-pixel during normal refresh within a single frame refresh cycle. The following section combines... Figure 3 The timing sequences of the multiple signals shown are for Figure 2 The operation of the sub-pixel within one frame refresh cycle is illustrated below. It can be seen that the pixel circuit M has five stages within one frame refresh cycle.

[0142] In the first stage T1, the enable signal EM is a high voltage signal, the first enable transistor BT5 and the second enable transistor BT6 are both in the off state. The first reset signal Reset-N is a low voltage signal, the first reset transistor BT1 is also in the off state. The second reset signal Reset-P is a low voltage signal, the second reset transistor BT7 is in the on state, the second initialization signal Vinit2 initializes the fourth node N4, and the third reset transistor BT8 is in the on state, the third initialization signal Vinit3 initializes the second node N2. The first gate signal Gate-P is a high voltage signal, the data write transistor BT4 is in the off state. The second gate signal Gate-N is a high voltage signal, the compensation transistor BT2 is in the on state, and the first node N1 is in the on state with the third node N3.

[0143] At this time, the first node N1 is at a low voltage, and the control drive transistor BT3 is in the on state. The second node N2 is in the on state with the third node N3 through the drive transistor BT3, and since the first node N1 is in the on state with the third node N3, the third initialization signal Vinit3 flows into the first node N1 through the second node N2 and the third node N3 in turn.

[0144] In the first stage T1, the third initialization signal Vinit3 gradually raises the voltage of the first node N1, and at the same time, the on state of the drive transistor BT3 gradually decreases. Until the voltage of the first node N1 is equal to the voltage of the third initialization signal Vinit3, the drive transistor BT3 is in the off state.

[0145] In the second stage T2, the enable signal EM is a high voltage signal, the first enable transistor BT5 and the second enable transistor BT6 continue to be in the off state. The first reset signal Reset-N is a high voltage signal, the first reset transistor BT1 is in the on state, the first initialization signal Vinit1 enters the first node N1, and the voltage of the first node N1 is pulled down to be equal to the voltage of the first initialization signal Vinit1. The second reset signal Reset-P is a high voltage signal, the second reset transistor BT7 and the third reset transistor BT8 are both in the off state. The first gate signal Gate-P is a high voltage signal, the data write transistor BT4 is in the off state. The second gate signal Gate-N is a low voltage signal, and the compensation transistor BT2 is in the off state.

[0146] In the process of pulling down the voltage of the first node N1, the first node N1 can control the drive transistor BT3 to be in the on state, and the second node N2 is in the on state with the third node N3.

[0147] In the third stage T3, the enable signal EM is a high voltage signal, the first enable transistor BT5 and the second enable transistor BT6 continue to be in the off state. The first reset signal Reset-N is a low voltage signal, the first reset transistor BT1 is also in the off state. The second reset signal Reset-P is a high voltage signal, the second reset transistor BT7 and the third reset transistor BT8 are both in the off state. The first gate signal Gate-P is a low voltage signal, the data write transistor BT4 is in the on state, and the data signal Data is written to the second node N2. The second gate signal Gate-N is a high voltage signal, and the compensation transistor BT2 is in the on state, and the third node N3 is connected to the first node N1.

[0148] In the second stage T2, the first node N1 controls the drive transistor BT3 to be in the on state, and the second node N2 is connected to the third node N3. Therefore, after the data signal Data is written to the second node N2 in the third stage T3, it can flow through the third node N3 into the first node N1 for storage. Therefore, the third stage T3 can also be called the data write stage.

[0149] In the fourth stage T4, the enable signal EM is a high voltage signal, the first enable transistor BT5 and the second enable transistor BT6 continue to be in the off state. The first reset signal Reset-N is a low voltage signal, the first reset transistor BT1 is also in the off state. The second reset signal Reset-P is a low voltage signal, the second reset transistor BT7 is in the on state, the second initialization signal Vinit2 initializes the fourth node N4, and the third reset transistor BT8 is in the on state, and the third initialization signal Vinit3 initializes the second node N2. The first gate signal Gate-P is a high voltage signal, and the data write transistor BT4 is in the off state. The second gate signal Gate-N is a low voltage signal, and the compensation transistor BT2 is in the off state.

[0150] In the fifth stage T5, the enable signal EM is a low voltage signal, the first enable transistor BT5 and the second enable transistor BT6 are both in the on state. The first reset signal Reset-N is a low voltage signal, the first reset transistor BT1 is in the off state. The second reset signal Reset-P is a high voltage signal, the second reset transistor BT7 and the third reset transistor BT8 are both in the off state. The first gate signal Gate-P is a high voltage signal, the data write transistor BT4 is in the off state. The second gate signal Gate-N is a low voltage signal, and the compensation transistor BT2 is in the off state.

[0151] In the fifth stage T5, the first enable transistor BT5, the second enable transistor BT6 and the driving transistor BT3 are all in the on state, so that the second voltage source VDD is in communication with the light emitting device E, so that the current is injected into the light emitting device E, and the light emitting device E is driven to emit light. Therefore, the fifth stage T5 can also be referred to as a light emitting stage.

[0152] In the fifth stage T5, the degree of conduction of the driving transistor BT3 is related to the data signal previously written into the first node N1, so that the data signal can control the size of the current injected into the light emitting device E.

[0153] It should be noted that, Figure 2 The pixel circuit M shown is only an example, and in some other examples, the pixel circuit M can also not have a third reset transistor BT8. In the case where the pixel circuit M does not have a third reset transistor BT8, the pixel circuit M can also not undergo the fourth stage T4 described above.

[0154] Figure 2 The pixel circuit M shown uses the fourth stage T4 mainly for initializing the voltages of the second node N2 and the fourth node N4. In different pixel circuits, due to the difference in the display of the previous frame of image, the voltages of the second node N2 and the fourth node N4 can have some impact on the performance of the driving transistor BT3, resulting in poor uniformity of the performance of the driving transistor BT3 in different pixel circuits. By initializing the voltages of the second node N2 and the fourth node N4 through the fourth stage T4, the uniformity of the performance of the driving transistor BT3 in different pixel circuits can be improved, thereby improving the uniformity of the display effect of the display panel.

[0155] It can be understood that in the fourth stage T4, the voltages of the second node N2 and the fourth node N4 are not initialized, and in the fifth stage, the first enable transistor BT5, the second enable transistor BT6 and the driving transistor BT3 can also be in the on state, and the current can be injected into the light emitting device E, and the light emitting device E can be driven to emit light.

[0156] It has been described above that the pixel circuit M can include N-type transistors. For example, Figure 2 The first reset transistor BT1 and the compensation transistor BT2 in the pixel circuit M are N-type transistors. When the shift register in the scan driving circuit (such as the second scan driving circuit 22 and the fifth scan driving circuit 25 described above) drives the N-type transistor, a high voltage signal needs to be output to control the N-type transistor to be in the on state, or a low voltage signal needs to be output to control the N-type transistor to be in the off state.

[0157] The shift register providing signals to the N-type transistor in the pixel circuit M includes P-type transistors inside. The P-type transistor is turned on when the voltage difference between the gate and the source of the P-type transistor is less than the threshold voltage (Vth). For example, when the Vth of the P-type transistor is -2V, the voltage difference between the gate and the source of the P-type transistor needs to be less than -2V to turn on the P-type transistor. In this case, the voltage of the gate needs to be lower than the voltage of the source.

[0158] When the P-type transistor transmits a low voltage signal, if the voltage of the low voltage signal is lower than the voltage of the gate of the P-type transistor, the low voltage signal needs to be transmitted from the drain to the source of the P-type transistor. In this case, the lowest voltage of the source of the P-type transistor needs to be higher than the voltage of the gate minus the threshold voltage of the P-type transistor (Vth). Because once the voltage of the source of the P-type transistor is lower than Vg-Vth, the P-type transistor will be turned off.

[0159] For example, when a low voltage first signal is input into the P-type transistor, the P-type transistor in the on state outputs a second signal. In this case, the Vth of the P-type transistor is -3V. When the voltage of the first signal and the voltage of the gate (Vg) are both -7V, the voltage of the second signal is -4V. Or, when the voltage of the first signal and the voltage of the gate (Vg) are both -10V, the voltage of the second signal is -7V.

[0160] As can be seen, when the P-type transistor transmits a low voltage signal, the threshold loss of the P-type transistor itself will cause the voltage signal output by the P-type transistor to be one threshold voltage lower than the voltage signal input into the P-type transistor.

[0161] Therefore, in order to overcome the problem of voltage loss caused by the threshold loss of the P-type transistor when transmitting a low voltage (VGL) signal, the current scanning driving circuit further pulls down the output voltage of the P-type transistor after the voltage loss of the output voltage of the P-type transistor, to overcome the problem of voltage loss caused by the P-type transistor when transmitting a low voltage signal.

[0162] For example, when the P-type transistor transmits a first voltage signal (VGL=-7V), the P-type transistor will initially output a lower voltage after voltage loss (for example, -4V), and then further pull down the output voltage of the P-type transistor, so that the P-type transistor outputs a voltage signal of -7V. In this way, the voltage waveform output by the P-type transistor has a step.

[0163] However, when the output end of the shift register is connected to the first voltage end through a P-type transistor, the synchronization will make the output waveform of the shift register also have a step because the output signal of the P-type transistor undergoes two voltage changes (i.e., the above-mentioned step), as shown in the waveform diagram in FIG. 8. Figure 4 As can be seen from (a) in FIG. 8, when the shift register switches from outputting a high-voltage signal to outputting a low-voltage signal, the output signal of the shift register has a step in the process of switching from a high voltage to a low voltage. Due to the existence of the step, the switching of the signal at the output end of the shift register may not be obvious, which causes the pixel circuit to fail to respond to the change of the signal at the output end of the shift register in time, and thus the pixel circuit has a control abnormality problem. Therefore, the existence of the step in the signal output by the shift register will reduce the stability and reliability of the control of the pixel circuit by the shift register (the scan driving circuit). Figure 4 Therefore, the embodiments of the present application provide a shift register, a scan driving circuit, a display panel, an electronic device, and a display method applied to an electronic device. By pulling down the voltage of the output signal of the P-type transistor at one time in the case that the P-type transistor transmits a low-voltage signal, the problem of the step in the process of switching the output signal of the shift register from a high-voltage signal to a low-voltage signal is avoided, and the stability and reliability of the control of the pixel circuit by the shift register (the scan driving circuit) are improved.

[0164] In the embodiments of the present application, before or at the same time when the P-type transistor starts to conduct and transmit a low-voltage signal, the capacitor is used to pull down the gate voltage of the P-type transistor, so that the voltage of the signal output by the P-type transistor at the beginning is equal to the voltage of the first electrode of the P-type transistor (as shown in (b) in FIG. 8), and the voltage will not undergo two changes. In this way, the output signal provided by the P-type transistor at the output end of the shift register will not have the problem of the step in the process of switching from a high-voltage signal to a low-voltage signal, and thus the stability and reliability of the control of the pixel circuit by the shift register (the scan driving circuit) are improved.

[0165] Figure 4 Taking the threshold voltage of the P-type transistor as -2V as an example: originally, the gate voltage of the P-type transistor is -7V, and the P-type transistor transmits a second voltage signal VGL of -7V, and thus the voltage of the signal output by the P-type transistor is -5V. In the embodiments of the present application, before or at the same time when the P-type transistor starts to conduct and transmit a low-voltage signal, the capacitor is used to pull down the gate voltage of the P-type transistor to -9V, and thus the voltage of the signal output by the P-type transistor at the beginning can be -7V, which is equal to the voltage of the second voltage signal VGL.

[0166] Taking the threshold voltage of the P-type transistor as -2V as an example: originally, the gate voltage of the P-type transistor is -7V, and the P-type transistor transmits a second voltage signal VGL of -7V, and thus the voltage of the signal output by the P-type transistor is -5V. In the embodiments of the present application, before or at the same time when the P-type transistor starts to conduct and transmit a low-voltage signal, the capacitor is used to pull down the gate voltage of the P-type transistor to -9V, and thus the voltage of the signal output by the P-type transistor at the beginning can be -7V, which is equal to the voltage of the second voltage signal VGL.

[0167] ​In this way, the output signal provided by the P-type transistor of the output of the shift register will not have a step problem in the process of switching from a high voltage signal to a low voltage signal, thereby improving the stability and reliability of the shift register (scanning driving circuit) in controlling the pixel circuit.

[0168] The structure of the second scanning driving circuit 22 providing the first reset signal to the first reset transistor BT1 in the pixel circuit M, and the fifth scanning driving circuit 25 providing the second gate signal to the compensation transistor BT2 in the pixel circuit M will be described in detail below.

[0169] Please refer to Figure 5 , Figure 5 The structure of the second scanning driving circuit provided in some embodiments of the present application is shown.

[0170] The second scanning driving circuit 22 includes n-stage cascaded shift registers (RS1, RS2, …, RS(n)); in this case, the display panel includes n first reset signal lines (L-ResetN) respectively and one-to-one coupled with the N-stage cascaded shift registers (RS1, RS2, …, RS(n)).

[0171] In addition, as Figure 5 shown, the shift registers (RS1, RS2, …, RS(n)) of the second scanning driving circuit 22 of some embodiments of the present disclosure are also provided with an input signal end Vin, a first clock signal end CK, a second clock signal end CB, a first voltage end (not shown in Figure 5 ), a second voltage end (not shown in Figure 5 ), a third clock signal end CCK, a fourth clock signal end CCB, and an output end OUT, and the circuit structure of each stage of shift registers in the second scanning driving circuit 22 can be the same.

[0172] On this basis, in the above-mentioned second scanning driving circuit 22, the signal input end Vin of the previous stage or multiple stages of shift registers is coupled with the frame start signal end ESTV, and the signal input end Vin of the subsequent stage of shift registers is coupled with the input signal end OUT of the previous stage of shift registers, except for the shift register coupled with the frame start signal end ESTV; here, the previous stage of shift registers and the subsequent stage of shift registers can be the shift registers located in adjacent stages, or can not be the shift registers located in adjacent stages.

[0173] Exemplarily, as Figure 5As shown in the second scanning driving circuit 22, the input signal terminal Vin of the first stage shift register RS1 is coupled with the frame start signal terminal ESTV, the input signal terminal Vin of the second stage shift register RS2 is coupled with the signal output terminal OUT of the first stage shift register RS1, and the signal output terminal Oput of the i-th stage shift register RS1 is coupled with the input signal terminal Vin of the (i+1)-th stage shift register RS(i+1), where 2≤i≤N-1, N is an integer.

[0174] As shown in the second scanning driving circuit 22, Figure 5 As shown in the second scanning driving circuit 22, the first clock signal terminal CK of the shift register is coupled with the first system clock signal line L-CK extending along the second direction Y; the second clock signal terminal CB of the shift register is coupled with the second system clock signal line L-CB extending along the second direction Y; the third clock signal terminal CCK of the shift register is coupled with the third clock signal line L-CCK (or L-CCK’) extending along the second direction Y; and the fourth clock signal terminal CCB of the shift register is coupled with the fourth clock signal line L-CCB (or L-CCB’) extending along the second direction Y.

[0175] The third clock signal on the third clock signal line L-CCK and the third clock signal on the third clock signal line L-CCK’ are inverse signals of each other. The third clock signal line L-CCK and the third clock signal line L-CCK’ are coupled with two adjacent shift registers respectively. Similarly, the fourth clock signal on the fourth clock signal line L-CCB and the fourth clock signal on the fourth clock signal line L-CCB’ are inverse signals of each other. The fourth clock signal line L-CCB and the fourth clock signal line L-CCB’ are coupled with two adjacent shift registers respectively.

[0176] It should be noted that the first system clock signal on the first system clock signal line L-CK and the second system clock signal on the second system clock signal line L-CB are inverse signals of each other. The first clock signal terminal CK of the odd-numbered shift register is coupled with the first system clock signal line L-CK, and the second clock signal terminal CB of the even-numbered shift register is coupled with the first system clock signal line L-CK. It can be understood that the first system clock signal on the first system clock signal line L-CK acts as the first clock signal in the odd-numbered shift register, and the same signal acts as the second clock signal in the even-numbered shift register.

[0177] Similarly, the second clock signal terminal CB of the odd-numbered shift register is coupled to the second system clock signal line L-CB, and the first clock signal terminal CK of the even-numbered shift register is coupled to the second system clock signal line L-CB. Understandably, the second system clock signal on the second system clock signal line L-CB serves as the second clock signal in the odd-numbered shift register, and the same signal serves as the first clock signal in the even-numbered shift register.

[0178] The structure of the fifth scan drive circuit 25 is basically the same as that of the second scan drive circuit 22, and will not be described in detail here.

[0179] The shift register provided in this application embodiment can be used with... Figure 2 The pixel circuit is coupled to control the transistors in the pixel circuit to be in the on or off state.

[0180] The following is about Figure 6 The structure of the shift register shown is explained in detail.

[0181] Figure 6 The diagram shows a schematic representation of the shift register provided in some embodiments of this application; Figure 7 It shows Figure 6 The diagram shows a possible structure of a shift register. Figure 8 It shows Figure 6 The diagram shows another possible structure of the shift register.

[0182] Please see Figure 6 The shift register 30 may include a first input circuit 31, a second input circuit 32, a fourth control circuit 33, a second control circuit 34, a third control circuit 35, a first control circuit 36, a first output circuit 37, and a second output circuit 38.

[0183] The first input circuit 31 can be coupled to the second voltage terminal VGL, the first clock signal terminal CK, and the fourth node S4, respectively. The first input circuit 31 is configured to write the second voltage signal provided by the second voltage terminal VGL to the fourth node S4 under the control of the first clock signal provided by the first clock signal terminal CK.

[0184] The second input circuit 32 can be coupled to the input signal terminal Vin, the first clock signal terminal CK, and the second node S2, respectively. The second input circuit 32 is configured to write the input signal provided by the input signal terminal Vin to the second node S2 under the control of the first clock signal provided by the first clock signal terminal CK.

[0185] The fourth control circuit 33 can be coupled with the second node S2, the first clock signal terminal CK and the fourth node S4 respectively. The fourth control circuit 33 is configured to write the first clock signal provided by the first clock signal terminal CK to the fourth node S4 under the control of the voltage of the second node S2.

[0186] The second control circuit 34 can be coupled with the fourth node S4, the second clock signal terminal CB and the first node S1 respectively. The second control circuit 34 is configured to write the second clock signal provided by the second clock signal terminal CB to the first node S1 under the control of the voltage of the fourth node S4 and the second clock signal provided by the second clock signal terminal CB.

[0187] The third control circuit 35 can be coupled with the second node S2, the first voltage terminal VGH and the first node S1 respectively. The third control circuit 35 is configured to write the second voltage signal provided by the first voltage terminal VGH to the first node S1 under the control of the voltage of the second node S2.

[0188] The first control circuit 36 can be coupled with the input signal terminal Vin, the first voltage terminal VGH, the first control source K1, the second control source K2, the third control source K3 and the second node S2 respectively. The first control circuit 36 is configured to further pull down the voltage of the second node S2 when the voltage of the second node S2 switches from a high voltage to a low voltage under the common control of the first control signal provided by the first control source K1, the third control signal provided by the third control source K3 and the voltage of the second node S2.

[0189] The first output circuit 37 can be coupled with the first node S1, the first voltage terminal VGH and the output terminal OUT of the shift register RS respectively. The first output circuit 37 is configured to write the first voltage signal provided by the first voltage terminal VGH to the output terminal OUT under the control of the voltage of the first node S1, so as to make the shift register output the first voltage signal.

[0190] The second output circuit 38 can be coupled with the second node S2, the second voltage output terminal VGL and the output terminal OUT respectively. The second output circuit 38 is configured to write the second voltage signal provided by the second voltage output terminal VGL to the output terminal OUT under the control of the voltage of the second node S2, so as to make the shift register output the second voltage signal.

[0191] The conduction degree of the second output circuit 38 when the second output circuit 38 is connected between the second voltage output terminal VGL and the output terminal OUT is related to the voltage of the second node S2. For example, the lower the voltage of the second node S2, the greater the conduction degree between the second voltage output terminal VGL and the output terminal OUT.

[0192] Understandably, the first input circuit 31 and the fourth control circuit 33 can jointly control the voltage of the fourth node S4. The second control circuit 34 and the third control circuit 35 jointly control the voltage of the first node S1. The second input circuit 32 and the first control circuit 36 ​​jointly control the voltage of the second node S2.

[0193] like Figure 6 In the illustrated embodiment, under the combined control of the first control signal provided by the first control source K1, the third control signal provided by the third control source K3, and the voltage of the second node S2, the first control circuit 36 ​​further pulls down the voltage of the second node S2 when the voltage of the second node S2 switches from high voltage to low voltage. This increases the conduction degree of the second output circuit 38 when connecting the second voltage output terminal VGL and the output terminal OUT, reducing or even eliminating the transmission loss of the second voltage signal provided by the second voltage terminal VGL in the second output circuit 38. Thus, the output terminal OUT of the shift register RS ​​can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL.

[0194] In this way, there will be no step problem when the output signal of the shift register OUT switches from high voltage to low voltage, thereby improving the stability and reliability of the shift register (scan drive circuit) in controlling the pixel circuit.

[0195] Figure 7 It shows Figure 6 The diagram shows a schematic of one type of shift register.

[0196] like Figure 7 As shown, the first input circuit 31 may include a first transistor (second input transistor) T1. The first terminal of the first transistor T1 is coupled to the input signal terminal Vin, the second terminal of the first transistor T1 is coupled to the second node S2, and the control terminal of the first transistor T1 is coupled to the first clock signal terminal CK. Under the control of the first clock signal provided by the first clock signal terminal CK, the first transistor T1 is in a conducting state, thereby connecting the input signal terminal Vin and the second node S2, allowing the input signal to be written into the second node S2.

[0197] The second input circuit 32 may include a second transistor (third input transistor) T2. The first terminal of the second transistor T2 is coupled to the second voltage terminal VGL, the second terminal of the second transistor T2 is coupled to the fourth node S4, and the control terminal of the second transistor T2 is coupled to the first clock signal terminal CK. Under the control of the first clock signal provided by the first clock signal terminal CK, the second transistor T2 is in a conducting state, thereby connecting the second voltage terminal VGL and the fourth node S4, allowing the second voltage signal to be written to the fourth node S4.

[0198] The fourth control circuit 33 can include a third transistor T3 and a fourth transistor T4. The first electrode of the third transistor T3 is coupled with the first clock signal terminal CK, the second electrode of the third transistor T3 is coupled with the first electrode of the fourth transistor T4, and the control electrode of the third transistor T3 is coupled with the second node S2. The second electrode of the fourth transistor T4 is coupled with the fourth node S4, and the control electrode of the fourth transistor T4 is also coupled with the second node S2.

[0199] Under the control of the voltage of the second node S2, the third transistor T3 and the fourth transistor T4 are simultaneously in the conductive state, thereby connecting the first clock signal terminal CK and the fourth node S4, so that the first clock signal is written to the fourth node S4.

[0200] In some other examples, only one of the third transistor T3 and the fourth transistor T4 can be retained. For example, the fourth control circuit 33 can include the third transistor T3 and not include the fourth transistor T4; or the fourth control circuit 33 can include the fourth transistor T4 and not include the third transistor T3.

[0201] The second control circuit 34 can include a first switch unit 341, a second switch unit 342, and a second pull-down unit 343.

[0202] As shown in FIG. 4, the first switch unit 341 can be coupled with the fourth node S4, the second clock signal terminal CB, and the fifth node S5, respectively. The first switch unit 341 is configured to write the second clock signal provided by the second clock signal terminal CB to the fifth node S5 under the control of the voltage of the fourth node S4. The first switch unit 341 is configured to write the second clock signal provided by the second clock signal terminal CB to the fifth node S5 under the control of the voltage of the fourth node S4. Figure 7 The first switch unit 341 is connected between the second clock signal terminal CB and the fifth node S5, and is related to the voltage of the fourth node S4. For example, the lower the voltage of the fourth node S4, the more stable the first switch unit 341 is connected between the second clock signal terminal CB and the fifth node S5.

[0203] The second switch unit 342 can be coupled with the fifth node S5, the second clock signal terminal CB, and the first node S1, respectively. The second switch unit 342 is configured to write the voltage of the fifth node S5 to the first node S1 under the control of the second clock signal provided by the second clock signal terminal CB. The second switch unit 342 is configured to write the voltage of the fifth node S5 to the first node S1 under the control of the second clock signal provided by the second clock signal terminal CB.

[0204] The second switch unit 342 is connected between the fifth node S5 and the first node S1, and is related to the second clock signal provided by the second clock signal terminal CB. For example, the higher the second clock signal provided by the second clock signal terminal CB, the more stable the second switch unit 342 is connected between the fifth node S5 and the first node S1.

[0205] The second pull-down unit 343 can be coupled to both the fourth node S4 and the fifth node S5. The second pull-down unit 343 is configured to pull down the voltage of the fourth node S4 when the voltage of the fifth node S5 drops. This makes the connection between the first switching unit 341 and the second clock signal terminal CB and the fifth node S5 more stable, thereby improving the reliability of the shift register RS.

[0206] In some examples, such as Figure 7 As shown, the first switching unit 341 may include a seventh transistor T7. The first terminal of the seventh transistor T7 is coupled to the second clock signal terminal CB, the second terminal of the seventh transistor T7 is coupled to the fifth node S5, and the control terminal of the seventh transistor T7 is coupled to the fourth node S4.

[0207] The second switching unit 342 may include an eighth transistor T8. The first terminal of the eighth transistor T8 is coupled to the fifth node S5, the second terminal of the eighth transistor T8 is coupled to the first node S1, and the control terminal of the eighth transistor is coupled to the second clock signal terminal CB.

[0208] The second pull-down unit 343 may include a second capacitor C2. The first plate of the second capacitor C2 is coupled to the fourth node S4, and the second plate of the second capacitor C2 is coupled to the fifth node S5.

[0209] Under the control of the voltage at the fourth node S4, the seventh transistor T7 is in the ON state, connecting the second clock signal terminal CB with the second plate of the first capacitor C1 (the fifth node S5), so that the second clock signal is written to the second plate of the first capacitor C1. Under the control of the second clock signal provided by the second clock signal terminal CB, the eighth transistor T8 is in the ON state, connecting the second plate of the first capacitor C1 with the first node S1, so that the voltage of the second plate of the first capacitor C1 is written to the first node S1.

[0210] like Figure 7 As shown, the third control circuit 35 may include a ninth transistor T9. The first terminal of the ninth transistor T9 is coupled to a first voltage terminal VGH, the second terminal of the ninth transistor T9 is coupled to a first node S1, and the control terminal of the ninth transistor T9 is coupled to a second node S2. Under the control of the voltage at the second node S2, the ninth transistor T9 is in a conducting state, thereby connecting the first node S1 and the first voltage terminal VGH, allowing a first voltage signal to be written into the first node S1.

[0211] The first output circuit 37 may include a tenth transistor T10. The first terminal of the tenth transistor T10 is coupled to a first voltage terminal VGH, the second terminal of the tenth transistor T10 is coupled to the output terminal OUT of the shift register RS, and the control terminal of the tenth transistor T10 is coupled to a first node S1. Under the control of the voltage at the first node S1, the tenth transistor T10 is in a conducting state, connecting the first voltage terminal VGH and the output terminal OUT, thereby outputting a first voltage signal (high voltage signal) at the output terminal OUT.

[0212] In some examples, the first output circuit 37 may also include a third capacitor C3. The first plate of the third capacitor C3 may be coupled to the first voltage terminal VGH, and the second plate of the third capacitor C3 may be coupled to the first node S1. Since the capacitor has the characteristic that the voltage difference between the first and second plates cannot change abruptly, and the first plate of the third capacitor C3 is coupled to the first voltage terminal VGH with a constant voltage, the third capacitor C3 can maintain the voltage stability of the first node S1, thereby improving the reliability of the shift register RS.

[0213] The second output circuit 38 may include an eleventh transistor T11. The first terminal of the eleventh transistor T11 is coupled to the second voltage terminal VHL, the second terminal of the eleventh transistor T11 is coupled to the output terminal OUT, and the control terminal of the eleventh transistor T11 is coupled to the second node S2. Under the control of the voltage at the second node S2, the eleventh transistor T11 is in a conducting state, connecting the second voltage terminal VHL and the output terminal OUT, thereby outputting a second voltage signal (low voltage signal) at the output terminal OUT.

[0214] like Figure 7 As shown, the first control circuit 36 ​​may include an input sub-circuit 361 and a pull-down sub-circuit 362. Both the input sub-circuit 361 and the pull-down sub-circuit 362 are coupled to the second node S2.

[0215] The input sub-circuit 361 is coupled to the third control source K3, the input signal terminal Vin, and the second node S2. The input sub-circuit 361 is configured to write the input signal provided by the input signal terminal Vin to the second node S2 under the control of the third control signal provided by the third control source K3.

[0216] The pull-down circuit 362 is coupled to the first control source K1, the second control source K2, the second node S2, and the first voltage terminal VGH. The pull-down circuit 362 is configured to pull down the voltage of the second node S2 under the control of the first control signal provided by the first control source K1 and the voltage of the second node S2.

[0217] like Figure 7In the embodiment shown, the input sub-circuit 361 is pulled down by the pull-down sub-circuit 362 to further reduce the voltage of the second node S2 when the second node S2 is switched from a high voltage to a low voltage, so that the eleventh transistor T11 in the second output circuit 38 has a larger on-state, and the output end of the eleventh transistor T11 can directly output the second voltage signal VGL. In this way, the output end OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL.

[0218] In Figure 7 Based on the shift register shown, in some other embodiments, the shift register RS can also have some variant structures. Figure 8 Another structure of the shift register is shown. Figure 6 Another structure of the shift register is shown.

[0219] In some embodiments, the shift register RS can further include a first protection circuit 391. The first protection circuit 391 is connected in series between the first input circuit 31 and the second control circuit 34. The first protection circuit 391 is coupled to the fourth node S4, the sixth node S6, and the second voltage terminal VGL. At this time, the second control circuit 34 is directly coupled to the sixth node S6 and indirectly coupled to the fourth node S4 through the sixth node S6. The first protection circuit 391 is configured to write the voltage of the fourth node S4 to the sixth node S6 under the control of the second voltage signal provided by the second voltage terminal VGL.

[0220] As Figure 8 shown, the first protection circuit 391 can include a twelfth transistor T12. The first pole of the twelfth transistor T12 is coupled to the fourth node S4, the second pole of the twelfth transistor T12 is coupled to the sixth node S6, and the control pole of the twelfth transistor T12 is coupled to the second voltage terminal VGL. The twelfth transistor T12 is in an on-state under the control of the second voltage signal provided by the second voltage terminal VGL, and is connected between the fourth node S4 and the sixth node S6.

[0221] In addition, the shift register RS can further include a second protection circuit 392. The second protection circuit 392 is connected in series between the second output circuit 38 and the second input circuit 32. The second protection circuit 392 is coupled to the second node S2 and the seventh node S7, respectively.

[0222] At this time, the third control circuit 35 is directly coupled with the seventh node S7 and indirectly coupled with the second node S2 through the seventh node S7. The third control circuit 35 can be coupled with the seventh node S7, the first voltage terminal VGH and the first node S1 respectively. The third control circuit 35 is configured to write the second voltage signal provided by the first voltage terminal VGH to the first node S1 under the control of the voltage of the seventh node S7.

[0223] Similarly, the fourth control circuit 33 is directly coupled with the seventh node S7 and indirectly coupled with the second node S2 through the seventh node S7. The fourth control circuit 33 can be coupled with the seventh node S7, the first clock signal terminal CK and the fourth node S4 respectively. The fourth control circuit 33 is configured to write the first clock signal provided by the first clock signal terminal CK to the fourth node S4 under the control of the voltage of the seventh node S7.

[0224] As shown in Figure 8 , the second protection circuit 392 can include the thirteenth transistor T13. The first electrode of the thirteenth transistor T13 is coupled with the seventh node S7, the second electrode of the thirteenth transistor T13 is coupled with the second node S2, and the control electrode of the thirteenth transistor T13 is coupled with the second voltage terminal VGL. The thirteenth transistor T13 is in a conductive state under the control of the second voltage signal provided by the second voltage terminal VGL for a long time, and the seventh node S7 and the second node S2 are connected.

[0225] In some embodiments, as shown in Figure 8 , the shift register RS can further include the sixteenth transistor T16. The first electrode of the sixteenth transistor T16 is coupled with the first voltage terminal VGH, the second electrode of the sixteenth transistor T16 is coupled with the second electrode of the first transistor T1 (the seventh node S7), and the control electrode of the sixteenth transistor T16 is coupled with the protection signal terminal BH.

[0226] The specific role of the protection signal terminal BH and the sixteenth transistor T16 is that before the display panel is lighted, the protection signal terminal BH provides a low voltage signal to the control electrode of the sixteenth transistor T16, so that the high voltage signal provided by the first voltage terminal VGH pulls up the voltage of the second electrode of the first transistor T1, so that the voltage of the second node S2 is high voltage, and the eleventh transistor T11 is in a cut-off state, avoiding the output terminal OUT of the shift register RS outputting the second voltage signal (low voltage signal).

[0227] In the process of refreshing the display image of the display panel, the protection signal terminal BH outputs a high voltage signal for a long time, so that the sixteenth transistor T16 is in an off state. There is no influence on the operation of the second output circuit 38. Therefore, under the premise of not affecting the operation of the shift register, the shift register can be additionally provided with the sixteenth transistor T16 and the protection signal terminal BH. In this way, it can be ensured that the shift register will not output a low voltage signal before the display panel is lit, so as to avoid the light-emitting device in the pixel circuit M from emitting light, thereby improving the reliability of the electronic device in the screen-off state.

[0228] In Figure 8 Based on the shift register shown in FIG. 1, the specific structures of the input sub-circuit 361 and the pull-down sub-circuit 362, and the specific forms of the first control source K1, the second control source K2 and the third control source K3 are described below through multiple embodiments.

[0229] Figure 9 A structural schematic diagram of the shift register shown in FIG. 1 is shown. Figure 8 A structural schematic diagram of the shift register shown in FIG. 1 is shown. Figure 9 In the shift register shown in FIG. 1, the first control source K1 is the fourth node S4, and the first control signal is the voltage of the fourth node S4; the second control source K2 is the fourth clock signal terminal CCB, and the second control signal is the fourth clock signal; and the third control source K3 is the third clock signal terminal, and the third control signal is the third clock signal.

[0230] The input sub-circuit 361 is coupled with the third clock signal terminal CCK, the input signal terminal Vin and the second node S2. The input sub-circuit 361 is configured to write the input signal provided by the input signal terminal Vin to the second node S2 under the control of the third clock signal provided by the third clock signal terminal CCK.

[0231] The pull-down sub-circuit 362 is coupled with the fourth node S4, the first voltage terminal VGH, the fourth clock signal terminal CCB and the second node S2, respectively. The pull-down sub-circuit 362 is configured to pull down the voltage of the second node S2 in the case that the first output circuit 37 provides the first voltage signal to the output terminal OUT and the second output circuit 38 provides the second voltage signal to the output terminal OUT under the control of the voltage of the fourth node S4 and the voltage of the second node S2.

[0232] In some examples, as Figure 9As shown, the input sub-circuit 361 can include a fourteenth transistor (first input transistor) T14. The first electrode of the fourteenth transistor T14 is coupled with the input signal terminal Vin, the second electrode of the fourteenth transistor T14 is coupled with the second node S2, and the control electrode of the fourteenth transistor T14 is coupled with the third clock signal terminal CCK. Under the control of the third clock signal provided by the third clock signal terminal CCK, the fourteenth transistor T14 is in a conductive state, thereby connecting the input signal terminal Vin and the second node S2, so that the input signal is written to the second node S2.

[0233] In some examples, as Figure 9 As shown, the pull-down sub-circuit 362 includes a first voltage regulating unit 41, a second voltage regulating unit 42, and a first pull-down unit 43.

[0234] The first voltage regulating unit 41 is coupled with the fourth node S4, the first voltage terminal VGH, and the third node S3, respectively. The first voltage regulating unit 41 is configured to write, under the control of the voltage of the fourth node S4, the first voltage signal provided by the first voltage terminal VGH to the third node S3.

[0235] The second voltage regulating unit 42 is coupled with the fourth clock signal terminal CCB, the third node S3, and the second node S2, respectively. The second voltage regulating unit 42 is configured to write, under the control of the voltage of the second node S2, the fourth clock signal provided by the fourth clock signal terminal CCB to the third node S3.

[0236] The first pull-down unit 43 is coupled with the third node S3 and the second node S2, respectively. The first pull-down unit 43 is configured to pull down the voltage of the second node S2 in the case that the voltage of the third node S3 drops.

[0237] The first voltage regulating unit 41 can write the first voltage signal (high voltage signal) to the third node S3 before the first output circuit 37 provides the first voltage signal to the output terminal OUT switches to the second output circuit 38 to provide the second voltage signal to the output terminal OUT. The second voltage regulating unit 42 can write the second voltage signal (low voltage signal) to the third node S3 in the case that the first output circuit 37 provides the first voltage signal to the output terminal OUT switches to the second output circuit 38 to provide the second voltage signal to the output terminal OUT. At this time, the voltage of the third node S3 drops.

[0238] The first pull-down unit 43 is connected to the third node S3, and the voltage of the first pull-down unit 43 is lowered. The voltage of the second node S2 connected to the first pull-down unit 43 is also lowered synchronously, so that the voltage of the second node S2 is lowered. In this way, the output end of the eleventh transistor T11 can directly output the second voltage signal VGL, and the output end OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL. The process of switching the signal output by the output end OUT of the shift register RS from a high voltage signal to a low voltage signal will not have a step problem, thereby improving the stability and reliability of the shift register (scanning driving circuit) for controlling the pixel circuit.

[0239] In some examples, the first voltage regulating unit 41 can include a fifth transistor (first control transistor) T5. The first electrode of the fifth transistor is coupled to the first voltage terminal VGH, the second electrode of the fifth transistor T5 is coupled to the third node S3, and the control electrode of the fifth transistor T5 is coupled to the fourth node S4. Under the control of the voltage of the fourth node S4, the fifth transistor T5 is in a conductive state, connecting the first voltage terminal VGH and the third node S3, so that the first voltage signal is written to the third node S3.

[0240] The second voltage regulating unit 42 can include a sixth transistor (second control transistor) T6. The first electrode of the sixth transistor T6 is coupled to the fourth clock signal terminal CCB, the second electrode of the sixth transistor T6 is coupled to the third node S3, and the control electrode of the sixth transistor T6 is coupled to the second node S2. Under the control of the voltage of the second node S2, the sixth transistor T6 is in a conductive state, connecting the fourth clock signal terminal CCB and the third node S3, so that the fourth clock signal is written to the third node S3.

[0241] The first pull-down unit 43 can include a first capacitor C1. The first plate of the first capacitor C1 is coupled to the third node S3, and the second plate of the first capacitor C1 is coupled to the second node S2. The first capacitor C1 can change (lower) the voltage of the other plate synchronously when the voltage of any plate changes (lowers).

[0242] It can be understood that the fifth transistor T5 and the sixth transistor T6 can change the voltage of the first plate (third node S3) of the third capacitor C3. As mentioned earlier, the voltage difference between the first plate and the second plate of the capacitor will not change abruptly, so when the voltage of the first plate of the third capacitor C3 decreases, the third capacitor C3 will also lower the voltage of the second node S2 connected to the second plate synchronously.

[0243] Therefore, before the voltage of the second node S2 switches from high voltage (VGH) to low voltage (VGL), the fifth transistor T5 writes the first voltage signal (high voltage signal) to the first plate of the third capacitor C3. Simultaneously with the voltage switch from high voltage (VGH) to low voltage (VGL) of the second node S2, the sixth transistor T6 writes the fourth clock signal, which serves as the low voltage signal, to the first plate of the third capacitor C3, causing a sudden drop in voltage at the first plate of the third capacitor C3. At this point, the third capacitor C3 further pulls down the low voltage (VGL) of the second node S2 (i.e., pulls the second node S2 down to a voltage lower than the low voltage input signal). This allows the output of the eleventh transistor T11 to directly output the second voltage signal VGL, and consequently, the output OUT of the shift register RS ​​to directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL. This ensures that the signal output from the output OUT of the shift register RS ​​does not experience a step-down during the switching process from a high voltage signal to a low voltage signal, thereby improving the stability and reliability of the shift register (scan drive circuit) in controlling the pixel circuit.

[0244] In addition, such as Figure 9 As shown, the shift register RS ​​may also include a fifteenth transistor T15. The first terminal of the fifteenth transistor T15 is coupled to the second terminal of the fourteenth transistor T14, the second terminal of the fifteenth transistor T15 is coupled to the second node S2, and the control terminal of the fifteenth transistor T15 is coupled to the second voltage terminal VGL. Under the control of the second voltage signal provided by the second voltage terminal VGL, the fifteenth transistor T15 remains in a continuously conducting state, connecting the second terminal of the fourteenth transistor T14 and the sixth node S6.

[0245] The following is combined Figure 9 The shift register shown illustrates the working process of the shift register.

[0246] Figure 10 The timing diagram of multiple signal terminals and circuit nodes of the shift register is shown. Figure 10 The diagram shows the timing changes of the input signal terminal Vin, the first clock signal terminal CK, the second clock signal terminal CB, the third clock signal terminal CCK / the fourth clock signal terminal CCB, the first node S1, the second node S2, the third node S3, the fourth node S4, the fifth node S5, the sixth node S6, the seventh node S7, and the output terminal OUT. Figures 11 to 18 It shows Figure 9 The diagram shows the operation of the shift register at each stage.

[0247] It should be noted that it has been explained previously that the protection signal terminal BH always provides a high voltage signal during the image display process of the display panel, and thus the sixteenth transistor T16 continuously stays in the off state. In addition, it has also been explained previously that the twelfth transistor T12, the thirteenth transistor T13 and the fifteenth transistor T15 stay in the on state for a long time. Therefore, the states of the twelfth transistor T12, the thirteenth transistor T13, the fifteenth transistor T15 and the sixteenth transistor T16 will not be explained in the following stages.

[0248] Working process of the shift register in the first stage P1: combined with Figure 10 and Figure 11 As shown in the figure, the first clock signal is a high voltage signal, and the first transistor T1 and the second transistor T2 stay in the off state. The second clock signal is a low voltage signal, and the eighth transistor T8 stays in the on state. The third clock signal is a high voltage signal, and the fourteenth transistor T14 stays in the off state.

[0249] Since the voltage of the seventh node S7 in the previous stage is a low voltage, the third transistor T3 and the fourth transistor T4 both stay in the on state, and the first clock signal can be written into the fourth node S4, so that the voltages of the fourth node S4 and the sixth node S6 are both high voltages. The fourth node S4 with a high voltage controls the fifth transistor T5 to stay in the off state. The sixth node S6 with a high voltage controls the seventh transistor T7 to stay in the off state, and the voltage of the seventh node S7 remains the high voltage in the previous stage. In addition, the voltage of the seventh node S7 is a low voltage, and the ninth transistor T9 stays in the on state, so that the first voltage signal is written into the first node S1. The first node S1 with a high voltage controls the tenth transistor T10 to stay in the off state.

[0250] Since the voltage of the second node S2 in the previous stage is a low voltage, the sixth transistor T6 is controlled to stay in the on state, and at this time the fourth clock signal with a high voltage can be written into the third node S3. Since no new signal is written into the second node S2, the second node S2 remains the low voltage in the previous stage, and controls the eleventh transistor T11 to stay in the on state, so that the second voltage signal is written into the output terminal OUT of the shift register RS, and the output terminal OUT of the shift register RS outputs a low voltage signal.

[0251] Working process of the shift register in the second stage P2: combined with Figure 10 and Figure 12 As shown in the figure, the first clock signal is a high voltage signal, and the first transistor T1 and the second transistor T2 stay in the off state. The second clock signal is a high voltage signal, and the eighth transistor T8 stays in the off state. The third clock signal is a low voltage signal, and the fourteenth transistor T14 stays in the on state.

[0252] The fourteenth transistor T14 is in the on state, and the input signal can be written into the second node S2 and the seventh node S7, so that the voltages of the second node S2 and the seventh node S7 are low voltages. The voltage of the second node S2 is a low voltage, and the sixth transistor T6 is in the on state, at this time, the fourth clock signal of the low voltage can be written into the third node S3. Since the voltage of the fifth node S5 is a high voltage in the first stage P1, and is pulled down to a low voltage in the second stage P2, the first capacitor C1 will synchronously pull down the voltage of the second node S2, so that the voltages of the second node S2 and the seventh node S7 are further pulled down.

[0253] The voltage of the seventh node S7 is a low voltage, and the third transistor T3 and the fourth transistor T4 are both in the on state, and the first clock signal can be written into the fourth node S4, so that the voltages of the fourth node S4 and the sixth node S6 are both high voltages. The fourth node S4 of the high voltage will control the fifth transistor T5 to be in the off state. The sixth node S6 of the high voltage will control the seventh transistor T7 to be in the off state, and the voltage of the fifth node S5 remains the high voltage of the previous stage. In addition, the voltage of the seventh node S7 is a low voltage, and the ninth transistor T9 is in the on state, so that the first voltage signal is written into the first node S1. The first node S1 of the high voltage will control the tenth transistor T10 to be in the off state.

[0254] The voltage of the second node S2 is a low voltage, and the eleventh transistor T11 is in the on state, and the second voltage signal is written into the output end OUT of the shift register RS, so that the output end OUT of the shift register RS outputs a low voltage signal.

[0255] The working process of the shift register in the third stage P3 is as follows: Figure 10 and Figure 13 As shown in FIG. 3, the first clock signal is a low voltage signal, and the first transistor T1 and the second transistor T2 are in the on state. The second clock signal is a high voltage signal, and the eighth transistor T8 is in the off state. The third clock signal is a high voltage signal, and the fourteenth transistor T14 is in the off state.

[0256] The first transistor T1 is in the on state, and the low-voltage input signal is written into the seventh node S7 and the second node S2. The voltage of the seventh node S7 is low, and the third transistor T3 and the fourth transistor T4 are both in the on state, so that the low-voltage first clock signal can be written into the fourth node S4, and the second transistor T2 is in the on state, so that the second voltage signal can also be written into the fourth node S4, so that the voltages of the fourth node S4 and the sixth node S6 are both low. The low-voltage sixth node S6 controls the seventh transistor T7 to be in the on state, and the high-voltage second clock signal is written into the fifth node S5. In addition, the voltage of the seventh node S7 is low, and the ninth transistor T9 is in the on state, so that the first voltage signal is written into the first node S1. The high-voltage first node S1 controls the tenth transistor T10 to be in the off state.

[0257] The voltage of the second node S2 is low, and the sixth transistor T6 is in the on state, so that the high-voltage fourth clock signal can be written into the third node S3. In addition, the voltage of the second node S2 is low, and the eleventh transistor T11 is in the on state, so that the second voltage signal is written into the output end OUT of the shift register RS, and the output end OUT of the shift register RS outputs a low-voltage signal.

[0258] The working process of the shift register in the fourth phase P4 is basically the same as that in the first phase P1, which will not be described here.

[0259] The working process of the shift register in the fifth phase P5 is as follows: Figure 10 and Figure 14 As shown in FIG. 5, the first clock signal is a high-voltage signal, and the first transistor T1 and the second transistor T2 are in the off state. The second clock signal is a high-voltage signal, and the eighth transistor T8 is in the off state. The third clock signal is a low-voltage signal, and the fourteenth transistor T14 is in the on state.

[0260] The fourteenth transistor T14 is in the on state, and the input signal of high voltage can be written into the second node S2 and the seventh node S7, so that the voltage of the second node S2 and the seventh node S7 is high voltage. The voltage of the seventh node S7 is high voltage, and the third transistor T3 and the fourth transistor T4 are both in the off state. The fourth node S4 has no new signal written in, and the fourth node S4 and the sixth node S6 maintain the high voltage of the fourth stage P4, and the seventh transistor T7 is in the off state. The fifth node S5 has no new signal written in, and maintains the high voltage of the fourth stage P4. The voltage of the fourth node S4 is high voltage, which controls the fifth transistor T5 to be in the off state, the voltage of the second node S2 is high voltage, which controls the sixth transistor T6 to be in the off state, so that the third node S3 has no new signal written in, and maintains the high voltage of the fourth stage P4. In addition, the voltage of the seventh node S7 is high voltage, which controls the ninth transistor T9 to be in the off state, the first node S1 has no new signal written in, and maintains the high voltage of the fourth stage P4, which controls the tenth transistor T10 to be in the off state.

[0261] The voltage of the second node S2 is low voltage, which controls the eleventh transistor T11 to be in the on state, and the second voltage signal is written into the output end OUT of the shift register RS, so that the output end OUT of the shift register RS outputs the low voltage signal.

[0262] The working process of the shift register in the sixth stage P6 is as follows: Figure 10 and Figure 15 As shown in the drawings, the first clock signal is a low voltage signal, and the first transistor T1 and the second transistor T2 are in the on state. The second clock signal is a high voltage signal, and the eighth transistor T8 is in the off state. The third clock signal is a high voltage signal, and the fourteenth transistor T14 is in the off state.

[0263] The first transistor T1 is in the on state, and the input signal of high voltage can be written into the seventh node S7 and the second node S2, so that the voltage of the second node S2 and the seventh node S7 is high voltage. The seventh node S7 is high voltage, so that the third transistor T3 and the fourth transistor T4 are both in the off state, the second transistor T2 is in the on state, the second voltage signal is written into the fourth node S4, and the voltage of the fourth node S4 and the sixth node S6 is low voltage. The sixth node S6 is low voltage, the seventh transistor T7 is in the on state, and the second clock signal of high voltage is written into the fifth node S5. In addition, the seventh node S7 is high voltage, the ninth transistor T9 is in the off state, the first node S1 has no new signal written in, maintains the high voltage of the fifth stage P5, and controls the tenth transistor T10 to be in the off state. In addition, the fourth node S4 is low voltage, which controls the fifth transistor T5 to be in the on state, and the first voltage signal is written into the third node S3.

[0264] The second node S2 is high voltage, the eleventh transistor T11 is controlled to be in the off state, and the output end OUT of the shift register RS has no new signal written in, and the fifth stage P5 outputs a low voltage signal.

[0265] The working process of the shift register at the seventh stage P7 is shown in Figure 10 and Figure 16 The first clock signal is a high voltage signal, and the first transistor T1 and the second transistor T2 are in the off state. The second clock signal is a low voltage signal, and the eighth transistor T8 is in the on state. The third clock signal is a high voltage signal, and the fourteenth transistor T14 is in the off state.

[0266] The first transistor T1 and the fifteenth transistor T15 are both in the off state, and the second node S2 and the seventh node S7 have no new signal written in. The second node S2 and the seventh node S7 keep the high voltage of the sixth stage P6. The seventh node S7 is high voltage, so that the third transistor T3 and the fourth transistor T4 are both in the off state. Since the second transistor T2 is also in the off state, the fourth node S4 and the sixth node S6 have no new signal written in, and the fourth node S4 and the sixth node S6 keep the low voltage of the sixth stage P6. The sixth node S6 is low voltage, controlling the seventh transistor T7 to be in the on state, and the low voltage second clock signal is written into the seventh node S7 and the first node S1. And the seventh node S7 is high voltage, controlling the ninth transistor T9 to be in the off state. In this way, only the low voltage second clock signal is written into the first node S1, and the first node S1 is low voltage, controlling the tenth transistor T10 to be in the on state, and the first voltage signal is written into the output end OUT of the shift register RS, so that the output end OUT of the shift register RS outputs a high voltage signal.

[0267] The fourth node S4 is low voltage, controlling the fifth transistor T5 to be in the on state, and the first voltage signal is written into the third node S3. The second node S2 is high voltage, controlling the sixth transistor T6 to be in the off state, and controlling the eleventh transistor T11 to be in the off state.

[0268] The working process of the shift register at the eighth stage P8 is shown in Figure 10 and Figure 17 The first clock signal is a high voltage signal, and the first transistor T1 and the second transistor T2 are in the off state. The second clock signal is a high voltage signal, and the eighth transistor T8 is in the off state. The third clock signal is a low voltage signal, and the fourteenth transistor T14 is in the on state.

[0269] The fourteenth transistor T14 is in the on state, and the input signal of low voltage is written into the second node S2 and the seventh node S7. The seventh node S7 is of low voltage, controlling the third transistor T3 and the fourth transistor T4 to be in the on state, and the first clock signal of high voltage is written into the fourth node S4 and the sixth node S6. The fourth node S4 is of high voltage, controlling the fifth transistor T5 to be in the off state. The sixth node S6 is of high voltage, controlling the seventh transistor T7 to be in the off state. In addition, the seventh node S7 is of low voltage, controlling the ninth transistor T9 to be in the on state, and the first voltage signal is written into the first node S1. The first node S1 is of high voltage, controlling the tenth transistor T10 to be in the off state.

[0270] The second node S2 is of low voltage, controlling the sixth transistor T6 to be in the on state, and the fourth clock signal of low voltage is written into the third node S3. Since the third node S3 is of high voltage at the seventh stage P7 and is pulled down to low voltage at the eighth stage P8, the first capacitor C1 will synchronously pull down the voltage of the second node S2, so that the voltages of the second node S2 and the seventh node S7 are further pulled down.

[0271] In this way, the second node S2 is pulled down to a voltage lower than the input signal of low voltage, so that the output end of the eleventh transistor T11 can directly output the second voltage signal VGL, and further so that the output end OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage end VGL, thereby avoiding the problem of steps when the shift register RS switches from the high voltage signal to the low voltage signal, and improving the stability and reliability of the shift register (scanning driving circuit) in controlling the pixel circuit.

[0272] The working process of the shift register at the ninth stage P9 is as follows: Figure 10 and Figure 18 As shown in the drawings, the first clock signal is a low voltage signal, and the first transistor T1 and the second transistor T2 are in the on state. The second clock signal is a high voltage signal, and the eighth transistor T8 is in the off state. The third clock signal is a high voltage signal, and the fourteenth transistor T14 is in the off state.

[0273] The first transistor T1 is in the on state, and the low-voltage input signal is written to the seventh node S7 and the second node S2. The voltage of the seventh node S7 is low, and the third transistor T3 and the fourth transistor T4 are both in the on state, and the low-voltage first clock signal can be written to the fourth node S4. At the same time, the second transistor T2 is in the on state, and the second voltage signal can also be written to the fourth node S4, so that the voltages of the fourth node S4 and the sixth node S6 are both low. The low-voltage sixth node S6 controls the seventh transistor T7 to be in the on state, and the high-voltage second clock signal is written to the seventh node S7. In addition, the voltage of the seventh node S7 is low, and the ninth transistor T9 is in the on state, so that the first voltage signal is written to the first node S1. The high-voltage first node S1 controls the tenth transistor T10 to be in the off state.

[0274] The voltage of the second node S2 is low, and the sixth transistor T6 is in the on state, so that the high-voltage fourth clock signal can be written to the third node S3. In addition, the eleventh transistor T11 is in the on state, and the second voltage signal is written to the output end OUT of the shift register RS, so that the output end OUT of the shift register RS outputs a low-voltage signal.

[0275] From the working process of the shift register in the first stage P1 to the ninth stage P9, it can be seen that in the case that the waveform output by the output end OUT of the shift register RS is switched from high voltage to low voltage, the second node S2 is pulled down to a voltage lower than the low-voltage input signal, so that the output end of the eleventh transistor T11 can directly output the second voltage signal VGL. In this way, the output end OUT of the shift register RS can directly output the second voltage signal (low-voltage signal) provided by the second voltage end VGL, avoiding the step problem mentioned in the prior art, so as to improve the stability and reliability of the shift register (scan driving circuit) in controlling the pixel circuit.

[0276] Figure 19 Another structural schematic diagram of the shift register is shown. Figure 8 Another structural schematic diagram of the shift register is shown. Figure 19 The first control source K1 is the sixth node S6, and the first control signal is the voltage of the fourth node S4; the second control source K2 is the fourth clock signal end CCB, and the second control signal is the fourth clock signal; and the third control source K3 is the third clock signal end, and the third control signal is the third clock signal.

[0277] Since the twelfth transistor T12 is in the on state for a long time, the voltage of the fourth node S4 and the voltage of the sixth node S6 are approximately equal. Therefore, as Figure 19As shown, the pull-down circuit 362 can be coupled to the sixth node S6, the second node S2, the first voltage terminal VGH, and the fourth clock signal terminal CCB, respectively. The pull-down circuit 362 is configured to pull down the voltage of the second node S2 under the control of the voltage of the sixth node S6 and the voltage of the second node S2.

[0278] although Figure 19 The pull-down circuit 362 in the example Figure 9 The pull-down circuit 362 in the diagram has different connection relationships, but since the voltage of the fourth node S4 and the voltage of the sixth node S6 are approximately equal, therefore... Figure 9 The pull-down circuit 362 in the example Figure 9 The pull-down circuit 362 in the middle has the same function and purpose, and is not limited here.

[0279] For example, such as Figure 19 As shown, the input sub-circuit 361 may include a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 is coupled to the input signal terminal Vin, the second terminal of the fourteenth transistor T14 is coupled to the second node S2, and the control terminal of the fourteenth transistor T14 is coupled to the third clock signal terminal CCK. Under the control of the third clock signal provided by the third clock signal terminal CCK, the fourteenth transistor T14 is in a conducting state, thereby connecting the input signal terminal Vin and the second node S2, allowing the input signal to be written into the second node S2.

[0280] The pull-down sub-circuit 362 may include a first voltage regulating unit 41, a second voltage regulating unit 42, and a first pull-down unit 43. Wherein, Figure 19 The connection relationship and function of the second voltage regulating unit 42 and the first pull-down unit 43 are related to... Figure 9 The connection relationship and function of the second voltage regulating unit 42 and the first pull-down unit 43 are basically the same, and will not be repeated here.

[0281] The first voltage regulating unit 41 is coupled to the sixth node S6, the first voltage terminal VGH, and the third node S3. The first voltage regulating unit 41 is configured to write the first voltage signal provided by the first voltage terminal VGH to the third node S3 under the control of the voltage of the sixth node S6.

[0282] In some examples, the first voltage regulating unit 41 may include a fifth transistor T5. The first terminal of the fifth transistor is coupled to the first voltage terminal VGH, the second terminal of the fifth transistor T5 is coupled to the third node S3, and the control terminal of the fifth transistor T5 is coupled to the sixth node S6. Under the control of the voltage at the sixth node S6, the fifth transistor T5 is in a conducting state, connecting the first voltage terminal VGH and the third node S3, so that the first voltage signal is written to the third node S3.

[0283] Figure 19 The timing diagram of each signal and circuit node in the shift register RS ​​shown is consistent with... Figure 9 The timing sequences shown are basically consistent; and, Figure 19 The working process of the shift register RS ​​shown in the diagram at each stage is also similar to that described above. Figure 9 The shift registers shown operate in a basically consistent manner at each stage, so they will not be described in detail here.

[0284] In this embodiment, the pull-down sub-circuit 362 can also pull down the second node S2 to a voltage lower than the low-voltage input signal when the waveform output at the output terminal OUT of the shift register RS ​​switches from high voltage to low voltage, so that the output terminal of the eleventh transistor T11 can directly output the second voltage signal VGL. In this way, the output terminal OUT of the shift register RS ​​can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL, avoiding the problem of step in the output of the shift register, thereby improving the stability and reliability of the shift register (scan driving circuit) in controlling the pixel circuit.

[0285] Furthermore, such as Figure 19 As shown, the shift register RS ​​may also include a seventeenth transistor T17. The first terminal of the seventeenth transistor T17 is coupled to the sixth node S6, the second terminal of the seventeenth transistor T17 is coupled to the control terminal of the fifth transistor T5, and the control terminal of the seventeenth transistor T17 is coupled to the second voltage terminal VGL.

[0286] The sixteenth transistor T16 is in a continuous conducting state under the control of the second voltage signal provided by the second voltage terminal VGL, connecting the sixth node S6 and the control electrode of the fifth transistor T5.

[0287] Figure 20 It shows Figure 8 The diagram shows another possible structure of the shift register. Figure 20 The first control source K1 is the first clock signal terminal CK, and the first control signal is the first clock signal; the second control source K2 is the fourth clock signal terminal CCB, and the second control signal is the fourth clock signal; the third control source K3 is the third clock signal terminal, and the third control signal is the third clock signal.

[0288] like Figure 20As shown, the first control circuit 36 can be coupled with the first clock signal terminal CK, the first voltage terminal VGH, the third clock signal terminal CCK, the fourth clock signal terminal CCB, the second node S2 and the input signal terminal Vin respectively. The first control circuit 36 is configured to pull down the voltage of the second node S2 under the control of the first clock signal provided by the first clock signal terminal CK and the third clock signal provided by the third clock signal terminal CCK. For example, when the waveform output by the output terminal OUT of the shift register RS switches from a high voltage to a low voltage, the first control circuit 36 pulls down the voltage of the second node S2.

[0289] It can be understood that, Figure 20 The shift register shown in Figure 9 The difference between the shift register shown in Figure 9 In the first control circuit 36 of the first clock signal terminal CK is coupled with the fourth node S4, while Figure 20 In the first control circuit 36 of the first clock signal terminal CK is coupled with the fourth node S4, while

[0290] In the present embodiment, Figure 20 In the first clock signal provided by the first clock signal terminal CK plays a role in the first control circuit 36, which is basically the same as Figure 9 In the first clock signal provided by the first clock signal terminal CK plays a role in the first control circuit 36, which is basically the same as

[0291] In some examples, the first control circuit 36 includes an input sub-circuit 361 and a pull-down sub-circuit 362. The input sub-circuit 361 and the pull-down sub-circuit 362 are both coupled with the second node S2. Among them, the connection relationship of the input sub-circuit 361 is basically the same as Figure 9 In some examples, the first control circuit 36 includes an input sub-circuit 361 and a pull-down sub-circuit 362. The input sub-circuit 361 and the pull-down sub-circuit 362 are both coupled with the second node S2. Among them, the connection relationship of the input sub-circuit 361 is basically the same as

[0292] The pull-down sub-circuit 362 is coupled with the first clock signal terminal CK, the second node S2, the first voltage terminal VGH and the fourth clock signal terminal CCB respectively. The pull-down sub-circuit 362 is configured to pull down the voltage of the second node S2 under the control of the first clock signal provided by the first clock signal terminal CK and the voltage of the second node S2.

[0293] As Figure 20In the illustrated embodiment, the voltage written to the second node S2 by the input sub-circuit 361 is pulled down by the pull-down sub-circuit 362, which can further reduce the voltage of the second node S2 while switching from a high voltage to a low voltage (i.e., pull down the second node S2 to a voltage lower than the low voltage input signal), so that the output end of the eleventh transistor T11 can directly output the second voltage signal VGL. In this way, the output end OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL.

[0294] The pull-down sub-circuit 362 can include a first voltage regulating unit 41, a second voltage regulating unit 42, and a first pull-down unit 43. Among them, Figure 20 The connection relationship and function of the second voltage regulating unit 42 and the first pull-down unit 43 in the embodiment are basically the same as those in the Figure 9 The connection relationship and function of the second voltage regulating unit 42 and the first pull-down unit 43 in the embodiment are basically the same as those in the

[0295] The first voltage regulating unit 41 is coupled with the first clock signal terminal CK, the first voltage terminal VGH, and the third node S3. The first voltage regulating unit 41 is configured to write the first voltage signal provided by the first voltage terminal VGH to the third node S3 under the control of the first clock signal provided by the first clock signal terminal CK.

[0296] In some examples, the first voltage regulating unit 41 can include a fifth transistor T5. The first electrode of the fifth transistor is coupled with the first voltage terminal VGH, the second electrode of the fifth transistor T5 is coupled with the third node S3, and the control electrode of the fifth transistor T5 is coupled with the first clock signal terminal CK. Under the control of the first clock signal provided by the first clock signal terminal CK, the fifth transistor T5 is in a conductive state, connecting the first voltage terminal VGH and the third node S3, so that the first voltage signal is written to the third node S3.

[0297] In this embodiment, before the voltage of the second node S2 is switched from the high voltage (VGH) to the low voltage (VGL), the first clock signal provided by the first clock signal terminal CK writes the first voltage signal (high voltage signal) into the first plate of the third capacitor C3 (the third node S3) by using the fifth transistor T5. At the same time when the voltage of the second node S2 is switched from the high voltage (VGH) to the low voltage (VGL), the fourth clock signal as a low voltage signal is written into the first plate of the third capacitor C3 by using the sixth transistor T6, so that the voltage of the first plate of the third capacitor C3 is suddenly lowered, and at this time, the third capacitor C3 further pulls down the low voltage (VGL) of the second node S2 (i.e., pulls down the second node S2 to a voltage lower than the input signal of the low voltage), so that the output terminal of the eleventh transistor T11 can directly output the second voltage signal VGL, and further, the output terminal of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL, thereby avoiding the problem of steps in the output of the shift register, and thus the stability and reliability of the shift register (scanning driving circuit) for controlling the pixel circuit can be improved.

[0298] As shown in Figure 20 , the function of the pull-down sub-circuit 362 is to control the voltage state of the third node S3. In this embodiment, in order to avoid the main stage of the output signal of the shift register RS from appearing steps, the working process of the shift register RS in the seventh stage P7 and the eighth stage P8 is mainly described.

[0299] The working process of the shift register in the seventh stage P7: in combination with Figure 10 and Figure 21 , the first clock signal is a high voltage signal, and the fifth transistor T5 is in the off state. Moreover, the second node S2 is at a high voltage, the sixth transistor T6 is in the off state, and the third node S5 has no new signal written into it, so the high voltage in the sixth stage P6 is maintained.

[0300] The working process of the shift register in the eighth stage P8: in combination with Figure 10 and as shown in Figure 22 , the first clock signal is a high voltage signal, and the fifth transistor T5 is in the off state. The fourth clock signal and the input signal are both low voltage signals, the fourteenth transistor T14 and the sixth transistor T6 are in the on state, the low voltage fourth clock signal is written into the third node S3, and the low voltage input signal is written into the second node S2 and the seventh node S7. Since the third node S3 is at a high voltage in the seventh stage P7, and the third node S3 is pulled down to a low voltage in the eighth stage P8, the third capacitor C3 will synchronously pull down the voltage of the second node S2, so that the voltages of the second node S2 and the seventh node S7 are further pulled down.

[0301] Thus, while the voltage of the second node S2 is switched from the high voltage (VGH) to the low voltage (VGL), the fourth clock signal as a low voltage signal is written into the first plate of the third capacitor C3 by the sixth transistor T6, so that the voltage of the first plate of the third capacitor C3 is suddenly lowered, at this time, the third capacitor C3 will further pull down the low voltage (VGL) of the second node S2 (i.e. pull down the second node S2 to a voltage lower than the input signal of the low voltage), so that the output end of the eleventh transistor T11 can directly output the second voltage signal VGL, and further make the output end OUT of the shift register RS directly output the second voltage signal (low voltage signal) provided by the second voltage end VGL, avoid the problem of step of the shift register output, so as to improve the stability and reliability of the shift register (scan driving circuit) to control the pixel circuit.

[0302] Figure 23 Another structural schematic diagram of the shift register is shown. Figure 8 Another structural schematic diagram of the shift register is shown. Figure 23 In the embodiment, the first control source K1 is the second clock signal end CB, and the first control signal is the second clock signal; the second control source K2 is the fourth clock signal end CCB, and the second control signal is the fourth clock signal; and the third control source K3 is the third clock signal end CCK, and the third control signal is the third clock signal.

[0303] It can be understood that, Figure 23 The difference between the shift register shown in the embodiment and the shift register shown in the embodiment is that, Figure 9 In the embodiment, the first control circuit 36 is coupled with the fourth node S4, and in the embodiment, Figure 9 In the embodiment, the first control circuit 36 is coupled with the second clock signal end CB. Figure 23 In the embodiment, the first control circuit 36 is coupled with the second clock signal end CB.

[0304] In the embodiment, Figure 23 In the embodiment, the second clock signal provided by the second clock signal end CB plays a role in the first control circuit 36, which is basically the same as the role of the fourth node S4 in the first control circuit 36. Therefore, they have the same effects, which will not be described here. Figure 9

[0305] In some examples, the first control circuit 36 includes an input sub-circuit 361 and a pull-down sub-circuit 362. The input sub-circuit 361 and the pull-down sub-circuit 362 are both coupled with the second node S2. Wherein, the connection relationship of the input sub-circuit 361 is basically the same as that of the input sub-circuit 361 in the embodiment, which will not be described here. Figure 9

[0306] ​​The pull-down circuit 362 is coupled to the second clock signal terminal CB, the second node S2, the first voltage terminal VGH, and the fourth clock signal terminal CCB. The pull-down circuit 362 is configured to pull down the voltage of the second node S2 under the control of the second clock signal provided by the second clock signal terminal CB and the voltage of the second node S2.

[0307] like Figure 23 In the illustrated embodiment, the voltage written to the second node S2 by the input sub-circuit 361 is pulled down by the pull-down sub-circuit 362. This further reduces the voltage of the second node S2 (i.e., pulls down the second node S2 to a voltage lower than the low voltage input signal) while the second node S2 switches from a high voltage to a low voltage, allowing the output of the eleventh transistor T11 to directly output the second voltage signal VGL. Thus, the output OUT of the shift register RS ​​can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL.

[0308] The pull-down sub-circuit 362 may include a first voltage regulating unit 41, a second voltage regulating unit 42, and a first pull-down unit 43. Wherein, Figure 23 The connection relationship and function of the second voltage regulating unit 42 and the first pull-down unit 43 are related to... Figure 9 The connection relationship and function of the second voltage regulating unit 42 and the first pull-down unit 43 are basically the same, and will not be repeated here.

[0309] The first voltage regulating unit 41 is coupled to the second clock signal terminal CB, the first voltage terminal VGH, and the third node S3. The first voltage regulating unit 41 is configured to write the first voltage signal provided by the first voltage terminal VGH to the third node S3 under the control of the second clock signal provided by the second clock signal terminal CB.

[0310] In some examples, the first voltage regulating unit 41 may include a fifth transistor T5. The first terminal of the fifth transistor is coupled to the first voltage terminal VGH, the second terminal of the fifth transistor T5 is coupled to the third node S3, and the control terminal of the fifth transistor T5 is coupled to the second clock signal terminal CB. Under the control of the second clock signal provided by the second clock signal terminal CB, the fifth transistor T5 is in a conducting state, connecting the first voltage terminal VGH and the third node S3, so that the first voltage signal is written to the third node S3.

[0311] In this embodiment, before the voltage of the second node S2 is switched from the high voltage (VGH) to the low voltage (VGL), the second clock signal provided by the second clock signal terminal CB writes the first voltage signal (high voltage signal) into the first plate of the third capacitor C3 (the third node S3) by using the fifth transistor T5. At the same time when the voltage of the second node S2 is switched from the high voltage (VGH) to the low voltage (VGL), the fourth clock signal as a low voltage signal is written into the first plate of the third capacitor C3 by using the sixth transistor T6, so that the voltage of the first plate of the third capacitor C3 is suddenly lowered, and at this time, the third capacitor C3 further pulls down the low voltage (VGL) of the second node S2 (i.e., pulls down the second node S2 to a voltage lower than the input signal of the low voltage), so that the output terminal of the eleventh transistor T11 can directly output the second voltage signal VGL, and further, the output terminal of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL, thereby avoiding the problem of steps in the output of the shift register, and thus the stability and reliability of the shift register (scanning driving circuit) for controlling the pixel circuit can be improved.

[0312] As shown in Figure 23 , the function of the pull-down sub-circuit 362 is to control the voltage state of the third node S3. In this embodiment, in order to avoid the main stage of the output signal of the shift register RS from appearing steps, the working process of the shift register RS in the seventh stage P7 and the eighth stage P8 is mainly described.

[0313] The working process of the shift register in the seventh stage P7: as shown in Figure 10 and Figure 24 , the second clock signal is a low voltage signal, the fifth transistor T5 is in the conductive state, and the first voltage signal (high voltage signal) provided by the first voltage terminal VGH is written into the third node S3.

[0314] The working process of the shift register in the eighth stage P8: as shown in Figure 10 and as shown in Figure 25 , the second clock signal is a high voltage signal, and the fifth transistor T5 is in the cut-off state. The fourth clock signal and the input signal are both low voltage signals, the fourteenth transistor T14 and the sixth transistor T6 are in the conductive state, the low voltage fourth clock signal is written into the third node S3, and the low voltage input signal is written into the second node S2 and the seventh node S7. Since the third node S3 is at a high voltage in the seventh stage P7 and is pulled down to a low voltage in the eighth stage P8, the third capacitor C3 will synchronously pull down the voltage of the second node S2, so that the voltages of the second node S2 and the seventh node S7 are further pulled down.

[0315] In this way, when the voltage of the second node S2 is switched from the high voltage (VGH) to the low voltage (VGL), the fourth clock signal as a low voltage signal is written into the first plate of the third capacitor C3 by the sixth transistor T6, so that the voltage of the first plate of the third capacitor C3 is suddenly lowered, at this time, the third capacitor C3 will further pull down the low voltage (VGL) of the second node S2 (that is, pull down the second node S2 to a voltage lower than the input signal of the low voltage), so that the output end of the eleventh transistor T11 can directly output the second voltage signal VGL, and then the output end of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage end VGL, avoiding the problem of step of the shift register output, thereby improving the stability and reliability of the shift register (scanning driving circuit) for controlling the pixel circuit.

[0316] Figure 26 Another structural schematic diagram of the shift register is shown. Figure 8 Another structural schematic diagram of the shift register is shown. Figure 26 In the first control circuit 36, the first control source K1 is the second clock signal end CB, and the first control signal is the second clock signal; the second control source K2 is the first clock signal end CK, and the second control signal is the first clock signal; and the third control source K3 is the first clock signal end CK, and the third control signal is the first clock signal.

[0317] In the embodiment, Figure 26 In the first control circuit 36, the second clock signal provided by the second clock signal end CB plays a role basically the same as that of the second clock signal provided by the second clock signal end CB in the first control circuit 36. Figure 9 In the first control circuit 36, the fourth node S4 plays a role basically the same as that of the fourth node S4 in the first control circuit 36. Figure 26 In the first control circuit 36, the first clock signal provided by the first clock signal end CK plays a role basically the same as that of the first clock signal provided by the first clock signal end CK in the first control circuit 36. Figure 9 In the first control circuit 36, the fourth clock signal end plays a role basically the same as that of the fourth clock signal end in the first control circuit 36. Therefore, Figure 26 In the first control circuit 36, the first control circuit 36 and Figure 9 In the first control circuit 36, Figure 26 In the first control circuit 36, the second clock signal provided by the second clock signal end CB has the same role and effect as that of the second clock signal provided by the second clock signal end CB in the first control circuit 36, which will not be described here.

[0318] In some examples, the first control circuit 36 includes an input sub-circuit 361 and a pull-down sub-circuit 362. The input sub-circuit 361 and the pull-down sub-circuit 362 are both coupled to the second node S2.

[0319] The input sub-circuit 361 is coupled to the first clock signal end CK, the input signal end Vin and the second node S2 respectively. The input sub-circuit 361 is configured to write the input signal provided by the input signal end Vin into the second node S2 under the control of the first clock signal provided by the first clock signal end CK.

[0320] The pull-down circuit 362 is coupled to the second clock signal terminal CB, the second node S2, the first voltage terminal VGH, and the first clock signal terminal CK, respectively. The pull-down circuit 362 is configured to pull down the voltage of the second node S2 under the control of the second clock signal provided by the second clock signal terminal CB and the voltage of the second node S2.

[0321] like Figure 26 In the illustrated embodiment, the voltage written to the second node S2 by the input sub-circuit 361 is pulled down by the pull-down sub-circuit 362. This further reduces the voltage of the second node S2 (i.e., pulls down the second node S2 to a voltage lower than the low voltage input signal) while the second node S2 switches from a high voltage to a low voltage, allowing the output of the eleventh transistor T11 to directly output the second voltage signal VGL. Thus, the output OUT of the shift register RS ​​can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL.

[0322] In some examples, the pull-down sub-circuit 362 includes a first voltage regulating unit 41, a second voltage regulating unit 42, and a first pull-down unit 43.

[0323] The first voltage regulating unit 41 is coupled to the second clock signal terminal CB, the first voltage terminal VGH, and the third node S3. The first voltage regulating unit 41 is configured to write the first voltage signal provided by the first voltage terminal VGH to the third node S3 under the control of the second clock signal provided by the second clock signal terminal CB.

[0324] The second voltage regulating unit 42 is coupled to the first clock signal terminal CK, the third node S3, and the second node S2, respectively. The second voltage regulating unit 42 is configured to write the first clock signal provided by the first clock signal terminal CK to the third node S3 under the control of the voltage of the second node S2.

[0325] The first pull-down unit 43 is coupled to the third node S3 and the second node S2. The first pull-down unit 43 is configured to pull down the voltage of the second node S2 when the voltage of the third node S3 drops.

[0326] Before the first output circuit 37 switches to providing a first voltage signal to the output terminal OUT and the second output circuit 38 switches to providing a second voltage signal to the output terminal OUT, the first voltage regulating unit 41 can write a first voltage signal (high voltage signal) to the third node S3. When the first output circuit 37 switches to providing a first voltage signal to the output terminal OUT and the second output circuit 38 switches to providing a second voltage signal to the output terminal OUT, the second voltage regulating unit 42 can write a second voltage signal (low voltage signal) to the third node S3. At this time, the voltage at the third node S3 decreases.

[0327] The first pull-down unit 43 is connected to the third node S3 side, and the voltage is lowered synchronously to the second node S2 side, thereby realizing the voltage of the second node S2 is pulled down. In this way, the output end of the eleventh transistor T11 can directly output the second voltage signal VGL, and the output end of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL. The process of switching the signal output by the output end of the shift register RS from a high voltage signal to a low voltage signal will not have a step problem, thereby improving the stability and reliability of the shift register (scanning driving circuit) for controlling the pixel circuit.

[0328] In some examples, the first voltage regulating unit 41 can include a fifth transistor T5. The first electrode of the fifth transistor is coupled to the first voltage terminal VGH, the second electrode of the fifth transistor T5 is coupled to the third node S3, and the control electrode of the fifth transistor T5 is coupled to the second clock signal terminal CB. Under the control of the first clock signal provided by the second clock signal terminal CB, the fifth transistor T5 is in a conductive state, connecting the first voltage terminal VGH and the third node S3, so that the first voltage signal is written to the third node S3.

[0329] The second voltage regulating unit 42 can include a sixth transistor T6. The first electrode of the sixth transistor T6 is coupled to the first clock signal terminal CK, the second electrode of the sixth transistor T6 is coupled to the third node S3, and the control electrode of the sixth transistor T6 is coupled to the second node S2. Under the control of the voltage of the second node S2, the sixth transistor T6 is in a conductive state, connecting the first clock signal terminal CK and the third node S3, so that the first clock signal is written to the third node S3.

[0330] The first pull-down unit 43 can include a first capacitor C1. The first plate of the first capacitor C1 is coupled to the third node S3, and the second plate of the first capacitor C1 is coupled to the second node S2. The first capacitor C1 can change (lower) the voltage of one plate synchronously when the voltage of the other plate changes (lowers).

[0331] Therefore, before the voltage of the second node S2 switches from high voltage (VGH) to low voltage (VGL), the fifth transistor T5 writes the first voltage signal (high voltage signal) to the first plate of the third capacitor C3. Simultaneously with the voltage switch of the second node S2 from high voltage (VGH) to low voltage (VGL), the sixth transistor T6 writes the first clock signal, which serves as the low voltage signal, to the first plate of the third capacitor C3, causing a sudden drop in voltage at the first plate of the third capacitor C3. At this point, the third capacitor C3 further pulls down the low voltage (VGL) of the second node S2 (i.e., pulls the second node S2 down to a voltage lower than the low voltage input signal). This allows the output of the eleventh transistor T11 to directly output the second voltage signal VGL, and consequently, the output OUT of the shift register RS ​​to directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL. This ensures that the signal output from the output OUT of the shift register RS ​​does not experience a step-down during the switching process from a high voltage signal to a low voltage signal, thereby improving the stability and reliability of the shift register (scan drive circuit) in controlling the pixel circuit.

[0332] like Figure 23 As shown, the function of the pull-down circuit 362 is to control the voltage state of the third node S3. In this embodiment, the main stages to avoid step-like output signals from the shift register RS ​​are from stage 7 P7 to stage 9 P9. Therefore, the description mainly focuses on the operation of the shift register RS ​​from stage 7 P7 to stage 9 P9.

[0333] The process of the shift register operating in stage P7: as follows Figure 27 As shown, the second clock signal is a low voltage signal, the fifth transistor T5 is in the on state, and the first voltage signal (high voltage signal) provided by the first voltage terminal VGH is written into the third node S3.

[0334] The process of the shift register operating in stage P8: as follows Figure 28 As shown, the second clock signal is a high voltage signal, and the fifth transistor T5 is in the off state. The first clock signal is a high voltage signal, and the fourteenth transistor T14 and the sixth transistor T6 are in the off state. Thus, no new signals are written to the third node S3 and the second node S2, and the voltages of both the third node S3 and the second node S2 remain at the high voltage of the seventh stage P7.

[0335] The process of the shift register operating in stage P9: as follows Figure 29As shown, the second clock signal is a high voltage signal, and the fifth transistor T5 is in an off state. The first clock signal is a low voltage signal, and the fourteenth transistor T14 and the sixth transistor T6 are in an on state. In this way, the fourth clock signal of low voltage is written to the third node S3, and the input signal of low voltage is written to the second node S2 and the seventh node S7. The voltage of the second node S2 is low, the sixth transistor T6 is in an on state, and the first clock signal of low voltage is written to the third node S3. Since the third node S3 is high voltage at the eighth stage P8, and the third node S3 is pulled down to low voltage at the ninth stage P9, the third capacitor C3 will synchronously pull down the voltage of the second node S2, so that the voltage of the second node S2 and the seventh node S7 is further pulled down.

[0336] In this way, while the voltage of the second node S2 is switched from high voltage (VGH) to low voltage (VGL), the first clock signal as a low voltage signal is written to the first plate of the third capacitor C3 by the sixth transistor T6, so that the voltage of the first plate of the third capacitor C3 suddenly drops, and at this time the third capacitor C3 will further pull down the low voltage (VGL) of the second node S2 (i.e. pull down the second node S2 to a voltage lower than the low voltage input signal), so that the output end of the eleventh transistor T11 can directly output the second voltage signal VGL, and further make the output end OUT of the shift register RS directly output the second voltage signal (low voltage signal) provided by the second voltage end VGL, avoid the problem of step of shift register output, so as to improve the stability and reliability of the shift register (scanning driving circuit) to control the pixel circuit.

[0337] Figure 30 Another structure diagram of the shift register is shown. Figure 8 Another structure diagram of the shift register is shown. Figure 30 The first control source K1 is the fourth node S4, and the first control signal is the voltage of the fourth node S4; the second control source K2 is the fourth clock signal end CCB, and the second control signal is the fourth clock signal; and the third control source K3 is the third clock signal end CCK, and the third control signal is the third clock signal.

[0338] The first control circuit 36 can include an input sub-circuit 361 and a pull-down sub-circuit 362. The input sub-circuit 361 and the pull-down sub-circuit 362 are coupled with the second node S2, and are used to pull down the voltage of the second node S2 in the case that the signal output by the shift register is switched from high voltage to low voltage.

[0339] The input sub-circuit 361 is coupled with the third clock signal terminal CCK, the input signal terminal Vin and the second node S2. The input sub-circuit 361 is configured to write the input signal provided by the input signal terminal Vin to the second node S2 under the control of the third clock signal provided by the third clock signal terminal CCK.

[0340] The pull-down sub-circuit 362 is coupled with the fourth node S4, the first voltage terminal VGH, the fourth clock signal terminal CCB and the second node S2 respectively. The pull-down sub-circuit 362 is configured to pull down the voltage of the second node S2 in the case that the first output circuit 37 provides the first voltage signal to the output terminal OUT switches to the second output circuit 38 providing the second voltage signal to the output terminal OUT under the control of the voltage of the fourth node S4 and the voltage of the second node S2.

[0341] As shown in the embodiment, Figure 30 by the pull-down of the voltage of the second node S2 written by the input sub-circuit 361 through the pull-down sub-circuit 362, the voltage of the second node S2 can be further reduced (i.e. the second node S2 is pulled down to a voltage lower than the low voltage input signal) while switching from high voltage to low voltage, so that the output terminal of the eleventh transistor T11 can directly output the second voltage signal VGL. In this way, the output terminal OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL.

[0342] The pull-down sub-circuit 362 can include a first voltage regulating unit 41, a second voltage regulating unit 42 and a first pull-down unit 43. The connection relationship and function of the pull-down sub-circuit 362 are basically the same as those of the pull-down sub-circuit 362 in Figure 9 the embodiment, and will not be described here. It should be noted that the second plate of the first capacitor C1 is referred to as the eighth node S8 in the embodiment.

[0343] In some embodiments, the input sub-circuit 361 includes a fourteenth transistor (first input transistor) T14 and an eighteenth transistor (second input transistor) T18.

[0344] The first pole of the fourteenth transistor T14 is coupled with the input signal terminal Vin, the second pole of the fourteenth transistor T14 is coupled with the eighth node S8, and the control pole of the fourteenth transistor T14 is coupled with the third clock signal terminal CCK. Under the control of the third clock signal provided by the third clock signal terminal CCK, the fourteenth transistor T14 is in the conductive state, thereby connecting the input signal terminal Vin and the eighth node S8, so that the input signal is written to the eighth node S8.

[0345] The first electrode of the eighteenth transistor T18 is coupled with the eighth node S8, the second electrode of the eighteenth transistor T18 is coupled with the second node S2, and the control electrode of the eighteenth transistor T18 is coupled with the eighth node S8.

[0346] The fourteenth transistor T14 writes the low-voltage input signal into the eighth node S8 under the control of the third clock signal provided by the third clock signal terminal CCK, so that the sixth transistor T6 and the eighteenth transistor T18 can be controlled to be in the conductive state. The sixth transistor T6 is in the conductive state, and the low-voltage fourth clock signal is written into the third node S3, so that the voltage of the third node S3 is suddenly changed from the high voltage to the low voltage, and the first capacitor C1 pulls down the voltage of the eighth node S8.

[0347] It should be noted that before the first capacitor C1 pulls down the voltage of the eighth node S8, the voltage of the eighth node S8 is already the low-voltage input signal, so after the first capacitor C1 pulls down the voltage of the eighth node S8, the voltage of the eighth node S8 is lower than the voltage of the low-voltage input signal.

[0348] In addition, due to the voltage of the eighth node S8 being pulled down by the first capacitor C1, the eighteenth transistor T18 will not have transmission loss, and can directly write the voltage of the eighth node S8 into the second node S2. In this way, the output end of the eighteenth transistor T18 can directly output the second voltage signal VGL, and further make the output end OUT of the shift register RS directly output the second voltage signal (low-voltage signal) provided by the second voltage terminal VGL. The process of switching the signal output by the output end OUT of the shift register RS from the high-voltage signal to the low-voltage signal will not have a step problem, thereby improving the stability and reliability of the shift register (scanning driving circuit) for controlling the pixel circuit.

[0349] In order to avoid the main stage of the shift register RS output signal appearing in the seventh stage P7 and the eighth stage P8 in the embodiment, the working process of the shift register RS in the seventh stage P7 and the eighth stage P8 is mainly described.

[0350] The working process of the shift register in the seventh stage P7: combined with Figure 10 and Figure 31 As shown in the figures, the voltage of the fourth node S4 is low, the fifth transistor T5 is in the conductive state, and the third node S3 writes the first voltage signal (high-voltage signal). And the eighth node S8 is high voltage, and the sixth transistor T6 is in the cut-off state.

[0351] The working process of the shift register in the eighth stage P8: combined with Figure 10 and as Figure 32As shown, the third clock signal is a low voltage signal, and the fifteenth transistor T15 is in the on state. A low voltage input signal is written to the eighth node S8, so that the sixth transistor T6 and the eighteenth transistor T18 can be controlled to be in the on state. The sixth transistor T6 is in the on state, and the low voltage fourth clock signal is written to the third node S3, so that the voltage of the third node S3 is abruptly changed from a high voltage to a low voltage, and the first capacitor C1 pulls down the voltage of the eighth node S8.

[0352] After the first capacitor C1 pulls down the eighth node S8, the voltage of the eighth node S8 is lower than the voltage of the low voltage input signal. In this way, the eighteenth transistor T18 has no transmission loss, and can directly write the voltage of the eighth node S8 to the second node S2. Similarly, the output end of the eighteenth transistor T18 can directly output the second voltage signal VGL, and further make the output end OUT of the shift register RS directly output the second voltage signal (low voltage signal) provided by the second voltage end VGL. In the process of switching the signal output by the output end OUT of the shift register RS from a high voltage signal to a low voltage signal, there is no step problem, thereby improving the stability and reliability of the shift register (scanning driving circuit) in controlling the pixel circuit.

[0353] In some embodiments, the fourth clock signal generates a falling edge at a time not later than the third clock signal generates a falling edge.

[0354] For example, as shown in FIG. 6, the third clock signal end CCK and the fourth clock signal end CCB are two signal ends, and output different third clock signals and fourth clock signals respectively. The fourth clock signal generates a falling edge at a time earlier than the third clock signal generates a falling edge, and the third clock signal generates a falling edge in a period in which the fourth clock signal is a low voltage. Figure 10 For example, as shown in FIG. 6, the third clock signal end CCK and the fourth clock signal end CCB are two signal ends, and output different third clock signals and fourth clock signals respectively. The fourth clock signal generates a falling edge at a time earlier than the third clock signal generates a falling edge, and the third clock signal generates a falling edge in a period in which the fourth clock signal is a low voltage.

[0355] For example, as shown in FIG. 6, the third clock signal end CCK and the fourth clock signal end CCB are two signal ends, and output different third clock signals and fourth clock signals respectively. The fourth clock signal generates a falling edge at a time earlier than the third clock signal generates a falling edge, and the third clock signal generates a falling edge in a period in which the fourth clock signal is a low voltage. Figure 33 For example, as shown in FIG. 6, the third clock signal end CCK and the fourth clock signal end CCB are two signal ends, and output different third clock signals and fourth clock signals respectively. The fourth clock signal generates a falling edge at a time earlier than the third clock signal generates a falling edge, and the third clock signal generates a falling edge in a period in which the fourth clock signal is a low voltage.

[0356] For example, as shown in FIG. 6, the third clock signal end CCK and the fourth clock signal end CCB are two signal ends, and output different third clock signals and fourth clock signals respectively. The fourth clock signal generates a falling edge at a time earlier than the third clock signal generates a falling edge, and the third clock signal generates a falling edge in a period in which the fourth clock signal is a low voltage. Figure 10 For example, as shown in FIG. 6, the third clock signal end CCK and the fourth clock signal end CCB are two signal ends, and output different third clock signals and fourth clock signals respectively. The fourth clock signal generates a falling edge at a time earlier than the third clock signal generates a falling edge, and the third clock signal generates a falling edge in a period in which the fourth clock signal is a low voltage. Figure 33 For example, as shown in FIG. 6, the third clock signal end CCK and the fourth clock signal end CCB are two signal ends, and output different third clock signals and fourth clock signals respectively. The fourth clock signal generates a falling edge at a time earlier than the third clock signal generates a falling edge, and the third clock signal generates a falling edge in a period in which the fourth clock signal is a low voltage.

[0357] The reason why the fourth clock signal generates a falling edge at a time not later than the third clock signal generates a falling edge will be explained below. For ease of understanding, the timing diagram shown in FIG. 6 is still taken as an example. Figure 9The shift register structure shown is used as an example, but it should be understood that other embodiments are consistent with the timing requirements of the fourth clock signal and the third clock signal.

[0358] As shown in Figure 34 , the fourth clock signal generates a falling edge at a time later than the time at which the third clock signal generates a falling edge. During the eighth phase P8, the shift register prepares the low voltage signal (the fourth clock signal) for pulling down the third node S3 at the first electrode of the sixth transistor T6 after the fourteenth transistor T14 is in the on state for a period of time. In this way, the second node S2, which is not pulled down, controls the eleventh transistor T11 to be on first, and the eleventh transistor T11 has transmission loss, which causes the output end OUT of the shift register RS to have a step when switching from a high voltage signal to a low voltage signal.

[0359] As shown in Figure 10 and Figure 33 , the fourth clock signal generates a falling edge at a time not later than the time at which the third clock signal generates a falling edge. During the eighth phase P8, the shift register can prepare the low voltage signal (the fourth clock signal) for pulling down the third node S3 at the first electrode of the sixth transistor T6 at the same time or in advance when the fourteenth transistor T14 is in the on state. Thus, the third capacitor C3 can immediately pull down the voltage of the second node S2 at the same time as the voltage of the third node S3 is pulled down. In this way, the pulled-down second node S2 can control the output end of the eleventh transistor T11 to directly output the second voltage signal VGL, and thus the output end OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage end VGL when switching from a high voltage to a low voltage, thereby avoiding the problem of a step when the shift register RS switches from a high voltage signal to a low voltage signal, and improving the stability and reliability of the shift register (scanning driving circuit) in controlling the pixel circuit.

[0360] In some embodiments, the input signal, the first clock signal, and the fourth clock signal cannot be low voltage signals at the same time.

[0361] When the first clock signal and the input signal are low voltage signals at the same time, the second node S2, the fourth node S4, the seventh node S7, and the sixth node S6 in the shift register RS are all at a low voltage. The fourth node S4 at a low voltage controls the fifth transistor T5 to be in the on state, so that the first voltage end VGH is directly connected to the third node S3. At the same time, the second node S2 at a low voltage controls the sixth transistor T6 to be in the on state, so that the fourth clock signal end CCB is directly connected to the third node S3. In this way, a path is actually formed in which the first voltage end VGH is directly connected to the fourth clock signal end CCB.

[0362] Since the first voltage terminal VGH constantly provides a high voltage signal, if the fourth clock signal provided by the fourth clock signal terminal CCB is a low voltage signal, a short circuit between the first voltage terminal VGH and the fourth clock signal terminal CCB will occur, which will cause a risk of burning the shift register and a safety hazard of the display panel.

[0363] Therefore, in the embodiment, by designing that the input signal, the first clock signal and the fourth clock signal cannot be low voltage signals at the same time, the safety of the shift register can be improved, and the safety of the display panel and the electronic device can be improved.

[0364] In other embodiments, in order to avoid a short circuit between the first voltage terminal VGH and the fourth clock signal terminal CCB, the fourth clock signal provided by the fourth clock signal terminal CCB can be continuously controlled to be a high voltage signal when the first clock signal provided by the first clock signal terminal CK is a low voltage signal.

[0365] As shown in FIG. 6, the time interval corresponding to the high voltage of the fourth clock signal completely covers the time interval corresponding to the low voltage of the first clock signal. Figure 35

[0366] In the embodiment, by controlling the fourth clock signal to be a high voltage when the first clock signal is a low voltage, the duration of the fourth clock signal being a low voltage can be lengthened, the time of the fourth clock signal generating a falling edge can be made earlier than the time of the third clock signal generating a falling edge, the voltage of the second node S2 can be pulled down and stabilized, the voltage of the control electrode of the eleventh transistor T11 can be pulled down, the output terminal of the eleventh transistor T11 can directly output the second voltage signal, and then the output terminal OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage terminal VGL when the output terminal OUT of the shift register RS switches from a high voltage to a low voltage, so that the problem of generating a step when the shift register RS switches from a high voltage signal to a low voltage signal can be avoided, and the stability and reliability of the shift register (scanning driving circuit) in controlling the pixel circuit can be improved.

[0367] In some embodiments, the time of the third clock signal generating a falling edge is not later than the time of the first clock signal generating a falling edge.

[0368] For example, the first clock signal terminal CK is multiplexed to be the third clock signal terminal CCK, or it can also be understood that the first clock signal and the third clock signal adopt the same signal. In this way, the time of the third clock signal generating a falling edge is equal to the time of the first clock signal generating a falling edge.

[0369] ​Exemplarily, the first clock signal terminal CK and the third clock signal terminal CCK are two signal terminals, and different first clock signals and third clock signals are output respectively. The moment when the third clock signal generates a falling edge is earlier than the moment when the first clock signal generates a falling edge.

[0370] Since the third clock signal can be used to control the fifteenth transistor T15 to be in the conductive state or the disconnected state, and the first clock signal can be used to control the first transistor T1 to be in the conductive state or the disconnected state, the moment when the third clock signal generates a falling edge is not later than the moment when the first clock signal generates a falling edge. It can be understood that the input signal is written from the fifteenth transistor T15 to the second node S2 not later than the input signal is written from the first transistor T1 to the second node S2.

[0371] In the case that the voltage of the second node S2 is switched from the high voltage to the low voltage, the input signal is first written to the second node S2 through the first transistor T1, and before the third capacitor C3 further pulls down the voltage of the second node S2, the second node S2 has controlled the eleventh transistor T11 to be in the conductive state. At this time, the transmission loss of the eleventh transistor T11 cannot be overcome, which will cause the output terminal OUT of the shift register RS to generate a higher low voltage when the output terminal OUT is switched from the high voltage to the low voltage. After the third capacitor C3 further pulls down the voltage of the second node S2, the transmission loss of the eleventh transistor T11 is overcome, and the output terminal OUT of the shift register RS outputs a lower low voltage (the first voltage signal). In this way, the output terminal OUT of the shift register RS generates a step (voltage change: from the high voltage to the higher low voltage, and then to the lower low voltage) when the output terminal OUT is switched from the high voltage to the low voltage, which reduces the stability and reliability of the shift register in controlling the pixel circuit.

[0372] In the case that the voltage of the second node S2 is switched from the high voltage to the low voltage, the input signal is first written to the second node S2 through the fifteenth transistor T15, or the input signal is written to the second node S2 through the first transistor T1 and the fifteenth transistor T15 at the same time. This can make the third capacitor C3 further pull down the voltage of the second node S2. In this way, the second node S2 after being pulled down can control the eleventh transistor T11 to be in the conductive state, pull down the voltage of the control electrode of the eleventh transistor T11, so that the output terminal of the eleventh transistor T11 can directly output the second voltage signal VGL, and further make the output terminal OUT of the shift register RS directly output the second voltage signal (the low voltage signal) provided by the second voltage terminal VGL when the output terminal OUT is switched from the high voltage to the low voltage.

[0373] Therefore, in the embodiment, by controlling the time when the third clock signal generates a falling edge to be no later than the time when the first clock signal generates a falling edge, the output end OUT of the shift register RS can directly output the second voltage signal (low voltage signal) provided by the second voltage end VGL when switching from a high voltage to a low voltage, thereby avoiding the problem of generating a step when the shift register RS switches from a high voltage signal to a low voltage signal, and improving the stability and reliability of the shift register (scan driving circuit) in controlling the pixel circuit.

[0374] In addition, since the time when the third clock signal generates a falling edge can be designed to be earlier than the time when the first clock signal generates a falling edge, the time of the scan control signals output by the plurality of shift registers can also be made not to overlap.

[0375] Because according to the analysis of each stage of the shift register RS shown in FIG. 7, it can be determined that: Figure 9

[0376] 1. In the seventh stage P7, the voltage of the fourth node S4 is a low voltage, the seventh transistor T7 is in a conductive state, and therefore when the second clock signal provided by the second clock signal end CB is a low voltage, the eighth transistor T8 can be controlled to be in a conductive state, so that the second clock signal provided by the second clock signal end CB is written to the first node S1, the tenth transistor T10 is controlled to be in a conductive state, and the scan control signal output by the output end of the shift register is switched from a low voltage to a high voltage.

[0377] It can be understood that the time of the falling edge of the second clock signal corresponds to the time when the scan control signal output by the output end of the shift register is switched from a low voltage to a high voltage.

[0378] 2. In the eighth stage P8, the fifteenth transistor T15 is controlled to be in a conductive state by the third clock signal provided by the third clock signal end CCK, so that the low voltage input signal is written to the second node S2, and the scan control signal output by the output end of the shift register is switched from a high voltage to a low voltage.

[0379] It can be understood that the time of the falling edge of the third clock signal corresponds to the time when the scan control signal output by the output end of the shift register is switched from a high voltage to a low voltage.

[0380] In the previous introduction Figure 5 ​As shown in the timing diagram of the scan driving circuit, the first clock signal used by the odd-numbered shift registers is the same as the second clock signal used by the even-numbered shift registers. Thus, taking the first shift register RS1 and the second shift register RS2 as two adjacent shift registers, and the first shift register RS1 outputs the scan control signal before the second shift register RS2, the time when the scan control signal output by the output end of the second shift register switches from low voltage to high voltage is the time corresponding to the falling edge of the first clock signal of the first shift register.

[0381] In the embodiment, the time when the third clock signal generates the falling edge is designed to be earlier than the time when the first clock signal generates the falling edge. Thus, the time when the scan control signal output by the output end of the first shift register RS1 switches from high voltage to low voltage is earlier than the time when the scan control signal output by the output end of the second shift register RS2 switches from low voltage to high voltage.

[0382] In this way, the scan control signals output by the plurality of shift registers in the scan driving circuit do not overlap in time.

[0383] Figure 36 The timing diagram of the scan control signals output by the plurality of shift registers corresponding to another scan driving circuit is shown. It can be seen that the time intervals of the scan control signals output by adjacent shift registers overlap with each other. This will cause the sub-pixels in adjacent rows of the display panel to be opened at the same time and wait for the data signal to be written. At this time, in order to accurately write the data signal to each row of sub-pixels, the data line L-Data needs to avoid the time interval when multiple rows of sub-pixels are opened at the same time and can only write data in the time interval when each row of sub-pixels is opened alone. In this way, it is easy to cause the problem of insufficient data signal writing time of the sub-pixels or incorrect data signal writing of the sub-pixels. Moreover, even if the data signal is written normally, the difficulty of data signal writing is additionally increased.

[0384] Figure 37 The timing diagram of the scan control signals output by the plurality of shift registers corresponding to another scan driving circuit is shown. It can be seen that the time intervals of the scan control signals output by adjacent shift registers overlap with each other. This will cause the sub-pixels in adjacent rows of the display panel to be opened at the same time and wait for the data signal to be written. At this time, in order to accurately write the data signal to each row of sub-pixels, the data line L-Data needs to avoid the time interval when multiple rows of sub-pixels are opened at the same time and can only write data in the time interval when each row of sub-pixels is opened alone. In this way, it is easy to cause the problem of insufficient data signal writing time of the sub-pixels or incorrect data signal writing of the sub-pixels. Moreover, even if the data signal is written normally, the difficulty of data signal writing is additionally increased. Figure 5 The timing diagram of the scan control signals output by the plurality of shift registers corresponding to another scan driving circuit is shown. It can be seen that the time intervals of the scan control signals output by adjacent shift registers overlap with each other. This will cause the sub-pixels in adjacent rows of the display panel to be opened at the same time and wait for the data signal to be written. At this time, in order to accurately write the data signal to each row of sub-pixels, the data line L-Data needs to avoid the time interval when multiple rows of sub-pixels are opened at the same time and can only write data in the time interval when each row of sub-pixels is opened alone. In this way, it is easy to cause the problem of insufficient data signal writing time of the sub-pixels or incorrect data signal writing of the sub-pixels. Moreover, even if the data signal is written normally, the difficulty of data signal writing is additionally increased. Figure 38 The corresponding relationship between the scan control signals output by the plurality of shift registers and the plurality of clock signals is shown. As shown in the timing diagram of the scan driving circuit, Figure 38 As shown, the time of the rising edge output by the output end OUT1 of the shift register RS1 corresponds to the time of one falling edge of the second clock signal (see the dashed line 1 in Figure 38 As shown, the time of the falling edge output by the output end OUT1 of the shift register RS1 corresponds to the time of one falling edge of the third clock signal CCK (see the dashed line 2 in Figure 38(Dash line 2). The rising edge of the output terminal OUT2 of shift register RS2 corresponds to the falling edge of the first clock signal (see...). Figure 38 (Dash line 3) The falling edge of the output terminal OUT2 of shift register RS2 corresponds to the falling edge of the third clock signal CCK' (see...). Figure 38 (4) (middle dashed line)

[0385] In this embodiment, by designing the falling edge of the third clock signal to occur no later than the falling edge of the first clock signal, the problem of data signal writing chaos caused by multiple rows of sub-pixels being open simultaneously can be avoided, thus improving the accuracy of sub-pixel data signal writing. Furthermore, the display panel can write data at any time within the sub-pixel open interval, reducing the difficulty of writing data signals to sub-pixels.

[0386] Since the time intervals of the scan control signals output by each shift register do not overlap, it is beneficial to write data to multiple rows of sub-pixels. Therefore, the scan drive circuit with the aforementioned shift registers can also be coupled to the data writing sub-circuit 72 of the pixel circuit as a scan drive circuit to control the data writing sub-circuit 72.

[0387] In some embodiments, the fourth clock signal terminal CCB in each of the above embodiments can be replaced with the third clock signal terminal CCK. It is understood that, in order to reduce the number of signal lines in the scan drive circuit and lower the cost of the scan drive circuit, the third clock signal terminal CCK can be multiplexed as the fourth clock signal terminal CCB.

[0388] When the third clock signal terminal CCK is multiplexed as the fourth clock signal terminal CCB Figure 5 The scan drive circuit shown can be simplified as follows: Figure 39 The scan drive circuit shown. Figure 40 It shows Figure 39 The scan control signals output by the multiple shift registers corresponding to the scan drive circuit shown correspond to the multiple clock signals. Figure 40 The rising and falling edges of the scan control signals output by each shift register can be referenced. Figure 38 The explanations in the text will not be repeated here.

[0389] The embodiments of the present application also provide an electronic device. The electronic device can include a processor and the display panel as described above. The processor can include one or more processing units, for example: the processor can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc.

[0390] For example, the processor can be a GPU. After the GPU renders and composites the display content to form the display data, the GPU can send the display data to the display panel to control the display panel to display a display picture corresponding to the display data.

[0391] The electronic device can include at least one of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a wearable device, a vehicle-mounted device, a smart home device, or a smart city device, etc. The embodiments of the present application do not have special limitations on the specific type of the electronic device 100.

[0392] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0393] The above describes only the specific implementation of the present application, but the protection scope of the present application is not limited thereto, any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A shift register, characterized by, The shift register comprises a first node, a second node, a first voltage terminal, a second voltage terminal, an output terminal, a first output circuit, a second output circuit and a first control circuit; The first output circuit is coupled with the first node, the first voltage terminal and the output terminal; the first output circuit is configured to write a first voltage signal provided by the first voltage terminal to the output terminal under control of a voltage of the first node; The second output circuit is coupled with the second node, the second voltage terminal and the output terminal; the second output circuit is configured to write a second voltage signal provided by the second voltage terminal to the output terminal under control of a voltage of the second node; The voltage value of the second voltage signal is less than the voltage value of the first voltage signal; The first control circuit is coupled with the second node; the first control circuit is configured to pull down the voltage of the second node in a process in which the output terminal outputs the first voltage signal switches to output the second voltage signal.

2. The shift register of claim 1, wherein, The shift register further comprises an input signal terminal, a first control source, a second control source and a third control source; The first control circuit comprises: An input sub-circuit coupled with the input signal terminal, the third control source and the second node; the input sub-circuit is configured to transmit an input signal provided by the input signal terminal to the second node under control of a third control signal provided by the third control source; A pull-down sub-circuit coupled with the first control source, the second control source, the first voltage terminal and the second node; the pull-down sub-circuit is configured to pull down the voltage of the second node in a process in which the input sub-circuit writes the input signal to the second node.

3. The shift register of claim 2, wherein, The shift register further comprises a third node; The pull-down sub-circuit comprises: A first voltage regulating unit coupled with the first voltage terminal, the third node and the first control source; the first voltage regulating unit is configured to write the first voltage signal provided by the first voltage terminal to the third node under control of a first control signal provided by the first control source; A second voltage regulating unit coupled with the second control source, the third node and the second node; the second voltage regulating unit is configured to write a second control signal provided by the second control source to the third node under control of the voltage of the second node; A pull-down unit coupled with the third node and the second node; the pull-down unit is configured to pull down the voltage of the second node in a case where the voltage of the third node drops.

4. The shift register of claim 3, wherein The first voltage regulating unit comprises a first control transistor; a first electrode of the first control transistor is coupled with the first voltage terminal, a second electrode of the first control transistor is coupled with a third node, and a control electrode of the first control transistor is coupled with the first control source; the first control transistor is configured to write the first voltage signal provided by the first voltage terminal to the third node under the control of the first control signal provided by the first control source; and / or, The second voltage regulating unit comprises a second control transistor; a first electrode of the second control transistor is coupled with the second control source, a second electrode of the second control transistor is coupled with the third node, and a control electrode of the second control transistor is coupled with the second node; the second control transistor is configured to write the second control signal provided by the second control source to the third node under the control of the voltage of the second node. and / or, The pull-down unit comprises a capacitor; a first electrode plate of the capacitor is coupled with the third node, and a second electrode plate of the capacitor is coupled with the second node; the capacitor is configured to pull down the voltage of the second node in the case that the voltage of the third node drops.

5. The shift register according to any one of claims 2-4, wherein, The input sub-circuit comprises: a first input transistor; a first electrode of the first input transistor is coupled with the input signal terminal, a second electrode of the first input transistor is coupled with the second node, and a control electrode of the first input transistor is coupled with the third control source; the first input transistor is configured to write the input signal provided by the input signal terminal to the second node under the control of the third control signal provided by the third control source.

6. The shift register of any one of claims 2-4, wherein, The input sub-circuit comprises a first input transistor and a second input transistor; a first electrode of the first input transistor is coupled with the input signal terminal, a second electrode of the first input transistor is coupled with a first electrode of the second input transistor, a control electrode of the first input transistor is coupled with the third control source, a second electrode of the second input transistor is coupled with the second node, and a control electrode of the second input transistor is coupled with the second electrode of the first input transistor; under the control of the third control signal provided by the third control source and the input signal provided by the input signal terminal, the first input transistor and the second input transistor are both in a conductive state, and the input signal provided by the input signal terminal is written to the second node.

7. The shift register of any of claims 2-6, wherein, The shift register further comprises a first clock signal terminal and a first input circuit; the first input circuit is coupled with the first clock signal terminal, the input signal terminal and the second node; the first input circuit is configured to write the input signal provided by the input signal terminal to the second node under the control of the first clock signal provided by the first clock signal terminal.

8. The shift register of claim 7, wherein, The first input circuit comprises a second input transistor; a first electrode of the second input transistor is coupled with the input signal terminal, a second electrode of the second input transistor is coupled with the second node, and a control electrode of the second input transistor is coupled with the first clock signal terminal; The second input transistor is configured to write an input signal provided by the input signal terminal to the second node under the control of a first clock signal provided by the first clock signal terminal.

9. The shift register according to claim 7 or 8, characterized in that, The shift register further comprises a third clock signal terminal and a fourth clock signal terminal; The first control source comprises the first clock signal terminal, the second control source comprises the fourth clock signal terminal, and the third control source comprises the third clock signal terminal.

10. The shift register of any one of claims 2-9, wherein, The shift register further comprises a fourth node, a second clock signal terminal, a second input circuit, a second control circuit, and a third control circuit; The second input circuit is coupled with the second voltage terminal, the first clock signal terminal, and the fourth node; the second input circuit is configured to write a second voltage signal provided by the second voltage terminal to the fourth node under the control of a first clock signal provided by the first clock signal terminal; The second control circuit is coupled with the fourth node, the second clock signal terminal, and the first node; The second control circuit is configured to write a second clock signal provided by the second clock signal terminal to the first node under the control of a voltage of the fourth node and a second clock signal provided by the second clock signal terminal; The third control circuit is coupled with the second node, the first voltage terminal, and the first node; the third control circuit is configured to write a first voltage signal provided by the first voltage terminal to the first node under the control of a voltage of the second node.

11. The shift register of claim 10, wherein, The shift register further comprises a third clock signal terminal and a fourth clock signal terminal; The first control source comprises the second clock signal terminal, the second control source comprises the fourth clock signal terminal, and the third control source comprises the third clock signal terminal.

12. The shift register of claim 10, wherein, The first control source comprises the second clock signal terminal, the second control source comprises the first clock signal terminal, and the third control source comprises the first clock signal terminal.

13. The shift register of claim 10, wherein, The shift register further comprises a third clock signal terminal and a fourth clock signal terminal; The first control source comprises the fourth node, the second control source comprises the fourth clock signal terminal, and the third control source comprises the third clock signal terminal.

14. The shift register of any of claims 10-13, wherein, The second input circuit comprises a third input transistor; A first electrode of the third input transistor is coupled with the second voltage terminal, a second electrode of the third input transistor is coupled with the fourth node, and a control electrode of the third input transistor is coupled with the first clock signal terminal; The third input transistor is configured to write a second voltage signal provided by the second voltage terminal to the fourth node under the control of a first clock signal provided by the first clock signal terminal.

15. The shift register according to any one of claims 10-14, wherein, The shift register further comprises a protection circuit and a sixth node; the protection circuit is connected in series between the second input circuit and the second control circuit; The protection circuit is coupled with the fourth node, the sixth node and the second voltage terminal; the second control circuit is directly coupled with the sixth node and indirectly coupled with the fourth node; The protection circuit is configured to write the voltage of the fourth node to the sixth node under the control of a second voltage signal provided by the second voltage terminal.

16. The shift register of claim 15, wherein, The shift register further comprises a third clock signal terminal and a fourth clock signal terminal; The first control source comprises the sixth node, the second control source comprises the fourth clock signal terminal, and the third control source comprises the third clock signal terminal.

17. The shift register of any one of claims 2-15, wherein, The signal provided by the second control source is the same as the signal provided by the third control source.

18. A control method of a shift register, characterized by, The shift register comprises any one of the shift registers according to claims 1-17; and the method comprises: During the process of switching from outputting the first voltage signal to outputting the second voltage signal at the output terminal, the first control circuit pulls down the voltage of the second node.

19. The method of claim 18, wherein, The method is applied to the shift register according to claim 3; and before the process of switching from outputting the first voltage signal to outputting the second voltage signal at the output terminal, the method further comprises: The first voltage regulating unit writes a high voltage signal to the third node; The first control circuit pulling down the voltage of the second node comprises: The second voltage regulating unit writes a low voltage signal to the third node, and the input sub-circuit writes a low voltage signal to the second node; in the case that the voltage of the third node drops, the pull-down unit pulls down the voltage of the second node.

20. A scan driving circuit, comprising: The display panel comprises a plurality of shift registers which are cascaded with each other, wherein at least one of the shift registers is the shift register according to any one of claims 1-17.

21. A display panel, comprising: The display panel comprises: a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns; a scan driving circuit coupled with the plurality of sub-pixels through a plurality of scan signal lines, each of the scan signal lines being coupled with a plurality of sub-pixels located in the same row; wherein at least one of the scan driving circuits comprises the scan driving circuit according to claim 20.

22. An electronic device, comprising: The display panel comprises: a display panel comprising the display panel according to claim 21; a processor configured to provide display data to the display panel. The display panel comprises:

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