Display panel driving method, device, display panel and electronic equipment

Abstract

This application provides a display panel driving method, apparatus, display panel, and electronic device. The method includes: receiving timing synchronization pixel data of a first target pixel and a second target pixel from a timing control chip; determining a first target grayscale voltage of the first target pixel and a second target grayscale voltage of the second target pixel based on the timing synchronization pixel data of the first and second target pixels; determining a target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the position information of the first and second target pixels in the display panel; and driving the first and second target pixels based on the target slew rate, the first target grayscale voltage, and the second target grayscale voltage. This application can make target pixels at different positions correspond to different target slew rates according to the signal delay of the traces in the display panel, which can effectively alleviate the mischarging problem caused by the signal delay effect of the traces in the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel driving method, device, display panel and electronic device. Background Technology

[0002] In large-size display panels, the gate line length increases, and the signal frequency increases with high refresh rates. The RC network formed by the resistance (R) and capacitance (C) of the traces will create a low-pass filtering effect, resulting in signal delay.

[0003] Signal delay can cause the data signal of the current row to be incorrectly charged into the capacitors of pixels in other rows, resulting in a serious mischarging phenomenon. Summary of the Invention

[0004] This application provides a display panel driving method, apparatus, display panel, and electronic device to solve the problem of incorrect charging caused by signal delay due to low-pass filtering effect on the gate line without shortening the charging time.

[0005] In a first aspect, embodiments of this application provide a display panel driving method, the method comprising:

[0006] Receive timing synchronization pixel data of a first target pixel and a second target pixel from a timing control chip; the first target pixel and the second target pixel are located in the same column, and the second target pixel is the pixel in the next row after the first target pixel;

[0007] Based on the time-synchronized pixel data of the first target pixel and the second target pixel, the first target gray level voltage of the first target pixel and the second target pixel are determined.

[0008] Based on the position information of the first target pixel and the second target pixel in the display panel, the target slew rate for the first target grayscale voltage to jump to the second target grayscale voltage is determined;

[0009] The first target pixel and the second target pixel are driven according to the target slew rate, the first target gray level voltage, and the second target gray level voltage.

[0010] In one possible implementation of the first aspect, the position information of the first target pixel and the second target pixel in the display panel includes:

[0011] The position information of the column pixels where the first target pixel and the second target pixel are located, and / or the position information of the row where the first target pixel is located and the row where the second target pixel is located in the display panel;

[0012] Specifically, within the effective display area of ​​the display panel, the target slew rate gradually decreases or decreases in gradient along the direction of transmitting the gate drive signal along the gate line; within the effective display area of ​​the display panel, the target slew rate gradually increases or increases in gradient along the direction of transmitting the source drive signal along the source line.

[0013] In one possible implementation of the first aspect, the display panel includes a plurality of first data driving chips, each of the first data driving chips being connected to at least one column of pixels via a source line, the plurality of first data driving chips having different or partially different first slew rates, the plurality of first data driving chips being arranged along the direction of transmitting gate driving signals along the gate line, and the first slew rate gradually decreasing or decreasing in gradient.

[0014] The step of determining the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the position information of the first target pixel and the second target pixel in the display panel includes:

[0015] The target slew rate at which the first target grayscale voltage jumps to the second target grayscale voltage is determined based on the first slew rate corresponding to the first data driver chip connected to the first target pixel and the second target pixel.

[0016] In one possible implementation of the first aspect, determining the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the first slew rate corresponding to the first data driving chip connected to the first target pixel and the second target pixel includes:

[0017] Obtain a first lookup table; the first lookup table is used to reflect the correspondence between the vertical partitions of the display panel and the slew rate coefficient. Each vertical partition includes one or more rows of adjacent pixels, and within the effective display area of ​​the display panel, along the direction of the source drive signal transmission of the source line, the slew rate coefficient corresponding to the vertical partition gradually increases or increases in gradient. The largest slew rate coefficient in the first lookup table is ≤100%.

[0018] The first target slew rate coefficient is obtained based on the slew rate coefficient corresponding to the vertical partition in the first lookup table where the rows of the first target pixel and the second target pixel are located.

[0019] The target slew rate at which the first target grayscale voltage jumps to the second target grayscale voltage is determined based on the first slew rate corresponding to the first data driver chip connected to the first target pixel and the second target pixel, and the first target slew rate coefficient.

[0020] In one possible implementation of the first aspect, the display panel includes a plurality of second data driving chips, each of the second data driving chips being connected to at least one column of pixels via the source line, the plurality of second data driving chips having the same second slew rate, each of the second data driving chips corresponding to at least one horizontal partition, each of the horizontal partitions including one or more columns of adjacent pixels;

[0021] The step of determining the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the position information of the first target pixel and the second target pixel in the display panel includes:

[0022] Obtain a second lookup table; the second lookup table is used to reflect the correspondence between the horizontal partitions of the display panel and the slew rate coefficient, and within the effective display area of ​​the display panel, along the direction of transmitting the gate drive signal along the gate line, the slew rate coefficient of the horizontal partition gradually decreases or decreases in gradient, and the largest slew rate coefficient in the second lookup table is ≤100%;

[0023] The second target slew rate coefficient is obtained based on the slew rate coefficient corresponding to the horizontal partition of the column pixels where the first target pixel and the second target pixel are located in the second lookup table;

[0024] The target slew rate at which the first target gray level voltage jumps to the second target gray level voltage is determined based on the second target slew rate coefficient and the second slew rate.

[0025] In one possible implementation of the first aspect, the second lookup table is further used to reflect the correspondence between the vertical partitions of the display panel and the slew rate coefficient, each vertical partition includes one or more rows of adjacent pixels, and within the effective display area of ​​the display panel, along the direction of the source drive signal delivered by the source line, the slew rate coefficient of the vertical partition gradually increases or increases in gradient.

[0026] The step of obtaining the second target slewing rate coefficient based on the slewing rate coefficient corresponding to the horizontal partition of the column pixels where the first target pixel and the second target pixel are located in the second lookup table includes:

[0027] The second target slewing rate coefficient is obtained by taking the slewing rate coefficient at the intersection of the horizontal partition where the column pixels of the first target pixel and the second target pixel are located in the second lookup table and the vertical partition where the row pixels of the first target pixel and the second target pixel are located in the second lookup table.

[0028] In one possible implementation of the first aspect, the gate line delivers the gate drive signal in the direction of: from both ends of the display panel toward the middle.

[0029] Secondly, embodiments of this application provide a display panel driving device, including:

[0030] The receiving unit is used to receive timing synchronization pixel data of a first target pixel and a second target pixel from the timing control chip; the first target pixel and the second target pixel are located in the same column, and the second target pixel is the pixel in the next row after the first target pixel;

[0031] The first determining unit is configured to determine the first target grayscale voltage of the first target pixel and the second target pixel based on the time-synchronized pixel data of the first target pixel and the second target pixel.

[0032] The second determining unit is used to determine the target slew rate of the first target grayscale voltage jump to the second target grayscale voltage based on the position information of the first target pixel and the second target pixel in the display panel;

[0033] The driving unit is configured to drive the first target pixel and the second target pixel according to the target slew rate, the first target grayscale voltage and the second target grayscale voltage.

[0034] Thirdly, embodiments of this application also provide a display panel, wherein a timing control chip and a plurality of data driver chips are disposed on the display panel, and any one of the plurality of data driver chips is used to perform the method as described in any embodiment of the first aspect.

[0035] Fourthly, embodiments of this application provide an electronic device including the display panel described in the third aspect.

[0036] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in any one of the first aspects.

[0037] In a sixth aspect, embodiments of this application provide a computer program product that, when run on an electronic device, causes the electronic device to perform the method described in any one of the first aspects.

[0038] It is understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0039] The beneficial effects of this embodiment compared to the prior art are as follows: This embodiment determines the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the position information of the first target pixel and the second target pixel in the display panel. This allows different target slew rates for target pixels at different positions based on the signal delay of the traces in the display panel, effectively mitigating the charging error problem caused by the signal delay effect of the traces in the display panel. Compared to the traditional method commonly used in the industry that sacrifices charging time to avoid charging errors, this embodiment significantly reduces the probability of charging errors without shortening the pixel charging time, thereby improving the quality and stability of the display image. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1A This is a schematic diagram of voltage jumps when an existing display panel experiences incorrect charging.

[0042] Figure 1B This is a schematic diagram of voltage jumps that currently solve the problem of incorrect charging by sacrificing pixel charging time;

[0043] Figure 2 This is a schematic diagram of the charging principle of a current TFT-LCD display panel;

[0044] Figure 3 This is a schematic diagram of the external frame of an existing display panel;

[0045] Figure 4 This is a flowchart illustrating the display panel driving method provided in an embodiment of this application;

[0046] Figure 5 This is a comparison diagram of the data signal provided in the embodiments of this application under high voltage slew rate and low voltage slew rate states;

[0047] Figure 6 This application provides a comparison diagram of voltage jumps with and without reduced slew rate, as shown in the embodiments of this application.

[0048] Figure 7 This is a schematic diagram of the structure of the external frame of the display panel provided in one embodiment of this application;

[0049] Figure 8 This is a schematic diagram of voltage jumps with different slew rates provided in the embodiments of this application;

[0050] Figure 9 This is a voltage jump diagram showing insufficient charging at the top of the source line due to a decrease in the slew rate of the data signal provided in the embodiments of this application;

[0051] Figure 10 This is a schematic diagram of the structure of the external frame of the display panel provided in another embodiment of this application;

[0052] Figure 11 This is a schematic diagram of the structure of the display panel driving device provided in the embodiments of this application. Detailed Implementation

[0053] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0054] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0055] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0056] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0057] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0058] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0059] In a display panel, the RC network formed by resistors (R) and capacitors (C) can cause signal delay, leading to mischarging.

[0060] like Figure 1A As shown, the falling edge delay of the gate signal (i.e., the gate signal) causes the second row of data signals (i.e., the data signal, used to provide the target grayscale voltage to the pixel capacitor) to arrive on the source line before the gate signal of the first row has dropped to the TFT turn-off voltage. Because the TFT (Thin Film Transistor) has not yet been turned off at this time, the data signal of the second row will be incorrectly charged into the pixel capacitor of the first row, resulting in a serious mischarging phenomenon.

[0061] To prevent incorrect charging, a standard industry practice is to set up anti-mischarge time intervals. For example... Figure 1B As shown, advancing the falling edge of the gate signal ensures that the signal on the source line is still the first row of data signals when the gate signal drops to the TFT turn-off voltage. However, this approach comes at the cost of sacrificing pixel charging time, which may lead to undercharging. As the size and refresh rate of display panels increase, the contradiction between ensuring charging time and reducing mischarging due to signal delay caused by the RC characteristics on the gate line becomes increasingly significant.

[0062] The charging principle of TFT-LCD display panels is as follows: Figure 2 As shown, the scan signal (i.e., Scan signal) is the gate signal (i.e. Gate signal) of the switching TFT (ThinFilm Transistor). When the scan signal is high, the TFTs of the entire row of the panel are switched on, and each source line sends the data signal to the pixel capacitor to charge the pixel capacitor to the same voltage as the data signal (target gray level voltage) and maintain it for one frame (the time it takes for all rows of the panel to be scanned once).

[0063] The external architecture of a TFT-LCD display panel is as follows Figure 3As shown, the PCBA (Printed Circuit Board Assembly) has a timing control chip (i.e., Tcon IC) and a gamma IC (gamma voltage level generation chip). The PCBA is connected to multiple data driver ICs (also called source driver chips). Each data driver chip is connected to multiple source lines, and transmits data signals (i.e., data signals) to the capacitor of the pixel through the source lines, so that the capacitor of the corresponding pixel is charged to the target gray level voltage.

[0064] As display panel sizes increase, gate line lengths increase, and gate signal frequencies increase, signals experience delays after passing through a certain length of gate line due to low-pass filtering. This can cause data signals from the second row to be incorrectly charged into the pixel capacitors of the first row, resulting in a serious mischarging phenomenon.

[0065] Example 1:

[0066] To solve the problem of incorrect filling Figure 4 A schematic flowchart of the display panel driving method provided in this application is shown. The method is applied to any one of a plurality of data driving chips in the display panel, and the method includes steps S110-S140.

[0067] S110: Receive timing synchronization pixel data of the first target pixel and the second target pixel from the timing control chip; the first target pixel and the second target pixel are located in the same column, and the second target pixel is the pixel in the next row of the first target pixel.

[0068] Specifically, timing-synchronized pixel data refers to pixel data containing precise timing information after being processed by the timing control chip (Tcon IC). Its function is to ensure that the pixel data is received and output by the data driver chip at the correct time, thereby achieving stable display of the image.

[0069] For example, for a UHD (Ultra High Definition) resolution (3840*2160) display panel, which includes 3840 columns of pixels and 2160 rows of pixels, if the display panel has a total of 6 data driver chips, the timing control chip allocates the 3840 column pixel data of the current row according to the pixel area each of the 6 data driver chips is responsible for. Each data driver chip is responsible for driving a portion of the column pixels, and the timing control chip sends the corresponding pixel data and the generated timing signal to the corresponding data driver chip through the data bus. For example, the leftmost data driver chip on the display panel is connected to the 1st to 640th column pixels through a source line, the second data driver chip from the left to the right on the display panel is connected to the 641st to 1208th column pixels through a source line, and so on.

[0070] The first target pixel and the second target pixel are located in the same column, and the second target pixel is the pixel in the next row of the first target pixel. Therefore, the data driver chip first receives the timing synchronization pixel data of the first target pixel from the timing control chip, and then receives the timing synchronization pixel data of the second target pixel.

[0071] S120: Based on the time-synchronized pixel data of the first target pixel and the second target pixel, determine the first target grayscale voltage of the first target pixel and the second target grayscale voltage of the second target pixel.

[0072] After receiving the timing synchronization pixel data, the data driver chip converts the digital pixel data into an analog voltage signal, namely the target grayscale voltage. The target grayscale voltage is used to drive the corresponding pixels on the display panel so that they display the correct grayscale and brightness.

[0073] S130: Determine the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the position information of the first target pixel and the second target pixel in the display panel.

[0074] Specifically, slew rate (SR) refers to the maximum rate of change of voltage per unit time. Also known as voltage slew rate or voltage transition rate, the formula is: Slew Rate = ΔV / Δt. A higher slew rate means that the signal can transition from one level to another more quickly. When charging or discharging the pixel capacitor, the target grayscale voltage can be reached more rapidly, making the state switching of the pixel capacitor more efficient and thus reducing motion blur.

[0075] Each data driver chip has its own basic slew rate (original slew rate). By adjusting the slew rate of the data driver chip, or by using data driver chips with different original slew rates, the first target pixel and the second target pixel at different positions can have different slew rates.

[0076] The terminal of the data driver chip that outputs the data signal (used to provide the target grayscale voltage to the pixel capacitor) is an OP (operational amplifier). For example... Figure 5 As shown, the imaginary line A represents a higher slew rate, and the real line B represents a lower slew rate. By controlling the slew rate of the OP output signal, the speed of data signal transitions can be slowed down, thereby improving the mischarging phenomenon that occurs as the gate line length increases.

[0077] like Figure 6 As shown, the first target pixel is located in the first row, and the second target pixel is located in the second row. It should be noted that the first row and the second row can refer to any two adjacent rows in the display panel. Figure 6 The data signal in the upper and middle graphs does not undergo any measures to reduce the slew rate (e.g., the original slew rate is used). Figure 6The data signal in the lower middle diagram has undergone measures to reduce the slew rate. Without these measures, the voltage of the first target grayscale level jumps to the second target grayscale level quickly. When the TFT is turned off, the data signal of the first row has already deviated significantly from the first target grayscale level, resulting in a charging error. Because... Figure 6 As the slew rate of the data signal decreases, the speed at which the first target gray level voltage jumps to the second target gray level voltage slows down. When the TFT is turned off, the data signal of the first row is in this transition process due to the gate line delay. Therefore, after the slew rate reduction measure is taken, the data signal is still very close to the first target gray level voltage of the first row due to the slow transition, thereby reducing the occurrence of mischarging.

[0078] Because current large-size display panels transmit scan signals simultaneously from both ends of the same gate line, the RC delay of the gate line is minimal at the left and right ends and maximum in the middle. Therefore, from the ends to the middle in the gate line direction (horizontal direction), the source line closest to the ends is made to have a high slew rate (such as the original slew rate), and the slew rate decreases as the source line gets closer to the middle (such as reducing the original slew rate).

[0079] S140: Drive the first target pixel and the second target pixel according to the target slew rate, the first target gray level voltage and the second target gray level voltage.

[0080] Specifically, the operational amplifier (OP) at the output end of the data driver chip can switch the first target grayscale voltage to the second target grayscale voltage at a voltage switching rate determined by the target slew rate. By changing the slew rate, even with RC delay in the gate line, the data signal can be made to switch slowly due to the voltage switching, thereby reducing the risk of incorrect charging and avoiding undercharging caused by sacrificing pixel charging time.

[0081] This embodiment determines the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the position information of the first and second target pixels in the display panel. This allows different target slew rates for target pixels at different positions based on the signal delay of the traces (including gate and source lines) in the display panel, effectively mitigating the charging error problem caused by the signal delay effect of the traces in the display panel. Compared to the traditional method commonly used in the industry that sacrifices charging time to avoid charging errors, this embodiment significantly reduces the probability of charging errors without shortening pixel charging time, thereby improving the quality and stability of the display image.

[0082] As an optional implementation, S130 specifically includes S131.

[0083] S131: Position information of the column pixels where the first target pixel and the second target pixel are located, and / or, position information of the row where the first target pixel and the row where the second target pixel are located in the display panel; wherein, within the effective display area of ​​the display panel, the target slew rate gradually decreases or the gradient decreases along the direction of the gate drive signal being delivered along the gate line; within the effective display area of ​​the display panel, the target slew rate gradually increases or the gradient increases along the direction of the source drive signal being delivered along the source line.

[0084] Specifically, within the effective display area of ​​the display panel, the gate lines are arranged horizontally. In small-sized LCD panels, due to the smaller load on the gate lines, the gate drive signal can be transmitted horizontally from the left to the right of the display panel. In medium- and large-sized LCD panels, due to the larger load on the gate lines, a dual-side drive method can be used, meaning the gate drive signal is transmitted horizontally from both ends of the display panel towards the middle.

[0085] As the gate drive signal is delivered along the gate line, the signal delay of the gate line increases, thereby gradually reducing the target slew rate or gradient in this embodiment. This causes the voltage jump to gradually slow down or the gradient to slow down. As a result, when the TFT is turned off, the data signal of the first row is in the jump process due to the gate line delay. Because the jump is slow, the data signal is still very close to the first target gray level voltage of the first row, thereby reducing the occurrence of mischarging.

[0086] Within the effective display area of ​​the display panel, the source lines are arranged vertically, and the direction in which the source lines transmit the source drive signal can be from the bottom to the top of the display panel.

[0087] For each source line, the data signal is transmitted from the bottom to the top, therefore the signal delay of the data signal will be greater. For example... Figure 9 As shown, the data signal of the top source line jumps too slowly due to the influence of RC delay and reduced slew rate, and cannot reach the target gray level voltage, resulting in insufficient charging. Therefore, in this embodiment, as the number of scan lines approaches the top, the restriction on slew rate is gradually released, and the incorrect charging is improved while ensuring that insufficient charging does not occur.

[0088] As an optional implementation, the plurality of data driving chips in the display panel are all first data driving chips. Each first data driving chip is connected to at least one column of pixels through a source line. The plurality of first data driving chips have different or partially different first slew rates. The plurality of first data driving chips are arranged along the direction of transmitting gate driving signals along the gate line (i.e., arranged in a horizontal direction), and the first slew rate gradually decreases or decreases in gradient. In this embodiment, S130 includes S132.

[0089] S132: Determine the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the first slew rate corresponding to the first data driving chip connected to the first target pixel and the second target pixel.

[0090] For example, the large-size display panel of this embodiment has a plurality of first data driving chips, the plurality of first data driving chips having different or partially different first slew rates, and the first slew rate gradually decreases from both ends of the display panel to the middle.

[0091] See Figure 7 The display panel uses three types of first slew rates that decrease sequentially in the horizontal direction (see appendix for the first slew rates of the three types of first data driver chips). Figure 8 The first data driver chips are identical to other parameters and specifications. There are six first data driver chips in total. In the display panel arrangement, the first data driver chips with higher slew rates (Class 1) are placed at the left and right ends of the display panel, where the gate line signal delay is relatively small. The first data driver chips with lower slew rates (Class 3) are placed in the middle area of ​​the panel, where the gate line RC delay effect is most significant. The first data driver chips with medium slew rates (Class 2) are placed between the Class 3 and Class 1 first data driver chips. In this way, a target slew rate matching the RC delay characteristics of the source line can be provided at different lateral positions, thereby achieving initial control of the signal transition speed without increasing the computational burden on the timing control chip.

[0092] It is easy to understand that the first target pixel and the second target pixel are connected to the first data driver chip via source lines. For the first target pixel and the second target pixel, their corresponding target slew rate is determined by the first slew rate inherent in the first data driver chip itself, which is connected by the source lines. This means that the specific slew rate characteristics of the output signal of the first data driver chip are fixed at the factory or during its design. When the first data driver chip is installed at a specific horizontal position on the display panel, the first target pixel and the second target pixel inherit the first slew rate of the first data driver chip.

[0093] Since the lateral slew rate adjustment is achieved by selecting and deploying different types of hardware (i.e., first data driver chips with different first slew rates), the timing control chip does not need to perform complex real-time calculations or dynamic settings for the slew rates corresponding to the first and second target pixels during operation. Instead, the first data driver chip uses its inherent first slew rate characteristics to transition the first target grayscale voltage to the second target grayscale voltage. This design reduces the computing power and storage capacity requirements of the timing control chip, while also reducing the complexity of the first data driver chip itself, resulting in a lower overall solution cost. It is particularly suitable for large-size high refresh rate panels (such as 55-inch and 65-inch panels) that are cost-sensitive and of relatively moderate size.

[0094] Specifically, S132 includes S133-S135.

[0095] S133: Obtain the first lookup table; the first lookup table is used to reflect the correspondence between the vertical partitions of the display panel and the slew rate coefficient. Each vertical partition includes one or more rows of adjacent pixels. In the effective display area of ​​the display panel, along the direction of the source drive signal transmission of the source line, the slew rate coefficient corresponding to the vertical partition gradually increases or increases in gradient, and the maximum slew rate coefficient is ≤100%.

[0096] Specifically, the first lookup table can be stored in the timing control chip (see...). Figure 7 The first data driver chip can call the first lookup table from the timing control chip, and can also debug the first lookup table in the timing control chip; in addition, the first lookup table can also be written into the first data driver chip.

[0097] For example, taking a 75-inch UHD resolution (3840*2160) display panel as an example, the vertical partitioning can be designed as follows: rows 1 to 270 are zone 1, rows 271 to 540 are zone 2, ... rows 1891 to 2160 are zone 8. Each zone corresponds to a different degree of slew rate restriction. As the partition value is smaller, the restriction is smaller. 100% means no restriction. The vertical partitioning of the slew rate is set as shown in Table 1 below.

[0098] Table 1 First Comparison Table

[0099]

[0100] Specifically, the row address of the current row of pixels can be determined based on the timing synchronization pixel data. The timing control chip can determine the target vertical partition based on the row address in the timing synchronization pixel data and the first lookup table.

[0101] S134: Obtain the first target slewing rate coefficient based on the slewing rate coefficient corresponding to the vertical partition of the row where the first target pixel and the second target pixel are located in the first lookup table.

[0102] For example, the first target pixel and the second target pixel are located in rows 100 and 101, respectively. Therefore, the vertical partition of the row where the first target pixel and the second target pixel are located in the first lookup table is zone 1. As can be seen from the above vertical partition table, the slewing rate coefficient of zone 1 is 100%, so the slewing rate coefficient of the first target pixel is 100%.

[0103] S135: Determine the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the first slew rate corresponding to the first data driving chip connected to the first target pixel and the second target pixel, and the first target slew rate coefficient.

[0104] Specifically, in this embodiment, the target slew rate for the first target pixel and the second target pixel is determined based on information from two dimensions: first, the first slew rate corresponding to the first data driver chip connected to the first target pixel and the second target pixel; and second, the first target slew rate coefficient. In this embodiment, the target slew rate = the first slew rate corresponding to the first data driver chip connected to the first target pixel and the second target pixel * the first target slew rate coefficient.

[0105] This embodiment mitigates the charging error problem caused by the RC delay of the gate line through a first lateral slew rate, while the slew rate coefficient of the vertical partition further optimizes the impact of the RC delay of the source line itself on the charging effect. By multiplying the two, the first data driver chip can generate a comprehensive optimal slew rate that takes into account both lateral charging error and vertical charging efficiency for the charging process of each target pixel. This can effectively reduce the occurrence of undercharging while reducing the possibility of charging error, thereby improving the overall display performance.

[0106] As an optional implementation, the multiple data driving chips in the display panel are all second data driving chips. Each second data driving chip is connected to at least one column of pixels through a source line. The multiple second data driving chips have the same second slew rate. Each second data driving chip corresponds to at least one horizontal partition. Each horizontal partition includes one or more columns of adjacent pixels.

[0107] Correspondingly, S130 above includes S136-S138.

[0108] S136: Obtain the second lookup table; the second lookup table is used to reflect the correspondence between the horizontal partitions of the display panel and the slew rate coefficient. In the effective display area of ​​the display panel, along the direction of the gate drive signal transmission of the gate line, the slew rate coefficient of the horizontal partition gradually decreases or decreases in gradient, and the maximum slew rate coefficient is ≤100%.

[0109] Specifically, unlike the above embodiments with first data driver chips having different first slew rates, the multiple second data driver chips on the display panel in this embodiment all have the same second slew rate, and the slew rate is adjusted horizontally by looking up a second lookup table.

[0110] The second lookup table can be stored in the timing control chip or written into the data driver chip.

[0111] The timing synchronization pixel data includes column addresses. The timing control chip can determine the horizontal partition to which the first target pixel and the second target pixel belong based on the column addresses in the second lookup table.

[0112] See Figure 10 The display panel has six second data driver chips, each controlling two horizontal partitions, resulting in 12 horizontal partitions for more precise slew rate adjustment. It's easy to understand that, depending on the size of the display panel, each second data driver chip can control more (e.g., three or more) or fewer (e.g., one) horizontal partitions.

[0113] The reason this embodiment is designed so that the slew rate coefficient of the horizontal partition gradually decreases or the gradient decreases along the direction of delivering the gate drive signal along the gate line (i.e., from both ends of the display panel to the middle) is because current display panels are large in size, so the gate drive signal is delivered simultaneously from both ends of the gate line to the middle. Therefore, as the gate line extends towards the middle, the signal delay on the gate line becomes increasingly severe.

[0114] S137: Obtain the second target slew rate coefficient based on the slew rate coefficient corresponding to the horizontal partition of the column pixel where the first target pixel and the second target pixel are located in the second lookup table.

[0115] S138: Determine the target slew rate for the transition from the first target gray level voltage to the second target gray level voltage based on the second target slew rate coefficient and the second slew rate.

[0116] Specifically, in this embodiment, the target slewing rate = the second slewing rate * the second target slewing rate coefficient.

[0117] This embodiment combines a second data driver chip with a unified second slew rate with a software-defined lateral adjustment strategy (slew rate coefficient) to generate a customized target slew rate for the first target pixel and the second target pixel, thereby reducing the mischarging phenomenon caused by gate line signal delay at different lateral positions.

[0118] As an optional implementation, considering the problem that the signal delay of the data signal increases from the bottom to the top of the source line, the second lookup table in this embodiment is also used to reflect the correspondence between the vertical partitions of the display panel and the slew rate coefficient. Each vertical partition includes one or more rows of adjacent pixels, and within the effective display area of ​​the display panel, the slew rate coefficient of the vertical partition gradually increases or the gradient increases along the direction of the source drive signal delivered along the source line (i.e. from the bottom to the top of the display panel).

[0119] Correspondingly, S138 also includes S139.

[0120] S139: The second target slewing rate coefficient is obtained by taking the slewing rate coefficient at the intersection of the horizontal partition of the column pixel where the first target pixel and the second target pixel are located in the second lookup table and the vertical partition of the row where the first target pixel and the second target pixel are located in the second lookup table.

[0121] Specifically, the row addresses of the first target pixel and the second target pixel can be determined from the timing synchronization pixel data. The timing control chip can then determine the target vertical partition of the first target pixel and the second target pixel in the second lookup table based on the row addresses in the timing synchronization pixel data.

[0122] Substituting the second target slewing rate coefficient from S139 into S138 yields the target slewing rate in this embodiment. Specifically, in this embodiment, the target slewing rate = the second slewing rate * the second target slewing rate coefficient obtained in S139.

[0123] See Figure 10 In this embodiment, the display panel is divided into sections, and each section has a corresponding slew rate coefficient. The overall second lookup table can be stored in the timing control chip, and the second lookup table is called when the second data driver chip outputs a signal.

[0124] For example, a second lookup table is shown in Table 2:

[0125] Table 2 Second Comparison Table

[0126]

[0127] This embodiment calculates a comprehensive slew rate coefficient by combining the lateral and longitudinal signal delay characteristics, and adjusts the target slew rate of the second data driver chip output based on this coefficient. This helps reduce the mischarging phenomenon caused by lateral gate line signal delay and effectively improves the problem of insufficient pixel charging caused by longitudinal source line signal delay.

[0128] This embodiment improves the flexibility and programmability of the display panel, and is especially suitable for extra-large display panels (such as 85-inch and 100-inch) that require higher control precision, because extra-large display panels usually require more precise SR distribution adjustment to cope with more complex signal transmission challenges.

[0129] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0130] Example 2:

[0131] Corresponding to the display panel driving method described in the above embodiments, Figure 11 A structural block diagram of a display panel driving device provided in an embodiment of this application is shown. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0132] Reference Figure 11 The device includes:

[0133] The receiving unit 210 is used to receive timing synchronization pixel data of a first target pixel and a second target pixel from the timing control chip; the first target pixel and the second target pixel are located in the same column, and the second target pixel is the pixel in the next row after the first target pixel;

[0134] The first determining unit 220 is used to determine the first target gray level voltage of the first target pixel and the second target gray level voltage of the second target pixel based on the time-synchronized pixel data of the first target pixel and the second target pixel.

[0135] The second determining unit 230 is used to determine the target slew rate of the first target gray level voltage jump to the second target gray level voltage based on the position information of the first target pixel and the second target pixel in the display panel.

[0136] The driving unit 240 is used to drive the first target pixel and the second target pixel according to the target slew rate, the first target gray level voltage and the second target gray level voltage.

[0137] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0138] Example 3:

[0139] This application embodiment also provides a display panel, on which a timing control chip and a plurality of first data driving chips are disposed. The plurality of first data driving chips have different or partially different first slew rates. The plurality of first data driving chips are arranged along the direction of transmitting gate driving signals along the gate line, and the first slew rate of the first data driving chips gradually decreases.

[0140] Any of the first data driver chips is used to perform the following steps:

[0141] Receive timing synchronization pixel data of a first target pixel and a second target pixel from the timing control chip; the first target pixel and the second target pixel are located in the same column, and the second target pixel is the pixel in the next row after the first target pixel;

[0142] Based on the time-synchronized pixel data of the first target pixel and the second target pixel, the first target gray level voltage of the first target pixel and the second target gray level voltage of the second target pixel are determined.

[0143] Based on the first slew rate corresponding to the first data driving chip connected to the first target pixel and the second target pixel, the target slew rate for the first target gray level voltage to jump to the second target gray level voltage is determined.

[0144] The first target pixel and the second target pixel are driven according to the target slew rate, the first target gray level voltage and the second target gray level voltage.

[0145] As an optional implementation, when the first data driver chip performs the step of determining the target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage based on the first slew rate corresponding to the first data driver chip connected to the first target pixel and the second target pixel, it is specifically configured as follows:

[0146] Obtain the first lookup table; the first lookup table is used to reflect the correspondence between the vertical partitions of the display panel and the slew rate coefficient. Each vertical partition includes one or more rows of adjacent pixels, and within the effective display area of ​​the display panel, along the direction of the source drive signal transmission along the source line, the slew rate coefficient corresponding to the vertical partition gradually increases or increases in gradient. The largest slew rate coefficient in the first lookup table is ≤100%.

[0147] The first target slew rate coefficient is obtained based on the slew rate coefficient corresponding to the vertical partition of the row where the first target pixel and the second target pixel are located in the first lookup table.

[0148] The target slew rate for the transition from the first target grayscale voltage to the second target grayscale voltage is determined based on the first slew rate corresponding to the first data driving chip connected to the first target pixel and the second target pixel, and the first target slew rate coefficient.

[0149] Example 4:

[0150] This application embodiment also provides a display panel, on which a timing control chip and a plurality of second data driving chips are disposed. Each second data driving chip is connected to at least one column of pixels through a source line. The plurality of second data driving chips have the same second slew rate. Each second data driving chip corresponds to at least one horizontal partition. Each horizontal partition includes one or more columns of adjacent pixels.

[0151] Any second data driver chip is configured as follows:

[0152] Receive timing synchronization pixel data of a first target pixel and a second target pixel from the timing control chip; the first target pixel and the second target pixel are located in the same column, and the second target pixel is the pixel in the next row after the first target pixel;

[0153] Based on the time-synchronized pixel data of the first target pixel and the second target pixel, the first target gray level voltage of the first target pixel and the second target gray level voltage of the second target pixel are determined.

[0154] Obtain the second lookup table; the second lookup table is used to reflect the correspondence between the horizontal partitions of the display panel and the slew rate coefficient. Within the effective display area of ​​the display panel, along the direction of the gate drive signal transmission of the gate line, the slew rate coefficient of the horizontal partition gradually decreases or decreases in gradient. The maximum slew rate coefficient in the second lookup table is ≤100%.

[0155] The second target slew rate coefficient is obtained based on the slew rate coefficient corresponding to the horizontal partition of the column pixel where the first target pixel and the second target pixel are located in the second lookup table.

[0156] Based on the second target slew rate coefficient and the second slew rate, determine the target slew rate for the transition from the first target gray level voltage to the second target gray level voltage;

[0157] The first target pixel and the second target pixel are driven according to the target slew rate, the first target gray level voltage and the second target gray level voltage.

[0158] As an optional implementation, the second lookup table is also used to reflect the correspondence between the vertical partitions of the display panel and the slew rate coefficient. Each vertical partition includes one or more rows of adjacent pixels, and within the effective display area of ​​the display panel, along the direction of the source drive signal delivered by the source line, the slew rate coefficient of the vertical partition gradually increases or the gradient increases.

[0159] When the second data driver chip performs the step of obtaining the second target slew rate coefficient based on the slew rate coefficient corresponding to the horizontal partition in the second lookup table where the column pixels of the first and second target pixels are located, it is specifically configured as follows:

[0160] The second target slew rate coefficient is obtained by taking the slew rate coefficient at the intersection of the horizontal partition of the column pixel where the first target pixel and the second target pixel are located in the second lookup table and the vertical partition of the row where the first target pixel and the second target pixel are located in the second lookup table.

[0161] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0162] Example 5:

[0163] This application also provides an electronic device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the steps in any of the above method embodiments.

[0164] Example 6:

[0165] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0166] Example 7:

[0167] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0168] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to an electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0169] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0170] Computer program code for performing the operations of the embodiments of this application can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include object-oriented programming languages ​​such as Python, Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0171] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0172] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0173] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0174] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0175] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display panel driving method, characterized by, The method comprises: receiving time sequence synchronization pixel data of a first target pixel and a second target pixel from a time sequence control chip; the first target pixel and the second target pixel are located in the same column, and the second target pixel is a next row pixel of the first target pixel; determining a first target gray scale voltage of the first target pixel and a second target gray scale voltage of the second target pixel according to the time sequence synchronization pixel data of the first target pixel and the second target pixel; determining a target slew rate of the first target gray scale voltage jumping to the second target gray scale voltage according to position information of the first target pixel and the second target pixel in the display panel; the position information of the first target pixel and the second target pixel in the display panel comprises position information of a column pixel where the first target pixel and the second target pixel are located and position information of rows where the first target pixel and the second target pixel are located in the display panel; wherein, within an effective display area of the display panel, the limit on the target slew rate is gradually increased along a direction of conveying a gate driving signal of a gate line, so that the target slew rate is gradually reduced or gradiently reduced; within the effective display area of the display panel, the limit on the target slew rate is gradually released along a direction of conveying a source driving signal of a source line, so that the target slew rate is gradually increased or gradiently increased; driving the first target pixel and the second target pixel according to the target slew rate, the first target gray scale voltage and the second target gray scale voltage.

2. The display panel driving method according to claim 1, wherein The display panel comprises a plurality of first data driving chips; any first data driving chip is connected with at least one column of pixels through a source line; the plurality of first data driving chips have first slew rates which are all different or partially different; the plurality of first data driving chips are arranged along a direction of conveying a gate driving signal of a gate line, and the first slew rates are gradually reduced or gradiently reduced; The method comprises: determining the target slew rate of the first target gray scale voltage jumping to the second target gray scale voltage according to the first slew rate corresponding to the first data driving chip connected with the first target pixel and the second target pixel.

3. The display panel driving method according to claim 2, wherein The method comprises: determining the target slew rate of the first target gray scale voltage jumping to the second target gray scale voltage according to the first slew rate corresponding to the first data driving chip connected with the first target pixel and the second target pixel. The method comprises: obtain a first correspondence table, the first correspondence table reflecting a correspondence between longitudinal partitions of the display panel and a slew rate coefficient, each of the longitudinal partitions including one or more rows of adjacent pixels, and in an effective display area of the display panel, the slew rate coefficient corresponding to the longitudinal partitions gradually increases or gradually increases in gradient, and the maximum slew rate coefficient in the first correspondence table is less than or equal to 100%; obtain a first target slew rate coefficient according to a slew rate coefficient corresponding to a longitudinal partition in which a row of the first target pixel and the second target pixel is located in the first correspondence table; determine the target slew rate at which the first target gray scale voltage jumps to the second target gray scale voltage according to the first slew rate corresponding to the first data driving chip connected to the first target pixel and the second target pixel and the first target slew rate coefficient.

4. The display panel driving method according to claim 1, wherein The display panel includes a plurality of second data driving chips, any of the second data driving chips being connected to at least one column of pixels through the source line, and the plurality of second data driving chips all having the same second slew rate, each of the second data driving chips corresponding to at least one horizontal partition, each of the horizontal partitions including one or more columns of adjacent pixels; The method further includes: obtain a second correspondence table, the second correspondence table reflecting a correspondence between the horizontal partitions of the display panel and a slew rate coefficient, and in an effective display area of the display panel, the slew rate coefficient of the horizontal partitions gradually decreases or gradually decreases in gradient, and the maximum slew rate coefficient in the second correspondence table is less than or equal to 100%; obtain a second target slew rate coefficient according to a slew rate coefficient corresponding to a horizontal partition in which a column of pixels in which the first target pixel and the second target pixel are located is located in the second correspondence table; determine the target slew rate at which the first target gray scale voltage jumps to the second target gray scale voltage according to the second target slew rate coefficient and the second slew rate.

5. The display panel driving method according to claim 4, wherein The second correspondence table is also used to reflect a correspondence between longitudinal partitions of the display panel and the slew rate coefficient, each of the longitudinal partitions including one or more rows of adjacent pixels, and in an effective display area of the display panel, the slew rate coefficient of the longitudinal partitions gradually increases or gradually increases in gradient along a direction in which the source line transports a source driving signal; The method further includes: obtain a second target slew rate coefficient according to a slew rate coefficient corresponding to a horizontal partition in which a column of pixels in which the first target pixel and the second target pixel are located is located in the second correspondence table; The second target slew rate coefficient is obtained according to a slew rate coefficient at a cross of the horizontal partition where the column pixel in which the first target pixel and the second target pixel are located is located in the second lookup table and the vertical partition where the row in which the first target pixel and the second target pixel are located is located in the second lookup table.

6. The display panel driving method according to any one of claims 1 to 5, wherein The gate lines carry gate driving signals in a direction from two ends of the display panel to the middle.

7. A display panel driving apparatus, characterized by, The receiving unit is configured to receive time sequence synchronization pixel data of a first target pixel and a second target pixel from a time sequence control chip. The first target pixel and the second target pixel are located in a same column, and the second target pixel is a pixel in a next row of the first target pixel. The first determining unit is configured to determine a first target gray scale voltage of the first target pixel and a second target gray scale voltage of the second target pixel according to the time sequence synchronization pixel data of the first target pixel and the second target pixel. The second determining unit is configured to determine a target slew rate of the first target gray scale voltage jumping to the second target gray scale voltage according to position information of the first target pixel and the second target pixel in the display panel. The position information of the first target pixel and the second target pixel in the display panel includes position information of a column pixel in which the first target pixel and the second target pixel are located and position information of a row in which the first target pixel is located and a row in which the second target pixel is located in the display panel; wherein, within an effective display area of the display panel, a limit on the target slew rate gradually increases in a direction of carrying gate driving signals by gate lines, so that the target slew rate gradually decreases or decreases in gradient; within the effective display area of the display panel, the limit on the target slew rate gradually releases in a direction of carrying source driving signals by source lines, so that the target slew rate gradually increases or increases in gradient. The driving unit is configured to drive the first target pixel and the second target pixel according to the target slew rate, the first target gray scale voltage and the second target gray scale voltage.

8. A display panel, characterized by, The display panel is provided with a time sequence control chip and a plurality of data driving chips, and any one of the data driving chips is configured to execute the method of any one of claims 1-6.

9. An electronic device, comprising: The display panel includes the display panel of claim 8. The display panel includes the display panel of claim 8.

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