Low-voltage topology identification method, system and equipment based on characteristic current real-time sampling analysis and medium

Abstract

The invention discloses a low-voltage topology identification method, system and device based on characteristic current real-time sampling analysis and a medium, and relates to the technical field of data processing, the identification method comprises the following steps: collecting sampled current signals in real time through a master control intelligent terminal, and carrying out grouping detection; dynamically selecting three detection points on a current signal propagation path, calculating a distribution characteristic value based on a spatial position coordinate, and generating a topological matching correction coefficient K; according to the correction coefficient K, dynamically adjusting a fault-tolerant threshold value matched with the sequence, and if an adjusted matching result meets a condition, generating an identification record representing that a connection relationship exists between the current sending node and the sampling node; and recursively sorting the hierarchical relationship of all the generated identification records according to the number of identification times of the nodes from low to high until identification and redisk of all the nodes are completed, and generating and storing a final topological structure. According to the invention, the operation and maintenance efficiency and the intelligent level of the power grid are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a low-voltage topology identification method, system, device and medium based on real-time sampling analysis of characteristic current. BACKGROUND

[0002] At present, with the continuous advancement of smart grid construction, the accurate identification of the topology structure of low-voltage transformer area, as the key terminal link of the power system facing users, is of great significance to the efficient and stable operation of the power system. The low-voltage transformer area undertakes the important task of power supply for various users such as residential, commercial and small industrial users. Clear and accurate topology structure can provide real-time and accurate data support for power dispatching, load forecasting and other aspects, help to realize more flexible and efficient power dispatching, and thus improve the reliability and economy of power grid operation.

[0003] Some existing low-voltage transformer area topology identification technologies have made some progress, but still have their own limitations. Some technologies have a large decline in recognition accuracy when facing complex electromagnetic environments or lines with more interference. Some methods have high computational complexity and require high performance of hardware devices, resulting in high cost and difficulty in large-scale application. Some technologies using complex clustering algorithms can improve the generalization ability to a certain extent, but when the collected data is missing, complex data preprocessing steps need to be added, which not only reduces the solving efficiency, but also greatly depends on the quality of the preprocessing effect.

[0004] Therefore, it is necessary to design a low-voltage topology identification method, system, device and medium based on real-time sampling analysis of characteristic current to solve the above problems. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a low-voltage topology identification method and system based on real-time sampling analysis of characteristic current, which improves the efficiency and intelligent level of power grid operation and maintenance.

[0006] To solve the above technical problems, the technical scheme of the present application is as follows:

[0007] A low-voltage topology identification method based on real-time sampling analysis of characteristic current,

[0008] characterized in that it comprises the following steps:

[0009] Step S1, generating a characteristic current signal in an intelligent terminal deployed at a key node of a low-voltage line in a transformer area;

[0010] Step S2, inject the characteristic current signal into the low-voltage line, and send a topology characteristic current sending instruction to all slave intelligent terminal nodes in the network to make each slave node execute the characteristic current signal sending process according to the received instruction to obtain the current signal in the sampled line;

[0011] Step S3, the master intelligent terminal collects the sampled current signal in real time and performs grouping detection; if 6 groups of characteristic currents are continuously detected, the identification process is started; and the code bit decision is made for the subsequent 10 groups of characteristic sequences, if more than 7 groups of characteristic currents exist, the code bit is marked as 1, otherwise, it is marked as 0; dynamically select 3 detection points on the current signal propagation path, calculate the distribution characteristic value based on the spatial position coordinates, and generate a topology matching correction coefficient K;

[0012] Step S4, dynamically adjust the fault tolerance threshold of the characteristic sequence matching according to the correction coefficient K, if the adjusted matching result meets the condition, generate an identification record representing the connection relationship between the current sending node and the sampling node;

[0013] Step S5, all generated identification records are recursively combed according to the node identification times from low to high to generate the final topology structure and store it.

[0014] As a preferred embodiment of the present application,

[0015] The step S1 comprises the following steps:

[0016] Step S11, generate a characteristic parameter group containing a characteristic frequency value f0, an N-bit characteristic amplitude sequence and a phase offset θ by the master intelligent terminal according to the preset topology coding rule;

[0017] Step S12, dynamically adjust the load impedance value based on the characteristic frequency value f0, so that the fundamental frequency of the output current is stable at f0; time-sharing switch the on-off state of the constant resistance load to generate a current waveform with stepped amplitude change, wherein each amplitude Aᵢ lasts for a fixed time length Δt; superimpose the phase offset θ to perform time domain translation on the current waveform to form a time-frequency composite characteristic signal different from the power frequency background noise;

[0018] Step S13, the generated time-frequency composite characteristic signal is used as the characteristic current signal.

[0019] As a preferred embodiment of the present application,

[0020] The step S2 comprises the following steps,

[0021] Step S21: inject the time-frequency composite characteristic signal into the low-voltage line to generate a topology instruction containing the target node address, the signal sending time window and the characteristic parameter group copy;

[0022] Step S22, topological instruction is sent to all slave nodes in address order through power line carrier communication;

[0023] Step S23, after the slave node receives the topological instruction, the local constant resistance load module is driven to generate a slave characteristic current signal homologous to the master node signal according to the feature parameter group copy in the topological instruction, and the slave characteristic current signal is injected into the low-voltage line in the allocated sending time window;

[0024] Step S24, the master intelligent terminal collects the superimposed signal in the line, and the superimposed signal is composed of the time-frequency composite characteristic signal injected by the master node and the slave characteristic current signals injected by all slave nodes in turn in the time domain, as a sample current signal to be processed.

[0025] As a preferred embodiment of the present application,

[0026] The step S3 comprises the following steps:

[0027] Step S31, the sampled current signal is collected by the master intelligent terminal in real time, the grouping detection operation is performed, and the detection result of whether the feature current exists in each group is outputted;

[0028] Step S32, according to the outputted grouping detection result, when the feature current exists in the continuous 6 groups of detection results, the topological identification process is triggered;

[0029] Step S33, in the triggered identification process, the subsequent continuous 10 groups of feature current sequences are extracted, the state marking operation is performed on each to-be-judged code bit, the number of groups in which the feature current appears in the 10 groups of sequences is counted, when the number of groups is more than 7 groups, the current code bit is marked as the first level state, otherwise it is marked as the second level state, and a feature marking sequence composed of the first level state and the second level state is generated;

[0030] Step S34, through the generated feature marking sequence, 3 detection points on the current signal propagation path are dynamically selected, the distribution characteristic value is calculated combining the spatial position coordinates of each detection point, and the topological matching correction coefficient K is generated according to the distribution characteristic value.

[0031] As a preferred embodiment of the present application,

[0032] The step S4 comprises the following steps:

[0033] Step S41, according to the correction coefficient K and the preset dynamic adjustment rule, the initial fault tolerance threshold of sequence matching is adjusted to obtain an adjusted fault tolerance threshold;

[0034] Step S42, the signal sequence sent by the sending node and the signal sequence collected by the sampling node are matched in sequence according to the adjusted fault tolerance threshold, and the timestamps, signal strengths and waveform feature key information in the signal sequences are compared and analyzed in the matching process;

[0035] Step S43, whether the adjusted matching result meets the pre-set condition is judged,

[0036] Step S44, if the matching result meets the pre-set condition, an identification record containing the sending node identifier, the sampling node identifier, the matching time and the matching similarity is generated.

[0037] As a preferred embodiment of the present application,

[0038] The step S5 comprises the following steps,

[0039] Step S51, the number of times of identification of each node in all generated identification records is counted, and the sending node and sampling node information are extracted; all nodes are sorted in order from low to high according to the number of times of identification of the nodes, and a node sorting list is obtained;

[0040] Step S52, the node with the lowest number of times of identification is selected as a starting node from the node sorting list, other nodes directly connected to the starting node are recursively found based on the connection relationship of the nodes in the identification records, and the hierarchical relationship between the nodes is determined, and in the recursive process, the nodes that have been processed are marked to avoid repeated calculation;

[0041] Step S53, the process of recursive finding and hierarchical relationship determining is repeatedly repeated, the adjacent nodes of the current processing node are taken as new starting nodes, the hierarchical relationship is continuously combed, and the hierarchical relationship network of all nodes is formed until the hierarchical relationship of all nodes is combed to form a complete node hierarchical relationship network;

[0042] Step S54, according to the node hierarchical relationship network, a final low-voltage topology structure of the transformer area is generated, and the connection relationship and hierarchical distribution between the nodes are clearly presented in the topology structure;

[0043] Step S55, the generated final topology structure is stored in a designated storage medium, so that subsequent query, analysis and update operations on the topology structure are performed.

[0044] As a preferred embodiment of the present application,

[0045] The pre-set condition in the step S43 includes that the matching similarity reaches a set threshold and the error of the key information is within an allowed range.

[0046] A low-voltage topology identification system based on real-time sampling analysis of feature current,

[0047] Characterized in that comprising:

[0048] A processing module is arranged in the intelligent terminal of the key node of the low-voltage line of the transformer area, and generates a characteristic current signal;

[0049] An execution module injects the characteristic current signal into the low-voltage line, and sends a topology characteristic current sending instruction to all slave intelligent terminal nodes in the transformer area in turn, so that each slave node executes the characteristic current signal sending process according to the received instruction to obtain the current signal in the sampled line;

[0050] A detection module collects the sampled current signal in real time through the master intelligent terminal, and performs grouping detection; if 6 groups of characteristic currents are continuously detected, the identification process is started; code bit judgment is performed on the subsequent 10 groups of characteristic sequences, if more than 7 groups of characteristic currents exist, the code bit is marked as 1, otherwise it is marked as 0; 3 detection points on the current signal propagation path are dynamically selected, and the distribution characteristic value is calculated based on the spatial position coordinates to generate a topology matching correction coefficient K;

[0051] An adjustment module dynamically adjusts the fault tolerance threshold of sequence matching according to the correction coefficient K, and generates an identification record representing the existence of a connection relationship between the current sending node and the sampling node if the adjusted matching result meets the condition;

[0052] A storage module recursively analyzes the hierarchical relationship of all generated identification records from low to high according to the number of times the nodes are identified, until all node identification reviews are completed, and generates and stores the final topology structure.

[0053] A computer device comprises:

[0054] a memory and a processor,

[0055] the memory and the processor are communicatively connected,

[0056] the memory stores computer instructions,

[0057] the processor executes the computer instructions, thereby executing a low-voltage topology identification method based on real-time sampling analysis of characteristic currents.

[0058] A computer readable storage medium,

[0059] the computer readable storage medium stores computer instructions,

[0060] the computer instructions are used to make the computer execute a low-voltage topology identification method based on real-time sampling analysis of characteristic currents.

[0061] Compared with the prior art, the present application has the following beneficial effects:

[0062] 1、The method of the present application generates all the identification records, and recursively combs the hierarchical relationship from low to high according to the number of times the node is identified, until all the node identification review is completed. This hierarchical combing method follows the internal logic of the low-voltage distribution area topology structure, starting from the low-frequency identification node, gradually building a complete and accurate topology structure, avoiding the node omission or hierarchical error problems that may occur in the traditional combing method, so that the final generated and stored topology structure is more in line with the actual situation.

[0063] 2、The method effectively fills the gap in low-voltage side Internet of Things sensing and control, and the accurate topology identification result provides real-time data basis for intelligent power grid core functions such as power dispatching, load forecasting, and fault location. For example, in fault location, based on the topology structure, the fault area can be quickly locked, and the power outage time is shortened; in load forecasting, combined with the topology structure and node power consumption, the power demand can be more accurately predicted. BRIEF DESCRIPTION OF DRAWINGS

[0064] Figure 1 A low-voltage topology identification method flowchart based on real-time sampling analysis of characteristic current is proposed for the present application;

[0065] Figure 2 A structure block diagram of a low-voltage topology identification system based on real-time sampling analysis of characteristic current is proposed for the present application.

[0066] BRIEF DESCRIPTION OF DRAWINGS:

[0067] 101、processing module,

[0068] 102、execution module,

[0069] 103、detection module,

[0070] 104、adjustment module,

[0071] 105、storage module. DETAILED DESCRIPTION

[0072] The specific embodiments of the present application will be described below in conjunction with the accompanying drawings and examples:

[0073] It should be noted that the structures, colors, proportions, sizes, etc. shown in the drawings attached to this specification are only used to cooperate with the content disclosed in the specification, so that people familiar with this technology can understand and read, and are not used to limit the implementation conditions of the present application. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effect and purpose that can be achieved by the present application, should still fall within the scope of the technology disclosed by the present application.

[0074] For example, Figure 1As shown, the low-voltage topology identification method based on real-time sampling analysis of characteristic current includes the following steps:

[0075] Step S1, generating a characteristic current signal in the intelligent terminal deployed at the key node of the low-voltage line in the transformer area;

[0076] Step S2, injecting the characteristic current signal into the low-voltage line, and sending a topology characteristic current sending instruction to all slave intelligent terminal nodes in the transformer area, so that each slave node executes the characteristic current signal sending process according to the received instruction to obtain the current signal in the sampling line;

[0077] Step S3, collecting the sampled current signal in real time by the master intelligent terminal, and performing grouping detection; if 6 groups of characteristic currents are continuously detected, the identification process is started; and the code bit decision is made for the subsequent 10 groups of characteristic sequences, if more than 7 groups of characteristic currents exist, the code bit is marked as 1, otherwise as 0; dynamically selecting 3 detection points on the current signal propagation path, calculating the distribution characteristic value based on the spatial position coordinates, and generating a topology matching correction coefficient K;

[0078] Step S4, dynamically adjusting the fault tolerance threshold of the characteristic sequence matching according to the correction coefficient K, if the adjusted matching result meets the condition, generating an identification record representing the connection relationship between the current sending node and the sampling node;

[0079] Step S5, recursively combing the hierarchical relationship of all generated identification records according to the number of times the nodes are identified from low to high, until all node identification reviews are completed, generating the final topology structure and storing it.

[0080] In this embodiment, all generated identification records are recursively combed according to the number of times the nodes are identified from low to high, until all node identification reviews are completed, and this hierarchical combing method follows the internal logic of the low-voltage transformer area topology structure, starting from the low-frequency identification node, gradually constructing a complete and accurate topology structure, avoiding the node omission or hierarchical error problems that may occur in traditional combing methods, so that the final generated and stored topology structure is more consistent with the actual situation.

[0081] This method effectively fills the gap in low-voltage side Internet of Things sensing and control, and the accurate topology identification result provides real-time data basis for the core functions of intelligent power grid such as power dispatching, load prediction, fault location, etc. For example, in fault location, based on the topology structure, the area where the fault occurs can be quickly locked, and the power-off time is shortened; in load prediction, combined with the topology structure and node power consumption, the power demand can be more accurately predicted.

[0082] In another embodiment, step S1 includes the following steps:

[0083] Step S11, generating a characteristic parameter group containing a characteristic frequency value f0, an N-bit characteristic amplitude sequence, and a phase offset θ according to a preset topology coding rule by the master intelligent terminal;

[0084] Step S12, dynamically adjusting the load impedance value based on the characteristic frequency value f0 to stabilize the fundamental frequency of the output current at f0; switching the on-off state of the constant resistance load in time to generate a current waveform with stepped amplitude changes, wherein each amplitude Aᵢ lasts for a fixed time length Δt; superimposing the phase offset θ to perform time domain translation on the current waveform to form a time-frequency composite characteristic signal that is different from the power frequency background noise;

[0085] Step S13, taking the generated time-frequency composite characteristic signal as a characteristic current signal.

[0086] In the embodiment, the above steps S11, S12, and S13 can be implemented by the following steps, specifically as follows:

[0087] Step S11: The master intelligent terminal digitally maps the line characteristics according to a preset coding logic based on the physical topology structure of the low-voltage line in the transformer area (such as node connection relationship, line branching level). For example, according to the line belonging to the transformer area number, node position order, and branch quantity information, the coding rule corresponding to the characteristic parameter generation logic is determined.

[0088] According to the topology coding result and the line communication requirement, a target frequency value f0 (for example, 100 Hz or 200 Hz) that is different from the power frequency (such as 50 Hz or 60 Hz) is selected to ensure that the frequency has small attenuation and strong anti-interference when transmitted in the low-voltage line.

[0089] According to the complexity of the topology structure or the node identification requirement, the sequence length N (such as N=8 or 16) is determined, and each sequence bit is assigned a corresponding current amplitude Aᵢ (i=1, 2, …, N). The design of the amplitude sequence needs to meet the stepped change rule, for example, setting each amplitude according to the increasing, decreasing, or specific mode (such as binary coding) to form a unique waveform feature in subsequent time-sharing switching.

[0090] According to the topology coding rule, a unique phase offset θ (such as an angle in the range of 0°~360°) is set in combination with the phases of the signals that may be generated by other nodes in the line to perform time domain translation on the current waveform in the subsequent step, avoiding signal overlapping interference.

[0091] Step S12: After receiving the characteristic frequency f0, the constant resistance load module automatically adjusts the parameters of the internal resistance or reactance elements (for example, by switching different resistance combinations through electronic switches) based on the relationship between circuit impedance and frequency (such as by detecting the deviation of the current output frequency from f0), so that the fundamental frequency of the output current is stabilized at f0. This process is achieved through closed-loop feedback, which monitors the frequency in real time and adjusts the impedance to ensure frequency accuracy.

[0092] According to the sequence of N-bit characteristic amplitudes, the time axis is divided into N equal time periods, each with a duration of Δt (such as 10ms or 20ms). In each time period, by controlling the on-off state of the switching device (such as IGBT or relay), the constant resistance load outputs the corresponding amplitude Aᵢ, thereby forming a continuous step-shaped current waveform in the time dimension. For example, output A1 in the first Δt, output A2 in the second Δt, and so on, until the switching of N amplitudes is completed.

[0093] Based on the generation of the step waveform, the corresponding time delay t = θ / (2πf0 is calculated according to the phase shift θ, and the starting time of the entire current waveform is delayed by t through hardware triggering or software control, achieving time domain translation. For example, if θ = 90° and f0 = 100Hz, then the delay time t = 0.25 / 100 = 2.5ms, which makes the waveform shift 2.5ms on the time axis, forming a unique phase feature.

[0094] Step S13: The signal generated by the master intelligent terminal is transmitted to the constant resistance load module through shielded cable or optical fiber, reducing signal interference.

[0095] At key nodes of the low-voltage line in the transformer area, such as the transformer outlet end and branch intersection, the signal is injected into the line using current transformer coupling or isolated transformer direct connection.

[0096] The intelligent terminal on the line monitors the signal in real time, and if there is attenuation or distortion, the module output parameters or injection position are adjusted in time to ensure effective signal transmission.

[0097] In this embodiment, the time-frequency composite characteristic signal forms a significant difference with the power frequency background noise in the low-voltage line through the non-power frequency characteristic frequency f0, the stepped amplitude change and the phase offset, improves the recognition degree of the signal in the complex electromagnetic environment, and reduces the misjudgment. The characteristic parameter group (frequency, amplitude sequence, phase) is bound with the line topology coding rule, each signal carries unique topology characteristic information, which is convenient for subsequent signal detection to realize accurate positioning of the line node and identification of the topology structure. The constant resistance load module can dynamically adjust the impedance according to f0 to ensure that the output current frequency is stable under different line impedance conditions; the time-sharing switching and phase offset design makes the signal have flexible coding ability to adapt to the differentiated needs of different line areas. After the characteristic signal is injected, the transmission path and attenuation characteristics of the signal can be detected to quickly locate the line fault point, shorten the fault troubleshooting time, and improve the operation and maintenance efficiency of the low-voltage distribution network.

[0098] In another embodiment, step S2 comprises the following steps,

[0099] Step S21: injecting a time-frequency composite characteristic signal into a low-voltage line to generate a topology instruction containing a target node address, a signal sending time window and a characteristic parameter group copy;

[0100] Step S22, sending the topology instruction to all slave nodes in address order through power line carrier communication;

[0101] Step S23, after the slave node receives the topology instruction, driving the local constant resistance load module to generate a slave characteristic current signal same as the master node signal according to the characteristic parameter group copy in the topology instruction, and injecting the slave characteristic current signal into the low-voltage line in the allocated sending time window;

[0102] Step S24, the master intelligent terminal collects superimposed signals in the line, the superimposed signals are composed of the time-frequency composite characteristic signal injected by the master node and the slave characteristic current signal injected by all slave nodes in turn in the time domain, as the sample current signal to be processed.

[0103] In this embodiment, the above-mentioned steps S21, S22, S23 and S24 can be realized by the following steps, as follows:

[0104] Step S21: the master intelligent terminal allocates a unique address code (such as a 16-bit binary address) for each networked slave node according to the topology structure of the line area low-voltage line and the physical position of the slave node. The address code needs to be associated with the hierarchical and branch relationship information of the node in the topology to ensure accurate instruction delivery.

[0105] According to the number of dependent nodes and signal transmission delay requirements, the total time is divided into a plurality of non-overlapping sub-periods as the transmission time window. For example, if there are N dependent nodes, the total time T is evenly divided into N parts, and each node is allocated a dedicated window of T / N, ensuring that the signal injection does not interfere with each other.

[0106] The master intelligent terminal copies the generated feature parameter set (including feature frequency f0, N-bit feature amplitude sequence and phase offset θ) as the reference basis for generating signals by the dependent nodes, ensuring that the dependent signals have the same characteristics as the master signal.

[0107] The target node address, allocated time window information and feature parameter set copy are integrated into a topology instruction data packet, and a check code (such as CRC check) is added to ensure the accuracy of the instruction transmission.

[0108] Step S22: The master intelligent terminal polls in the preset address order (such as the hierarchical order from the root node to the branch node) in turn, and sends the topology instruction to the dependent nodes with the corresponding address through power line carrier communication (PLC) technology.

[0109] According to the line impedance and signal attenuation characteristics, the carrier frequency, modulation method (such as FSK, OFDM) and transmission power of PLC communication are dynamically adjusted to ensure reliable transmission of the instruction. For example, if the line distance is long, the transmission power is increased; if there is electromagnetic interference, the modulation method with stronger anti-interference capability is switched to.

[0110] Step S23: After the dependent node receives the topology instruction, it first verifies the check code to confirm that the instruction is complete and correct; then extracts the feature parameter set copy, time window information and target address, and compares them with the local address to ensure that the instruction is for itself.

[0111] Based on the feature parameter set copy, the dependent node executes the calculation process through the local constant resistance load module: first, dynamically adjusts the load impedance to stabilize the fundamental frequency according to the feature frequency f0, then generates a staircase waveform by time-sharing switching the load on-off according to the amplitude sequence, and finally completes the time domain translation by superimposing the phase offset θ, to generate the dependent feature current signal.

[0112] The dependent node injects the dependent feature current signal into the low-voltage line through current coupling (such as CT injection or direct connection through an isolation transformer) at the start time of the allocated time window, ensuring that the signal is transmitted within the specified time period.

[0113] Step S24: The master intelligent terminal continuously collects current data in the low-voltage line through a high-precision current transformer, and captures the superimposed waveform in the time domain of the time-frequency composite feature signal injected by the master node and the dependent feature current signal injected by the dependent nodes in turn.

[0114] The collected superimposed signals are aligned in time domain by using preset time stamps or synchronous clock signals, waveform misalignment caused by signal transmission delay or node clock error is eliminated, and complete and accurate sample current signals to be processed are formed.

[0115] In the embodiment, the topological connection relationship and line state of each node in the transformer area can be acquired simultaneously by the master-slave node cooperative injection of homologous characteristic current signals, global perception of the low-voltage line network is realized, and the limitation of single-point detection is avoided. The slave signals are homologous to the master signals and are injected in time, and the mutual interference between the signals is reduced. Even if the signal transmission of part of the nodes is abnormal, the topological analysis can still be completed through the superimposed signals of other nodes, and the system reliability is improved. The superimposed signals contain the characteristic information of each node, and the fault node or line branch can be quickly located by analyzing the amplitude, phase and attenuation of the signals, and the fault troubleshooting time is significantly shortened.

[0116] Based on the instruction issuing and time-sharing sending mechanism of the power line carrier, the low-voltage line is fully utilized as a communication medium, and additional communication lines do not need to be laid, thereby reducing the hardware cost. At the same time, signal conflicts are avoided, and the communication efficiency is improved.

[0117] In another embodiment, the step S3 comprises the following steps:

[0118] In step S31, the master intelligent terminal collects the sampled current signals in real time, performs grouping detection operation, and outputs the detection result of whether the characteristic current exists in each group;

[0119] In step S32, according to the output grouping detection result, when the characteristic current exists in the continuous 6 groups of detection results, the topological identification process is triggered;

[0120] In step S33, in the triggered identification process, the subsequent continuous 10 groups of characteristic current sequences are extracted, the state marking operation is performed on each to-be-judged code bit, the number of groups in which the characteristic current appears in the 10 groups of sequences is counted, when the number of groups is more than 7, the current code bit is marked as the first level state, otherwise, it is marked as the second level state, and a characteristic marking sequence composed of the first level state and the second level state is generated;

[0121] In step S34, the three detection points on the current signal propagation path are dynamically selected by using the generated characteristic marking sequence, the distribution characteristic value is calculated in combination with the spatial position coordinates of each detection point, and the topological matching correction coefficient K is generated according to the distribution characteristic value.

[0122] In the embodiment, the above-mentioned steps S31, S32, S33 and S34 can be realized by the following steps, and the details are as follows:

[0123] In step S31, the master intelligent terminal continuously samples the line current at a fixed sampling frequency (such as 10 kHz) to obtain time domain waveform data.

[0124] The original sampling signal is band-pass filtered to extract the frequency band around the target feature frequency f0 (e.g. ±5Hz) and filter out power frequency interference (50Hz / 60Hz) and other noise.

[0125] The filtered signal is segmented by time window (e.g. every 20ms as a group), each group containing N sampling points. Short-time Fourier transform (STFT) or wavelet transform is performed on each group of signals to extract time-frequency features.

[0126] Based on the preset feature threshold (e.g. amplitude threshold, phase consistency threshold), if the signal amplitude exceeds the threshold and the phase matches the expected feature parameter θ, it is determined that the group has characteristic current; otherwise, it is determined that there is no characteristic current; the detection result of each group is output.

[0127] Step S32: The master intelligent terminal maintains a sliding window and monitors the sequence of grouping detection results in real time.

[0128] When the window contains 6 consecutive detection results of "characteristic current exists" (marked as 1), the topology recognition process is triggered. If an interruption is detected (e.g. 0 appears), the count is reset and the number of consecutive 1s is accumulated again.

[0129] Step S33: After triggering the recognition process, the next 10 consecutive groups of detection results are extracted as the feature decision sequence. For each decision code bit (corresponding to a bit in the characteristic amplitude sequence), the number of times the code bit appears 1 in the 10-group sequence is counted. If the number of times exceeds 7 (i.e. 70% confidence), the code bit is marked as the first level state (usually high level 1); otherwise, it is marked as the second level state (usually low level 0).

[0130] The decision results of all code bits are combined to form a complete feature marker sequence (e.g. 1011001010), which is used for subsequent topology matching.

[0131] Step S34: Based on the current feature marker sequence, the signal transmission direction is determined by the feature amplitude decay law; combined with the preset line topology model, the detection points that may be located on the current propagation path are selected.

[0132] Three spatially independent detection points (e.g. located on different branch lines) are dynamically selected from the selected detection points to ensure that the key areas of signal propagation are covered. The spatial position coordinates (e.g. longitude, latitude, altitude) of the three detection points are obtained.

[0133] A triangle is constructed to calculate the side length (Euclidean distance), internal angle and area; the uniformity of the detection point distribution is analyzed (e.g. by judging the shape of the triangle). Combined with the characteristic current signal strength received by each detection point, a weighted distribution characteristic value is calculated to reflect the propagation characteristics of the signal in space.

[0134] The distribution characteristic value is mapped into a preset correction coefficient table to generate a topology matching correction coefficient K (usually a floating point number between 0.8 and 1.2). The K value is used in a subsequent topology matching algorithm to adjust the weight of feature similarity calculation and improve the accuracy of topology identification.

[0135] In this embodiment, six groups of continuous feature detection are used as trigger conditions to effectively filter random noise interference and avoid false triggering. A 70% confidence code bit decision mechanism is adopted to enhance the tolerance to signal fluctuations and interference and improve the accuracy of feature sequence extraction. The detection points are dynamically selected and the spatial distribution features are calculated, so that the system can adapt to changes in different line topology structures, especially for complex branch networks. The introduction of the correction coefficient K compensates for the nonlinear attenuation and multipath effect in the signal propagation process, improving the accuracy of topology matching. The grouping detection and sliding window mechanism support real-time signal analysis, shortening the response time of topology identification. The feature decision process is simplified to binary statistics, with low computational complexity, suitable for running on resource-limited intelligent terminals. Combining time-frequency domain feature detection and spatial distribution analysis, the system's resistance to environmental factors such as electromagnetic interference and harmonic pollution is enhanced from multiple dimensions. Even if some detection points have abnormal signals, topology identification can still be completed through information from other detection points, improving the system's robustness.

[0136] In another embodiment, step S4 comprises the following steps:

[0137] Step S41, adjusting the initial fault tolerance threshold of sequence matching according to the correction coefficient K and a preset dynamic adjustment rule to obtain an adjusted fault tolerance threshold;

[0138] Step S42, performing sequence matching on the signal sequence sent by the sending node and the signal sequence collected by the sampling node according to the adjusted fault tolerance threshold, and comparing and analyzing the time stamp, signal strength and waveform feature key information in the signal sequence during the matching process;

[0139] Step S43, judging whether the adjusted matching result meets a preset condition,

[0140] Step S44, if the matching result meets the preset condition, generating an identification record containing the sending node identifier, the sampling node identifier, the matching time and the matching similarity.

[0141] In this embodiment, the above steps S41, S42, S43 and S44 can be implemented by the following steps, as follows:

[0142] Step S41: preset an initial fault tolerance threshold value as T0=20 (representing the maximum allowed matching error, which can be set according to the signal type, such as the timestamp error unit in milliseconds). The correction coefficient K=0.8 (assuming generated by the current network load, the higher the load, the smaller the K value to tighten the threshold). The dynamic adjustment rule is: adjusted threshold value=initial threshold value x correction coefficient. The adjusted fault tolerance threshold value T=20x0.8=16. If the rule is "adjusted threshold value=initial threshold value-(initial threshold value x(1-K))", the result is consistent. The core is to dynamically scale the threshold value through K. The adjusted threshold value is used to relax or tighten the tolerance of error when matching the sequence.

[0143] The correction coefficient K is associated and integrated with the current sampled current signal data, and the basic information of the sending node and the sampling node, such as node position, device parameters.

[0144] Step S42: respectively from the signal sequence sent by the sending node and the signal sequence collected by the sampling node, extract the timestamp, signal strength, and waveform feature (such as step-shaped amplitude change, phase shift) key information.

[0145] Calculate whether the time deviation is within the time range allowed by the adjusted fault tolerance threshold value; compare the difference in signal amplitude to determine whether the error percentage is less than the adjusted fault tolerance threshold value; through the visually observable waveform similarity, phase shift angle difference, etc., combined with the fault tolerance threshold value, to determine whether it is matched. According to the matching situation of the key information, calculate the overall matching similarity. For example, the matching scores (0-100 points) of the timestamp, signal strength, and waveform features are weighted and summed according to the preset weight (such as 3:4:3) to obtain the final matching similarity percentage.

[0146] Step S43: compare the calculated matching similarity, key information error value, and pre-set conditions.

[0147] Step S44: when the matching result is valid, integrate the sending node identification, sampling node identification, matching time, matching similarity, and correction coefficient K information.

[0148] According to the preset data format, generate an identification record representing the connection relationship between the two nodes, and store it in the database of the main control intelligent terminal for subsequent line topology analysis and fault location.

[0149] In this embodiment, the fault tolerance threshold is dynamically adjusted by the correction coefficient K, so that the system can adapt to the complex environment of different transformer area low-voltage lines (such as signal attenuation caused by line aging, equipment interference, etc.), and avoid false positives or false negatives caused by fixed threshold. Based on the multi-dimensional comparison of key information and the dynamic fault tolerance mechanism, the accuracy of node connection relationship identification is improved, and the identification result of the topology structure is more in line with the actual line situation. The generated identification record contains rich node and matching information, which provides reliable data basis for power operation and maintenance personnel to analyze line topology and locate fault points, and improves the operation and maintenance efficiency. The dynamic adjustment rule is based on a large amount of actual data, which enhances the stability and reliability of the system under different working conditions, and reduces the influence of environmental changes on the topology identification result.

[0150] In another embodiment, step S5 comprises the following steps,

[0151] Step S51, count the number of times each node is identified in all generated identification records, and extract the sending node and sampling node information; sort all nodes in order from low to high according to the number of times the node is identified, and obtain a node sorting list;

[0152] Step S52, select the node with the lowest number of times from the node sorting list as the starting node, recursively find other nodes directly connected to it based on the connection relationship of the node in the identification record, and determine the hierarchical relationship between them. In the recursive process, mark the nodes that have been processed to avoid repeated calculation;

[0153] Step S53, repeatedly repeat the recursive finding and hierarchical relationship determining process, take the adjacent nodes of the current processing node as new starting nodes, continuously comb the hierarchical relationship, and until all nodes complete the hierarchical relationship combing, form a complete node hierarchical relationship network;

[0154] Step S54, according to the node hierarchical relationship network, generate the final transformer area low-voltage topology structure, which clearly presents the connection relationship and hierarchical distribution between nodes in the topology structure;

[0155] Step S55, store the generated final topology structure in a designated storage medium, so as to facilitate subsequent query, analysis and update operations on the topology structure.

[0156] In this embodiment, the above steps S51, S52, S53, S54 and S55 can be implemented by the following steps, as follows:

[0157] Step S51: The master intelligent terminal traverses all the identification records and extracts the sending node and sampling node identification information involved therein. Each time a node is extracted, the corresponding position in the node count table is increased by 1 count. For example, if there are 3 records in the identification records containing node A, the number of times node A is identified is recorded as 3.

[0158] All the nodes and their corresponding identification times are sorted in ascending order of the identification times. When sorting, a stable sorting algorithm (such as merge sorting or insertion sorting) can be used to ensure that nodes with the same identification time are arranged in dictionary order according to their identification, and finally a node sorting list is obtained.

[0159] Step S52: The node with the lowest identification time is taken out from the node sorting list as the starting node. For example, if the identification time of node X in the node sorting list is 1 and is the lowest in the list, then node X is taken as the starting node.

[0160] The records containing the starting node are searched in all the identification records to obtain other nodes directly connected to the starting node. For example, if the identification records show that the starting node X is connected to node Y and node Z, then node Y and node Z are taken as the directly connected nodes.

[0161] The starting node is marked as a processed state, and the hierarchical relationship between the starting node and the directly connected nodes is determined, such as marking the directly connected nodes as the next level of the starting node. For example, node X is the first level, and nodes Y and Z are marked as the second level.

[0162] Step S53: The directly connected nodes (nodes marked as the next level) of the processed starting node are taken as new starting nodes. For example, nodes Y and Z are taken as new starting nodes and are processed in turn.

[0163] For each new starting node, the operation is repeated, the directly connected nodes are searched in the identification records, the hierarchical relationship is determined, and the newly processed nodes are marked as processed. For example, node Y is connected to node M and node N, then nodes M and N are marked as the third level, and nodes M and N are marked as processed.

[0164] The above process is continuously repeated, and after all the directly connected nodes of the current starting node are processed, it is checked whether there are any unprocessed nodes. If all the nodes have been marked as processed, the recursion is stopped, and at this time a complete node hierarchical relationship network has been formed.

[0165] Step S54: Based on the node hierarchy network, map each node and its hierarchical relationships and connections to the topology. For example, in a graphical representation, place the node at level 1 at the top, connect it to the nodes at the next level, and so on, intuitively showing the connection relationships and hierarchical distribution between nodes.

[0166] The generated topology is optimized to avoid problems such as intersecting lines and overlapping nodes. At the same time, each node is labeled with its identification information to make the topology clearer and easier to understand.

[0167] Step S55: Convert the generated topology data into a suitable storage format, such as JSON, XML, or a specific database table structure. For example, convert node information and connection relationships into JSON format strings to facilitate subsequent data reading and parsing.

[0168] The transformed topology data is stored on a specified storage medium, such as a local hard drive, database server, or cloud storage. During storage, a timestamp is recorded for subsequent version management and update operations on the topology.

[0169] In this embodiment, the hierarchical relationships are sorted from low to high based on the number of times nodes are identified, prioritizing nodes with simple connections to reduce redundant calculations in the recursive process and improve the efficiency of topology generation. Recursively determining node connections and hierarchical relationships based on identification records accurately reflects the actual topology of low-voltage lines in the distribution area, avoiding errors caused by manual drawing or guesswork. The generated topology stores complete node and connection information, facilitating subsequent queries of node connection history and analysis of line changes, providing reliable data support for power operation and maintenance. After storing the topology, it can be queried, analyzed, and updated at any time. When nodes are added, deleted, or modified in the line, the topology can be quickly regenerated, maintaining data real-time performance and accuracy, and improving the convenience and intelligence of power system management.

[0170] In another embodiment, the pre-set conditions in step S43 include matching similarity reaching a set threshold and the error of key information being within an allowable range.

[0171] For example, the matching similarity must be ≥85%, and the error values ​​of each key piece of information must not exceed the adjusted tolerance threshold. If all conditions are met, the matching result is considered valid; if any condition is not met, the matching result is considered invalid.

[0172] like Figure 2 As shown, a low-voltage topology identification system based on real-time sampling and analysis of characteristic current includes:

[0173] The processing module 101 is arranged in the intelligent terminal of the key node of the low-voltage line of the transformer area, and generates a characteristic current signal.

[0174] The execution module 102 injects the characteristic current signal into the low-voltage line, and sends a topology characteristic current sending instruction to all slave intelligent terminal nodes in the transformer area in turn, so that each slave node executes the characteristic current signal sending process according to the received instruction to obtain the current signal in the sampled line.

[0175] The detection module 103 collects the sampled current signal in real time through the master intelligent terminal, and performs grouping detection; if 6 groups of characteristic currents are continuously detected, the identification process is started; the code bit is judged for the subsequent 10 groups of characteristic sequences, if more than 7 groups of characteristic currents exist, the code bit is marked as 1, otherwise, it is marked as 0; 3 detection points on the current signal propagation path are dynamically selected, the distribution characteristic value is calculated based on the spatial position coordinates, and the topology matching correction coefficient K is generated.

[0176] The adjustment module 104 dynamically adjusts the fault tolerance threshold of the sequence matching according to the correction coefficient K, and if the adjusted matching result meets the condition, an identification record representing that the current sending node and the sampling node exist a connection relationship is generated.

[0177] The storage module 105 recursively analyzes the hierarchical relationship of all generated identification records according to the number of times of being identified from low to high, until the identification of all nodes is completed, and finally generates and stores the topology structure.

[0178] The system corresponds to the above method. All implementation manners in the above method embodiment are applicable to this embodiment, and the same technical effects can be achieved.

[0179] A computer device has the above Figure 2 A low-voltage topology identification system based on real-time sampling analysis of characteristic currents. It contains a memory and a processor, which are connected to each other in communication, the memory stores computer instructions, and the processor executes the computer instructions, thereby realizing the above-mentioned low-voltage topology identification method based on real-time sampling analysis of characteristic currents.

[0180] A computer readable storage medium, the method of the above embodiment of the application can be realized in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and stored in a local storage medium through network download of computer code, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a special-purpose processor or programmable or special-purpose hardware.

[0181] The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, the processor, or the hardware, implements the method shown in the above embodiments.

[0182] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in a computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way in which the computer program instructions are executed by the computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0183] The preferred embodiments of the present application are described in detail above in combination with the drawings, but the present application is not limited to the above-mentioned embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the purpose of the present application.

[0184] Many other changes and modifications can be made without departing from the spirit and scope of the present application. It should be understood that the present application is not limited to a particular embodiment, and the scope of the present application is defined by the appended claims.

Claims

1. A low-voltage topology identification method based on real-time sampling analysis of characteristic current, characterized in that comprising the following steps: Step S1, generating a characteristic current signal in an intelligent terminal deployed at a key node of a low-voltage line in a transformer area; Step S2, injecting the characteristic current signal into the low-voltage line and sequentially sending a topology characteristic current sending instruction to all slave intelligent terminal nodes in the transformer area, so that each slave node executes a characteristic current signal sending process according to the received instruction to obtain a current signal in the sampled line; Step S3, collecting the sampled current signal in real time by the master intelligent terminal and performing grouping detection; if 6 groups of characteristic currents are continuously detected, the identification process is started; and code bit decision is made on the subsequent 10 groups of characteristic sequences; if more than 7 groups of characteristic currents exist, the code bit is marked as 1, otherwise as 0; dynamically selecting 3 detection points on the current signal propagation path, calculating the distribution characteristic value based on the spatial position coordinates, and generating a topology matching correction coefficient K; Step S4, dynamically adjusting the fault tolerance threshold of the characteristic sequence matching according to the correction coefficient K; if the adjusted matching result meets the condition, an identification record representing the existence of a connection relationship between the current sending node and the sampling node is generated; Step S5, recursively combing the hierarchical relationship of all generated identification records from low to high according to the number of nodes identified, until all node identification reviews are completed, generating the final topology structure and storing it. 2.The low-voltage topology identification method based on real-time sampling analysis of characteristic current according to claim 1, characterized in that the step S1 comprises the following steps: Step S11, generating a characteristic parameter group containing a characteristic frequency value f0, an N-bit characteristic amplitude sequence, and a phase offset θ by the master intelligent terminal according to a preset topology coding rule; Step S12, dynamically adjusting the load impedance value based on the characteristic frequency value f0 so that the fundamental frequency of the output current is stabilized at f0; time-sharing switching the on-off state of the constant resistance load to generate a current waveform with step-shaped amplitude variation, wherein each amplitude Aᵢ lasts for a fixed time length Δt; superimposing the phase offset θ to perform time domain translation on the current waveform to form a time-frequency composite characteristic signal different from the power frequency background noise; Step S13, taking the generated time-frequency composite characteristic signal as the characteristic current signal. 3.The low-voltage topology identification method based on real-time sampling analysis of characteristic current according to claim 2, characterized in that the step S2 comprises the following steps, Step S21: injecting the time-frequency composite characteristic signal into the low-voltage line to generate a topology instruction containing a target node address, a signal sending time window, and a copy of the characteristic parameter group; Step S22, sequentially sending the topology instruction to all slave nodes in address order through power line carrier communication; Step S23, after the slave node receives the topology instruction, driving the local constant resistance load module to generate a slave characteristic current signal homologous to the master node signal according to the copy of the characteristic parameter group in the topology instruction, and injecting the slave characteristic current signal into the low-voltage line within the allocated sending time window; Step S24, the master intelligent terminal collects the superimposed signal in the line, the superimposed signal is composed of the time-frequency composite characteristic signal injected by the master node and the slave characteristic current signal injected by all the slave nodes in turn in the time domain, as a sample current signal to be processed.

4. The low-voltage topology identification method based on real-time sampling analysis of characteristic current according to claim 3, characterized in that, the step S3 comprises the following steps: Step S31, by the master intelligent terminal real-time collection of the sampled current signal, performing grouping detection operation, outputting the detection result of whether each group exists characteristic current; Step S32, according to the output of the grouping detection result, when the continuous 6 groups of detection results all exist characteristic current, trigger the topology identification process; Step S33, in the triggered identification process, extract the subsequent 10 groups of characteristic current sequence, perform state marking operation on each to-be-judged code bit, count the number of groups in which the characteristic current appears, when the number of groups exceeds 7, mark the current code bit as the first level state, otherwise mark it as the second level state, generate a characteristic marking sequence composed of the first level state and the second level state; Step S34, by the generated characteristic marking sequence, dynamically select 3 detection points on the current signal propagation path, calculate the distribution characteristic value according to the spatial position coordinates of each detection point, and generate a topology matching correction coefficient K according to the distribution characteristic value.

5. The low-voltage topology identification method based on real-time sampling analysis of characteristic current according to claim 4, characterized in that, the step S4 comprises the following steps: Step S41, according to the correction coefficient K and the preset dynamic adjustment rule, adjust the initial fault tolerance threshold of sequence matching to obtain the adjusted fault tolerance threshold; Step S42, compare and analyze the time stamp, signal strength and waveform characteristic key information in the signal sequence according to the adjusted fault tolerance threshold, when the signal sequence sent by the sending node and the signal sequence collected by the sampling node are matched; Step S43, judge whether the adjusted matching result meets the pre-set condition, Step S44, if the matching result meets the pre-set condition, generate an identification record containing the sending node identifier, the sampling node identifier, the matching time and the matching similarity.

6. The low-voltage topology identification method based on real-time sampling analysis of characteristic current according to claim 5, characterized in that, the step S5 comprises the following steps, Step S51, count the number of times each node is identified in all generated identification records, extract the sending node and sampling node information; sort all nodes in order from low to high according to the number of times the nodes are identified, and obtain a node sorting list; Step S52, select the node with the lowest number of times identified from the node sorting list as the starting node, recursively find other nodes directly connected to it based on the connection relationship of the nodes in the identification record, and determine the hierarchical relationship between them, and mark the nodes that have been processed in the recursion process to avoid repeated calculation; Step S53, the process of recursive search and hierarchical relationship determination is repeatedly executed, taking the adjacent node of the current processing node as a new starting node, continuously combing the hierarchical relationship, until all nodes complete the hierarchical relationship combing, forming a complete node hierarchical relationship network; Step S54, according to the node hierarchical relationship network, generating the final low-voltage topology structure of the transformer area, the connection relationship and hierarchical distribution between nodes in the topology structure are clearly presented; Step S55, storing the generated final topology structure into a designated storage medium, so as to subsequently query, analyze and update the topology structure.

7. The low-voltage topology identification method based on feature current real-time sampling analysis according to claim 6, characterized in that, the conditions preset in the step S43 include that the matching similarity reaches a set threshold and the error of the key information is within an allowable range.

8. A low-voltage topology identification system based on feature current real-time sampling analysis, characterized in that, the low-voltage topology identification method based on feature current real-time sampling analysis according to claim 7 is adopted, including: a processing module, which is arranged in an intelligent terminal of a key node of a low-voltage line of a transformer area, and generates a feature current signal; an execution module, which injects the feature current signal into the low-voltage line, and sends a topology feature current sending instruction to all slave intelligent terminal nodes in the transformer area, so that each slave node executes a feature current signal sending process according to the received instruction to obtain a current signal in a sampling line; a detection module, which collects the sampled current signals in real time through the master intelligent terminal, and performs grouping detection; if 6 groups of feature currents are continuously detected, the identification process is started; code bits are judged for 10 groups of feature sequences in succession, if more than 7 groups of feature currents exist, the code bits are marked as 1, otherwise as 0; 3 detection points on the current signal propagation path are dynamically selected, and a distribution feature value is calculated based on the spatial position coordinates to generate a topology matching correction coefficient K; an adjustment module, which dynamically adjusts a fault tolerance threshold of sequence matching according to the correction coefficient K, and generates an identification record representing that a connection relationship exists between a current sending node and a sampling node if the adjusted matching result meets the conditions; a storage module, which recursively combs the hierarchical relationship of all identification records generated according to the number of times each node is identified from low to high, until all node identification reviews are completed, to generate and store a final topology structure.

9. A computer device, characterized in that, including: a memory and a processor, the memory and the processor are communicatively connected, the memory stores computer instructions, the processor executes the computer instructions to execute the low-voltage topology identification method based on feature current real-time sampling analysis according to claim 7.

10. A computer readable storage medium, characterized in that, the computer readable storage medium stores computer instructions, the computer instructions are used to make the computer execute the low-voltage topology identification method based on feature current real-time sampling analysis according to claim 7.

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