Adaptive tuning of memory device clock rate based on use of workloads

Abstract

Different operations have different clock rate bottleneck points. For example, during read operations, the processor may be a bottleneck, while for other operations, the processor may not be a bottleneck. These other operations may reduce its clock rate to conserve power since the bottleneck is elsewhere, so higher clock rates are not beneficial. Prediction of the bottleneck will be beneficial. Statistical information relating bottleneck points to workload and clock rate is tracked. When the workload changes, the statistical information may be consulted to determine where the bottleneck is located, and then the clock rate of the non-bottleneck operation is slowed down. A clock rate table is maintained in a device controller. The table maintains a clock rate for each component. Predicting workload and thus predicting clock rate reduces power consumption, improves performance, and has better quality of service (QoS) compatibility characteristics.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of the entire contents of U.S. Non-Provisional Application No. 18 / 483,488, entitled “Adaptive Tuning Of Memory Device Clock Rates Based On Usage Workloads”, filed October 9, 2023, with the United States Patent and Trademark Office, and the entire contents are incorporated herein by reference for all purposes. Background Technology Technical Field

[0003] The embodiments disclosed herein generally relate to improving the adaptive tuning of memory devices for different clock rates.

[0004] Description of the Related Art

[0005] Storage devices comprise different components that can operate at different clock rates. Clock rate is critical to overall system performance, both in terms of read / write latency and power consumption. Components are typically synthesized to support the highest possible clock rate, but clock rates can also be reduced without negative impact. The clock rate of each hardware (HW) component has a direct impact on the performance of that component, power consumption (and other metrics), and overall system performance. Components that may have different clock rates include: internal processors, data paths, host interfaces, memory device (e.g., NAND) switching modes, dynamic random access memory (DRAM), and error correction code (ECC) engines.

[0006] The clock rate is not adaptive, but rather typically based on a set of frequencies fixed to a rate defined in the table. A higher clock rate means higher power consumption, and ideally (but not always) higher performance. Using a set of frequencies prevents the clock rate from changing based on different system environments, which can lead to performance issues and latency.

[0007] Therefore, there is a need in the art to improve the adaptive tuning of memory devices at different clock rates. Summary of the Invention

[0008] Different operations have different clock rate bottleneck points. For example, during read operations, the processor can be the bottleneck, while for other operations, the processor will not be the bottleneck. These other operations can reduce their clock rate to save power because the bottleneck is elsewhere, so a higher clock rate is of no benefit. It would be beneficial to predict the bottleneck. Statistics are tracked that relate the bottleneck point to the workload and clock rate. When the workload changes, the statistics can be consulted to determine where the bottleneck is located, and then the clock rate of the non-bottleneck operations is slowed down. A clock rate table is maintained in the device controller. The table keeps the clock rate of each component. Predicting the workload and thus the clock rate reduction reduces power consumption, improves performance, and has better quality of service (QoS) compatibility characteristics.

[0009] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine a workload of the data storage device; determine a bottleneck element of the workload; select a clock rate of the bottleneck element to be a maximum clock rate of the bottleneck element; and select a clock rate of elements other than the bottleneck element to be lower than a maximum clock rate of the respective element.

[0010] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: classify a current workload of the data storage device; determine that the current workload is to switch to a new workload; and select a clock rate from a stored table based on the new workload.

[0011] In another embodiment, a data storage device includes: means for storing data; and a controller coupled to the means for storing data, wherein the controller is configured to: determine that a workload of the data storage device is one of: random read, sequential read, random write, sequential write, and mixed workload; obtain a clock rate from a table corresponding to the workload; and set the clock rate for a plurality of components of the data storage device, wherein the set clock rate is the obtained clock rate. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure can admit to other equally effective embodiments.

[0013] Figure 1is a schematic block diagram illustrating a storage system in which a data storage device can be used as a storage device of a host device, according to some embodiments.

[0014] Figure 2 is a schematic block diagram illustrating a storage system, according to one embodiment.

[0015] Figure 3 is a flow diagram illustrating clock management, according to one embodiment.

[0016] Figure 4 is a plot of the correlation between doorbell rate and clock frequency, according to one embodiment.

[0017] Figure 5 is a table indicating clock allocation per workload, according to one embodiment.

[0018] Figure 6 is a flow diagram illustrating clock frequency management, according to one embodiment.

[0019] Figure 7 is a flow diagram illustrating doorbell frequency tracking, according to one embodiment.

[0020] Figure 8 is a flow diagram illustrating clock frequency management, according to another embodiment.

[0021] For ease of understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment can be advantageously used in other embodiments without specific recitation. DETAILED DESCRIPTION

[0022] Hereinafter, reference is made to embodiments of the present disclosure. However, it is understood that the present disclosure is not limited to the particularly described embodiments. Rather, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the present disclosure. Furthermore, although embodiments of the present disclosure can achieve advantages over other possible solutions and / or over the prior art, whether or not a given embodiment achieves an advantage is not a limitation of the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims unless expressly stated otherwise. Likewise, the reference to "the disclosure" should not be construed as a generalization of any inventive concept or aspects disclosed herein and shall only be considered to refer to certain embodiments of the features disclosed herein, unless expressly stated otherwise.

[0023] Different operations have different clock rate bottlenecks. For example, the processor might be the bottleneck during a read operation, but not for other operations. These other operations can reduce their clock rates to save power because the bottleneck is elsewhere, so a higher clock rate offers no benefit. Predicting bottlenecks is beneficial. Track statistics that correlate bottleneck points with workload and clock rate. When the workload changes, consult the statistics to determine where the bottleneck is, and then slow down the clock rates of non-bottleneck operations. Maintain a clock rate table in the device controller. This table keeps track of the clock rate for each component. Predicting workload and therefore clock rate reduces power consumption, improves performance, and provides better Quality of Service (QoS) compatibility.

[0024] Figure 1 This is a schematic block diagram illustrating a storage system 100 in which a host device 104 communicates with a data storage device 106 according to certain embodiments. For example, the host device 104 may utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host DRAM 138 and optionally includes a host memory buffer (HMB) 150. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / disk-only (RAID) that collectively serve as a large-capacity storage device for the host device 104.

[0025] Host device 104 can store data to or retrieve data from one or more storage devices, such as data storage device 106. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a wide range of devices, including: computer servers, network attached storage (NAS) units, desktop computers, laptops, tablet computers, set-top boxes, telephone receivers (such as so-called "smart" phones, so-called "smart" tablets), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from data storage devices.

[0026] Data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, and a write buffer 116. In some examples, data storage device 106 may include additional components, which are not shown for clarity. Figure 1The additional components are shown in FIG. 1. The controller 108 can include volatile memory, such as DRAM 152, and a controller memory buffer (CMB) 154 dedicated for use by the host device 104. For example, the data storage device 106 can include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached and which includes electrically conductive traces that electrically interconnect the components of the data storage device 106. In some examples, the physical size and connector configuration of the data storage device 106 can conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5-inch data storage devices (e.g., HDDs or SSDs), 2.5-inch data storage devices, 1.8-inch data storage devices, peripheral component interconnect (PCI), extended PCI (PCI-X), fast PCI (PCIe) (e.g., PCIe xl, x4, x8, x16, PCIe mini card, mini PCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered or plugged into a connector) to a motherboard of the host device 104.

[0027] The interface 114 can include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 can operate according to any suitable protocol. For example, the interface 114 can operate according to one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial ATA (SATA) and parallel ATA (PATA)), fiber channel protocol (FCP), small computer system interface (SCSI), serial attached SCSI (SAS), PCI and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, cache coherent interface accelerator (CCIX), open channel SSD (OCSSD), etc. The interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to the controller 108, providing an electrical connection between the host device 104 and the controller 108 that enables data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 can also allow the data storage device 106 to receive power from the host device 104. For example, as Figure 1 illustrated, the power supply 111 can receive power from the host device 104 via the interface 114.

[0028] The NVM 110 can include a plurality of memory devices or memory units. The NVM 110 can be configured to store and / or retrieve data. For example, a memory unit of the NVM 110 can receive data and a message instructing the memory unit to store the data from the controller 108. Similarly, the memory unit can receive a message instructing the memory unit to retrieve data from the controller 108. In some examples, each of the memory units can be referred to as a die. In some examples, the NVM 110 can include a plurality of dies (i.e., a plurality of memory units). In some examples, each memory unit can be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0029] In some examples, each memory unit can include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0030] The NVM 110 can include a plurality of flash memory devices or memory units. The NVM flash memory devices can include NAND or NOR based flash memory devices and can store data based on charge contained in a floating gate of a transistor of each flash memory unit. In NVM flash memory devices, a flash memory device can be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks, which can be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device can include a plurality of NVM units. Rows of NVM units can be electrically connected using word lines to define a page of the plurality of pages. Respective units in each page of the plurality of pages can be electrically connected to a respective bit line. Further, the NVM flash memory devices can be 2D or 3D devices and can be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 can write data to and read data from the NVM flash memory devices at a page level and erase data from the NVM flash memory devices at a block level.

[0031] Power source 111 can provide power to one or more components of data storage device 106. When operating in a standard mode, power source 111 can use power provided by an external device, such as host device 104, to provide power to one or more components. For example, power source 111 can use power received from host device 104 via interface 114 to provide power to one or more components. In some examples, power source 111 can include one or more power storage components configured to provide power to one or more components when operating in an off mode, such as in the event that power is stopped being received from an external device. In this way, power source 111 can act as an on-board backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0032] Controller 108 can use volatile memory 112 to store information. Volatile memory 112 can include one or more volatile memory devices. In some examples, controller 108 can use volatile memory 112 as a cache. For example, controller 108 can store cached information in volatile memory 112 before the cached information is written to NVM 110. As shown, volatile memory 112 can consume power received from power source 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.). Figure 1

[0033] ​The controller 108 can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operational characteristic of the storage system 100 and store the at least one operational characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0034] As will be discussed below, the present disclosure relates to adaptive tuning of different clock rates of a data storage device based on a prediction-based classification of a current workload into one or more predefined workload categories. The present disclosure relates to a trade-off between power and performance. Logic predicts when performance is required and adjusts the clock rate accordingly. When performance is not required, the clock rate can be slowed down to save power consumption.

[0035] The present disclosure relates to an offline phase and an online phase. For the offline phase, several combinations of system clock values are defined according to workload classifications. The online phase involves classifying a current workload into one of the predefined categories and setting the system clock to the particular predefined value of the predicted category. A clock rate table (or clock frequency table) is maintained in the controller. The table keeps the clock frequency (or rate) of each component per workload. The controller predicts the next workload category and selects the clock frequency (or rate) accordingly. Throughout the disclosure, the terms clock rate and clock frequency are used interchangeably.

[0036] Preliminary offline analysis will include defining several workload types with different characteristics. For example, the following workload types can be defined as different categories: random read workload, sequential read workload, random write workload, sequential write workload, mixed workload, and low queue depth workload. A mixed workload is a workload in which a certain percentage (e.g., 70%) of commands are random, while another percentage (e.g., 30%) of commands are sequential. It should be understood that the 70 / 30 percentage is merely an example, as other percentages are also contemplated. Each of these workload types includes a primary characteristic from a system perspective, including system element bottlenecks, etc. For example, a sequential write workload can be gated by memory device (e.g., NAND) write speed, while a sequential write workload can be gated by an interface such as a flash interface module (FIM) and / or a host interface module (HIM). Balancing the clock of a non-gated system reduces peak power events.

[0037] For example, for a low queue depth workload, all clock rates are at maximum because the queue needs to be serviced regularly so that there is virtually no opportunity to save power, but for a random read workload, the processor can be the bottleneck. For a sequential read workload, the HIM and / or FIM can be the bottleneck. For a random write workload, the processor can again be the bottleneck, while for a sequential write, the memory device (e.g., NAND) can be the bottleneck. For a mixed workload, the DRAM can be the bottleneck. It is important to note that the bottleneck for each workload identified herein is merely an example and not a limitation of the present disclosure. For example, for a mixed workload, the DRAM is identified as the bottleneck, but it should be understood that other components can also be the bottleneck. Additionally, it is contemplated that depending on the workload and individual data storage device characteristics, multiple components can equally be the bottleneck.

[0038] Each workload category can be characterized by allowing a quick identification of a series of characteristics of the workload. In addition to common characteristics such as average command size and power of read / write / idle commands, simple characteristics can be added that can help in a quick classification of the workload type. Such example additional characteristics can include the following: command length diversity level, average or standard deviation (STD) of logical block addresses (LBAs) between adjacent commands, average number or STD of subsequent write / read commands, and queue depth.

[0039] Figure 2is an illustrative block diagram of a storage system 200 according to one embodiment. The storage system 200 includes a host device 202, a controller 204, and one or more memory devices 206. The controller includes a HIM 208, a FIM 218, a workload analysis module 210 that receives input from the HIM 208, and an adaptive frequency table 212 that receives input from the workload analysis module. The adaptive frequency table 212 outputs to the HIM 208, the FIM 218, an error correction code (ECC) module 216, and one or more processors 214A-214N. The FIM is coupled to the memory devices 206, and the HIM 208 is coupled to the host device 202. The workload analysis module 210 receives input from the HIM 208 with the features mentioned above. The adaptive frequency table 212 then receives an indication of a change in workload class and provides a frequency (or rate) from a predefined set of tables to all system components.

[0040] The online phase is a dynamic inference phase that includes performing a number of steps. One step is to track the values of the predefined feature parts by sampling the features at a predetermined interval (e.g., once every 1 second). Another step is to operate a simple inference prediction mechanism based on the offline defined model, which aims to classify the current workload into one of several predefined workload types. Another step is to identify a change in the current workload type to modify the different system clocks accordingly. The adaptation of the system clocks can be manipulated by the operating firmware (FW) or adjusted by a minimum distance metric within the feature parts such that the reconfiguration of the clocks is only initiated when there is a significant change in the workload type. Another step is to monitor the impact of the clock change and feedback the effectiveness of the proposed adaptive mechanism such that it is skipped when it has minimal / negative impact on the system performance / power management.

[0041] Figure 3 is a flowchart 300 illustrating clock management according to one embodiment. The method involves the workload analysis module classifying the current workload at 302 after a predetermined time has passed or some other trigger has occurred. Thereafter, at 304, it is determined whether the host has switched or is predicted to switch the workload type. If there is no switch or no prediction of a switch, then no operation is performed at 308, but if a switch has occurred or is predicted to occur, then a clock frequency is selected from a stored table according to the workload type at 306.

[0042] In one example, the clock rate can be selected based on the doorbell rate. In this example, the prediction of the upcoming workload is based on the doorbell rate. The doorbell is a message sent by the host to inform the data storage device that a new command is queued in one of the submission queues (SQs). The controller measures the rate of these messages while taking into account the number of new available commands in each doorbell and the average command size per SQ. Based on this information, the controller classifies the current workload and selects the clock frequency along with the predicted size of the pending transfer.

[0043] Figure 4 is a schematic diagram 400 of the correlation between the doorbell rate and the clock frequency according to one embodiment. A plurality of SQs 402A-402N have doorbells and a doorbell rate measurement module 404 measures the rate of the doorbells of the respective SQs and collectively measures the rate of these doorbells. The doorbell rate measurement module 404 feeds the results into a clock control manager 406. The clock control manager 406 also receives input of SQ statistics 408 and outputs the clock frequency to be utilized. The SQ statistics can include the command type of each SQ and the average size of the commands. For example, SQ1 402A can have an average command size of 4KB for read commands but 16KB for write commands. SQN can have an average command size of 16KB for read commands but 32KB for copy commands. Using a simple prediction mechanism (i.e., using only the average command size if unknown), the controller adaptively and in advance manages the clock frequency as the clock frequency is a function of the doorbell messages which are early enough before the traffic is available. Both the rate of the doorbell and the average size of the doorbell commands predict what the next workload will be.

[0044] Figure 5 is a table indicating the clock allocation per workload according to one embodiment. In the embodiment of Figure 5 In the embodiment of

[0045] For example, for a maximum frequency workload, there is no limiting bottleneck. In a maximum frequency workload, the processor operates at a clock rate of 1200 MHz, the datapath operates at a clock rate of 800 MHz, the HIM operates at a clock rate of 1 GHz (i.e., 15 GB / second), the memory device (e.g., NAND) switching mode operates at a clock rate of 3200, and the DRAM operates at a clock rate of 4266 MT / second. Since there is no bottlenecking component, the clock rates do not decrease, and each component operates at the maximum clock rate.

[0046] For a random read workload, the processor is the limiting bottleneck. Thus, the processor limits system performance even when it is operating at its maximum clock rate. Accordingly, operating the other components at their respective maximum clock rates would utilize unnecessary power without a corresponding increase in performance and / or QoS. In a random read workload, the processor operates at its maximum clock rate of 1200 MHz, while the datapath, HIM, memory device switching mode, and DRAM clock rates are all decreased below their respective maximum clock rates. Specifically, the datapath operates at a clock rate of 400 MHz, the HIM operates at a clock rate of 500 MHz (i.e., 7.3 GB / second), the memory device (e.g., NAND) switching mode operates at a clock rate of 2800, and the DRAM operates at a clock rate of 3200 MT / second.

[0047] For a sequential read workload, the HIM is the limiting bottleneck. Thus, the HIM limits system performance even when it is operating at its maximum clock rate. Accordingly, operating the other components at their respective maximum clock rates would utilize unnecessary power without a corresponding increase in performance and / or QoS. In a sequential read workload, the HIM operates at its maximum clock rate of 1 GHz (15 GB / second), while the datapath, processor, memory device switching mode, and DRAM clock rates are all decreased below their respective maximum clock rates. Specifically, the datapath operates at a clock rate of less than 800 MHz, the processor operates at a clock rate of 600 MHz, the memory device (e.g., NAND) switching mode operates at a clock rate of 2800, and the DRAM operates at a clock rate of 3200 MT / second.

[0048] For a random write workload, the processor is the limiting bottleneck. Thus, the processor limits system performance even when it is operating at its maximum clock rate. Accordingly, operating other components at their respective maximum clock rates would utilize unnecessary power without a corresponding increase in performance and / or QoS. In a random write workload, the processor operates at its maximum clock rate of 1200 MHz, while the data path, HIM, memory device switching mode, and DRAM clock rates are all reduced below their respective maximum clock rates. Specifically, the data path operates at a clock rate of 400 MHz, the HIM operates at a clock rate of 250 MHz (i.e., 3.2 GB / sec), the memory device (e.g., NAND) switching mode operates at a clock rate of 2800, and the DRAM operates at a clock rate of 3200 MT / sec.

[0049] For a sequential write workload, the memory device is the limiting bottleneck. Thus, the memory device limits system performance even when it is operating at its maximum clock rate. Accordingly, operating other components at their respective maximum clock rates would utilize unnecessary power without a corresponding increase in performance and / or QoS. In a sequential write workload, the memory device operates at its maximum clock rate of 3200, while the data path, HIM, processor, and DRAM clock rates are all reduced below their respective maximum clock rates. Specifically, the data path operates at a clock rate of 600 MHz, the HIM operates at a clock rate of 500 MHz (i.e., 7.3 GB / sec), the processor operates at a clock rate of 600 MHz, and the DRAM operates at a clock rate of 3200 MT / sec.

[0050] For a mixed workload, the DRAM is the limiting bottleneck. Thus, the DRAM limits system performance even when it is operating at its maximum clock rate. Accordingly, operating other components at their respective maximum clock rates would utilize unnecessary power without a corresponding increase in performance and / or QoS. In a mixed workload, the DRAM operates at its maximum clock rate of 4266 MT / sec, while the data path, HIM, memory device switching mode, and processor clock rates are all reduced below their respective maximum clock rates. Specifically, the data path operates at a clock rate of 600 MHz, the HIM operates at a clock rate of 500 MHz (i.e., 7.3 GB / sec), the memory device (e.g., NAND) switching mode operates at a clock rate of 3000, and the processor operates at a clock rate of 800 MHz.

[0051] In each case of the table, the bottleneck operates at a maximum clock rate, while the other components operate at a rate less than their respective clock rates. The amount below the respective maximum clock rate can be selected as a value that is below the maximum clock rate but above a clock rate that would result in another component becoming the bottleneck.

[0052] Figure 6 is a flowchart 600 illustrating clock frequency management according to one embodiment. Figure 6 The method of involves performing offline analysis to determine limiting elements (i.e., bottlenecks) based on workloads. Accordingly, the controller creates baseline data at 602. The system then operates using the baseline data at 604 and tracks values of predefined features (i.e., elements of the system having clock rates) at 606. The controller operates a simple extrapolation prediction mechanism at 608 and modifies clock rates based on identified changes in workload type at 610. At 612, the controller monitors any impact of the clock rate changes.

[0053] Figure 7 is a flowchart 700 illustrating doorbell frequency tracking according to one embodiment. Figure 7 The method of involves separately and collectively tracking doorbell rates for each SQ at 702. At 704, SQ statistics for each SQ are also tracked. Blocks 702 and 704 can be performed in any order. The controller predicts the next workload based on the rates of the doorbells at 706 and adjusts clock rates based on the predicted workload and SQ statistics at 708.

[0054] Figure 8 is a flowchart 800 illustrating clock frequency management according to another embodiment. Figure 8 The method of involves operating the data storage device according to a current clock rate setting at 802. At 804, it is determined whether the workload has changed. If the workload has not changed, the method returns to 802. If the workload has changed, at 806, the controller looks up a table for a clock rate value corresponding to the new workload. Then, at 808, the controller changes the clock rate to the new clock rate from the table and operates the data storage device at the new clock rate. Then, at 810, the controller determines whether the new clock rate is sufficient. If the new clock rate is sufficient, the method returns to 802, but if the new clock rate is not sufficient, the controller reevaluates the clock rate for the workload type at 812 and can initiate retraining to update the table offline or simply update the table dynamically.

[0055] By maximizing the clock rate of bottleneck components and reducing the clock rate of non-bottleneck components, more flexible system designs are able to adapt according to workloads. Such systems reduce peak power consumption, improve performance, and provide better QoS compatibility features.

[0056] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine a workload of the data storage device; determine a bottleneck element of the workload; select a clock rate of the bottleneck element to be a maximum clock rate of the bottleneck element; and select clock rates of elements other than the bottleneck element to be lower than maximum clock frequencies of the respective elements. The controller is configured to define a plurality of combinations of clock rates of the respective elements and the bottleneck element. The controller is configured to maintain a table of clock rates. The controller is configured to define different categories of workloads. The different categories are selected from the group consisting of: random reads, sequential reads, random writes, sequential writes, mixed workloads, and low queue depth. The different categories are characterized by average command size, fraction of read commands, write commands, and idle time. The different categories are characterized by command length diversity level, average or standard deviation (STD) of logical block address (LBA) distance between adjacent commands, average number or STD of subsequent write / read commands, and queue depth. The controller includes a workload analysis module and an adaptive frequency table. The controller is configured to detect a change in the workload. The controller is configured to monitor an impact of a change in clock rate. The clock rate is based on a doorbell rate. The clock rate is additionally based on submission queue statistics maintained by the controller.

[0057] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: classify a current workload of the data storage device; determine that the current workload is to switch to a new workload; and select a clock rate from a stored table based on the new workload. The determination is based on a rate at which a doorbell rings. The controller is configured to track the rate at which the doorbell rings. The controller is configured to track a number of new available commands in each doorbell and an average command size per submission queue. The controller is configured to predict a pending transfer size of commands in the new workload.

[0058] In another embodiment, a data storage device includes: means for storing data; and a controller coupled to the means for storing data, wherein the controller is configured to: determine that a workload of the data storage device is one of: random reads, sequential reads, random writes, sequential writes, and mixed workloads; obtain a clock rate from a table corresponding to the workload; and set a clock rate for a plurality of components of the data storage device, wherein the set clock rate is the obtained clock rate. The clock rate of the processor is different from the clock rate of the host interface. For one or more of the plurality of components, different workloads have different clock rates.

[0059] While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the claims that follow.

Claims

1. A data storage device, the data storage device comprising: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine a workload of the data storage device; determine a bottleneck element of the workload; select a clock rate of the bottleneck element to be a maximum clock rate of the bottleneck element; and select clock rates of elements other than the bottleneck element to be lower than a maximum clock frequency of the respective element.

2. The data storage device of claim 1, wherein the controller is configured to define a plurality of combinations of clock rates of the respective elements and the bottleneck element.

3. The data storage device of claim 1, wherein the controller is configured to maintain a clock rate table.

4. The data storage device of claim 1, wherein the controller is configured to define different categories of workloads.

5. The data storage device of claim 4, wherein the different categories are selected from the group consisting of: random reads, sequential reads, random writes, sequential writes, mixed workloads, and low queue depth.

6. The data storage device of claim 5, wherein the different categories are characterized by average command size, fraction of read commands, write commands, and idle time.

7. The data storage device of claim 5, wherein the different categories are characterized by a command length diversity level, an average or standard deviation (STD) of logical block address (LBA) distance between adjacent commands, an average number or STD of subsequent write / read commands, and a queue depth.

8. The data storage device of claim 1, wherein the controller comprises a workload analysis module and an adaptive frequency table.

9. The data storage device of claim 1, wherein the controller is configured to detect a change in workload.

10. The data storage device of claim 1, wherein the controller is configured to monitor an impact of a clock rate change.

11. The data storage device of claim 1, wherein the clock rate is based on a doorbell rate.

12. The data storage device of claim 11, wherein the clock rate is additionally based on submission queue statistics maintained by the controller.

13. A data storage device, the data storage device comprising: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: classify a current workload of the data storage device; determine that the current workload is to switch to a new workload; and select a clock rate from a stored table based on the new workload.

14. The data storage device of claim 13, wherein the determination is based on a rate at which a doorbell rings.

15. The data storage device of claim 14, wherein the controller is configured to track the rate at which the doorbell rings. ​ 16. The data storage device of claim 15, wherein the controller is configured to track a number of new available commands in each doorbell and an average command size of each submission queue.

17. The data storage device of claim 16, wherein the controller is configured to predict a pending transfer size of commands in the new workload.

18. A data storage device, the data storage device comprising: a means for storing data; and a controller coupled to the means for storing data, wherein the controller is configured to: determine a workload of the data storage device is one of: random read, sequential read, random write, sequential write, and mixed workload; obtain a clock rate from a table corresponding to the workload; and set a clock rate for a plurality of components of the data storage device, wherein the set clock rate is the obtained clock rate.

19. The data storage device of claim 18, wherein a clock rate of a processor is different from a clock rate of a host interface.

20. The data storage device of claim 18, wherein different workloads have different clock rates for one or more of the plurality of components. ​

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