Non-volatile memory with three-dimensional stacked word line switches

Abstract

A non-volatile memory includes: a plurality of word lines connected to a non-volatile memory cell; a plurality of driver lines configured to carry one or more word line voltages; and a plurality of word line switches that selectively connect the driver lines to the word lines. To make more efficient use of the space on the die, the word line switches are arranged in a plurality of three-dimensional stacks such that each stack of the plurality of stacks includes a plurality of word line switches that are vertically stacked.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the entire content of U.S. Non-Provisional Application No. 18 / 507,026, entitled “NON-VOLATILE MEMORY WITH THREE DIMENSIONAL STACKED WORD LINE SWITCHES,” filed on November 11, 2023, in the U.S. Patent and Trademark Office, and which is hereby incorporated by reference for all purposes. BACKGROUND

[0003] The present disclosure relates to non-volatile memory.

[0004] Semiconductor memory is widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows storage and retention of information even when not connected to a power source (e.g., a battery). One example of non-volatile memory is flash memory (e.g., NAND and NOR flash memory).

[0005] Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read the data back. For example, a digital camera can take a photograph and store the photograph in non-volatile memory. Later, a user of the digital camera can view the photograph by causing the digital camera to read the photograph from the non-volatile memory.

[0006] As users want to store as much data as possible, there is a trend to increase the amount of storage available in non-volatile memory. As the amount of available storage increases, the amount of space in the memory available to support circuitry becomes limited. Thus, there is a need to more efficiently utilize space in non-volatile memory. BRIEF DESCRIPTION OF DRAWINGS

[0007] Like-numbered elements represent common parts across different drawings.

[0008] Figure 1 FIG. 1 is a block diagram depicting one embodiment of a storage system.

[0009] Figure 2A FIG. 2 is a block diagram of one embodiment of a memory die.

[0010] Figure 2B FIG. 3 is a block diagram of one embodiment of an integrated memory component.

[0011] Figure 3A and Figure 3B Different embodiments of integrated memory components are depicted.

[0012] Figure 4 Perspective view of one embodiment of a monolithic three-dimensional memory structure.

[0013] Figure 4A Block diagram of one embodiment of a memory structure having two planes.

[0014] Figure 4B Top view depicting a portion of one embodiment of a memory cell.

[0015] Figure 4C Cross-sectional view depicting a portion of one embodiment of a memory cell.

[0016] Figure 4D Cross-sectional view depicting a portion of one embodiment of a memory cell.

[0017] Figure 4E Cross-sectional view of one embodiment of a vertical column of memory cells.

[0018] Figure 4F Diagram of multiple NAND strings in multiple regions of the same die.

[0019] Figure 5A Threshold voltage distributions are depicted.

[0020] Figure 5B Threshold voltage distributions are depicted.

[0021] Figure 5C Threshold voltage distributions are depicted.

[0022] Figure 5D Threshold voltage distributions are depicted.

[0023] Figure 6 Flowchart of one embodiment of a process to program non-volatile memory.

[0024] Figure 7 Voltage signals applied to a selected word line during programming are depicted.

[0025] Figure 8A Two program voltage pulses applied to a selected word line during programming and a verify voltage pulse between the two program voltage pulses are depicted.

[0026] Figure 8B Two program voltage pulses applied to a selected word line during programming and a verify voltage pulse between the two program voltage pulses are depicted.

[0027] Figure 9 is a block diagram depicting one embodiment of a system for supplying voltages to word lines.

[0028] Figure 10 is a cross-sectional view of one embodiment of a three-dimensional stack of word line switches.

[0029] Figure 11 is a cross-sectional view of one embodiment of a word line switch.

[0030] Figure 12A is a perspective view of one embodiment of a word line switch.

[0031] Figure 12B is a top view of a channel of a word line switch.

[0032] Figure 13 is a top view of one embodiment of a three-dimensional stack of word line switches.

[0033] Figure 14 is a flowchart depicting one embodiment of a process for fabricating a three- dimensional stack of word line switches including Figure 10 structures.

[0034] Figure 15 is a flowchart depicting one embodiment of a process for fabricating a three- dimensional stack of word line switches including Figure 10 structures.

[0035] Figures 16 to 28 depicts one embodiment of a three-dimensional stack of word line switches during a fabrication process. DETAILED DESCRIPTION

[0036] A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on a die, the word line switches are arranged into a plurality of three-dimensional stacks such that each stack of the plurality of stacks includes a plurality of word line switches stacked vertically.

[0037] Figure 1is a block diagram of one embodiment of a storage system 100 that implements the proposed technology described herein. In one embodiment, the storage system 100 is a solid state drive (“SSD”). The storage system 100 can also be a memory card, a USB drive, or another type of storage system. The proposed technology is not limited to any one type of memory system. The storage system 100 is connected to a host 102, which can be a computer, a server, an electronic device (e.g., a smartphone, a tablet, or other mobile device), an appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from but connected to the storage system 100. In other embodiments, the storage system 100 is embedded within the host 102.

[0038] Figure 1 The components of the storage system 100 depicted in the middle are circuits. The storage system 100 includes a memory controller 120 that is connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores a logical-to-physical address translation table (“L2P table”).

[0039] The memory controller 120 includes a host interface 152 that is connected to and in communication with the host 102. In one embodiment, the host interface 152 implements fast NVM (NVMe) over fast PCI (PCIe). Other interfaces such as SCSI, SATA, etc. can also be used. The host interface 152 is also connected to a network on chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. A NOC can span synchronous and asynchronous clock domains or use non-clock asynchronous logic. NOC technology applies networking theory and methods to on-chip communication and brings significant improvements over conventional bus and crossbar interconnects. A NOC improves the scalability of a system on chip (SoC) and the power efficiency of a complex SoC compared to other designs. The wires and links of a NOC are shared by many signals. Because all links in a NOC can operate on different data packets at the same time, a high level of parallelism is achieved. Thus, as the complexity of integrated subsystems continues to grow, a NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. Connected to and in communication with the NOC 154 are a processor 156, an ECC engine 158, a memory interface 160, and a DRAM controller 164. The DRAM controller 164 is used to operate and communicate with the local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 140 can be SRAM or another type of volatile memory.

[0040] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding in accordance with the implemented ECC technology. In one embodiment, the ECC engine 158 is a circuit programmed by software. For example, the ECC engine 158 can be a processor that can be programmed. In other embodiments, the ECC engine 158 is a custom, dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0041] The processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, the processor 156 is programmed by firmware. In other embodiments, the processor 156 is a custom application-specific hardware circuit without any software. The processor 156 also implements the translation module as software / firmware processing or as a special-purpose hardware circuit. In many systems, the non-volatile memory is internally addressed by the storage system using physical addresses associated with one or more memory dies. However, the host system will address various memory locations using logical addresses. This enables the host to allocate data to consecutive logical addresses while the storage system is free to store the data wherever it wishes among the locations of one or more memory dies. To implement this system, the memory controller 120 (e.g., the translation module) performs address translations between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain a table that identifies the current translations between logical addresses and physical addresses (i.e., the L2P table described above). An entry in the L2P table can include an identification of a logical address and a corresponding physical address. Although the logical address to physical address table (or L2P table) includes the word “table,” they need not be a table in the literal sense. Rather, the logical address to physical address table (or L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all of the L2P table. In this case, the entire set of L2P tables is stored in the memory dies 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0042] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a toggle mode interface. Other interfaces can also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffers for sending data to and receiving data from one or more memory dies.

[0043] In one embodiment, the non-volatile memory 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 that includes the non-volatile memory 130. Each of the one or more memory dies of the non-volatile memory 130 can be implemented as Figure 2A the memory die 200 of FIG. 1. Figure 2AThe components depicted are circuitry. The memory die 200 includes a memory array 202, which can include non-volatile memory cells, as described in greater detail below. The array terminal lines of the memory array 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations can also be implemented. The memory die 200 includes a row control circuit 220, the output 208 of which is connected to respective word lines of the memory array 202. The row control circuit 220 receives a set of M row address signals and one or more various control signals from system control logic 260, and can generally include circuitry for both read and write (program) operations, such as a row decoder 222, array terminal drivers 224, and block select circuitry 226. The row control circuit 220 can also include read / write circuitry. The memory die 200 also includes a column control circuit 210, which includes sense amplifiers 230, the input / output 206 of which is connected to respective bit lines of the memory array 202. Although only a single block is shown for the array 202, the memory die can include multiple arrays that can be accessed individually. The column control circuit 210 receives a set of N column address signals and one or more various control signals from the system control logic 260, and can generally include circuitry such as a column decoder 212, array terminal receiver or driver circuit 214, block select circuitry 216, and read / write circuitry and I / O multiplexers.

[0044] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260, which includes one or more circuits, includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is implemented entirely in hardware (e.g., circuitry). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor on or off the memory chip. The system control logic 262 can also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operations, and can include charge pumps and regulator circuitry for generating regulated voltages. The system control logic 262 includes storage 366 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory array 202.

[0045] Commands and data are transferred between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a “communication interface”). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a Toggle Mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces can also be used.

[0046] In some implementations, all elements of the memory die 200, including the system control logic 260, can be formed as part of a single die. In other implementations, some or all of the system control logic 260 can be formed on a different die.

[0047] In one implementation, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple levels of memory are formed over a single substrate, such as a wafer. The memory structure can include any type of non-volatile memory formed in monolithic integrated fashion in one or more physical levels of memory cells having active regions above a silicon substrate (or other type of substrate) with on-chip interconnects between the levels of memory. In one example, the non-volatile memory cells include vertical NAND strings with charge-trapping layers.

[0048] In another implementation, the memory structure 302 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells with floating gates. Other types of memory cells (e.g., NOR type flash memory) can also be used.

[0049] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. For the purposes of the newly claimed embodiments presented herein, a particular non-volatile memory technology is not required. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0050] One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in a cross-point array accessed by X and Y lines (e.g., word and bit lines). In another implementation, the memory cells can include a conductive-bridge memory element. The conductive-bridge memory element can also be referred to as a programmable metallization cell. The conductive-bridge memory element can be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive-bridge memory element can include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, resulting in a lower programming threshold for the conductive-bridge memory cell. Thus, the conductive-bridge memory element can have a wide range of programming thresholds that vary with temperature.

[0051] Another example is a magnetoresistive random access memory (MRAM) that stores data by the magnetic resistance of a memory element. The element is formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the magnetization of the other layer can be changed to match that of an external field, thereby storing the memory. The memory device is constructed from a grid of such memory cells. In one implementation for programming, each memory cell is located between a pair of write lines, which are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When a current is passed through the pair of write lines, an induced magnetic field is created. MRAM-based memory implementations are discussed in more detail below.

[0052] A phase change memory (PCM) takes advantage of the unique behavior of chalcogenide glasses. One implementation uses a GeTe-Sb2Te3superlattice to achieve non-thermal phase changes by simply changing the coordination state of the germanium atoms with a laser pulse (or a light pulse from another source). Thus, the dose of programming is the laser pulse. A memory cell can be inhibited from receiving the light by a barrier. In other PCM implementations, the memory cells are programmed by a current pulse. Note that the use of "pulse" in this document does not require a square pulse, but includes a burst of oscillations (continuous or non-continuous) or sound, current, voltage light, or other wave. These memory elements within a single selectable memory cell or bit can include another series element as a selector, such as a bidirectional threshold switch or metal insulator substrate.

[0053] One of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory construction, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

[0054] Figure 2A The elements of the memory system 100 can be divided into two parts: (1) the memory structure 202 and (2) the peripheral circuitry, including Figure 2A All other components depicted in FIG. 1. An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of the memory die of the memory system 100 on the memory structure 202; however, this decreases the area of the memory die that can be used for the peripheral circuitry. This can impose quite stringent limitations on these elements of the peripheral circuitry. For example, the need to fit the sense amplifier circuitry within the available area can greatly limit the sense amplifier design architecture. With respect to the system control logic component 260, the decrease in area availability can limit the available functionality that can be implemented on-chip. Thus, a fundamental tradeoff in the design of the memory die for the memory system 100 is the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry.

[0055] Another area in which the memory structure 202 and the peripheral circuitry are typically not uniform is the processing involved in forming these areas, as these areas typically involve different processing technologies and compromises in using different technologies on a single die. For example, when the memory structure 202 is NAND flash memory, this is an NMOS structure, while the peripheral circuitry is typically CMOS-based. For example, elements such as the sense amplifier circuitry, charge pump, logic elements in the state machine, and other peripheral circuitry in the system control logic component 260 typically employ PMOS devices. The processing operations used to fabricate a CMOS die will differ in many respects from processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0056] To ameliorate these limitations, the embodiments described below can provide for Figure 2Aelements are separated onto individually formed dies, which are then bonded together. More specifically, the memory structures 202 can be formed on one die (referred to as a memory die), and some or all of the peripheral circuit elements, including one or more control circuits, can be formed on a separate die (referred to as a control die). For example, the memory die can be formed of only memory elements, such as an array of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory types. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved to a separate control die. This allows each of the memory dies to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure, without worrying about CMOS elements that have now moved to a control die that can be optimized for CMOS processing. This frees up more space for peripheral elements that can now incorporate additional capabilities that would have been difficult to incorporate due to the margin constraints of keeping the memory cell array on the same die. The two dies can then be bonded together in a bonded multi-die memory circuit, with the array on one die connected to the peripheral elements on the other die. While the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more dies, such as, for example, two memory dies and one control die.

[0057] Figure 2B An alternative arrangement of the arrangement of FIG. 1 is shown, which can be implemented using wafer-to-wafer bonding to provide a bonded pair of dies. Figure 2A An alternative arrangement of the arrangement of FIG. 1 is shown, which can be implemented using wafer-to-wafer bonding to provide a bonded pair of dies. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 can be used to implement the non-volatile memory 130 of the storage system 100. The integrated memory component 207 includes two types of semiconductor dies (or more simply, “dies”). The memory die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

[0058] Figure 2B An example of the peripheral circuitry (including control circuitry) formed in the control die 211 or peripheral circuitry coupled to the memory structure 202 formed in the memory die 201 is shown. Common components are labeled with the same reference numerals as in FIG. 1. Figure 2ASimilarly labeled. The system control logic 260, row control circuit 220, and column control circuit 210 are located in the control die 211. In some embodiments, all or a portion of the column control circuit 210 and all or a portion of the row control circuit 220 are located on the memory die 201. In some embodiments, some of the circuitry in the system control logic 260 is located on the memory die 201.

[0059] The system control logic 260, row control circuit 220, and column control circuit 210 can be formed through a common process (e.g., a CMOS process) such that additional elements and functionality (such as ECC) that are more typically found on a memory controller 120 can require little or no additional process steps (i.e., the same process steps used to fabricate the controller 120 can also be used to fabricate the system control logic 260, row control circuit 220, and column control circuit 210). Thus, while moving such circuitry from a die (such as the memory 2 die 201) can reduce the number of steps required to fabricate such a die, adding such circuitry to a die (such as the control die 211) can not require many additional process steps. Because some or all of the control circuitry 260, 210, 220 is implemented using CMOS technology, the control die 211 can also be referred to as a CMOS die.

[0060] Figure 2B The column control circuit 210, including sense amplifiers 230, on the control die 211 is shown coupled to the memory structure 202 on the memory die 201 through electrical paths 206. For example, the electrical paths 206 can provide electrical connections between the column decoders 212, driver circuit 214, and block select 216 and the bit lines of the memory structure 202. The electrical paths can extend from the column control circuit 210 in the control die 211 through bond pads on the control die 211 to corresponding pads on the memory die 201 that are connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 can have a corresponding electrical path in the electrical paths 206, including a pair of bond pads connected to the column control circuit 210. Similarly, the row control circuit 220, including row decoders 222, array drivers 224, and block select 226, is coupled to the memory structure 202 through electrical paths 208. Each of the electrical paths in the electrical paths 208 can correspond to a word line, dummy word line, or select gate line. Additional electrical paths can also be provided between the control die 211 and the memory die 201.

[0061] For the purposes of this document, the phrase “control circuit” or “one or more control circuits” can include any or any combination of the memory controller 120, the state machine 262, all or a portion of the system control logic 260, all or a portion of the row control circuit 220, all or a portion of the column control circuit 210, a microcontroller, a microprocessor, and / or other similar functional circuitry. The control circuit can include only hardware or a combination of hardware and software, including firmware. For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. The control circuit can include a processor, an FGA, an ASIC, an integrated circuit, or other type of circuit.

[0062] In some embodiments, there is more than one control die 211 and more than one memory die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 3A A side view of an embodiment of the integrated memory component 207 (e.g., including a stack of control dies 211 and memory dies 201) stacked on a substrate 271 is depicted. The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0063] Each control die 211 is attached (e.g., bonded) to at least one of the memory dies 201. Some of the bond pads 282 / 284 are depicted. There can be more bond pads. The space between the two dies 201, 211 that are bonded together is filled with a solid layer 280, which can be formed of an epoxy or other resin or polymer. This solid layer 280 protects the electrical connections between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280, but in embodiments it can be Hysol epoxy from Henkel Corp. with offices in California, USA.

[0064] The integrated memory component 207 can be stacked, for example, in a staggered offset, so that the bond pads at each level are not covered and are accessible from above. Wire bonds 270, which connect to the bond pads, connect the control dies 211 to the substrate 271. Multiple such wire bonds can be formed across the width of each control die 211 (i.e., into the page). Figure 3A Multiple such wire bonds can be formed across the width of each control die 211 (i.e., into the page).

[0065] Memory die through-silicon vias (TSVs) 276 can be used to route signals through the memory dies 201. Control die through-silicon vias (TSVs) 278 can be used to route signals through the control dies 211. The TSVs 276, 278 can be formed before, during, or after the integrated circuits are formed in the semiconductor dies 201, 211. The TSVs can be formed by etching holes through a wafer. The holes can then be lined with a barrier layer to prevent diffusion of metals. The barrier layer in turn can be lined with a seed layer, and the seed layer can be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof can also be used.

[0066] Solder balls 272 can optionally be attached to contact pads 274 on the lower surface of the substrate 271. The solder balls 272 can be used to electrically and mechanically couple the integrated memory assembly 207 to a host device such as a printed circuit board. In cases where the integrated memory assembly 207 is to be used as an LGA package, the solder balls 272 can be omitted. The solder balls 272 can form part of the interface between the integrated memory assembly 207 and the memory controller 120.

[0067] Figure 3B A side view of another embodiment of the integrated memory assembly 207 stacked on a substrate 271 is depicted. Figure 3B The integrated memory assembly 207 of FIG. 1 has three control dies 211 and three memory dies 201. In some embodiments, there are many more than three memory dies 201 and many more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 can be bonded to two or more memory dies 201.

[0068] Some of the bond pads 282, 284 are shown. There can be many more bond pads. The space between the two dies 201, 211 that are bonded together is filled with a solid layer 280, which can be formed of epoxy or other resin or polymer. As with the example of FIG. 1, Figure 3A In contrast to the example of FIG. 1, Figure 3B The integrated memory assembly 207 of FIG. 2 does not have a stepped offset. Memory die through-silicon vias (TSVs) 276 can be used to route signals through the memory dies 201. Control die through-silicon vias (TSVs) 278 can be used to route signals through the control dies 211.

[0069] Solder balls 272 can optionally be attached to contact pads 274 on the lower surface of the substrate 271. The solder balls 272 can be used to electrically and mechanically couple the integrated memory assembly 207 to a host device such as a printed circuit board. In cases where the integrated memory assembly 207 is to be used as an LGA package, the solder balls 272 can be omitted.

[0070] As has been briefly discussed above, the control die 211 and the memory die 201 can be bonded together. Bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in a so-called Cu-to-Cu bonding process, the bonding pads are bonded directly to one another without the need for solder or other added material. In a Cu-to-Cu bonding process, the bonding pads are controlled to be highly planar and formed in a highly controlled environment that is largely free of environmental particles that might otherwise deposit on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against one another to form a mutual bond based on surface tension. Such bonding can be formed at room temperature, although heat can also be applied. In embodiments that use Cu-to-Cu bonding, the bonding pads can be about 5 pm square and spaced apart from one another at a pitch of 5 pm to 5 pm. While this process is referred to herein as Cu-to-Cu bonding, the term can also apply where the bonding pads are formed from materials other than Cu.

[0071] When the area of the bonding pads is small, it can be difficult to bond the semiconductor dies together. By providing a film layer on the surface of the semiconductor dies that includes the bonding pads, the size of the bonding pads and the pitch between the bonding pads can be further reduced. The film layer is disposed around the bonding pads. When the dies are brought together, the bonding pads can bond to one another and the film layers on the respective dies can bond to one another. Such a bonding technique can be referred to as hybrid bonding. In embodiments that use hybrid bonding, the bonding pads can be about 5 pm square and spaced apart from one another at a pitch of 1 pm to 5 pm. Bonding techniques can be used to provide bonding pads having even smaller (or larger) sizes and pitches.

[0072] Some embodiments can include a film on the surface of the dies 201, 211. In cases where such a film is not initially provided, the space between the dies can be filled with an epoxy or other resin or polymer as a bottom fill. The bottom fill material can be applied as a liquid, which then hardens into a solid layer. This bottom fill step protects the electrical connections between the dies 201, 211 and further secures the dies together. Various materials can be used as the bottom fill material, but in embodiments it can be Hysol epoxy from Henkel Corp. having an office in California, USA.

[0073] Figure 4 is a perspective view of part of one example embodiment of a monolithic three-dimensional memory array / structure that can include a memory structure 202, which includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4A portion 400 of one block of memory is shown. The depicted structure includes a set of bit lines BL positioned above a stack 401 of alternating dielectric layers and conductive layers. For purposes of example, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as word line layers) is labeled W. The number of alternating dielectric layers and conductive layers can vary based on particular implementation requirements. As will be explained below, in one embodiment, the alternating dielectric layers and conductive layers are divided into four or five (or a different number of) regions by isolation regions IR. Figure 4 One of the isolation regions IR separating two regions is shown. Below the alternating dielectric layers and word line layers are source line layers SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is labeled MH. Note that in Figure 4 In the middle, the dielectric layers are depicted as transparent so that the reader can see the memory holes located in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory holes with material that includes charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. Thus, non-volatile memory cells are disposed in the memory holes. More details of a three-dimensional monolithic memory array including the memory structure 202 are provided below.

[0074] Figure 4A is a block diagram explaining one example organization of the memory structure 202, which is divided into four planes 402, 403, 404, and 405. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, the blocks of memory cells are erase units. That is, all of the memory cells of a block are erased together. In other embodiments, the blocks can be divided into sub-blocks and these sub-blocks can be erase units. The memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuitry. In some embodiments, a block represents a group of connected memory cells, as the memory cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block. Although Figure 4A Four planes are shown, but more or less than four planes can be implemented. In some embodiments, the memory structure 202 includes eight planes.

[0075] Figures 4B to 4 G depicts an example three-dimensional (“3D”) NAND structure corresponding to the structure of Figure 4 and that can be used to implement the memory structure 202 of Figure 2A and Figure 2B . Figure 4Bis a block diagram depicting a top view of portion 406 of block 2 of plane 402. From Figure 4B As can be seen, Figure 4B The block depicted in FIG. 4A extends in the direction of 432. In one embodiment, the memory array has many tiers; however, Figure 4B Only the top tier is shown.

[0076] Figure 4B A plurality of circles representing memory holes, also referred to as vertical columns, are depicted. Each of the memory holes / vertical columns includes a plurality of select transistors (also referred to as select gates) and a plurality of memory cells. In one embodiment, each memory hole / vertical column implements a NAND string. For example, Figure 4B A subset of the memory holes / vertical columns / NAND strings 432, 436, 446, 456, 462, 466, 472, 474, and 476 are labeled.

[0077] Figure 4B A set of bit lines 415, including bit lines 411, 412, 413, 414, …, 419, are also depicted. Figure 4B Twenty-four bit lines are shown because only a portion of a block is depicted. More than twenty-four bit lines are contemplated to be connected to the memory holes / vertical columns of a block. Each of the circles representing the memory holes / vertical columns has an “x” to indicate its connection to one bit line. For example, bit line 411 is connected to memory holes / vertical columns 436, 446, 456, 466, and 476.

[0078] Figure 4B The block depicted in FIG. 4A includes a set of isolation regions 482, 484, 486, and 488, which are formed of SiO2; however, other dielectric materials can also be used. Isolation regions 482, 484, 486, and 488 are used to divide the top tier of the block into five regions; for example, Figure 4B The top tier depicted in FIG. 4A is divided into regions 430, 440, 450, 460, and 470. In one embodiment, the isolation regions divide only the tier used to implement select gates, so that the NAND strings in different regions can be independently selected. In one example implementation, a bit line is connected to one memory hole / vertical column / NAND string in each of regions 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to five rows in each block. In one embodiment, all five memory holes / vertical columns / NAND strings connected to a common bit line are connected to the same set of word lines; therefore, the system uses a drain side select line to select one (or another subset) of the five memory holes / vertical columns / NAND strings to be subjected to a memory operation (program, verify, read, and / or erase).

[0079] Figure 4B Also shown are line interconnects LI, which are metal connections from above the memory array to the source lines SL. The line interconnects LI are positioned adjacent to regions 430 and 470.

[0080] Although Figure 4B Each region 430, 440, 450, 460, and 470 is shown as having four rows of memory holes / vertical columns, five regions, and twenty-four rows of memory holes / vertical columns in a block, these exact numbers are example implementations. Other implementations can include more or fewer regions per block, more or fewer rows of memory holes / vertical columns per region, and more or fewer rows of vertical columns per block. Figure 4B Also shown is that the memory holes / vertical columns are staggered. In other implementations, different staggering patterns can be used. In some implementations, the memory holes / vertical columns are not staggered.

[0081] Figure 4C A portion of one implementation of a three-dimensional memory structure 202 is depicted, showing a cross-sectional view along line AA of Figure 4B The cross-sectional view cuts through memory holes / vertical columns (NAND strings) 472 and 474 of region 470 (see Figure 4B ). Figure 4C The structure of FIG. 1 1 includes two drain side select layers SGD0 and SGD; two source side select layers SGS0 and SGS1; two drain side GIDL generation transistor layers SGDT0 and SGDT1; two source side GIDL generation transistor layers SGSB0 and SGSB1; two drain side dummy word line layers DD0 and DD1; two source side dummy word line layers DS0 and DS1; dummy word line layers DU and DL; one hundred sixty-two word line layers WLO-WL161 for connection to data memory cells, and a dielectric layer DL. Other implementations can implement more or fewer than the numbers described above for FIG. 1 1. In one implementation, SGD0 and SGD1 are connected together; and SGS0 and SGS1 are connected together. In other implementations, a greater or fewer number of SGD (greater or fewer than two SGD) are connected together, and a greater or fewer number of SGS (greater or fewer than two SGS) are connected together. Figure 4C

[0082] In one implementation, erase memory cells is performed using gate induced drain leakage (GIDL), which includes generating charge carriers at a GIDL generation transistor such that the carriers are injected into a charge trapping layer of a NAND string to change a threshold voltage of the memory cell. Figure 4C ​Two GIDL generation transistors are shown at each end of the NAND string; however, in other implementations, there are more or less than three GIDL generation transistors. Implementations that use GIDL on both sides of the NAND string can have GIDL generation transistors on both sides. Implementations that use GIDL only on the drain side of the NAND string can have GIDL generation transistors only on the drain side. Implementations that use GIDL only on the source side of the NAND string can have GIDL generation transistors only on the source side.

[0083] Figure 4C Two GIDL generation transistors are shown at each end of the NAND string. It is likely that charge carriers are generated by GIDL at only one of the two GIDL generation transistors at each end of the NAND string. Based on process variations during manufacturing, it is likely that one of the two GIDL generation transistors at one end of the NAND string is best suited for GIDL. For example, the GIDL generation transistor has a abrupt pn junction to generate charge carriers for GIDL, and during fabrication, a phosphorous diffusion is performed at the polysilicon channel of the GIDL generation transistor. In some cases, the GIDL generation transistor with the shallowest phosphorous diffusion is the GIDL generation transistor that generates charge carriers during erase. However, in some implementations, charge carriers can be generated by GIDL at multiple GIDL generation transistors of a particular side of the NAND string.

[0084] Memory holes / vertical columns 472 and 474 are depicted as protruding through the drain side select layer, the source side select layer, the dummy word line layer, the GIDL generation transistor layer, and the word line layer. In one implementation, each memory hole / vertical column includes a vertical NAND string. Under the memory hole / vertical column and the layers listed below, is the substrate 453, an insulating film 454 on the substrate, and a source line SL. The NAND string of memory hole / vertical column 472 has a source end at the bottom of the stack and a drain end at the top of the stack. The NAND string of memory hole / vertical column 474 has a source end at the top of the stack and a drain end at the bottom of the stack. The NAND string of memory hole / vertical column 472 is connected to the source line SL at the bottom of the stack and to the bit line BL at the top of the stack. The NAND string of memory hole / vertical column 474 is connected to the source line SL at the top of the stack and to the bit line BL at the bottom of the stack. Figure 4B Consistent with, Figure 4C A vertical memory hole / column 472 is shown connected to the bit line 414 via the connection 417.

[0085] For ease of reference, the drain-side select layer; the source-side select layer, the dummy word line layer, the GIDL generation transistor layer, and the data word line layer are collectively referred to as conductive layers. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, a metal such as tungsten, a metal silicide such as nickel silicide, tungsten silicide, aluminum silicide, or a combination thereof. In some embodiments, different conductive layers can be formed of different materials. Between the conductive layers are dielectric layers DL. In one embodiment, the dielectric layers are made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0086] Non-volatile memory cells are formed along memory holes / vertical columns that extend through the alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged into NAND strings. The word line layers WL0-WL161 are connected to memory cells (also referred to as data memory cells). The dummy word line layers are connected to dummy memory cells. The dummy memory cells do not store and are not eligible to store host data (data provided from a host, such as data from a user of the host), while the data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells can have the same structure. The drain-side select layers SGD0 and SGD1 are used to electrically connect and disconnect the NAND strings to bit lines. The source-side select layers SGS0 and SGS1 are used to electrically connect and disconnect the NAND strings to source lines SL.

[0087] Figure 4C It is shown that the memory array is implemented as a two-tier architecture, where the tiers are separated by a joint. In one embodiment, it is expensive and / or challenging to etch so many word line layers mixed with dielectric layers. To alleviate this burden, one embodiment includes laying out a first tier of word line layers (e.g., WL0-WL80) alternating with dielectric layers, laying out a joint, and laying out a second tier of word line layers (e.g., WL81-WL161) alternating with dielectric layers. The joint is located between the first tier and the second tier. In one embodiment, the joint is made of the same material as the word line layers. In other embodiments, there can be no joint or there can be multiple joints.

[0088] Figure 4D A portion of one embodiment of a three-dimensional memory structure 202 is depicted showing a cross-sectional view along a line BB of Figure 4B The cross-sectional view cuts through memory holes / vertical columns (NAND strings) 432 and 434 of region 430 (see Figure 4B ). Figure 4D It is shown that the memory array is implemented as a two-tier architecture, where the tiers are separated by a joint. In one embodiment, it is expensive and / or challenging to etch so many word line layers mixed with dielectric layers. To alleviate this burden, one embodiment includes laying out a first tier of word line layers (e.g., WL0-WL80) alternating with dielectric layers, laying out a joint, and laying out a second tier of word line layers (e.g., WL81-WL161) alternating with dielectric layers. The joint is located between the first tier and the second tier. In one embodiment, the joint is made of the same material as the word line layers. In other embodiments, there can be no joint or there can be multiple joints. Figure 4CThe same alternating conductive and dielectric layers. Figure 4D Isolation regions 482 are also shown. Isolation regions 482, 484, 486, and 488 occupy space that would otherwise be used for a portion of the memory hole / vertical column / NAND string. For example, isolation region 482 occupies space that would otherwise be used for a portion of memory hole / vertical column 434. More specifically, a portion (e.g., half of the diameter) of vertical column 434 has been removed in layers SGDT0, SGDT1, SGD0, and SGD1 to accommodate isolation region 482. Thus, while most of vertical column 434 is cylindrical (has a circular cross-section), the portion of vertical column 434 in layers SGDT0, SGDT1, SGD0, and SGD1 has a semi-circular cross-section. In one embodiment, after the stack of alternating conductive and dielectric layers is formed, the stack is etched to create space for the isolation region, which is then filled with SiO2. This structure allows for individual control of SGDT0, SGDT1, SGD0, and SGD1 for regions 430, 440, 450, 460, and 470.

[0089] Figure 4E A cross-sectional view of region 429, which includes a portion of memory hole / vertical column 472, is depicted. Figure 4C In one embodiment, the memory hole / vertical column is circular; however, in other embodiments, other shapes can be used. In one embodiment, memory hole / vertical column 472 includes an inner core layer 490 made of a dielectric, such as SiO2. Other materials can also be used. Surrounding inner core 490 is a polysilicon channel 491. Materials other than polysilicon can also be used. Note that channel 491 is connected to the bit line and source line. Surrounding channel 491 is a tunneling dielectric 492. In one embodiment, tunneling dielectric 492 has an ONO structure. Surrounding tunneling dielectric 492 is a charge trapping layer 493, such as (for example) silicon nitride. Other memory materials and structures can also be used. The techniques described herein are not limited to any particular material or structure.

[0090] Figure 4EThe dielectric layers DL and the word line layers WL160, WL159, WL158, WL157, and WL156 are depicted. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer that is parallel and adjacent to the charge trapping layer 493. The physical interaction of the word line layers with the vertical columns forms a memory cell. Thus, in one embodiment, a memory cell includes the channel 491, the tunneling dielectric 492, the charge trapping layer 493, the blocking oxide layer 498, the aluminum oxide layer 497, and the word line region 496. For example, the word line layer WL160 and a portion of the memory hole / vertical column 472 constitute a memory cell MC1. The word line layer WL159 and a portion of the memory hole / vertical column 472 constitute a memory cell MC2. The word line layer WL158 and a portion of the memory hole / vertical column 472 constitute a memory cell MC3. The word line layer WL157 and a portion of the memory hole / vertical column 472 constitute a memory cell MC4. The word line layer WL156 and a portion of the memory hole / vertical column 472 constitute a memory cell MC5. In other architectures, the memory cells can have different structures; however, the memory cells will still be the unit of storage.

[0091] When a memory cell is programmed, an electron is stored in the portion of the charge trapping layer 493 associated with (e.g., in) the memory cell. In response to an appropriate voltage on the word line region 496, these electrons are attracted from the channel 491 into the charge trapping layer 493 through the tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is achieved through Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, the electrons return to the channel, or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erase is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0092] Figure 4F is Figures 4 to 4E schematic diagram of a portion of the three-dimensional memory array 202 depicted in FIG. 2. Figure 4F Physical data word lines WL0-WL161 extending across the entire block are shown. Figure 4F The structure of FIG. 4 corresponds to Figure 4A A portion 406 in block 2 of FIG. 4, including bit line 411. Within a block, in one embodiment, each bit line is connected to five NAND strings, one in each of the regions 430, 440, 450, 460, 470. Thus, Figure 4FBit lines 411 are shown connected to NAND string NSO (which corresponds to memory holes / vertical columns 436 of region 430), NAND string NSl (which corresponds to memory holes / vertical columns 446 of region 440), NAND string NS2 (which corresponds to vertical columns 456 of region 450), NAND string NS3 (which corresponds to memory holes / vertical columns 466 of region 460), and NAND string NS4 (which corresponds to memory holes / vertical columns 476 of region 470).

[0093] Drain side select lines / layers SGD0 are separated by isolation regions 482, 484, 486, and 488 to form SGD0-s0, SGD0-s1, SGD0-s2, SGD0-s3, and SGD0-s4, to separately connect to and independently control regions 430, 440, 450, 460, 470. Similarly, drain side select lines / layers SGD1 are separated by isolation regions 482, 484, 486, and 488 to form SGD1-s0, SGD1-s1, SGD1-s2, SGD1-s3, and SGD1-s4, to separately connect to and independently control regions 430, 440, 450, 460, 470; drain side GIDL generation transistor control lines / layers SGDT0 are separated by isolation regions 482, 484, 486, and 488 to form SGDT0-s0, SGDT0-s1, SGDT0-s2, SGDT0-s3, and SGDT0-s4, to separately connect to and independently control regions 430, 440, 450, 460, 470; drain side GIDL generation transistor control lines / layers SGDT1 are separated by isolation regions 482, 484, 486, and 488 to form SGDT1-s0, SGDT1-s1, SGDT1-s2, SGDT1-s3, and SGDT1-s4, to separately connect to and independently control regions 430, 440, 450, 460, 470.

[0094] Figure 4F Only NAND strings connected to bit lines 411 are shown. However, a full schematic of a block would show each bit line and five vertical NAND strings connected to each bit line (which are in separate regions).

[0095] Although Figures 4 to 4F The example memory of is a three-dimensional memory structure including vertical NAND strings with charge-trapping material, but other (2D and 3D) memory structures can also be used with the techniques described herein.

[0096] The memory systems discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltages of the memory cells should be appropriately within one or more distributions of threshold voltages of programmed memory cells or within a distribution of threshold voltages of erased memory cells. Figure 5A is a plot of threshold voltage versus number of memory cells, and illustrates an example threshold voltage distribution of a memory array when each memory cell stores one bit of data per memory cell. Memory cells that store one bit of data per memory cell are referred to as single-level cells (“SLCs”). Data stored in SLC memory cells is referred to as SLC data; thus, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Memory cells having threshold voltages in threshold voltage distribution E are thus in an erased data state (e.g., they are erased). Memory cells having threshold voltages in threshold voltage distribution P are thus in a programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data “1” and programmed memory cells store data “0.” Figure 5A A read reference voltage Vr is depicted. By testing (e.g., performing one or more sense operations) whether a given memory cell’s threshold voltage is above or below Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A A verify reference voltage Vv is also depicted. In some embodiments, when programming memory cells to data state P, the system will test whether those memory cells have threshold voltages greater than or equal to Vv.

[0097] Figures 5B to 5D Example threshold voltage distributions of a memory array are illustrated when each memory cell stores multiple bits of data per memory cell. Memory cells that store multiple bits of data per memory cell are referred to as multi-level cells (“MLCs”). Data stored in MLC memory cells is referred to as MLC data; thus, MLC data comprises multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. In Figure 5B In example embodiments of, each memory cell stores two bits of data. Other embodiments can use other data capacities per memory cell (e.g., such as three, four, or five bits of data per memory cell).

[0098] Figure 5BA first threshold voltage distribution E of erased memory cells is shown. Three threshold voltage distributions A, B, and C of programmed memory cells are also depicted. In one embodiment, the threshold voltages in distribution E are negative and the threshold voltages in distributions A, B, and C are positive. Figure 5B Each of the different threshold voltage distributions corresponds to a predetermined value of a set of data bits. In one embodiment, each of the two data bits stored in a memory cell is in a different logical page, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all of the data bits stored in a memory cell are in a common logical page. The particular relationship between the data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. Table 1 provides example encoding schemes.

[0099] Table 1

[0100] E A B C LP 1 0 0 1 UP 1 1 0 0

[0101] In one embodiment, referred to as full sequence programming, the process (discussed below) can be used to program memory cells directly from the erased data state E to any of the programmed data states A, B, or C. For example, a population of memory cells to be programmed can first be erased so that all of the memory cells in the population are in the erased data state E. Then, the memory cells are programmed directly into data states A, B, and / or C using the programming process. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 6 The arrows of FIG. 1C represent full sequence programming. In some embodiments, data states A through C can overlap, with the memory controller 120 (or control die 211) relying on error correction to identify the correct data being stored. Figure 5B

[0102] Figure 5C An example threshold voltage distribution of memory cells is depicted, where each memory cell stores three data bits per memory cell (which is another example of MLC data). Figure 5C ​Eight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) A through G represent programmed memory cells, and are thus also referred to as program states. Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The particular relationship between data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. In one embodiment, a Gray code allocation is used to allocate data values to threshold voltage ranges such that if the threshold voltage of a memory shifts erroneously to its adjacent physical state, only one bit will be affected. Table 2 provides an example of an encoding scheme for an embodiment in which each of the three data bits stored in a memory cell is in a different logical page, referred to as a lower page (LP), a middle page (MP), and an upper page (UP).

[0103] Table 2

[0104] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0105] Figure 5C Seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG are shown for reading data from a memory cell. By testing (e.g., performing a sense operation) whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D,...) the memory cell is in.

[0106] Figure 5C Seven verify reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG are also shown. In some embodiments, when programming memory cells to data state A, the system will test those memory cells for a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test memory cells for a threshold voltage greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether memory cells have a threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test those memory cells for a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test those memory cells for a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test those memory cells for a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test those memory cells for a threshold voltage greater than or equal to VvG. Figure 5CAlso shown is Vev, which is an erase verify reference voltage used to test whether a memory cell has been properly erased.

[0107] In implementations utilizing full sequence programming, the process (discussed below) of Figure 6 can be used to program memory cells directly from an erased data state, Er, to any of the programmed data states, A through G. For example, a population of memory cells to be programmed can first be erased so that all of the memory cells in the population are in the erased data state, Er. Then, using the programming process, the memory cells are programmed directly to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and / or from data state Er to data state C, and so on. Figure 5C The arrows of FIG. 1 1 represent full sequence programming. In some implementations, the data states A through G can overlap, with control die 21 1 and / or memory controller 120 relying on error correction to identify the correct data being stored. Note that in some implementations, the system can use a multi-pass programming process known in the art, rather than using full sequence programming.

[0108] In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), and for each read operation (see, e.g., FIG. 12), the level of that voltage is specified (see, e.g., FIG. 13) in order to determine whether the threshold voltage of the memory cell of interest has reached that level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell turns on (conducts current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a particular value, then the memory cell is assumed to turn on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the particular value, then the memory cell is assumed not to turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During read or verify processes, unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether they are programmed or erased). Figure 5C Figure 5C In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), and for each read operation (see, e.g., FIG. 12), the level of that voltage is specified (see, e.g., FIG. 13) in order to determine whether the threshold voltage of the memory cell of interest has reached that level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell turns on (conducts current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a particular value, then the memory cell is assumed to turn on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the particular value, then the memory cell is assumed not to turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During read or verify processes, unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether they are programmed or erased).

[0109] ​There are a number of ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) a NAND string including the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see if it has been discharged. Note that the techniques described herein can be used with different methods for verify / read known in the art. Other read and verify techniques known in the art can also be used.

[0110] Figure 5D Threshold voltage distributions are depicted when each memory cell stores four data bits (which is another example of MLC data). Figure 5D It is possible that there is some overlap between the threshold voltage distributions (data states) SO through S15. The overlap can occur due to factors such as memory cells losing charge (and thus the threshold voltage dropping). Program disturb can inadvertently increase the threshold voltage of a memory cell. Likewise, read disturb can inadvertently increase the threshold voltage of a memory cell. Over time, the location of the threshold voltage distributions can change. This change can increase the bit error rate, increasing the decode time or even making decoding impossible. Changing the read reference voltage can help mitigate such effects. Using ECC during the read process can repair errors and ambiguities. Note that in some embodiments, the threshold voltage distributions of the population of memory cells that store four data bits per memory cell do not overlap and are separated from each other. Figure 5D The threshold voltage distributions of the 3D NAND memory cell of FIG. 1 would include a read reference voltage and a verify reference voltage, as discussed above.

[0111] When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above or a multi-pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) of the 3D NAND memory cell of FIG. 1 corresponds to a predetermined value of a set of data bits. The particular relationship between the data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. Table 3 provides an example of an encoding scheme for an embodiment in which each of the four data bits stored in a memory cell is in a different logical page (referred to as a lower page (LP), a middle page (MP), an upper page (UP), and a top page (TP)).

[0112] Table 3

[0113] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

[0114] Figure 6This is a flowchart describing one implementation of the process for programming memory cells. For the purposes of this document, the terms programming and writing are synonymous. In one example implementation, one or more control circuits discussed above (e.g., system control logic unit 260, column control circuit 210, row control circuit 220) are used to perform operations on memory array 202. Figure 6 The process. In one example implementation, Figure 6 The process is performed by the integrated memory component 207 using one or more control circuits (e.g., system control logic unit 260, column control circuitry 210, row control circuitry 220) controlling the die 211 to program the memory cells on the memory die 201. This process includes multiple loops, each of which includes a programming phase and a verification phase. Figure 6 The process is to achieve full-sequence programming as well as other programming schemes including multi-stage programming. When implementing multi-stage programming, Figure 6 The process is used to implement any / every stage of a multi-stage programming process.

[0115] Typically, during programming operations (via selected data word lines), the programming voltage applied to the control gate is applied as a series of programming voltage pulses. Between the programming voltage pulses is a set of verification pulses (e.g., voltage pulses) used to perform verification. In many implementations, the amplitude of the programming voltage pulses increases by a predetermined step with each successive pulse. Figure 6In step 602, the program voltage signal (Vpgm) is initialized to a starting amplitude (e.g., about 12V to 16V or another suitable level) and a program counter PC maintained by state machine 262 is initialized to 1. In one embodiment, the group of memory cells selected for programming (referred to herein as selected memory cells) are programmed concurrently and are all connected to the same word line (selected word line). There can be other memory cells (unselected memory cells) that are not selected for programming that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be inhibited from programming. In addition, when a memory cell reaches its intended target data state, it will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When the channel has a boosted voltage, the voltage difference between the channel and the word line is not large enough to cause programming. To assist with boosting, in step 604, the control die precharges the channels of the NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In step 606, the NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7 volts to 11 volts) to perform a boosting scheme. A program inhibit voltage is applied to the bit lines coupled to the unselected NAND strings.

[0116] In step 608, a program voltage pulse of the program voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, the corresponding bit line is biased at a program enable voltage. In step 608, the program pulse is applied concurrently to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times, which are considered concurrent. In this way, all memory cells connected to the selected word line will concurrently have their threshold voltages changed, unless they are inhibited from programming.

[0117] In step 610, program verification is performed, which includes testing whether the memory cells being programmed have successfully reached their target data states. Memory cells that have reached their target states are locked from further programming by the control die. Step 610 includes performing verification of the programming by sensing at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltages. In step 610, a memory cell can be locked after it has been verified (by testing of Vt) that the memory cell has reached its target state.

[0118] In one embodiment of step 610, smart verify techniques are used such that the system verifies only a subset of the data states during the programming loops (steps 604-628). For example, a first programming loop includes verifying data state A (see Figure 5C ), depending on the results of the verify operation, a second programming loop can perform verification on data states A and B, depending on the results of the verify operation, a third programming loop can perform verification on data states B and C, and so on.

[0119] In step 616, the number of memory cells that have not reached their respective target threshold voltage distributions is counted. That is, the number of memory cells that have failed to reach their target states to date is counted. This count can be done by state machine 262, memory controller 120, or another circuit. In one embodiment, there is one total count that reflects the total number of memory cells being programmed that have failed the last verify step. In another embodiment, a separate count is kept for each data state.

[0120] In step 617, the system determines whether the verify operation in the most recent execution of step 610 included verifying the last data state (e.g., Figure 5Cthe data state G). If yes, then in step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, then the programming process can stop and a "pass" status is reported in step 614. In this case, enough memory cells were programmed correctly so that a small number of remaining memory cells that have not been fully programmed can be corrected using ECC during a read process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during a read process to allow for future / additional errors. When programming less than all of the memory cells for a page, the predetermined limit can be a fraction (in proportion or not) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Rather, the limit varies based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0121] If it is determined in step 617 that the verify operation in the most recent performance of step 610 did not include verifying the last data state, or if it is determined in step 618 that the number of failed memory cells is not less than the predetermined limit, then in step 619, the data state that will be verified in the next performance of step 610 (in the next program loop) is adjusted in accordance with the intelligent verify scheme discussed above. In step 620, the program counter PC is checked against a program limit value (PL). Examples of program limit values include 6, 12, 16, 19, 20, and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the programming process is considered to have failed, and a failed status is reported in step 624. If the program counter PC is less than the program limit value PL, then the process continues at step 626, during which the program counter PC is incremented by 1 and the program voltage signal Vpgm is incrementally increased to the next amplitude. For example, the next pulse will have an amplitude that is larger than the previous pulse by a step size AVpgm (e.g., a step size of 0.1 volts to 1.0 volt). After step 626, the process continues at step 604, and another program pulse is applied to the selected word line (by controlling the die) so that another program loop (steps 604-626) of the programming process is performed. Figure 6

[0122] In one embodiment, the memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a program data state to an erase data state. For example, the threshold voltage of one or more memory cells is changed from a state P to a state E, from Figure 5A a state E to a state P, from​Figure 5B from state A / B / C to state E, from Figure 5C from state A to G to state Er, or from Figure 5D from state S1 to S15 to state S0. In one embodiment, the control circuit is configured to program the memory cells in a direction from the erased data state toward the highest data state (e.g., from data state Er to data state G) and to erase the memory cells in a direction from the highest data state toward the erased data state (e.g., from data state G to data state Er).

[0123] One technique for erasing memory cells in some memory devices is to bias the p-well (or other type of) substrate to a high voltage to charge the NAND channel. An erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell while the NAND channel is at a high voltage to erase the memory cell. This is referred to herein as p-well erase.

[0124] Another method for erasing memory cells is to generate a gate-induced drain leakage (“GIDL”) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while the NAND string channel potential is maintained to erase the memory cell. This is referred to herein as GIDL erase. Both p-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of the memory cell.

[0125] In one embodiment, the GIDL current is generated by inducing a drain-gate voltage at a GIDL generation transistor (e.g., a transistor connected to SGDT0, SGDT1, SGSB0, and SGSB1). In some embodiments, a select gate (e.g., SGD or SGS) can be used as the GIDL generation transistor. The transistor drain-gate voltage that generates the GIDL current is referred to herein as the GIDL voltage. The GIDL current can be generated when the GIDL generation transistor drain voltage is significantly higher than the GIDL generation transistor control gate voltage. The GIDL current is a result of carrier generation, i.e., the generation of electron-hole pairs due to band-to-band tunneling and / or trap-assisted generation. In one embodiment, the GIDL current can cause one type of carrier (also referred to as charge carrier) (e.g., a hole) to predominantly move into the NAND channel, thereby raising or changing the potential of the channel. The other type of carrier (e.g., an electron) is extracted from the channel by the electric field in the direction of the bit line or in the direction of the source line. During erase, the holes can tunnel from the channel to the charge storage region of the memory cell (e.g., to the charge trapping layer 493) and recombine with electrons there to lower the threshold voltage of the memory cell.

[0126] GIDL current can be generated at either end (or both ends) of a NAND string. A first GIDL voltage can be generated between two terminals of a GIDL generation transistor connected to or near a bit line (e.g., connected to SGDT0, SGDT1) to generate a first GIDL current. A second GIDL voltage can be generated between two terminals of a GIDL generation transistor connected to or near a source line (e.g., SGSB0, SGSB1) to generate a second GIDL current. Erasure based on GIDL current of only one end of a NAND string is referred to as one-sided GIDL erasure. Erasure based on GIDL current of both ends of a NAND string is referred to as two-sided GIDL erasure. The techniques described herein can be used with one-sided GIDL erasure and two-sided GIDL erasure.

[0127] Figure 7 The program signal Vpgm is depicted as a series of program voltage pulses such that one pulse of the program signal Vpgm is applied at each execution of step 608. These program voltage pulses are one example of a program dose applied to the plurality of non-volatile memory cells being programmed. In one embodiment, the voltage magnitude of the program voltage pulses increases by a step size AVpgm from pulse to pulse. In some embodiments, AVpgm can change during the program process. As described below, the system performs program verification between program doses (between or after program voltage pulses) as depicted by steps 610 and 612. Figure 6 Figure 6 Figure 8A Figure 8B Figure 8A An example is illustrated of performing program verification for one verify level, depicting two of the program voltage pulses 702 and 704 of Figure 7 . Between program voltage pulses 702 and 704 is a verify voltage pulse 710. In one embodiment, verify voltage pulse 710 has a magnitude of any of the verify reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG (see Figure 5C ) and represents the system performing program verification (step 610) between program doses (successive iterations of step 608). In some embodiments, between program voltage pulses, the system will perform program-verify for multiple or all data states, while in other embodiments, the system will perform program-verify one data state at a time or for a subset of data states. Figure 8B An example is illustrated of performing program-verify for two verify levels, depicting two of the program voltage pulses 702 and 704 of Figure 7 . Between program voltage pulses 702 and 704 are verify voltage pulses 710 and 712. In one embodiment, verify voltage pulses 710 and 712 are for different data states. ​​​​

[0128] The programming, verify / sense, and erase processes discussed above require the application of various voltages to the word lines of the selected block of memory cells. Figure 9 is a block diagram depicting charge pumps, control gate drivers, a switch network, and word line switches used to apply those voltages to the word lines. Figure 9 A set of charge pumps 902 is shown that provide a plurality of different voltage sources to a plurality of sets of control gate drivers, including a first set of control gate drivers 904, a second set of control gate drivers 906, a third set of control gate drivers 908,... an Xth set of control gate drivers 910. The charge pumps 902 include a plurality of charge pumps that provide different voltages needed to perform memory operations. In some embodiments, the voltage generators can also generate some of the different voltages needed to perform memory operations. In one embodiment, there is a separate set of one or more charge pumps or voltage generators for each voltage needed to be applied to the word lines. In other embodiments, some charge pumps and / or voltage generators can be sources of multiple voltages through the use of voltage dividers or other circuitry. Some embodiments can include only one charge pump or one source of one or more word line voltages.

[0129] In one embodiment, the first set of control gate drivers 904 includes a plurality of control gate drivers for providing the necessary voltages to the data word lines (e.g., Wl - WL161) in order to perform programming, erase, and read. The outputs CGout A of the first set of control gate drivers 904, which include one separate output signal for each control gate driver, are provided (connected) to the switch network 920. The outputs of the switch network 920 are driver lines 980, which are configured to carry one or more word line voltages. The first set of control gate drivers 904 are connected to the data word lines via the switch network 920 and the driver lines 980. In one embodiment, all of the control gate drivers of the first set of control gate drivers 904 have the same structure, receive the same inputs (voltage sources), and provide the same set of voltage outputs.

[0130] In one embodiment, the second set of control gate drivers 906 includes a plurality of control gate drivers for providing the necessary voltages to the dummy word lines in order to perform programming, erase, and read. The outputs CGout B of the second set of control gate drivers 906, which include one separate output signal for each control gate driver, are provided (connected) to the switch network 920. The second set of control gate drivers 906 are connected to the dummy word lines via the switch network 920 and the driver lines 980. In one embodiment, all of the control gate drivers of the second set of control gate drivers 906 have the same structure, receive the same inputs (voltage sources), and provide the same set of voltage outputs.

[0131] In one embodiment, the third set of control gate drivers 908 includes a plurality of control gate drivers for providing the necessary voltages to the select lines (e.g., SGD and SGS) in order to perform programming, erasing, and reading. The outputs CGout C of the third set of control gate drivers 908, which include one separate output signal for each control gate driver, are provided (connected) to the switch network 920. The third set of control gate drivers 908 are connected to the select lines via the switch network 920 and the driver lines 980. In one embodiment, all of the control gate drivers of the third set of control gate drivers 908 have the same structure, receive the same inputs (voltage sources), and provide the same set of voltage outputs.

[0132] Figure 9 Word lines WL0-WL161 for two example blocks (Block A and Block B) are shown. Each word line WL0-WL161 of each block is connected to one of the driver lines 980 via a word line switch (e.g., 940-966). Thus, the word line switches selectively connect the driver lines 980 to the word lines. In one embodiment, each of the word line switches 940-966 is implemented as a transistor. For example, word line WL0 of Block A is connected to the output of word line switch 966, WL159 of Block A is connected to the output of word line switch 964, WL160 of Block A is connected to the output of word line switch 962, WL161 of Block A is connected to the output of word line switch 960, WL0 of Block B is connected to the output of word line switch 946, WL159 of Block B is connected to the output of word line switch 944, WL160 of Block B is connected to the output of word line switch 942, and WL161 of Block 1 is connected to the output of word line transistor 960. The inputs of the word line switches are connected to the driver lines 980, which are the outputs of the switch network 920. In one embodiment, the switch network 920 includes a plurality of high voltage switches (e.g., transistors) to connect the control gate drivers to the appropriate word line switches transistors 940-966 by routing the output voltages from the control gate drivers to the appropriate word line switches connected to the word lines WL0-WL161 of each block. Note that in some embodiments, multiple word lines can share a single control gate driver. The switch network is also connected to the select lines SGS and SGD (to enable the selection of the appropriate word line for a given block) and the control gate lines CG1-CG8 (to enable the selection of the appropriate control gate driver for a given block). Figure 9 For easier reading, they are omitted from Figure 9 .

[0133] Figure 9A voltage control circuit 903 is also depicted, which is connected to the charge pump 902 (via signal 905), the voltage control circuit 903 controlling the output of the charge pump 902. In one embodiment, the voltage control circuit 903 receives a digital signal from a state machine or other processor indicating a desired charge pump output, and the voltage control circuit 903 includes a digital-to-analog conversion circuit that outputs a signal 905 to the charge pump 902, the output signal indicating a requested voltage signal to be output by the charge pump.

[0134] There is a trend to increase the density of non-volatile memory. This includes implementing more non-volatile memory cells in the memory array 202. One means for including more non-volatile memory cells in the memory array 202 is to implement additional levels of three-dimensional memory. For example, Figure 4C One hundred sixty-one word lines are shown stacked vertically. To include more non-volatile memory cells in the memory array 202, the memory can be implemented with more than 161 word lines stacked vertically. Adding additional word lines will require adding additional word line switches. Word line switches are traditionally implemented on the substrate of a die; for example, as part of the row control circuit 220 or power control 264 on the memory die 200 (see Figure 2A ) or the control die 211 (see Figure 2B ). Thus, adding more word line switches will take up more space on the substrate of the die, possibly requiring a larger die. However, since users want smaller electronic devices, there is a trend to use smaller or the same size dies. To add more word line switches without increasing the size of the die, it is proposed to stack the word line switches vertically, such that the word line switches take up less space on the die. Thus, the word line switches are arranged in multiple three-dimensional stacks, where each stack of the multiple three-dimensional stacks includes a plurality of word line switches stacked vertically. Such an arrangement is depicted in Figure 10 .

[0135] Figure 10 is a cross-sectional view of one embodiment of a three-dimensional stack 802 of word line switches. The number of word line switches in the stack can vary. For example purposes only, the three-dimensional stack 802 of word line switches includes four word line switches 804, 806, 808, and 810, which can be used to implement Figure 9any of the word line switches 940-966. The three-dimensional stack 802 of word line switches is surrounded by oxide (e.g., Si02) 812. At the center of the stack 802 of word line switches is a center tower of gate material 814 that includes multiple gates (for different word line switches of the stack) that are mechanically and electrically connected together. The center tower of gate material 814 contains metal. Various different metals can be used. A non-exhaustive set of examples of suitable metals for the center tower of gate material 814 includes tungsten and copper. The center tower of gate material 814 is patterned into multiple gate regions to form a gate for each of the word line switches 804, 806, 808, and 810 of the stack 802. For example, regions 816 and 818 of the gate material 814 form a gate for the word line switch 810; regions 818 and 820 of the gate material 814 form a gate for the word line switch 808; regions 820 and 822 of the gate material 814 form a gate for the word line switch 806; and regions 822 and 824 of the gate material 814 form a gate for the word line switch 804. In this way, each of the multiple three-dimensional stacks includes multiple word line switches that are vertically stacked and electrically connected together.

[0136] Each word line switch of the stack 902 includes a gate, a source connected to one of the driver lines (e.g., driver lines 980 of FIG. 9), and a drain connected to one of the word lines (e.g., word lines 920-936 of FIG. 9). Figure 9 Figure 9 ​the drain of one of the word lines 940-966. For example, the word line switch 804 includes: a gate formed by regions 822 and 824; a drain 830 (e.g., tungsten or other suitable metal); a lightly doped drain 832 (e.g., silicon that has been lightly doped, unlike the channel, to ensure high voltage operation); a channel 834 (e.g., silicon); a gate oxide 836 (formed as part of the oxide 814); a lightly doped drain 840 and a source 842 (e.g., tungsten or other suitable metal). The word line switch 806 includes: a gate formed by regions 820 and 822; a drain 844 (e.g., tungsten or other suitable metal); a lightly doped drain 846 (e.g., silicon that has been lightly doped, unlike the channel, to ensure high voltage operation); a channel 848 (e.g., silicon); a gate oxide 836 (formed as part of the oxide 814); a lightly doped drain 852 and a source 854 (e.g., tungsten or other suitable metal). The word line switch 808 includes: a gate formed by regions 818 and 820; a drain 856 (e.g., tungsten or other suitable metal); a lightly doped drain 860 (e.g., silicon that has been lightly doped, unlike the channel, to ensure high voltage operation); a channel 858 (e.g., silicon); a gate oxide 836 (formed as part of the oxide 814); a lightly doped drain 864 and a source 866 (e.g., tungsten or other suitable metal). The word line switch 810 includes: a gate formed by regions 816 and 818; a drain 868 (e.g., tungsten or other suitable metal); a lightly doped drain 870 (e.g., silicon that has been lightly doped, unlike the channel, to ensure high voltage operation); a channel 872 (e.g., silicon); a gate oxide 836 (formed as part of the oxide 814); a lightly doped drain 876 and a source 880 (e.g., tungsten or other suitable metal). Between the source layers and between the drain layers are dielectric regions 826 (e.g., Si02). Figure 10 Also shown are columnar structures 882 and 884 (partially obscured) that extend from above the stack 802 and through the stack 802 to the bottom of the stack 802 in order to mechanically hold and support the stack 802 so that it does not collapse when portions of the stack are removed during fabrication.

[0137] As mentioned above, each word line switch of the stack 902 includes a source connected to one of the drivers and a drain connected to one of the word lines. In this regard, Figure 10Connection lines 890-897 are shown. Connection line 890 connects source region 842 to a driver line, connection line 892 connects source region 854 to a driver line, connection line 894 connects source region 866 to a driver line, connection line 896 connects source region 880 to a driver line, connection line 891 connects drain region 830 to a word line, connection line 893 connects drain region 844 to a word line, connection line 895 connects drain region 856 to a word line, and connection line 897 connects drain region 868 to a word line.

[0138] As can be seen from Figure 10 It can be seen that stack 802 has a profile that tapers toward the top of the respective stack. That is, the plurality of word line switches (804, 806, 808, 810) of stack 802 differ in horizontal width such that lower word line switches are wider than upper word line switches, forming a stepped profile in cross-section. For example, word line switch 808 is wider than word line switch 810, word line switch 806 is wider than word line switch 808, and word line switch 804 is wider than word line switch 806. In other words, the plurality of word line switches of stack 802 differ in horizontal width such that a word line switch protrudes in a first direction from one or more word line switches above to connect to one of the word lines, and protrudes in a second direction from one or more word line switches above to connect to one of the driver lines (e.g., word line switch 804 protrudes from word line switch 806, word line switch 806 protrudes from word line switch 808, and word line switch 808 protrudes from word line switch 810).

[0139] Figure 11 is a close-up cross-sectional view of word line switch 806, showing the gate formed by regions 820 and 822, drain 844, lightly doped drain 846, channel 848, gate oxide 836, lightly doped drain 852, and source 854. Each word line switch includes a gate (e.g., formed by the combination of regions 820 and 822) that surrounds a channel (e.g., channel 848), e.g., on at least four sides of the channel. In one example, the height of the gate and the height of the word line switch is 154 nm (see arrow 1102). In one embodiment, the height of drain 844, lightly doped drain 846, channel 848, lightly doped drain 852, and source 854 is 50 nm (see arrow 1104). The gate includes a center portion 860 that protrudes through the channel 848. This can also be seen in Figure 12B Figure 12B is a top view of channel 848, with the center portion 860 of the gate protruding through a hole in channel 848. Figure 12A ​is a perspective view of a portion of word line switch 806 showing a portion of gate (G) 820, lightly doped drain 846, and lightly doped drain 852. Note that the hole in channel 848 and the center portion of gate 860 are not visible.

[0140] Figure 13 is a top view of one embodiment of a three-dimensional stack of word line switches. In some embodiments, a memory system will include many word line switches arranged into multiple three-dimensional stacks, such that each stack of the multiple three-dimensional stacks includes a vertically stacked plurality of word line switches. Figure 13 Three stacks of word line switches 802, 1302, and 1304 are shown adjacent to a block 1312 of non-volatile memory cells that are part of memory array 202. In various embodiments, stacks of word line switches can be on the same die as the memory cells or on a different die, and stacks of word line switches can be adjacent to memory array 202, under memory array 202, or in another location. Figure 13 Regions are shown that implement a stepped profile on the drain side and a stepped profile on the source side. Between stacks 802, 1302, and 1304 are dielectric regions 1306, 1308, and 1310 that electrically separate these stacks. Figure 13 The tops of connection lines 890, 891, 892, 893, 894, 895, 896, and 897 are shown. Figure 13 The tops of columnar structures 882 and 884 are also shown. In Figure 10 , columnar structures 882 and 884 are each depicted as one column to keep the drawing simple. However, in some embodiments, columnar structures 882 and 884 each include nine columns, as Figure 13 is depicted in Figure 13 . Eight columns made of SiO2(e.g., columns 1320, 1322, 1324, 1326, 1328, and 1330) are also shown that surround each of connection lines 890, 891, 892, 893, 894, 895, 896, and 897.

[0141] Figure 14 is a flowchart that describes one embodiment of a process for making a stack of word line switches that includes Figure 10 structures. Figure 14Step 1402 of the process 1400 includes creating a stack of alternating layers of material and one or more support structures through the layers to mechanically hold the stack so that the stack does not collapse when portions of the stack are removed. Step 1404 includes adding source regions and drain regions at multiple levels of the stack. Step 1406 includes adding gate layers connected to each other at multiple levels of the stack to form wordline switches at multiple levels of the stack. Step 1408 includes connecting the source regions and drain regions at multiple levels of the stack to one or more sources of wordline and wordline voltage.

[0142] Figure 15 is a flowchart describing one embodiment of a process for making a stack of wordline switches for a structure including Figure 10 is a flowchart describing one embodiment of a process for making a stack of wordline switches for a structure including Figure 15 is an example implementation of the process of Figure 14 is an example implementation of the process of Figures 16 to 28 depicts one embodiment of a three-dimensional stack of wordline switches during the fabrication process of Figure 15 is a cross-section of the stack of is a cross-section of the stack of

[0143] is a cross-section of the stack of Figure 15 Step 1502 of the process 1500 includes creating a stack of alternating layers of Si and SiGe. Figure 16 depicts the stack after step 1502 and shows alternating layers of Si (1606) and SiGe (1608) under an oxide top layer 1604 (e.g., SiO2) and over a wafer 1602.

[0144] Step 1504 includes creating columnar structures to mechanically hold the stack so that the stack does not collapse when portions of the stack are removed. In one embodiment, step 1504 includes performing a dry etch to create holes and then filling with SiO2. Figure 17A and Figure 17B depicts the stack after step 1502 and shows columnar structures 882 and 884 through the alternating layers of Si (1606) and SiGe (1608) in the stack. Figure 17A and Figure 17B shows the stack at different cross-sections so that Figure 17B is a cross-section of the stack of Figure 17B is a cross-section of the stack of Figure 14 are example implementations of step 1402 of the process of

[0145] Step 1506 includes creating a recess in the SiGe layers of the stack. In one embodiment, step 1506 includes performing a selective ion etch. Figure 18 depicts the stack after step 1506 and shows a recess 1802.

[0146] Step 1508 includes lining the recess with doped Si. In one embodiment, step 1508 includes performing chemical vapor deposition (“CVD”) or atomic layer deposition (“ALD”) to add doped silicon. Figure 19 The stack after step 1508 is depicted, and shows the doped Si liner 1902.

[0147] Step 1510 includes annealing and diffusing the dopant of the doped Si liner 1902. Figure 20 The stack after step 1510 is depicted, and shows that the outer portion that was previously the Si layer 1606 is now a lightly doped region 2002.

[0148] Step 1512 includes creating a recess in the doped Si. For example, a dry etch is used to remove a portion of the liner 1902 and the lightly doped region 2002. Figure 21 The stack after step 1512 is depicted.

[0149] Step 1514 includes filling the recess with a dielectric material. In one embodiment, SiO2 is added to the recess using conformal CVD. Figure 22 The stack after step 1514 is depicted, and shows the dielectric region 826 added during step 1514. In one embodiment, the dielectric region 826 and the oxide top layer 1604 have different densities.

[0150] Step 1516 includes creating a stepped profile in the cross-section. In one embodiment, a dry etch process is used to etch away portions of the lightly doped region 2002 and the dielectric region 826 to create a step. Figure 23 The stack after step 1516 is depicted, and shows the lightly doped region 2002 and the dielectric region 826 etched to form a step.

[0151] Step 1518 includes replacing a portion of the doped Si with tungsten. In one embodiment, a wet etch process is used to remove the lightly doped region 2002, and CVD or physical vapor deposition (“PVD”) is used to add tungsten to replace the lightly doped region 2002. Figure 24 The stack after step 1518 is depicted, and shows the addition of tungsten regions 830, 844, 856, and 868 that serve as drains, and tungsten regions 842, 854, 866, and 880 that serve as sources. Steps 1506-1518 are Figure 14 example implementations of step 1404.

[0152] Step 1520 includes creating slots in the gate region and depositing oxide. In one embodiment, holes are drilled through the stack, and oxide is deposited on the stack. Figure 25The stack after step 1520 is depicted and shows the hole 2502. Figure 25 The oxide 812 deposited on the stack is also shown. Note that in one embodiment, the oxide 812 has a different density than the pillars 882 / 884.

[0153] Step 1522 includes removing the Si in the slot and lining with oxide. Figure 26 The stack after step 1522 is depicted and shows that the region 2602 of the Si layer 1606 has been removed around the hole 2503 and filled with oxide (oxide deposition).

[0154] Step 1524 includes replacing the SiGe with a metal gate material and depositing a liner oxide. This step forms the connection gate for the word line switch of the stack. Figure 27 The stack after step 1524 is depicted and shows the center tower of gate material 814 with a liner 2702 of oxide around the center tower of gate material 814. Steps 1520-1524 are an example implementation of step 1406. Figure 14

[0155] Step 1526 includes adding signal lines to the source and drain of each level of the stack. Figure 27 The stack after step 1524 is depicted and shows the addition of connection lines 890, 891, 892, 893, 894, 895, 896, and 897. Step 1526 is an example implementation of step 1408. Figure 14

[0156] A non-volatile memory system has been proposed that more efficiently utilizes space by stacking word line switch transistors.

[0157] One embodiment includes a non-volatile memory device, comprising: a plurality of non-volatile memory cells; a plurality of word lines connected to the non-volatile memory cells; a plurality of driver lines configured to carry one or more word line voltages; and a plurality of word line switches selectively connecting the driver lines to the word lines, the word line switches arranged in a plurality of three-dimensional stacks, each stack of the plurality of three-dimensional stacks comprising a plurality of word line switches vertically stacked and electrically connected together.

[0158] In one example implementation, each word line switch includes a gate, a source connected to one of the driver lines, and a drain connected to one of the word lines.

[0159] In one example implementation, each stack of the plurality of three-dimensional stacks comprises a plurality of word line switches vertically stacked and electrically connected together. ​​

[0160] In one example implementation, each stack of the plurality of three-dimensional stacks includes a plurality of word line switches that are vertically stacked and have gates mechanically and electrically connected together.

[0161] In one example implementation, each stack of the plurality of three-dimensional stacks includes a plurality of word line switches that are vertically stacked and have gates mechanically and electrically connected together.

[0162] In one example implementation, each stack of the plurality of stacks has a profile that tapers toward a top of the respective stack.

[0163] In one example implementation, the plurality of word line switches of a stack differ in horizontal width such that lower word line switches are wider than upper word line switches.

[0164] In one example implementation, the plurality of word line switches of a stack differ in horizontal width, forming a stepped profile in cross-section.

[0165] In one example implementation, the plurality of word line switches of a stack differ in horizontal width such that word line switches protrude from one or more word line switches above in a first direction to connect to one of the word lines and protrude from one or more word line switches above in a second direction to connect to one of the driver lines.

[0166] In one example implementation, each word line switch includes a gate that surrounds a channel.

[0167] In one example implementation, each word line switch includes a gate, a source, a drain, and a channel; and the gate surrounds the channel on at least four sides of the channel.

[0168] In one example implementation, each word line switch includes a gate and a channel; and the gate protrudes through the channel.

[0169] One example implementation also includes one or more sources of word line voltage connected to the plurality of driver lines.

[0170] In one example implementation, the plurality of non-volatile memory cells are arranged into a three-dimensional memory structure having a plurality of levels of non-volatile memory cells above one or more other levels of non-volatile memory cells.

[0171] In one example implementation, the plurality of non-volatile memory cells are arranged into a three-dimensional memory structure including vertical NAND strings.

[0172] One embodiment includes a non-volatile memory device comprising: a block of non-volatile memory cells arranged into a three-dimensional memory structure having a plurality of levels of non-volatile memory cells above other levels of non-volatile memory cells; a plurality of word lines connected to the non-volatile memory cells of the block; one or more sources of word line voltage; and a plurality of word line switches for the block that selectively connect the one or more sources of word line voltage to the word lines, the word line switches arranged into three-dimensional stacks, each stack comprising a vertically stacked plurality of word line switches.

[0173] One embodiment includes a method comprising: generating a stack of alternating layers of material and support structures through the layers to mechanically hold the stack such that the stack does not collapse when portions of the stack are removed; adding source regions and drain regions at a plurality of levels of the stack; adding gate layers connected to each other at a plurality of levels of the stack to form word line switches at the plurality of levels of the stack; and connecting the source regions and the drain regions at a plurality of levels of the stack to word lines and one or more sources of word line voltage.

[0174] In one example implementation, generating the stack of alternating layers of material and support structures comprises: generating a stack of alternating layers of Si and SiGe; and generating columnar structures to mechanically hold the stack such that the stack does not collapse when portions of the stack are removed.

[0175] In one example implementation, adding source regions and drain regions at a plurality of levels of the stack comprises: generating recesses in the SiGe layers of the stack; lining the recesses with doped Si; annealing and diffusing dopants; generating recesses in the doped Si; filling the recesses with a dielectric material; generating a staircase profile in cross-section; and replacing a portion of the doped Si with tungsten.

[0176] In one example implementation, adding gate layers comprises: generating slots in gate regions and depositing oxide; removing Si in the slots and lining with oxide; and replacing SiGe with metal gate material and depositing liner oxide.

[0177] For purposes of this document, reference to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” can mean different embodiments or the same embodiment.

[0178] For purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element can be directly connected or coupled to the other element or connected or coupled to the other element via one or more intervening elements. When an element is referred to as being directly connected or directly coupled to another element, then, in that instance, there are no intervening elements. If two devices are connected, they are either directly or indirectly connected such that an electronic signal can be communicated between them.

[0179] For purposes of this document, the term “based on” can be understood as “based at least in part on.”

[0180] For purposes of this document, the use of the term “about” in conjunction with a numerical value or a range of values can be understood as “substantially around” or “substantially approximately.”

[0181] For purposes of this document, the term “set” of objects can refer to one or more “sets” of objects.

[0182] The preceding detailed description has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best illustrate the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the technology be defined by the claims appended hereto.

Claims

1. A non-volatile memory device, comprising: a plurality of non-volatile memory cells; a plurality of word lines connected to the non-volatile memory cells; a plurality of driver lines configured to carry one or more word line voltages; and a plurality of word line switches selectively connecting the driver lines to the word lines, the word line switches arranged in a plurality of three-dimensional stacks, each stack of the plurality of three-dimensional stacks comprising a plurality of word line switches vertically stacked.

2. The non-volatile memory device of claim 1, wherein: each word line switch comprises a gate, a source connected to one of the driver lines, and a drain connected to one of the word lines.

3. The non-volatile memory device of claim 1, wherein: each stack of the plurality of three-dimensional stacks comprises a plurality of word line switches vertically stacked and electrically connected together.

4. The non-volatile memory device of claim 1, wherein: each stack of the plurality of three-dimensional stacks comprises a plurality of word line switches vertically stacked and having gates electrically connected together.

5. The non-volatile memory device of claim 1, wherein: each stack of the plurality of three-dimensional stacks comprises a plurality of word line switches vertically stacked and a center tower of gate material electrically connected to the gate of each word line switch of the respective stack.

6. The non-volatile memory device of claim 1, wherein: each stack of the plurality of stacks has a profile that tapers toward a top of the respective stack.

7. The non-volatile memory device of claim 1, wherein: the plurality of word line switches of a stack differ in horizontal width such that lower word line switches are wider than upper word line switches.

8. The non-volatile memory device of claim 1, wherein: the plurality of word line switches of a stack differ in horizontal width forming a stepped profile in cross-section.

9. The non-volatile memory device of claim 1, wherein: the plurality of word line switches of a stack differ in horizontal width such that a word line switch protrudes from one or more word line switches above in a first direction to connect to one of the word lines and protrudes from one or more word line switches above in a second direction to connect to one of the driver lines.

10. The non-volatile memory device of claim 1, wherein: each word line switch comprises a gate surrounding a channel.

11. The non-volatile memory device of claim 1, wherein: each word line switch comprises a gate, a source, a drain, and a channel; and the gate surrounds the channel on at least four sides of the channel.

12. The non-volatile memory device of claim 1, wherein: each word line switch comprises a gate and a channel; and the gate protrudes through the channel.

13. The non-volatile memory device of claim 1, further comprising: ​ One or more sources of word line voltage, the one or more sources of word line voltage connected to the plurality of driver lines.

14. The non-volatile memory device of claim 1, wherein: the plurality of non-volatile memory cells are arranged into a three-dimensional memory structure, the three-dimensional memory structure having a plurality of levels of non-volatile memory cells above one or more other levels of non-volatile memory cells.

15. The non-volatile memory device of claim 1, wherein: the plurality of non-volatile memory cells are arranged into a three-dimensional memory structure comprising vertical NAND strings.

16. A non-volatile memory device, the non-volatile memory device comprising: a block of non-volatile memory cells arranged into a three-dimensional memory structure, the three-dimensional memory structure having a plurality of levels of non-volatile memory cells above other levels of non-volatile memory cells; a plurality of word lines connected to the non-volatile memory cells of the block; one or more sources of word line voltage; and a plurality of word line switches for the block, the plurality of word line switches selectively connecting the one or more sources of word line voltage to the word lines, the word line switches arranged into a three-dimensional stack, each stack comprising a plurality of word line switches stacked vertically.

17. A method, the method comprising: generating a stack of alternating layers of material and support structures through the layers to mechanically hold the stack such that the stack does not collapse when portions of the stack are removed; adding source regions and drain regions at a plurality of levels of the stack; adding gate layers connected to each other at a plurality of levels of the stack to form word line switches at the plurality of levels of the stack; and connecting the source regions and the drain regions at a plurality of levels of the stack to a word line and one or more sources of word line voltage.

18. The method of claim 17, wherein generating the stack of alternating layers of material and support structures comprises: generating a stack of alternating layers of Si and SiGe; and generating columnar structures to mechanically hold the stack such that the stack does not collapse when portions of the stack are removed.

19. The method of claim 17, wherein adding source regions and drain regions at a plurality of levels of the stack comprises: generating a recess in the SiGe layers of the stack; lining the recess with doped Si; annealing and diffusing dopants; generating a recess in the doped Si; filling the recess with a dielectric material; generating a staircase profile in cross-section; and replacing a portion of doped Si with tungsten.

20. The method of claim 17, wherein adding gate layers comprises: generating slots in gate regions and depositing an oxide; removing Si in the slots and lining with an oxide; and replacing SiGe with a metal gate material and depositing a liner oxide.

Images