IGBT fault identification and positioning method, system and device

Abstract

The invention belongs to the field of IGBT fault identification, and particularly relates to an IGBT fault identification and positioning method, system and device and a storage medium, and the method comprises the steps: carrying out the cross-correlation operation of a detection signal and an observation signal, obtaining a first time delay, carrying out the cross-correlation operation of the detection signal and a mixed reflection signal, obtaining a second time delay, and obtaining a second time delay; calculating according to the first time delay and the second time delay to obtain an initial time delay, then obtaining a reflection superposition signal according to the reflection signal and the mixed reflection signal, obtaining a time delay matrix by combining the reflection times, obtaining a coefficient matrix according to the signal constraint and the time delay matrix, and solving the coefficient matrix; and obtaining the coefficient and the time delay of the first reflection signal, and determining whether the IGBT has a fault or not and the fault position. According to the invention, the principal component extraction is carried out on the complex reflection waveform, the synchronous recognition of the spatial position and impedance characteristics of the device is realized, and the problems of positioning errors and impedance extraction blind areas caused by short-line multi-reflection superposition are solved.

Description

Technical Field

[0001] This invention belongs to the field of IGBT fault identification, specifically relating to a method, system, and device for IGBT fault identification and location. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are key components in high-voltage, high-capacity power electronic converters, and their operational reliability plays a decisive role in the performance and stability of the entire power electronic system. Because IGBTs operate in high-power, high-voltage environments, they are susceptible to multiple stresses simultaneously, including thermal, mechanical, and electrical stresses. Therefore, common fault types include short circuits, open circuits, and thermal failures. These faults not only severely reduce system efficiency and safety but can also lead to irreversible device damage or complete system failure. When monitoring and diagnosing the health status of IGBTs, the device's "equivalent impedance" is often considered an important indicator for judging the degree of fault and aging.

[0003] In related technologies, the reflection method diagnoses faults in a system by evaluating the characteristics of reflected signals from abnormal points and comparing them with the original detection signal. It is an effective fault detection method that can be used for remote detection, location, and characterization of the features of a live system under test. Among these, STDR / SSTDR signals are approximately white noise, possessing strong anti-interference capabilities. They can achieve high-precision online fault detection in complex circuit topologies without interfering with the original circuit's operating signals.

[0004] Regarding the aforementioned technologies, the relatively short line length of power electronic circuits makes the reflected signal at the receiving end more susceptible to signal aliasing due to multipath effects. Multipath echoes are highly superimposed on the time axis, resulting in multiple reflection components with similar phases but different amplitudes within the same measurement window. These reflection components interfere with each other during cross-correlation calculations, potentially causing a shift or even blurring of the target reflection peak position, creating a detection blind zone where impedance characteristic values ​​are difficult to extract. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method, system and device for fault identification and location of IGBTs, and to solve the problem of location error and impedance extraction blind zone caused by multiple reflections superimposed on short wires.

[0006] A fault identification method for IGBTs includes:

[0007] Acquire detection signals and observation signals. The observation signal is the signal obtained after the detection signal is input into the IGBT through the transmission line, and the reflected signal is the signal collected at the input point of the observation signal after the observation signal is transmitted to the IGBT.

[0008] Perform cross-correlation calculation on the detected signal and the observed signal, and extract the first time delay corresponding to the cross-correlation peak value;

[0009] The detection signal is filtered out from the observed signal to obtain the mixed reflection signal;

[0010] The detection signal and the mixed reflection signal are cross-correlated, and the second time delay corresponding to the correlation peak is extracted. The initial time delay is calculated based on the first time delay and the second time delay.

[0011] Obtain the i-th reflection signal and signal constraints;

[0012] Based on the i-th reflection signal and the mixed reflection signal, the superimposed reflection signal is obtained;

[0013] Set the number of reflections;

[0014] The time delay matrix is ​​obtained based on the number of reflections and the superimposed reflected signals;

[0015] Based on the signal constraints and the time delay matrix, the coefficient matrix is ​​obtained;

[0016] Solving the coefficient matrix yields the coefficients and time delay of the first reflected signal;

[0017] Based on the coefficients and time delay of the first reflected signal, determine whether the IGBT has malfunctioned and the location of the malfunction.

[0018] Optionally, the step of performing cross-correlation calculation on the detected signal and the observed signal, and extracting the first time delay corresponding to the cross-correlation peak value includes:

[0019] The detected signal and the observed signal are cross-correlated to obtain the cross-correlation waveform, which is represented as follows:

[0020]

[0021] Where T is the period, τ is the time for one round trip of the signal, and S in (t) is the detection signal, S obs (t) represents the observed signal;

[0022] In the cross-correlation waveform, the horizontal coordinate value corresponding to the cross-correlation peak is used as the first time delay.

[0023] Optionally, the step of filtering out the detection signal from the observed signal to obtain the mixed reflection signal is represented as follows:

[0024]

[0025] Among them, S in (t) is the detection signal, S obs(t) represents the observed signal, ρ A Let F be the transmission coefficient at point A. i (t) represents the i-th reflected signal, N represents the number of signal reflections, and point A is the point where the detection signal is injected.

[0026] Optionally, the step of performing cross-correlation operation on the detected signal and the mixed reflected signal, extracting the second time delay corresponding to the correlation peak, and calculating the initial time delay based on the first time delay and the second time delay includes:

[0027] The cross-correlation operation between the detected signal and the mixed reflected signal yields a mixed waveform, represented as follows:

[0028]

[0029] Based on the mixed waveform, the horizontal coordinate value corresponding to the maximum correlation peak is obtained as the second time delay;

[0030] The initial delay is calculated based on the first delay and the second delay, and is expressed as follows:

[0031] τ0=τ SF -τ SS

[0032] Where τ0 is the initial time delay, τ SF For the second time delay, τ SS This is the first time delay.

[0033] Optionally, the i-th reflected signal is represented as:

[0034] F i (t)=a i ·S in (ti·τ1)

[0035] Among them, F i (t) is the reflected signal, a i S is the reflection signal coefficient. in (t) is the detection signal, τ1=τ0+y is the time for the signal to travel back and forth once, and y is the correction amount.

[0036] Optionally, the superimposed reflection signal obtained from the i-th reflection signal and the mixed reflection signal is represented as follows:

[0037]

[0038] Among them, F A (t) represents the reflected superimposed signal, ρ A Let a be the transmission coefficient at point A. i S is the reflection signal coefficient. in(t) represents the detection signal, τ1 = τ0 + y represents the time it takes for the signal to travel back and forth once, y represents the correction amount, and N represents the number of signal reflections.

[0039] Optionally, determining whether the IGBT has malfunctioned and its location as the identification result based on the coefficients and time delay of the first reflected signal includes:

[0040] The coefficient of the first reflected signal is used as a characteristic impedance index;

[0041] If the characteristic impedance index is greater than a preset threshold, then the IGBT is determined to be faulty.

[0042] If the characteristic impedance index is less than or equal to a preset threshold, then it is determined that the IGBT has not failed.

[0043] Based on the time delay and signal propagation speed of the first reflected signal, the fault location is calculated, and whether the IGBT has failed and the fault location are used as the identification results.

[0044] A method for fault identification and localization of IGBTs, comprising:

[0045] The first acquisition module is used to acquire detection signals and observation signals. The observation signal is the signal acquired after the detection signal is input into the IGBT through the transmission line, and the reflected signal is the signal collected at the input point of the observation signal after the observation signal is transmitted to the IGBT and then returns.

[0046] The first calculation module is used to perform cross-correlation operation on the detected signal and the observed signal, and extract the first time delay corresponding to the cross-correlation peak value;

[0047] The filtering module is used to filter out the detection signal from the observed signal to obtain the mixed reflection signal;

[0048] The second calculation module is used to perform cross-correlation operation on the detected signal and the mixed reflection signal, extract the second time delay corresponding to the correlation peak, and calculate the initial time delay based on the first time delay and the second time delay;

[0049] The second acquisition module is used to acquire the i-th reflection signal and signal constraints;

[0050] The superposition module is used to obtain the superimposed reflection signal based on the i-th reflection signal and the mixed reflection signal;

[0051] The settings module is used to set the number of reflections;

[0052] The third calculation module is used to obtain the time delay matrix based on the number of reflections and the superimposed reflected signals;

[0053] The fourth calculation module is used to obtain the coefficient matrix based on the signal constraints and the time delay matrix;

[0054] The solution module is used to solve the coefficient matrix to obtain the coefficients and time delay of the first reflected signal;

[0055] The judgment module is used to determine whether the IGBT has failed and the location of the failure based on the coefficient and time delay of the first reflected signal.

[0056] A terminal device includes a memory and a processor. The memory stores a computer program that can run on the processor. When the processor loads and executes the computer program, it employs a fault identification and location method for IGBTs.

[0057] A computer-readable storage medium storing a computer program, which, when loaded and executed by a processor, employs a method for fault identification and location of an IGBT.

[0058] The beneficial effects of this invention are:

[0059] First, the detected signal and the observed signal are cross-correlated to obtain the first time delay. Then, the detected signal and the mixed reflected signal are cross-correlated to obtain the second time delay. The initial time delay is calculated based on the first and second time delays for coarse positioning. Next, the superimposed reflected signal is obtained from the reflected signal and the mixed reflected signal, and the time delay matrix is ​​obtained by combining the number of reflections. Based on signal constraints and the time delay matrix, the coefficient matrix is ​​obtained. Solving the coefficient matrix yields the coefficients and time delay of the first reflected signal. Based on the coefficients and time delay of the first reflected signal, it is determined whether the IGBT has failed and its location. This application extracts the principal components of complex reflected waveforms to achieve synchronous identification of device spatial location and impedance characteristics, solving the positioning error and impedance extraction blind zone problems caused by multiple reflections from short lines. Attached Figure Description

[0060] Figure 1 This is a topology diagram of the IGBT state detection circuit of the present invention;

[0061] Figure 2 This is a flowchart illustrating a fault identification method for IGBTs according to the present invention.

[0062] Figure 3 The fitted waveform F of this invention fit and residual sequence diagram, Figure 3 (a) is the fitted waveform F under SSTDR. fit and residual sequence diagram, Figure 3 (b) is the fitted waveform F under STDR. fit And residual sequence diagram.

[0063] Figure 4 For the performance of the fitting algorithm of the detection signals with different frequencies of the present invention, Figure 4 (a) is a schematic diagram of performance evaluation at 250M, Figure 4 (b) is a schematic diagram of performance evaluation at 10M / 20M;

[0064] Figure 5 is a schematic diagram of the multi-chip parallel structure, Figure 5 (a) is a schematic diagram of the FF450R12ME7 structure, Figure 5 (b) is a multi-chip parallel connection structure diagram.

[0065] Figure 6 is a schematic diagram of the relationship between the capacitance impedance of a 1pF capacitor and frequency;

[0066] Figure 7 is the STDR observation signal and its related waveform diagrams before and after leakage voltage filtering, Figure 7 (a) is a schematic diagram of the observation signal before and after filtering, Figure 7 (b) is a schematic diagram of the cross-correlation waveform before and after filtering;

[0067] Figure 8 is a schematic diagram of the IGBT feature extraction results based on the low-frequency positive-biased STDR / SSTDR detection signals, Figure 8 (a) is the position extraction result, Figure 8 (b) is the impedance feature extraction result.

[0068] Figure 9 is the highly aliased waveform diagram when τ << TS, Figure 9 (a) is the STDR receiver end observation signal and the mixed reflection signal diagram, Figure 9 (b) is the STDR / SSTDR cross-correlation waveform diagram.

[0069] Figure 10 is a schematic diagram of the IGBT position extraction results based on the high-frequency positive-biased STDR / SSTDR detection signals. Specific embodiments

[0070] Specifically, for IGBT fault identification, an IGBT state detection circuit is required. The topology diagram of the IGBT state detection circuit is as Figure 1 shown, and it mainly consists of a test end (including a signal generation module and a signal acquisition module) and a device under test end (including a transmission cable and a device under test). The signal generation module is responsible for generating the STDR (Sequential Time Domain Reflectometry) / SSTDR (Spread Spectrum Time Domain Reflectometry) detection signal S in (t), and injecting it into the circuit under test. This detection signal passes through a characteristic impedance of Z LThe transmission cable transmits the data to the IGBT under test. Due to the characteristic impedance Z of the IGBT... IGBT Incompatible with transmission cable (Z) L =Z IGBT Part of the detection signal will be reflected at the impedance mismatch point, and these reflected signals carry the characteristic impedance information of the reflection point. The reflected signals propagate in the reverse direction along the transmission cable and are eventually captured by the signal acquisition module.

[0071] Figure 1 In the diagram, point A serves as both the injection point for the detection signal and the acquisition point for the reflected signal. The detection signal travels along the characteristic impedance Z. L The characteristic impedance of the transmission cable is Z. DUT The connection point between the signal transmission cable and the device under test (DUT) is denoted as point B. Then, the reflection coefficient and transmission coefficient at point A are constant values.

[0072]

[0073] Among them, Γ A Let ρ be the reflection coefficient at point A. A Z is the transmission coefficient at point A. T Z0 is the impedance when the signal flows through the T-type interface, and Z0 is the characteristic impedance of the cable.

[0074] The reflection coefficient at point B is only related to the characteristic impedance of the device under test:

[0075]

[0076] Among them, Z L =Z0.

[0077] A fault identification method for IGBTs, such as Figure 2 As shown, the present invention includes:

[0078] S1. Acquire detection signals and observation signals. The observation signal is the signal obtained after the detection signal is input into the IGBT through the transmission wire. The reflected signal is the signal collected at the input point of the observation signal after it is transmitted to the IGBT.

[0079] Specifically, the first reflected signal F1(t) received at the signal input terminal and the detection signal S in The relationship between (t) can be expressed as:

[0080] F1(t)=Γ·S in (t-τ0)

[0081] Where τ0 is the incident signal S in The time delay between the reflected signal F1(t) and the reflected signal F1(t) is Γ, where Γ is the emission coefficient.

[0082] Let the characteristic impedance of the transmission line be Z. L When signal S in (t) Through a transmission line of length l and the device under test Z x At this impedance mismatch point, the reflection coefficient Γ is defined as the ratio of the reflected signal to the incident signal, and the transmission coefficient ρ is defined as the ratio of the transmitted signal to the incident signal. According to Kirchhoff's laws, their expressions are as follows:

[0083]

[0084] Among them, V in Indicates signal S in (t) The effective value of the voltage propagating in the forward direction along the transmission line, V ref Indicates signal S in (t) The voltage that returns in the reverse direction along the transmission line after encountering an impedance mismatch point.

[0085] When Z L At a given time, both the reflection coefficient Γ and the transmission coefficient ρ are related to Z. x They are positively correlated. As shown in Fig. 2, when Z... x <Z L When Γ < 0; when Z x >Z L When Γ>0. Furthermore, there are three special cases for different impedances:

[0086] When Z x =Z L At this time, the reflection coefficient Γ = 0, meaning the impedance remains continuous and there is no reflected signal;

[0087] When Z x When Γ = 0, the reflection coefficient Γ = -1, meaning that when the line is short-circuited, the reflected signal and the incident signal have the same amplitude but opposite polarity.

[0088] When Z x When Γ = +∞, the reflection coefficient Γ = 1, meaning that when the line is open, the reflected signal and the incident signal have the same amplitude and polarity.

[0089] S2. Perform cross-correlation calculation on the detected signal and the observed signal, and extract the first time delay corresponding to the cross-correlation peak.

[0090] The detection signal and the observed signal are cross-correlated, and the first time delay corresponding to the cross-correlation peak is extracted, including:

[0091] The cross-correlation operation is performed on the detected signal and the observed signal to obtain the cross-correlation waveform, which is represented as follows:

[0092]

[0093] Where T is the period, τ is the time for one round trip of the signal, and S in (t) is the detection signal, S obs (t) represents the observed signal;

[0094] In the cross-correlation waveform, the horizontal coordinate value corresponding to the cross-correlation peak is used as the first time delay.

[0095] S3. Filter out the detection signal from the observed signal to obtain the mixed reflection signal.

[0096] Specifically, based on the detection circuit structure and the linear superposition formula, the detection signal in the observed signal is filtered out to obtain a relatively pure mixed reflection waveform:

[0097] The formula for linear superposition is:

[0098]

[0099] Among them, F i (t) represents the i-th reflected signal.

[0100] After filtering out the detection signal from the observed signal, the resulting mixed reflection signal is represented as follows:

[0101]

[0102] Among them, S in (t) is the detection signal, S obs (t) represents the observed signal, ρ A Let F be the transmission coefficient at point A. i (t) represents the i-th reflected signal, and N represents the number of signal reflections.

[0103] S4. Perform cross-correlation operation on the detected signal and the mixed reflection signal, and extract the second time delay corresponding to the correlation peak. Calculate the initial time delay based on the first time delay and the second time delay.

[0104] The detected signal and the mixed reflected signal are cross-correlated, and the second time delay corresponding to the correlation peak is extracted. The initial time delay is calculated based on the first and second time delays, including:

[0105] The detected signal and the mixed reflected signal are cross-correlated to obtain the mixed waveform, which is represented as follows:

[0106]

[0107] Based on the mixed waveform, the horizontal coordinate value corresponding to the maximum correlation peak is obtained and used as the second time delay;

[0108] The initial delay is calculated based on the first and second delays and is expressed as follows:

[0109] τ0=τSF -τ SS

[0110] Where τ0 is the initial time delay, τ SF For the second time delay, τ SS This is the first time delay.

[0111] S5. Obtain the i-th reflection signal and signal constraints.

[0112] Specifically, the i-th reflected signal is represented as:

[0113] F i (t)=a i ·S in (ti·τ1)

[0114] Among them, F i (t) is the reflected signal, a i S is the reflection signal coefficient. in (t) is the detection signal, τ1=τ0+y is the time for the signal to travel back and forth once, and y is the correction amount.

[0115] The signal constraint is a constraint on the reflected signal coefficient, expressed as:

[0116]

[0117] Among them, Γ A Let be the reflection coefficient at point A.

[0118] S6. Based on the i-th reflection signal and the mixed reflection signal, obtain the superimposed reflection signal.

[0119] Based on the i-th reflection signal and the mixed reflection signal, the superimposed reflection signal is represented as follows:

[0120]

[0121] Among them, F A (t) represents the reflected superimposed signal, ρ A Let a be the transmission coefficient at point A. i S is the reflection signal coefficient. in (t) represents the detection signal, τ1 = τ0 + y represents the time it takes for the signal to travel back and forth once, y represents the correction amount, and N represents the number of signal reflections.

[0122] S7. Set the number of reflections.

[0123] S8. Based on the number of reflections and the superimposed reflected signals, obtain the time delay matrix.

[0124] Specifically, assuming the signal travels back and forth between A and B m times, the time delay matrix can be obtained as follows:

[0125]

[0126] Where m is the number of reflections.

[0127] S9. Based on the signal constraints and the time delay matrix, the coefficient matrix is ​​obtained.

[0128] Specifically, let b i =ρ A ·a i Then, combining the signal constraints, we can obtain the coefficient matrix and its range of values:

[0129]

[0130] S10. Solve the coefficient matrix to obtain the coefficients and time delay of the first reflected signal.

[0131] Specifically, this is achieved by performing multiple linear regression on multiple reflected waves and solving for the coefficient vector that minimizes the sum of squared residuals.

[0132]

[0133] Provided that the range of values ​​is satisfied, the algorithm uses an iterative search strategy to continuously update the coefficient vector. The time delay τ1 is used until the solution converges to the optimal solution of the residual sum of squares.

[0134] Through the regression analysis described above, the coefficient a1 and time delay τ1 of the first reflected signal can be separated. The coefficient a1 is the reflection coefficient at point B. This algorithm does not rely on fixed IGBT test platform parameters. Under certain prior measurement conditions, it can also be applied to other signal aliasing dead zones to extract the effective features of the DUT and directly use them as the characteristic impedance index of the IGBT under test.

[0135] This algorithm does not rely on fixed IGBT test platform parameters. Under certain prior measurement conditions, it can also be applied to extract effective features of the DUT in other signal aliasing dead zones.

[0136] S11. Based on the coefficient and time delay of the first reflected signal, determine whether the IGBT has failed and the location of the failure.

[0137] Based on the coefficients and time delay of the first reflected signal, determine whether the IGBT has failed and the location of the fault, including:

[0138] The coefficient of the first reflected signal is used as the characteristic impedance index;

[0139] If the characteristic impedance index is greater than the preset threshold, it is determined that the IGBT has failed.

[0140] If the characteristic impedance is less than or equal to a preset threshold, then the IGBT is determined not to be faulty.

[0141] The fault location is calculated based on the time delay of the first reflected signal and the signal propagation speed.

[0142] Specifically, the fault location is calculated as follows:

[0143]

[0144] Among them, v S This refers to the speed of signal propagation.

[0145] Experimental verification:

[0146] The main experimental equipment models and experimental parameter settings are shown in Table 1.

[0147] Table 1

[0148]

[0149] The signal generator outputs two synchronous STDR / SSTDR signals: one is used as a detection signal, which is injected into the CE terminal of the IGBT via a coaxial cable; the other is used as a reference signal, which is synchronously recorded by the signal acquisition module.

[0150] Based on the fitting algorithm proposed in this paper, the best-fit waveform Ffit and its residual sequence diagram (F-Ffit) of the STDR / SSTDR signal in the on-state of the medium-power IGBT device (FF450R12ME7) are shown as follows. Figure 3 As shown in the figure. Experimental results show that the residual amplitude under SSTDR signal is smaller, the fluctuation is more stable, and the fitting curve has a higher degree of overlap with the original reflection signal.

[0151] To quantitatively evaluate the performance of the fitting algorithm, this paper introduces the following two evaluation metrics:

[0152] 1) Coefficient of determination R 2 :

[0153]

[0154] Where y is the actual observed value, y' is the fitted value, and y mean R is the mean of the observed values. 2 Used to measure the ability of the fitting result to explain the variance of the original signal, with a value range of (-∞, 1). When R 2 When R approaches 1, it indicates that the fitted model fits the observed data well; if R... 2 If the value is less than 0, it indicates that the fit is worse than that of the simple average estimate.

[0155] 2) Mean Square Error (MSE):

[0156]

[0157] Mean squared error (MSE) measures the overall deviation between the fitted values ​​and the true values. A smaller MSE indicates a lower fitting error and a stronger ability of the model to approximate the actual data.

[0158] Figure 4 The performance evaluation results are presented, obtained by fitting and analyzing the reflection waveforms of two types of IGBTs in different health states under STDR / SSTDR detection signals at different frequencies. Figure 4 (a) corresponds to a 250MHz high-frequency STDR / SSTDR signal. Figure 4 (b) covers the evaluation of low-frequency test signals at 10MHz (FZ750R65KE3) and 20MHz (FF450R17ME7) (see Chapter 4 for the basis of frequency selection).

[0159] Under high-frequency SSTDR testing conditions, the fitting results showed significant advantages: the determination coefficient R of each sample... 2 All values ​​were above 0.9 and all MSE values ​​were less than 2 × 10⁻⁶. -3 This indicates that the fitted curve can effectively suppress the structural features of the residual reconstruction of the original reflection waveform. However, when using an STDR signal of the same frequency, although the R-values ​​of some samples... 2 The values ​​are still positive, but some are below 0.5, indicating a significant decrease in fitting accuracy and explanatory power; the corresponding MSE values ​​are mostly distributed between 0.02 and 0.06, indicating a certain degree of fitting error.

[0160] Due to bandwidth limitations, low-frequency signals exhibit greater overlap in reflected waveforms, increasing the difficulty of fitting and ultimately resulting in slightly inferior overall performance compared to high-frequency conditions. However, as shown in Fig. 9(b), the proposed impedance feature extraction algorithm still demonstrates good adaptability and robustness: for most samples R... 2 The values ​​>0.8 and MSE <0.015 indicate that the structural characteristics of the received mixed reflection waveform can still be effectively restored under strong aliasing background, providing reliable parameter support for subsequent IGBT fault identification.

[0161] Compared to single-chip structures, multi-chip parallel IGBT modules construct current paths by connecting multiple power chips in parallel, thereby improving overall current carrying capacity and thermal redundancy performance, and are widely used in medium- and high-power applications. However, the parallel complexity of this structure also makes the dynamic impedance characteristics of the device more complex. The total impedance state of the device is not only determined by a single conduction path, but also by the combined effect of its constituent structure and the conduction states of each sub-module. Especially under STDR / SSTDR test conditions, different chip conduction combinations, the impedance of parallel wires between chips, and package parasitic parameters will all affect the reflected signal pattern, increasing the complexity of impedance state identification. Among these, the internal parasitic inductance value of the device is usually in the nH range, and its corresponding impedance Z in the MHz frequency range involved in SSTDR testing is... L <<50Ω, which is negligible.

[0162] like Figure 5 As shown, taking the typical three-chip parallel medium-power IGBT module FF450R12ME7 as an example, this type of device consists of n=3 independent IGBT chips and m=3 anti-parallel diodes forming a parallel structure. The modules are electrically connected via bonding wires, with the collector (C) and emitter (E) pins leading out as external power interfaces. Due to the impedance Z of the device's collector, emitter, and bonding wire pins... CE Z BW It can be regarded as a fixed constant, and within the MHz frequency range involved in STDR / SSTDR testing, its value is much smaller than the impedance difference between the chip's on and off states, so it can be ignored.

[0163] Therefore, the total equivalent impedance Z of the multi-chip parallel structure eq This can be simplified to:

[0164]

[0165] Among them, Z IGBTi Z represents the equivalent impedance of the i-th IGBT submodule, where n is the number of IGBT chips connected in parallel; Diodei Z represents the equivalent impedance of the i-th anti-parallel diode module, where m is the number of parallel diodes; C =1 / (j2πfC) is the impedance of the internal parasitic capacitance C of the device. For example... Figure 6 As shown, taking a capacitance value of C = 1pF as an example, the capacitive reactance Z C It decreases rapidly as the test frequency f increases. Therefore, there exists a critical frequency f. C When f <f C At that time, Z C >>(Z IGBT ||Z Diode When the parasitic capacitance is approximately open-circuited, the characteristic impedance of the device mainly reflects the impedance characteristics of the power chip and the anti-parallel diode; however, when f > fC At that time, Z C <<(Z IGBT ||Z Diode Parasitic capacitance is equivalent to a short circuit, causing the characteristic impedance Z of the device to... eq It exhibits capacitive-dominated low impedance behavior.

[0166] Furthermore, to achieve separate measurement of the conduction state of the IGBT chip and the anti-parallel diode, this application introduces a signal bias voltage control strategy. By applying an appropriate DC bias to the test signal, the operating state of the anti-parallel diode can be controlled: when the detection signal is positively biased, the reverse diode is cut off, and the measured impedance mainly comes from the power chip and parasitic capacitance; when the detection signal is negatively biased, the reverse diode is turned on, and the measurement result shows the combined behavior of the diode current path and parasitic capacitance.

[0167] Based on the relationship between the IGBT state response and the test signal parameters (frequency, bias voltage) mentioned above, this paper introduces the following signal modulation strategy in the STDR / SSTDR test of multi-chip structures to enhance the state recognition capability:

[0168] 1) Low-frequency detection signals are used to suppress the effects of parasitic capacitance: when the test frequency f <f C At the critical frequency, the parasitic capacitance impedance Z C Significantly higher than the chip impedance, approximately open circuit. The total impedance of the device is mainly determined by the conduction state of the power chip and diode, which can more accurately reflect the characteristics of the device itself and is helpful in judging the chip's open / closed state and fault characteristics.

[0169] 2) Positive bias signal is used to separate diode impedance: By applying a positive DC bias to the SSTDR signal, the anti-parallel diode is turned off, thereby avoiding interference in its conduction path, effectively distinguishing the reflection components generated by the power chip and the diode, and improving the device structure resolution capability.

[0170] Under the above testing conditions, the impedance state of the multi-chip IGBT module exhibits the following characteristics:

[0171] 1) If all IGBT submodules are in the ON state, then Z IGBTi It exhibits low impedance and overall Z-axis. eq Minimum;

[0172] 2) If some sub-modules are turned on and some are turned off (ON / OFF), the overall impedance exhibits a parallel mixed characteristic;

[0173] 3) If all IGBT submodules are turned off, then Z IGBTi It exhibits high impedance, and the device impedance tends to be open circuit, Z eq maximum.

[0174] In practical testing, this paper mainly considers two typical states: healthy state (new) and open-circuit fault state (OC). The impedance behavior of IGBTs in these two states is summarized in Table 2 below (denoted as 0 when Z < 50Ω and 1 when Z > 50Ω is high impedance): Under low-frequency STDR and low-frequency positive-biased SSTDR signal conditions, only OC faulty devices still exhibit a high impedance state under the action of the conduction voltage, i.e., the reflection coefficient Γ > 0. The impedance characteristic value a1 > 0 can be extracted by the fitting algorithm. Therefore, by judging the sign and amplitude of the reflection characteristic peak under the conduction voltage under fixed test conditions, the OC faulty device can be reliably identified.

[0175] Table 2. Correspondence between SSTDR detection signal parameters and IGBT impedance state

[0176]

[0177] It is worth noting that STDR, as a baseband (0Hz) signal, has its spectral center located in the DC region, thus failing to effectively excite the frequency response of parasitic capacitances. However, the parasitic capacitances within the device, together with the wiring resistance in the test channel, form an RC network, which superimposes a slowly varying DC offset (i.e., leakage voltage) onto the received signal, manifesting as a rise or fall in the baseline of the echo waveform (e.g., ...). Figure 7 (as shown in (a)). As... Figure 7 (b) To avoid the DC component raising the overall correlation waveform baseline in subsequent cross-correlation analysis and causing errors in main peak identification, a baseline correction strategy needs to be adopted in the signal preprocessing stage to eliminate the DC component and ensure the accuracy of peak amplitude and time delay judgment. Although using STDR signals can effectively avoid amplitude roll-off and spectral aliasing caused by high-frequency signals and improve the stability of impedance state identification, it should be noted that compared with SSTDR, STDR has certain disadvantages in terms of anti-interference capability and adaptability to complex circuits, limiting its promotion in application scenarios with multiple devices in parallel and complex electromagnetic environments.

[0178] Therefore, by constructing an impedance state mapping model for multi-chip parallel IGBTs and combining it with test signal frequency and bias control strategies, it is possible to effectively identify chip conduction combinations and separate chip impedance components in complex structures, thereby improving the ability to identify the health status and fault modes of medium and high power devices.

[0179] IGBT Localization and State Identification Experiment and Verification

[0180] To verify the effectiveness of the proposed multi-chip IGBT impedance characteristic value extraction method and open-circuit (OC) state identification strategy, this paper selects IGBT samples of models FZ750R65KE3 (high-power IGBT) and FF450R12ME7 (medium-power IGBT), with a critical frequency f0. C The sampling rates were 20 MSa / s and 30 MSa / s, respectively. To avoid the detection frequency being in the high impedance region of the capacitor and introducing related capacitive reactance interference, the sampling rates of the low-frequency detection signals used in this experiment were set to 10 MSa / s and 20 MSa / s, respectively. The experimental tests used a low-frequency positive bias STDR / SSTDR signal injection method, and the results are as follows: Figure 8 As shown.

[0181] exist Figure 8 In the positioning results shown in (a), it can be observed that the DUT's identification position is generally 20m away from the theoretical position, and some data deviations are even more than double, indicating a significant positioning error.

[0182] Comparative analysis revealed that the positioning error was particularly pronounced in the following two aspects:

[0183] 1) Comparison between medium-power and high-power IGBTs: High-power IGBTs (FZ750R65KE3) have a more complex internal packaging structure, more chips, and larger parasitic parameters, resulting in more reflection paths and a significantly higher degree of echo signal overlap compared to medium-power devices (FF450R12ME7). Therefore, the positioning offset of high-power IGBTs is generally higher than that of medium-power devices.

[0184] 2) Comparison under different trigger voltages (on / off): Healthy IGBTs have lower path impedance, fewer reflection points, clearer main lobe morphology, and smaller positioning errors when on. However, in the off state or under OC fault state, the device is in a high-impedance state, the reflection coefficient increases, and multiple impedance transition points inside simultaneously reflect the signal, superimposing into a complex waveform, causing aggravated main lobe offset. In particular, OC fault devices still have no effective conduction path after applying the on-voltage, the reflected signal strength is enhanced, the reflection points are denser, leading to a further increase in positioning error.

[0185] In summary, the root cause of this type of positioning error lies in the high overlap and aliasing phenomenon caused by multipath reflections within the device. Differences in conduction state, parasitic parameter distribution, and reflection path length among the sub-modules in the multi-chip structure lead to the superposition of multiple reflected waves on the time axis, disrupting the symmetry and concentration of the main peak. This ultimately results in a shift in the main peak position in the cross-correlation results, affecting the accurate extraction of echo delay.

[0186] like Figure 9As shown, when using low-frequency signals, the received signal and the mixed reflected wave exhibit a high degree of aliasing, the cross-correlation peak of the STDR signal is distorted, and the amplitudes of the sidelobe peak S-Pk2 and the main peak S-Pk1 of the STDR signal are close, which seriously affects accurate positioning. This complex aliasing phenomenon is mainly reflected in high reflection density structures (such as multi-chip parallel IGBTs), reflecting the substantial impact of the number of parasitic reflection paths on the accuracy of time delay identification.

[0187] However, in terms of impedance state identification, the low-frequency STDR signal still exhibits good state differentiation capability, but it failed to identify the OC state of high-power IGBTs. For example... Figure 9 The impedance characteristic value a1 extracted as shown in (b) indicates that:

[0188] 1) For high-power IGBTs (FZ750R65KE3), using low-frequency STDR signals for testing, open-circuit (OC) fault samples still exhibit significant high resistance (a1>0) under the influence of conduction voltage, while healthy samples show low resistance (a1<0), accurately identifying their OC faults. However, under SSTDR conditions, it can only distinguish whether the device is driven, making it difficult to further identify its internal state, thus limiting the accuracy of identification.

[0189] 2) For medium power IGBTs (FF450R12ME7), whether using low-frequency STDR signals or low-frequency positive bias SSTDR signals, it is possible to effectively distinguish between healthy and over-current (OC) fault states.

[0190] However, it should be noted that relying solely on a single impedance characteristic value under the conduction voltage for state determination may lead to misjudgment. This is especially true for high-power IGBT devices, which are susceptible to varying degrees of response changes due to the complexity of their internal structure. Figure 9 (b) High-power IGBTs with OC faults still exhibit the opposite high-resistance behavior under the conduction voltage. Therefore, judging the device state solely based on a1>0 is still limited, and it is necessary to combine other characteristics such as signal morphology, response waveform phase, or cross-cycle behavior to make a comprehensive judgment.

[0191] Experiment and Verification of IGBT Positioning Based on High-Frequency Signals

[0192] From the perspective of positioning accuracy, using a high-frequency excitation signal can effectively excite the parasitic capacitance response inside the device, enhance the amplitude of the main lobe of the reflection, and widen the time difference between the main peak and the side lobes, which helps to extract the echo position more accurately.

[0193] like Figure 10 As shown in the experimental results, the positioning effect of the high-frequency SSTDR signal is generally better than that of the high-frequency STDR signal. Under the condition of high-frequency SSTDR detection signal, the positioning results are all around the theoretical value of 20m, avoiding the difference between τ and T.b The strong overlap between signals leads to a blind spot in positioning. STDR performs well in the IGBT on state, with positioning results mostly concentrated around 20m; however, in other healthy states (such as off, open circuit, etc.), the positioning results show a significant shift, clustering around n×20m (n is an integer), possibly due to misjudgment of main and secondary peaks or signal aliasing. This difference mainly stems from the compact internal packaging structure of the IGBT, which contains multiple similar reflection points. STDR signals have poor anti-interference capabilities, making it difficult to form a stable main peak positioning point in complex structures. SSTDR, with its stronger anti-interference capabilities and ability to distinguish between main and secondary peaks, can effectively improve positioning accuracy and consistency.

[0194] Therefore, the two frequency bands can be combined to extract the characteristic values ​​of the IGBT under test, that is, a two-stage testing strategy of "high-frequency positioning + low-frequency feature recognition" can be adopted:

[0195] 1) High-frequency SSTDR signals are used for device location extraction, improving the identification of the main peak of the echo and avoiding location aliasing;

[0196] 2) Low-frequency positive bias signal is used for IGBT chip impedance status identification, shielding parasitic capacitance and reverse diode interference, extracting chip impedance characteristics and then identifying device health status and open circuit faults.

[0197] This paper proposes an improved STDR / SSTDR detection method for IGBT devices in power electronic systems to address the challenges of location deviation and impedance parameter extraction caused by short-distance transmission and multiple overlapping signal reflections. This method significantly improves the adaptability and versatility of the detection system by constructing a test framework that eliminates the need for pre-setting device positions. To enhance the identification capability of faulty IGBT devices, a dual modulation strategy combining frequency adjustment and bias voltage control is introduced. The high-frequency SSTDR signal is used to improve the resolution and location accuracy of the main reflection peak and reduce signal aliasing errors caused by multiple reflections; the low-frequency positive bias signal is used to effectively excite the IGBT chip's intrinsic impedance response, shielding the effects of parasitic capacitance and anti-parallel diodes, thereby achieving accurate identification of the device's true health status, especially reliable determination of open-circuit (OC) faults. Experimental results show that this detection method exhibits significant advantages in the detection of open-circuit (OC) faults in medium- and high-power IGBTs, not only accurately locating the device under test but also accurately extracting the device's impedance characteristics to distinguish between normal states and typical faults.

[0198] A method for fault identification and localization of IGBTs, comprising:

[0199] The first acquisition module is used to acquire detection signals and observation signals. The observation signal is the signal acquired after the detection signal is input into the IGBT through the transmission line, and the reflected signal is the signal collected at the input point of the observation signal after the observation signal is transmitted to the IGBT and then returns.

[0200] The first calculation module is used to perform cross-correlation operation on the detected signal and the observed signal, and extract the first time delay corresponding to the cross-correlation peak value;

[0201] The filtering module is used to filter out the detection signal from the observed signal to obtain the mixed reflection signal;

[0202] The second calculation module is used to perform cross-correlation operation on the detected signal and the mixed reflection signal, extract the second time delay corresponding to the correlation peak, and calculate the initial time delay based on the first time delay and the second time delay;

[0203] The second acquisition module is used to acquire the i-th reflection signal and signal constraints;

[0204] The superposition module is used to obtain the superimposed reflection signal based on the i-th reflection signal and the mixed reflection signal;

[0205] The settings module is used to set the number of reflections;

[0206] The third calculation module is used to obtain the time delay matrix based on the number of reflections and the superimposed reflected signals;

[0207] The fourth calculation module is used to obtain the coefficient matrix based on the signal constraints and the time delay matrix;

[0208] The solution module is used to solve the coefficient matrix to obtain the coefficients and time delay of the first reflected signal;

[0209] The judgment module is used to determine whether the IGBT has failed and the location of the failure based on the coefficient and time delay of the first reflected signal.

[0210] This application also discloses a terminal device, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor loads and executes the computer program, it employs an IGBT fault identification method.

[0211] The terminal device can be a computer device such as a desktop computer, a laptop computer, or a cloud server. The terminal device includes, but is not limited to, a processor and a memory. For example, the terminal device may also include input / output devices, network access devices, and buses.

[0212] The processor can be a central processing unit (CPU). Of course, depending on the actual use, it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc., and this application does not limit it in this regard.

[0213] The memory can be an internal storage unit of the terminal device, such as a hard disk or RAM of the terminal device, or an external storage device of the terminal device, such as a plug-in hard disk, smart memory card (SMC), secure digital card (SD), or flash memory card (FC) equipped on the terminal device. Furthermore, the memory can be a combination of internal storage units and external storage devices of the terminal device. The memory is used to store computer programs and other programs and data required by the terminal device. The memory can also be used to temporarily store data that has been output or will be output. This application does not limit this.

[0214] In this terminal device, the fault identification method of IGBT in the above embodiment is stored in the memory of the terminal device and loaded and executed on the processor of the terminal device for convenient use.

[0215] This application also discloses a computer-readable storage medium, which stores a computer program, wherein when the computer program is executed by a processor, it employs an IGBT fault identification method described in the above embodiments.

[0216] The computer program can be stored in a computer-readable medium. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or certain middleware. The computer-readable medium includes any entity or device capable of carrying computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the computer-readable medium includes, but is not limited to, the above-mentioned components.

[0217] The above-described IGBT fault identification method is stored in the computer-readable storage medium and loaded and executed on the processor to facilitate the storage and application of the method.

[0218] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0219] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. A method for fault identification and location of IGBTs, characterized in that, include: Acquire detection signals and observation signals. The observation signal is the signal obtained after the detection signal is input into the IGBT through the transmission line, and the reflected signal is the signal collected at the input point of the observation signal after the observation signal is transmitted to the IGBT. Perform cross-correlation calculation on the detected signal and the observed signal, and extract the first time delay corresponding to the cross-correlation peak value; The detection signal is filtered out from the observed signal to obtain the mixed reflection signal; The detection signal and the mixed reflection signal are cross-correlated, and the second time delay corresponding to the correlation peak is extracted. The initial time delay is calculated based on the first time delay and the second time delay. Obtain the i-th reflection signal and signal constraints; Based on the i-th reflection signal and the mixed reflection signal, the superimposed reflection signal is obtained; Set the number of reflections; The time delay matrix is ​​obtained based on the number of reflections and the superimposed reflected signals; Based on the signal constraints and the time delay matrix, the coefficient matrix is ​​obtained; Solving the coefficient matrix yields the coefficients and time delay of the first reflected signal; Based on the coefficients and time delay of the first reflected signal, determine whether the IGBT has malfunctioned and the location of the malfunction.

2. The fault identification method for IGBTs as described in claim 1, characterized in that, The step of performing cross-correlation calculation on the detected signal and the observed signal, and extracting the first time delay corresponding to the cross-correlation peak value includes: The detected signal and the observed signal are cross-correlated to obtain the cross-correlation waveform, which is represented as follows: Where T is the period, τ is the time for one round trip of the signal, and S in (t) is the detection signal, S obs (t) represents the observed signal; In the cross-correlation waveform, the horizontal coordinate value corresponding to the cross-correlation peak is used as the first time delay.

3. The fault identification method for IGBTs as described in claim 1, characterized in that, The process of filtering out the detection signal from the observed signal to obtain the mixed reflection signal is represented as follows: Among them, S in (t) is the detection signal, S obs (t) represents the observed signal, ρ A Let F be the transmission coefficient at point A. i (t) represents the i-th reflected signal, N represents the number of signal reflections, and point A is the point where the detection signal is injected.

4. The fault identification method for IGBTs as described in claim 1, characterized in that, The step of performing cross-correlation operation on the detected signal and the mixed reflected signal, extracting the second time delay corresponding to the correlation peak, and calculating the initial time delay based on the first time delay and the second time delay includes: The cross-correlation operation between the detected signal and the mixed reflected signal yields a mixed waveform, represented as follows: Based on the mixed waveform, the horizontal coordinate value corresponding to the maximum correlation peak is obtained as the second time delay; The initial delay is calculated based on the first delay and the second delay, and is expressed as follows: τ0=τ SF -t SS Where τ0 is the initial time delay, τ SF For the second time delay, τ SS This is the first time delay.

5. The fault identification method for IGBTs as described in claim 1, characterized in that, The i-th reflected signal is represented as: F i (t)=a i ·S in (t-i·τ1) Among them, F i (t) is the reflected signal, a i S is the reflection signal coefficient. in (t) is the detection signal, τ1=τ0+y is the time for the signal to travel back and forth once, and y is the correction amount.

6. The fault identification method for IGBTs as described in claim 1, characterized in that, The superimposed reflection signal obtained from the i-th reflection signal and the mixed reflection signal is expressed as follows: Among them, F A (t) represents the reflected superimposed signal, ρ A Let a be the transmission coefficient at point A. i S is the reflection signal coefficient. in (t) represents the detection signal, τ1 = τ0 + y represents the time it takes for the signal to travel back and forth once, y represents the correction amount, and N represents the number of signal reflections.

7. The fault identification method for IGBTs as described in claim 1, characterized in that, Determining whether an IGBT has malfunctioned and its location based on the coefficients and time delay of the first reflected signal includes: The coefficient of the first reflected signal is used as a characteristic impedance index; If the characteristic impedance index is greater than a preset threshold, then the IGBT is determined to be faulty. If the characteristic impedance index is less than or equal to a preset threshold, then it is determined that the IGBT has not failed. The fault location is calculated based on the time delay of the first reflected signal and the signal propagation speed.

8. A method for fault identification and location of IGBTs, characterized in that, include: The first acquisition module is used to acquire detection signals and observation signals. The observation signal is the signal acquired after the detection signal is input into the IGBT through the transmission line, and the reflected signal is the signal collected at the input point of the observation signal after the observation signal is transmitted to the IGBT and then returns. The first calculation module is used to perform cross-correlation operation on the detected signal and the observed signal, and extract the first time delay corresponding to the cross-correlation peak value; The filtering module is used to filter out the detection signal from the observed signal to obtain the mixed reflection signal; The second calculation module is used to perform cross-correlation operation on the detected signal and the mixed reflection signal, extract the second time delay corresponding to the correlation peak, and calculate the initial time delay based on the first time delay and the second time delay; The second acquisition module is used to acquire the i-th reflection signal and signal constraints; The superposition module is used to obtain the superimposed reflection signal based on the i-th reflection signal and the mixed reflection signal; The settings module is used to set the number of reflections; The third calculation module is used to obtain the time delay matrix based on the number of reflections and the superimposed reflected signals; The fourth calculation module is used to obtain the coefficient matrix based on the signal constraints and the time delay matrix; The solution module is used to solve the coefficient matrix to obtain the coefficients and time delay of the first reflected signal; The judgment module is used to determine whether the IGBT has failed and the location of the failure based on the coefficient and time delay of the first reflected signal.

9. A terminal device, comprising a memory and a processor, characterized in that, The memory stores a computer program that can run on a processor, and when the processor loads and executes the computer program, it employs the method described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is loaded and executed by the processor, it employs the method described in any one of claims 1 to 7.

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