Video memory prefetching method, system and device, electronic equipment and computer storage medium

Abstract

The invention provides a video memory prefetching method, system and device, electronic equipment and a computer storage medium, and belongs to the technical field of graphic processing.The video memory prefetching method comprises the steps that a video memory operation sequence of an application program is determined based on historical video memory use data of the application program; determining a target data reading instruction according to the video memory operation sequence; and based on the target data reading instruction, reading data corresponding to the target data reading instruction from the video memory, and pre-storing the data in a memory buffer area. Data in a video memory required by an application program can be read into a memory in advance so as to solve the problem that time delay is increased due to the fact that data is read from the video memory in real time.

Description

Technical Field

[0001] This disclosure relates to the field of graphics processing technology, and in particular to a video memory prefetching method, system, apparatus, electronic device, and computer storage medium. Background Technology

[0002] In a computer system, the graphics card connects to the host system via the Peripheral Component Interconnect Express (PCIe) interface, and applications access video memory (VRAM) through PCIe. When an application needs to perform graphics rendering or computational tasks, it sends real-time read / write data requests to the VRAM, and the data is transferred to the graphics card via the PCIe bus. This process requires every VRAM operation to go through PCIe, forming a complete data path of "application-PCIe-VRAM-PCIe-application". Because VRAM is a dedicated storage medium for the graphics card, applications cannot bypass PCIe to access it directly, causing all operations to be limited by the PCIe transfer efficiency.

[0003] However, as a serial interface, PCIe's frequent small-scale data transfers can significantly reduce its transfer rate. Furthermore, graphics cards typically use Graphics Double Data Rate (GDDR) memory, which is inherently slower than RAM Double Data Rate (DDR) memory. The combined effect of these factors causes applications to spend a significant amount of time waiting for data transfers to complete, severely impacting application performance. Summary of the Invention

[0004] This disclosure provides a video memory prefetching method, system, apparatus, electronic device, and computer storage medium; it can prefetch data from video memory required by applications into memory to solve the problem of increased latency caused by reading data from video memory.

[0005] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a video memory prefetching method, which includes: determining a video memory operation sequence of an application based on historical video memory usage data of an application; determining a target read data instruction based on the video memory operation sequence; and reading data corresponding to the target read data instruction from video memory and pre-storing it in a memory buffer based on the target read data instruction.

[0006] Secondly, this disclosure provides a video memory prefetching system, which includes: a program execution pattern learning unit configured to determine the video memory operation sequence of an application based on the application's historical video memory usage data; a cache management unit configured to determine a target read data instruction based on the video memory operation sequence and send it to a read / write scheduling unit; a read / write scheduling unit configured to read data corresponding to the target read data instruction from video memory based on the target read data instruction and send it to the cache management unit; and the cache management unit is further configured to pre-store the data corresponding to the target read data instruction into a memory buffer.

[0007] Thirdly, this disclosure provides a video memory prefetching device, which includes: a determination module and a read and store module; the determination module is used to determine the video memory operation sequence of the application based on the historical video memory usage data of the application; and to determine the target read data instruction according to the video memory operation sequence; the read and store module is used to read the data corresponding to the target read data instruction from the video memory and pre-store it into the memory buffer based on the target read data instruction.

[0008] Fourthly, this disclosure provides an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the video memory prefetching method as described in the first aspect.

[0009] Fifthly, this disclosure provides a computer-readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the video memory prefetching method as described in the first aspect.

[0010] In a sixth aspect, this disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions, which, when run on a processor, cause the processor to execute the computer program or instructions to implement the steps of the video memory prefetching method as described in the first aspect.

[0011] In a seventh aspect, this disclosure provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the video memory prefetching method as described in the first aspect.

[0012] This disclosure provides a video memory prefetching method. Based on historical video memory usage data of an application, the method analyzes the application's video memory operation sequence. Using this sequence, it proactively predicts the data to be read before the application actually initiates a data read request. By predicting this sequence, the method copies the data to be read from video memory to a memory buffer in advance, effectively transforming high-latency video memory operations into background tasks. This prefetching mechanism based on video memory operation sequence prediction significantly improves the matching accuracy between prefetched data and actual needs. When the application subsequently needs to read this data, it can directly retrieve it from the memory buffer at high speed. Since the latency of memory access is much lower than the latency of video memory transfer across the PCIe bus, this avoids the significant latency problem caused by real-time data reading from video memory via the PCIe bus, thus improving application performance. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating the interaction between the application program and the video memory in the related technologies provided in this disclosure.

[0014] Figure 2 This is a flowchart illustrating a video memory pre-storage method provided in this disclosure.

[0015] Figure 3 This is a flowchart illustrating another method for pre-storing video memory provided in this disclosure.

[0016] Figure 4 This is a schematic diagram illustrating the principle of instruction merging provided in this disclosure.

[0017] Figure 5 This is a flowchart illustrating another method for pre-storing video memory provided in this disclosure.

[0018] Figure 6 This is a schematic diagram of the structure of a video memory pre-storage system provided in this disclosure.

[0019] Figure 7 This is a structural block diagram of a video memory pre-storage device provided in this disclosure.

[0020] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in this disclosure. Detailed Implementation

[0021] The technical solutions in the embodiments of this disclosure will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure are within the scope of protection of this disclosure.

[0022] PCIe is a high-speed serial computer expansion bus standard. In a computer system, PCIe plays a core bridging role in connecting the CPU with peripheral devices (such as graphics cards, solid-state drives, and network cards), providing a data exchange path for high-performance devices such as graphics processors, enabling peripheral devices to directly access system memory and work with the CPU.

[0023] like Figure 1 The diagram illustrates the interaction between application 101 and video memory via PCIe. Application 101 transfers data to be written to video memory 102 via PCIe, and video memory 102 transfers data to be read by application 101 via PCIe. Due to the limitations of PCIe bus serial transmission and the read speed of video memory 102, application 101 consumes a significant amount of waiting time during operations on video memory 102, severely impacting program performance.

[0024] Based on the above problems, this disclosure aims to provide a memory prefetching method that can reduce memory operation latency, such as... Figure 2 As shown, the video memory prefetching method may include the following steps S201 to S203.

[0025] In step S201, the application's video memory operation sequence is determined based on the application's historical video memory usage data.

[0026] Historical video memory usage data refers to the collection of records of video memory operations performed by the application during its runtime, which can reflect the application's behavioral habits in video memory operations during its runtime cycle.

[0027] In some embodiments, historical video memory usage data may include: historical video memory allocation data, historical video memory read data, historical video memory write data, and historical video memory release data. Historical video memory allocation data refers to the video memory address, size, and timestamp requested by the application; historical video memory read data refers to the source address, data block size, and timestamp of the read operation; historical video memory write data refers to the target address, data content, and timing of the write operation; and historical video memory release data refers to the address range and triggering timing of the release operation. By monitoring the correlation between these four types of data in real time, the video memory operation sequence of the application is constructed.

[0028] For example, in a 3D rendering application, the historical video memory usage data is as follows: t=10ms, allocation, address: 0x1000-0x2000, size: 4KB; t=15ms, write, address: 0x1000, data: vertex coordinates [a, b, ...]; t=20ms, read, address: 0x1000, size: 1KB; t=60ms, release, address: 0x1000-0x2000.

[0029] A memory operation sequence refers to the sequential order in which an application performs various operations on memory, extracted from its historical memory usage data. This includes: time sequences, such as data access at fixed time intervals; spatial sequences, such as consecutive address accesses or fixed offset jumps (e.g., texture mipmap level access); and instruction sequence correlations, such as the recurrence of specific instruction combinations. Memory operation sequences are obtained from historical memory usage data using data mining algorithms (such as time series analysis and association rule learning). These sequences can then be used to predict future memory operations.

[0030] For example, memory operation sequence 1: access texture addresses 0x5000-0x6000 5ms after the start of each frame, memory operation sequence 2: trigger the fragment shader to read texture address 0x8000 within 2ms after reading vertex data, memory operation sequence 3: access global illumination data once every 120 frames, address 0xF000.

[0031] In step S202, the target read data instruction is determined according to the video memory operation sequence.

[0032] The target read data instruction refers to the video memory read instruction that the application is about to execute, which is predicted based on the video memory operation sequence.

[0033] In step S203, based on the target read data instruction, the data corresponding to the target read data instruction is read from the video memory and pre-stored into the memory buffer.

[0034] A memory buffer is a high-speed cache area located in system memory (excluding video memory) used to temporarily store prefetched video memory data. As a temporary storage layer for prefetched data, it can be quickly retrieved from the memory buffer when the application actually needs to read it, without having to retrieve it from video memory via PCIe.

[0035] This disclosure analyzes historical video memory usage data of an application to obtain its video memory operation sequence. Based on this sequence, it proactively predicts the data to be read before the application actually initiates a data read request. By anticipating this, the required data is copied from video memory to a memory buffer in advance, effectively transforming high-latency video memory operations into background tasks. Since the video memory operation sequence summarizes the application's habits in handling video memory, this prefetching mechanism significantly improves the matching accuracy between prefetched data and actual needs. When the application actually needs to read this data later, it can directly retrieve it from the memory buffer at high speed. Because the latency of memory access is much lower than the latency of video memory transfer across the PCIe bus, this avoids the significant latency issues caused by real-time data reading from video memory via the PCIe bus, thus improving application performance.

[0036] In some embodiments, such as Figure 3As shown, the video memory prefetching method can also be implemented through the following steps S301 to S304.

[0037] In step S301, the historical video memory usage data is classified according to the application scenario to obtain the sub-historical video memory usage data corresponding to each application scenario.

[0038] Application scenarios refer to the runtime phases of an application with independent functional goals, whose memory access behaviors are highly cohesive and identifiable. For example, for game applications, these could include combat scenarios (triggered when a character releases a skill), map loading scenarios (triggered when entering a teleportation point), and cutscene scenarios (triggered at plot nodes); for 3D modeling applications, these could include model rotation and rendering scenarios (continuously active when the user drags the viewpoint), and ray tracing calculation scenarios (triggered when the "Render" button is clicked); for video editing applications, these could include timeline preview scenarios (activated when the playback head moves), and 4K video export scenarios (started after selecting the output format).

[0039] Sub-history memory usage data refers to a set of memory operations belonging to the same application scenario, including: memory allocation and release records and their timestamps within the scenario period, the addresses and data sizes of all read and write operations, and the time interval sequence between memory operations.

[0040] Each application scenario has a corresponding scene trigger event. For example, the scene trigger event for the ray tracing calculation scenario is triggered by clicking the "Render" button. The timestamp of the scene trigger event is used as the starting point, and the timestamp of the scene switching is used as the ending point. The historical video memory usage data between the starting point and the ending point is the sub-historical video memory usage data corresponding to this application scenario.

[0041] In step S302, based on the sub-historical video memory usage data corresponding to each application scenario, the scene video memory operation sequence corresponding to each application scenario is determined as included in the video memory operation sequence.

[0042] A scene memory operation sequence refers to a memory operation sequence that appears repeatedly in a specific application scenario and has a certain regularity. For example, it can be a timing pattern used to indicate a fixed time node or period when a memory operation occurs, a spatial pattern used to indicate the address continuity or offset characteristics of data access, or an instruction pattern used to indicate the correlation of the memory operation sequence. Specifically, statistical induction can be used to analyze historical video memory usage data to determine the average relative time of each type of video memory operation (e.g., in a combat scene, a texture must be loaded 5.2±0.3ms after a skill is released), identify high-frequency periodic behaviors (e.g., requesting 128MB of cache every 2 seconds during video export), and obtain temporal patterns; identify the regular changing trend of operation addresses during video memory operations (e.g., vertex data is read by jumping between consecutive addresses of 0x1000 when the model rotates), mark hot spots (e.g., in a combat scene, the 0x5000-0x6000 range accounts for 70% of the read volume), and obtain spatial patterns; establish causal rules between instructions (e.g., when the vertex buffer data is written, a fragment shader must read the texture within 1.5ms±0.2ms), and obtain instruction patterns.

[0043] For example, the ray tracing scene pattern of a 3D modeling application has the following temporal pattern: after clicking to render, the light source data buffer is requested 3ms later; the spatial pattern is that the photon map is stored continuously at 256-byte intervals; and the instruction pattern is that after requesting the light source data, the sampling result is written, and finally, the neighboring photons are read.

[0044] In step S303, the target read data instruction is determined according to the scene memory operation sequence corresponding to the current application scenario.

[0045] Real-time detection of the current application scenario (e.g., entering the rendering scene upon detecting the BeginRendering call). Based on the scene memory operation sequence corresponding to the current application scenario, the prefetch rule is triggered (e.g., 2ms after the start of the battle scene, the enemy model data at address 0x8000 is predicted to be read), and the target data read instruction is determined.

[0046] In step S304, based on the target read data instruction, the data corresponding to the target read data instruction is read from the video memory and pre-stored into the memory buffer.

[0047] It should be noted that the description of step S304 can be referred to step S203 above, and will not be repeated here.

[0048] Since the video memory operations of applications are relatively fixed in different application scenarios, this disclosure determines the scene video memory operation sequence for each application scenario based on the sub-historical video memory usage data under various application scenarios, thereby improving the data prefetching accuracy.

[0049] In some embodiments, step S302 above, which determines the target read data instruction based on the video memory operation sequence, includes: determining multiple pre-read data instructions based on the video memory operation sequence; and merging the multiple pre-read data instructions in address order to obtain the target read data instruction.

[0050] If multiple prefetch instructions, determined by the memory operation sequence, were to read data from memory independently via PCIe, it would result in low transmission efficiency. This is because each PCIe transfer requires a fixed-length header (typically 128 bytes), and these fragmented small data packets cause significant protocol overhead. For example, when reading data blocks at three addresses, three requests are sent, each including header overhead. PCIe must perform an arbitration-handshake-transfer process for each prefetch instruction, and frequent fragmented requests increase bus contention latency. Furthermore, fragmented address access forces memory to frequently switch row buffers, which also reduces the access speed of the storage medium.

[0051] Therefore, this disclosure combines multiple prefetch data instructions according to the order of the requested addresses, merging consecutive prefetch data instructions at the requested addresses to obtain the target read data instruction. For example... Figure 4 As shown, the prefetch instruction 1 reads from address 0x03, the prefetch instruction 2 reads from address 0x01, and the prefetch instruction 3 reads from address 0x02. After sorting, they become: prefetch instruction 2 reads from address 0x01, prefetch instruction 3 reads from address 0x02, and prefetch instruction 1 reads from address 0x03. The resulting target read instruction is at address 0x01 and has a size of 3. Thus, compared to the number of prefetch instructions, the number of target read instructions is reduced, thereby reducing the transmission pressure on the PCIe and lowering the latency of reading data from video memory.

[0052] In some embodiments, the video memory prefetching method may further include: during a timeout period, merging multiple write data requests from the application by address to obtain a merged write data request; and after a timeout, performing a write operation on the video memory based on the merged write data request.

[0053] Specifically, upon receiving the first write data request, a timer is immediately started. All subsequent write data requests arriving within the timer's set timeout period are collected and sorted in ascending order by their address. Requests with consecutive addresses are merged to generate a single merged write data request containing a larger data block. Once the timer expires, the merged write data request is transmitted to the video memory via PCIe for write operation. This delayed write mechanism efficiently consolidates fragmented, small-scale write data requests into fewer but larger block requests. This significantly reduces the transmission load on the high-bandwidth PCIe, avoiding the overhead of frequent small packet transmissions. Furthermore, the larger data volume per transmission improves the write efficiency of the video memory itself, ultimately reducing overall write latency.

[0054] In some embodiments, the video memory prefetching method further includes: if the PCIe bus occupancy rate is less than or equal to the occupancy rate threshold and the video memory idle rate is greater than or equal to the idle rate threshold during the timeout period, then performing a write operation on the video memory based on a merged write data request; the above-mentioned performing a write operation on the video memory based on a merged write data request after the timeout includes: if the PCIe bus occupancy rate is greater than the occupancy rate threshold or the video memory idle rate is greater than the idle rate threshold during the timeout period, then performing a write operation on the video memory based on a merged write data request after the timeout.

[0055] The utilization threshold is the upper limit percentage of PCIe bandwidth utilization, used to characterize the real-time load pressure on the PCIe bus. When the PCIe utilization rate consistently exceeds the threshold, it indicates that the PCIe transmission bandwidth has reached saturation, and continuing to perform video memory write operations will exacerbate PCIe congestion. Therefore, if the PCIe utilization rate is detected to exceed this threshold, write operations will be delayed until the timer times out to avoid bus contention.

[0056] The idle rate threshold refers to the minimum safe threshold for the percentage of available video memory resources, used to determine the real-time writable capability of video memory. The idle rate is calculated as the proportion of unused video memory blocks to the total capacity (e.g., the ratio of available video memory space to total video memory capacity). When the idle rate falls below the threshold, it indicates that video memory resources are strained, and immediate writing may trigger memory scheduling blocking. Therefore, it is necessary to delay writes, processing and merging requests uniformly after the timer expires. Batch writing reduces the number of video memory accesses, thereby optimizing resource utilization.

[0057] This mechanism fully utilizes the instantaneous spare bandwidth of PCIe and the batch write characteristics of video memory, and forces write operations before resource conditions deteriorate, avoiding indefinite delays or operation blockages caused by continuous bus overload or video memory resource depletion. Specifically, when the PCIe occupancy rate is detected to be less than or equal to the occupancy rate threshold and the video memory idle rate is detected to be greater than or equal to the idle rate threshold, the relatively idle transmission channel and sufficient video memory resources are immediately used to submit and merge write data requests in advance, significantly reducing transmission latency. Conversely, when the PCIe occupancy rate is detected to be continuously exceeding the limit or the video memory idle rate is continuously lower than the idle rate threshold during the timeout period, the write operation is forced after the timeout to prevent the bus congestion or video memory resource shortage from worsening. This dynamic strategy can capture the optimal resource window to achieve low-latency transmission, while ensuring that the write latency is not too long through the timeout mechanism, achieving a balance between throughput efficiency and response time.

[0058] In some embodiments, such as Figure 5 As shown, the video memory prefetching method can also be implemented through the following steps S501 to S508.

[0059] In step S501, the application's video memory operation sequence is determined based on the application's historical video memory usage data.

[0060] In step S502, the target read data instruction is determined according to the video memory operation sequence.

[0061] In step S503, based on the target read data instruction, the data corresponding to the target read data instruction is read from the video memory and pre-stored into the memory buffer.

[0062] In step S504, based on the application's read data request, the corresponding requested data is searched from the memory buffer.

[0063] In step S505, if the memory buffer contains the corresponding request data, the corresponding request data is retrieved from the memory buffer.

[0064] In step S506, if the memory buffer does not contain the corresponding request data, the corresponding request data is obtained from the video memory.

[0065] When a read data request is received, it is first determined whether the data prefetched in the memory buffer matches the requested data. If it matches, the requested data is directly retrieved from the memory buffer. If it does not match (i.e., it is not prefetched in the memory buffer), the corresponding requested data is retrieved from the video memory via PCIe. Alternatively, within the aforementioned timeout period, the missed read data requests are sorted and merged. If the PCIe utilization rate is less than or equal to the utilization rate threshold and the video memory idle rate is greater than or equal to the idle rate threshold, the corresponding requested data is retrieved from the video memory via PCIe based on the merged read data request. If, within the timeout period, the PCIe utilization rate is greater than the utilization rate threshold or the video memory idle rate is less than the idle rate threshold, the corresponding requested data is retrieved from the video memory via PCIe based on the merged read data request after the timeout. This ensures that even if a read request is not hit by the memory buffer, the requested data can still be efficiently read from the video memory. At the same time, through the scheduling mechanism of request merging and dual threshold coordination, it can also avoid PCIe bandwidth overload and video memory access conflicts caused by sudden dense small-granular read requests, significantly reducing the global latency of read operations and improving system throughput efficiency.

[0066] In step S507, based on the application's write data requests, within the timeout period, multiple write data requests from the application are sorted and merged by address to obtain a merged write data request.

[0067] In step S508, after the timeout, a write operation is performed on the video memory based on the merged write data request.

[0068] It should be noted that the descriptions of steps S501 to S503, as well as steps S507 and S508, can be found in the descriptions of the same steps mentioned above, and will not be repeated here.

[0069] Figure 6 This disclosure presents a structural block diagram of a video memory prefetching system, which includes: The program execution pattern learning unit 601 is configured to determine the corresponding video memory operation sequences 1 to N for applications 1 to N based on the historical video memory usage data of applications 1 to N. The cache management unit 602 is configured to determine the target read data instruction based on the video memory operation sequences 1 to N and send it to the read / write scheduling unit 603. The read / write scheduling unit 603 is configured to read the data corresponding to the target read data instruction from video memory 60 and send it to the cache management unit 602. The cache management unit 602 is also configured to pre-store the data corresponding to the target read data instruction into a memory buffer. Here, N is an integer greater than 1, applications 1 to N are located in the application space of the computer system, the program execution pattern learning unit 601, the cache management unit 602, and the read / write scheduling unit 603 are located in the kernel space of the computer system, video memory 60 is located in the hardware layer of the computer system, and each video memory operation sequence 1 to N includes at least one operation sequence.

[0070] Figure 7 This is a structural block diagram of a video memory prefetching device disclosed herein, such as... Figure 7 As shown, it includes: The system includes a determination module 701 and a read and store module 702. The determination module 701 is used to determine the video memory operation sequence of the application based on the application's historical video memory usage data, and to determine the target read data instruction based on the video memory operation sequence. The read and store module 702 is used to read the data corresponding to the target read data instruction from the video memory and pre-store it in the memory buffer based on the target read data instruction.

[0071] In some embodiments, the determining module 701 is configured to classify historical video memory usage data according to application scenarios to obtain sub-historical video memory usage data corresponding to each application scenario; determine the scene video memory operation sequence corresponding to each application scenario included in the video memory operation sequence according to the sub-historical video memory usage data corresponding to each application scenario; and determine the target read data instruction according to the scene video memory operation sequence corresponding to the current application scenario.

[0072] In some embodiments, the determining module 701 is configured to determine multiple pre-fetch data instructions based on the video memory operation sequence; and merge the multiple pre-fetch data instructions in address order to obtain the target read data instruction.

[0073] In some embodiments, the video memory prefetching device further includes a merging module and an execution module; the merging module is configured to merge multiple write data requests from an application in order of address during a timeout period to obtain a merged write data request; the execution module is configured to perform a write operation on the video memory based on the merged write data request after a timeout.

[0074] In some embodiments, the execution module is configured to perform a write operation on the video memory based on a merged write data request if the PCIe bus occupancy rate is less than or equal to the occupancy rate threshold and the video memory free rate is greater than or equal to the free rate threshold during the timeout period; and to perform a write operation on the video memory based on a merged write data request after the timeout if the PCIe bus occupancy rate is greater than the occupancy rate threshold or the video memory free rate is greater than the free rate threshold during the timeout period.

[0075] In some embodiments, the video memory prefetching device further includes: a search module and an acquisition module; the search module is configured to search for corresponding request data from a memory buffer based on a read data request from an application; the acquisition module is configured to acquire corresponding request data from a memory buffer if the memory buffer includes the corresponding request data; and acquire corresponding request data from video memory if the memory buffer does not include the corresponding request data.

[0076] In this embodiment, each module can implement the memory prefetching method provided in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0077] Please refer to Figure 8 This illustration shows a schematic diagram of the hardware structure of an electronic device provided in an exemplary embodiment of this disclosure. In some examples, the electronic device may be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The electronic device has communication capabilities and can access wired or wireless networks. The term "electronic device" can refer to one of multiple terminals; those skilled in the art will understand that the number of such terminals may be more or less.

[0078] like Figure 8 As shown, the electronic device in this disclosure may include one or more of the following components: processor 810 and memory 820.

[0079] Optionally, the processor 810 connects various parts within the electronic device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 820, and by calling data stored in the memory 820. Optionally, the processor 810 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 810 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used to handle wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 810, but may be implemented using a separate chip.

[0080] The memory 820 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 820 may include a non-transitory computer-readable storage medium. The memory 820 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 820 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created based on the use of the electronic device, etc.

[0081] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above figures does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0082] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the video memory prefetching method as described in the above embodiments.

[0083] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the memory prefetching method described in the above embodiments.

[0084] This disclosure also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described video memory prefetch method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0085] It should be understood that the chip mentioned in the embodiments of this disclosure may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0086] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, servers, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0087] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0089] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0090] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0091] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0092] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A video memory prefetching method, characterized in that, The video memory prefetching method includes: Based on the application's historical video memory usage data, determine the application's video memory operation sequence; The target read data instruction is determined based on the video memory operation sequence; Based on the target read data instruction, the data corresponding to the target read data instruction is read from the video memory and pre-stored into the memory buffer.

2. The memory prefetching method according to claim 1, characterized in that, The determination of the application's video memory operation sequence based on the application's historical video memory usage data includes: Based on the application scenario, the historical video memory usage data is classified to obtain sub-historical video memory usage data corresponding to each application scenario. Based on the sub-historical video memory usage data corresponding to each application scenario, determine the scene video memory operation sequence corresponding to each application scenario included in the video memory operation sequence; The step of determining the target read data instruction based on the video memory operation sequence includes: The target read data instruction is determined based on the scene memory operation sequence corresponding to the current application scenario.

3. The memory prefetching method according to claim 1, characterized in that, The step of determining the target read data instruction based on the video memory operation sequence includes: Based on the memory operation sequence, multiple prefetch data instructions are determined; The multiple pre-read data instructions are merged in address order to obtain the target read data instruction.

4. The memory prefetching method according to claim 1, characterized in that, The video memory prefetching method further includes: During the timeout period, multiple write data requests from the application are sorted by address and merged to obtain a merged write data request. After the timeout, a write operation is performed on the video memory based on the merged write data request.

5. The video memory prefetching method according to claim 4, characterized in that, The video memory prefetching method further includes: If the PCIe bus occupancy rate is less than or equal to the occupancy rate threshold and the video memory idle rate is greater than or equal to the idle rate threshold during the timeout period, then a write operation is performed on the video memory based on the merged write data request. The step of performing a write operation on the video memory based on the merged write data request after the timeout includes: If the PCIe bus occupancy rate is greater than the occupancy rate threshold or the video memory idle rate is greater than the idle rate threshold during the timeout period, then a write operation will be performed on the video memory based on the merged write data request after the timeout.

6. The video memory prefetching method according to claim 1, characterized in that, The video memory prefetching method further includes: Based on the application's read data request, search for the corresponding requested data from the memory buffer; If the memory buffer contains the corresponding request data, the corresponding request data is obtained from the memory buffer. If the memory buffer does not contain the corresponding requested data, the corresponding requested data is retrieved from the video memory.

7. A video memory prefetching system, characterized in that, The video memory prefetch system includes: The program execution pattern learning unit is configured to determine the application's memory operation sequence based on the application's historical memory usage data. The cache management unit is configured to determine the target read data instruction based on the video memory operation sequence and send it to the read / write scheduling unit; The read / write scheduling unit is configured to read data corresponding to the target read data instruction from the video memory and send it to the cache management unit based on the target read data instruction. The cache management unit is also configured to pre-store the data corresponding to the target read data instruction into the memory buffer.

8. A video memory prefetching device, characterized in that, The video memory prefetching device includes: a determination module and a read and store module; The determining module is used to determine the video memory operation sequence of the application based on the application's historical video memory usage data. And, based on the memory operation sequence, determine the target read data instruction; The read and store module is used to read the data corresponding to the target read data instruction from the video memory and pre-store it into the memory buffer based on the target read data instruction.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the video memory prefetch method as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the video memory prefetch method as described in any one of claims 1 to 6.

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