Project-level board card generation method and device, board card, medium and product

Abstract

The invention relates to the technical field of chips, and discloses an engineering-level board card generation method and device, a board card, a medium and a product. The method comprises the following steps: acquiring health states corresponding to intellectual property cores in an initial board card, and acquiring a dependency relationship among the intellectual property cores; according to the health state corresponding to each intellectual property core and the dependency relationship among the intellectual property cores, carrying out associated cutting on each intellectual property core to obtain the working state corresponding to each intellectual property core; and obtaining a target result corresponding to each test case according to the working state corresponding to each intellectual property core, and determining the initial board card as an engineering-level board card when the screening test result corresponding to the initial board card is detected to pass the screening test according to the target result corresponding to each test case. According to the scheme of the embodiment, the defective chip can be effectively utilized, and the product research and development progress can be accelerated while resource waste is avoided.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method, apparatus, board, medium and product for generating engineering-grade boards. Background Technology

[0002] As the complexity of AI chip design continues to increase, the yield rate of early-stage chip production is low, with over 50% potentially being defective, especially before manufacturing processes and equipment are fully developed. Utilizing these defective chips is crucial for avoiding resource waste and improving development efficiency.

[0003] Currently, for chips with a small number of defective subsystems, commercial utilization is typically achieved by creating low- to mid-range inventory units. However, this approach still has limitations. Firstly, even low- to mid-range inventory units must be functionally complete chips, thus usually only allowing one or two defects in one or two subsystems. Only a small fraction of the initial low-yield defective products meet this requirement. Secondly, only a few specific subsystems with redundant designs can be made into low- to mid-range inventory units through trimming. If other subsystems fail during automated testing, the entire chip is rendered unusable. Therefore, current technology still involves significant resource waste, reducing the number of usable chips in subsequent development stages and impacting the progress of chip verification and upper-layer software development. Summary of the Invention

[0004] This invention provides a method, apparatus, board, medium, and product for generating engineering-grade boards, which can effectively utilize defective chips and accelerate product development while avoiding resource waste.

[0005] According to one aspect of the present invention, a method for generating an engineering-grade board is provided, comprising:

[0006] Obtain the health status of each intellectual property core in the initial board and obtain the dependency relationships between each intellectual property core;

[0007] Based on the health status of each intellectual property core and the dependencies between each intellectual property core, the intellectual property cores are pruned together to obtain the working status of each intellectual property core.

[0008] Based on the working status of each intellectual property core, the target result corresponding to each test case is obtained, and when the screening result corresponding to the initial board is detected as passing the screening based on the target result corresponding to each test case, the initial board is determined to be an engineering-level board.

[0009] According to another aspect of the present invention, an apparatus for generating engineering-grade circuit boards is provided, comprising:

[0010] The dependency acquisition module is used to obtain the health status of each intellectual property core in the initial board and to obtain the dependency relationships between each intellectual property core.

[0011] The working status acquisition module is used to perform joint pruning on each intellectual property core according to the health status of each intellectual property core and the dependency relationship between each intellectual property core, and to obtain the working status of each intellectual property core.

[0012] The target result acquisition module is used to acquire the target result corresponding to each test case based on the working status of each intellectual property core, and when the initial board is detected to have passed the screening result based on the target result corresponding to each test case, the initial board is identified as an engineering-level board.

[0013] According to another aspect of the present invention, a circuit board is provided, the circuit board comprising:

[0014] At least one processor, and

[0015] A memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the method for generating an engineering-grade board according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, the computer program being configured to cause a processor to execute and implement the method for generating an engineering-grade board according to any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method for generating engineering-grade boards according to any embodiment of the present invention.

[0019] The technical solution of this invention involves obtaining the health status of each intellectual property core in the initial board and the dependencies between them; based on the health status and dependencies of each intellectual property core, the intellectual property cores are pruned to obtain their working status; based on their working status, the target results of each test case are obtained; and when the initial board is found to have passed the screening test based on the target results of each test case, it is designated as an engineering-grade board. By pruning intellectual property cores with abnormal health status based on their dependencies and testing and screening the pruned board using test cases, a final engineering-usable board can be obtained. This approach enables the effective utilization of defective chips and accelerates product development while avoiding resource waste.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a method for generating an engineering-grade board according to Embodiment 1 of the present invention;

[0023] Figure 2 This is a flowchart of a method for generating an engineering-grade board according to Embodiment 2 of the present invention;

[0024] Figure 3 This is a flowchart of another method for generating an engineering-grade board according to Embodiment 2 of the present invention;

[0025] Figure 4 This is a schematic diagram of the structure of an engineering-grade board generation device according to Embodiment 3 of the present invention;

[0026] Figure 5 This is a schematic diagram of the structure of a board for implementing the method of generating an engineering-level board according to an embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," "target," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] Example 1

[0030] Figure 1 The flowchart of an engineering-grade board generation method provided in Embodiment 1 of the present invention is applicable to the situation of manufacturing engineering-usable boards using defective chips. The method can be executed by an engineering-grade board generation device, which can be implemented in hardware and / or software. Typically, the engineering-grade board generation device can be configured in the board.

[0031] like Figure 1 As shown, the method includes:

[0032] S110. Obtain the health status of each intellectual property core in the initial board and obtain the dependency relationship between each intellectual property core.

[0033] In this embodiment, after automating the testing and sorting of chips using Automatic Test Equipment (ATE), it is possible to determine whether each Intellectual Property Core (IP) is defective and which specific part is defective, thereby obtaining the health status of each IP. For example, if the ATE marks an IP as defective, then the health status of that IP is determined to be unhealthy; if the ATE marks an IP as not defective, then the health status of that IP is determined to be healthy. Subsequently, the health status of each IP can be written into the One-Time Programmable (OTP) memory in the chip, and an initial board can be fabricated using the chip containing the OTP information.

[0034] Upon power-up, the firmware reads information from the OTP (Optical Pointer) to obtain the health status of each IP. Simultaneously, the firmware can determine the dependencies between IPs based on a pre-defined dependency table. This dependency table can be pre-obtained during chip and board design.

[0035] Optionally, obtaining the dependencies between the various intellectual property cores may include:

[0036] Obtain the register-transfer level design requirements, and based on the register-transfer level design requirements, obtain the dependencies between each intellectual property core.

[0037] Understandably, the binding or dependency relationships between IPs are typically determined during the chip design phase. Therefore, in this embodiment, the Register Transfer Level (RTL) design text can be obtained, and natural language processing techniques can be used to extract its content to obtain the RTL design requirements. Then, based on these RTL design requirements, it can be determined whether each IP has dependencies on other IPs to determine the dependencies between them.

[0038] For example, in the Global Control Unit (GCU), the system-level package and its L1 cache are likely to be strongly bound together in the RTL design. In this case, if the system-level package is unhealthy, even if the L1 cache is healthy, it cannot be used and needs to be removed together.

[0039] The advantage of the above settings is that they allow for accurate acquisition of dependencies between IPs, thereby improving the accuracy of related pruning.

[0040] S120. Based on the health status of each intellectual property core and the dependencies between each intellectual property core, perform joint pruning on each intellectual property core to obtain the working status of each intellectual property core.

[0041] In this embodiment, if an IP is detected to be in an unhealthy state, other IPs that depend on that IP can be found based on the dependencies between IPs. This unhealthy IP, along with all other found IPs, is then pruned, thus achieving the cascading pruning of defective IPs. Specifically, the pruned IPs are set to a disabled state, while the retained IPs are set to a working state, thus determining the working state of each IP and enabling only the retained IPs.

[0042] S130. Based on the working status corresponding to each intellectual property core, obtain the target result corresponding to each test case, and when the screening result corresponding to the initial board is detected as passing the screening based on the target result corresponding to each test case, determine the initial board as an engineering-level board.

[0043] In this embodiment, for the usable chips on the trimmed board, only the functionality of the usable portion is tested, thereby creating multiple types of engineering-grade boards. Specifically, after obtaining the working status of each IP, preset test cases can be used to test each IP based on its working status and preset test rules, and the test results of each test case are obtained as the target results. The preset test rules can be that if the working status of the IP is not working, the relevant test cases are skipped; if the working status of the IP is working, the relevant test cases are executed one by one. The target results can include working normally and not working normally. Further, it is determined whether there is a case of not working normally among all target results. If so, the initial board is determined to have failed the screening; otherwise, the initial board is determined to have successfully passed the screening, and thus the initial board can be identified as an engineering-grade board.

[0044] Among them, engineering-grade boards are mainly used by R&D engineers for engineering development and are not provided to customers for commercial use. In this embodiment, after identifying the engineering-grade boards, the result combinations corresponding to each engineering-grade board can be obtained based on the target results corresponding to each test case. Then, a unique identifier can be set for each result combination to classify the engineering-grade boards. R&D engineers can independently select the corresponding category of engineering-grade boards for the verification of relevant subsystems and the development of upper-layer software based on their respective areas of research focus.

[0045] The technical solution of this invention involves obtaining the health status of each intellectual property core in the initial board and the dependencies between them; based on the health status and dependencies of each intellectual property core, the intellectual property cores are pruned to obtain their working status; based on their working status, the target results of each test case are obtained; and when the initial board is found to have passed the screening test based on the target results of each test case, it is designated as an engineering-grade board. By pruning intellectual property cores with abnormal health status based on their dependencies and testing and screening the pruned board using test cases, a final engineering-usable board can be obtained. This approach enables the effective utilization of defective chips and accelerates product development while avoiding resource waste.

[0046] Example 2

[0047] Figure 2 This is a flowchart illustrating a method for generating an engineering-grade circuit board according to Embodiment 2 of the present invention. This embodiment is a further refinement of the above technical solution, and the technical solution in this embodiment can be combined with one or more of the above implementation methods. For example... Figure 2 As shown, the method includes:

[0048] S210. Obtain the health status of each intellectual property core in the initial board and obtain the dependency relationship between each intellectual property core.

[0049] S220. Obtain the engineering requirement rules, and based on the health status of each intellectual property core, the dependencies between each intellectual property core, and the engineering requirement rules, perform joint pruning on each intellectual property core to obtain the working status of each intellectual property core.

[0050] It's important to note that after tailoring based on IP dependencies, the engineering application significance must be considered. Only "low-spec" versions that meet engineering requirements can be used as engineering-grade boards. For example, a good chip might have four memory controllers (MCs), but only one can function, albeit with less storage space. After ATE screening, if MC0, MC2, and MC3 are healthy, but only MC1 is faulty, from an RTL design perspective, only MC1 needs to be removed, keeping the other three. However, from an engineering perspective, memory addresses must be contiguous. Gaps in the address space can cause issues with upper-layer software, and modifying the code of various layers for such special chips is not worthwhile. Therefore, an engineering requirement of "contiguous addresses" needs to be added. In this case, for chips where MC0, MC2, and MC3 are healthy, but only MC1 is faulty, the firmware will also remove MC2 and MC3, keeping only MC0.

[0051] In this embodiment, firstly, pre-set engineering requirement rules can be obtained; then, based on the health status of each IP and the dependencies between IPs, each IP is initially trimmed; then, based on the engineering requirement rules, the board after the initial trimming is trimmed again to complete the final trimming and obtain the working status of each IP.

[0052] Among these, engineering requirement rules can be set based on historical experience or relevant requirement documents. It is understandable that engineering requirement rules can be adaptively adjusted according to the task scenario.

[0053] S230. Initialize the intellectual property cores that are in working condition, and generate a mapping relationship between each intellectual property core and its corresponding working condition, storing it in the hardware information register.

[0054] Initialization may include operations such as enabling clock gating, providing power to the power domain, and granting bus access permissions. In this embodiment, only IPs in a working state are initialized; IPs in a non-working state are not initialized. Next, the trimming result is stored and displayed through a set of hardware information registers. Specifically, a mapping relationship between IPs and their working states is generated and stored in the hardware information registers. Different working states are represented by different values; for example, working corresponds to the value 1, and non-working corresponds to the value 0.

[0055] S240. Read the working status corresponding to each intellectual property core from the hardware information register, and obtain the execution requirements corresponding to each test case.

[0056] Specifically, before conducting actual testing using test cases, the firmware can first read the working status of each IP from the hardware information register, and simultaneously obtain the preset execution requirements for each test case. In this embodiment, the execution requirements for each test case can be preset. For example, the execution requirements may include executing the IP, the execution operation when the IP does not exist, and the execution operation when the IP exists.

[0057] S250. Based on the working status corresponding to each intellectual property core and the execution requirements corresponding to each test case, obtain the expected results and actual results corresponding to each test case, and based on the expected results and actual results, obtain the target results corresponding to each test case.

[0058] Specifically, before conducting actual test case testing, the expected results for each test case are obtained based on the working status of each IP and the execution requirements of each test case. Expected results can include whether the test case is expected to work or not. Then, actual testing is performed based on the test cases to obtain the actual results for each test case. Actual results can include whether the test case actually works, does not work, or is skipped. Finally, the target results for each test case can be obtained by combining the expected and actual results. Typically, target results can include expected to work - actually works, expected to work - actually does not work, and expected not to work - test skipped, etc.

[0059] Optionally, based on the working status corresponding to each intellectual property core and the execution requirements corresponding to each test case, obtaining the expected and actual results corresponding to each test case may include:

[0060] Based on the execution requirements of the current test case, obtain the current intellectual property core corresponding to the current test case;

[0061] If the current working status of the intellectual property core is not working, then the expected result of the current test case is expected to be not working, and the execution of the current test case is skipped;

[0062] If the current working status of the intellectual property core is "working", then the expected result of the current test case is "expected to work", and the current test case is executed through the current intellectual property core to obtain the actual result of the current test case.

[0063] In one optional implementation, firstly, based on the execution requirements corresponding to the current test case, the execution IP of the current test case is obtained and used as the current IP; then, it is determined whether the working status corresponding to the current IP is "not working". If so, the expected result of the current test case is determined to be "expected not working", and the execution of the current test case is skipped. Under normal circumstances, the target result of the current test case is "expected not working" - the test is skipped.

[0064] If the current IP's working status is "working," then the expected result is first determined to be "expected to work." Next, based on the current test case, corresponding test instructions are written and sent to the current IP, and the instruction execution results are collected. If the instruction execution result matches the expected result, then the actual result is determined to be "actually working." If the instruction execution result does not match the expected result, then the actual result is determined to be "actually not working."

[0065] The advantage of the above settings is that they enable efficient and accurate acquisition of expected and actual results, thereby improving the accuracy of the target results.

[0066] S260. When the screening result corresponding to the initial board is detected as passing the screening based on the target result corresponding to each test case, the initial board is determined to be an engineering-grade board.

[0067] Optionally, based on the target results corresponding to each test case, detecting that the screening result corresponding to the initial board is passed can include:

[0068] Based on the target results corresponding to each test case, determine whether there are any target test cases that are expected to work but actually do not work. If it is determined that there are none, then the screening result corresponding to the initial board is determined to be a pass.

[0069] In an optional example, if the target result of the test case shows a situation where the expected function works but the actual function does not, the initial board is considered to have failed the screening; otherwise, the initial board is considered to have passed the screening.

[0070] The advantage of the above setup is that the same screening process can be used to screen good products and a variety of defective products. It does not require additional production time or costs due to the wide variety of defects in the chips, and can reduce screening costs while improving screening efficiency.

[0071] The technical solution of this invention obtains engineering requirement rules and, based on the health status of each intellectual property core, the dependencies between intellectual property cores, and the engineering requirement rules, performs joint pruning on each intellectual property core to obtain its working status. By combining the dependencies between IPs and the engineering requirement rules to jointly prune defective IPs, the accuracy of pruning can be improved, and the engineering availability of engineering-level boards can be enhanced. After obtaining the working status of each intellectual property core, the intellectual property cores with a working status are initialized, and a mapping relationship between each intellectual property core and its corresponding working status is generated and stored in a hardware information register. From the hardware information register, the working status of each intellectual property core is read, and the execution requirements of each test case are obtained. Based on the working status of each intellectual property core and the execution requirements of each test case, the expected results and actual results of each test case are obtained, and the target results of each test case are obtained based on the expected results and actual results. By combining the expected results and actual results to obtain the final target results, the efficiency and accuracy of board screening can be improved.

[0072] In one specific embodiment of this example, the process of generating an engineering-grade board can be as follows: Figure 3 As shown. First, during the ATE testing phase, the health status of each IP is acquired: PASS for healthy and FAIL for unhealthy. This health status is stored in the OTP (Overlay Protocol), resulting in a chip with recorded OTP information. Next, the chip with OTP information is fabricated into an initial board. The firmware reads the health status of each IP within the OTP, and then, based on the dependencies between IPs and the project availability, each IP is harvested to obtain its corresponding working status. This working status is stored in a hardware information register HW_INFO. Further, only IPs with a working status are initialized, resulting in a board where only IPs marked "exist" in HW_INFO are initialized.

[0073] Finally, the card screening program reads the information in HW_INFO and, for each test case, determines whether the required IP exists (meaning it can work). If it does not exist, the result for the test case is C (expected not to work - test skipped). If it exists, the corresponding card screening test is executed using the test case to obtain the actual result, and it is determined whether the actual result is actually usable (PASS). If yes, the result for the test case is A (expected to work - actually works); if no, the result is B (expected to work - actually not works). If a card exhibits condition B, the screening is deemed failed (FAIL); if condition B does not exist, the screening is deemed passed (PASS).

[0074] It's important to note that existing technologies for creating inventory units are designed from a commercial perspective, aiming to produce fully functional boards from trimmed chips that are ready for user use. In contrast, the engineering-grade boards created in this invention are not intended for direct customer use. To save costs, incomplete functionality is permissible, retaining as many chips as possible for engineering development. Secondly, existing technologies typically offer only two to three types of inventory units, usually limited to scenarios with a large number of redundant IPs within subsystems. Currently, due to the recent shift of advanced manufacturing processes to domestic production, early chip yields are very low, and defective components are diverse, potentially arising from various subsystems. Utilizing these defective chips requires supporting a wide variety of inventory unit types, while this invention allows for dozens to hundreds of different types. Furthermore, the mixed-printing method provides a new approach for providing R&D cards during the new product introduction phase.

[0075] For R&D engineers, only chips with partially functional capabilities are needed to carry out their work. For example, engineers responsible for multimedia codec verification don't actually care whether the interconnect functionality is available; engineers responsible for developing interconnect modules don't care whether the card has 24 GCUs or only 4. In this case, many chips that would otherwise be considered scrap can be effectively utilized. Currently, 8 major categories and 47 subcategories of engineering-grade boards have been supported and produced.

[0076] Example 3

[0077] Figure 4 This is a schematic diagram of a device for generating an engineering-grade circuit board according to Embodiment 3 of the present invention. Figure 4 As shown, the device includes: a dependency acquisition module 310, a working status acquisition module 320, and a target result acquisition module 330; wherein,

[0078] The dependency acquisition module 310 is used to acquire the health status of each intellectual property core in the initial board and to acquire the dependency relationship between each intellectual property core.

[0079] The working status acquisition module 320 is used to perform joint pruning on each intellectual property core according to the health status of each intellectual property core and the dependency relationship between each intellectual property core, and to obtain the working status of each intellectual property core.

[0080] The target result acquisition module 330 is used to acquire the target result corresponding to each test case according to the working status of each intellectual property core, and when the initial board is detected to have passed the screening result according to the target result corresponding to each test case, the initial board is determined to be an engineering-level board.

[0081] The technical solution of this invention involves obtaining the health status of each intellectual property core in the initial board and the dependencies between them; based on the health status and dependencies of each intellectual property core, the intellectual property cores are pruned to obtain their working status; based on their working status, the target results of each test case are obtained; and when the initial board is found to have passed the screening test based on the target results of each test case, it is designated as an engineering-grade board. By pruning intellectual property cores with abnormal health status based on their dependencies and testing and screening the pruned board using test cases, a final engineering-usable board can be obtained. This approach enables the effective utilization of defective chips and accelerates product development while avoiding resource waste.

[0082] Optionally, the working status acquisition module 320 is specifically used to acquire the engineering requirement rules, and based on the health status of each intellectual property core, the dependency relationship between each intellectual property core and the engineering requirement rules, to perform joint pruning on each intellectual property core and acquire the working status of each intellectual property core.

[0083] Optionally, the apparatus for producing engineering-grade boards also includes:

[0084] The initialization module is used to initialize the intellectual property cores that are in a working state and generate a mapping relationship between each intellectual property core and its corresponding working state, which is then stored in the hardware information register.

[0085] Correspondingly, the target result acquisition module 330 is specifically used to read the working status corresponding to each of the intellectual property cores from the hardware information register, and to obtain the execution requirements corresponding to each of the test cases;

[0086] Based on the working status of each intellectual property core and the execution requirements of each test case, the expected results and actual results of each test case are obtained, and based on the expected results and actual results, the target results of each test case are obtained.

[0087] Optionally, the target result acquisition module 330 is specifically used to acquire the current intellectual property core corresponding to the current test case based on the execution requirements corresponding to the current test case;

[0088] If the current working status of the intellectual property core is not working, then the expected result of the current test case is expected to be not working, and the execution of the current test case is skipped;

[0089] If the current working status of the intellectual property core is "working", then the expected result of the current test case is "expected to work", and the current test case is executed through the current intellectual property core to obtain the actual result of the current test case.

[0090] Optionally, the target result acquisition module 330 is specifically used to determine, based on the target results corresponding to each test case, whether there are any target test cases whose expected result is that they can work, but whose actual result is that they cannot work. If it is determined that they do not exist, then the screening result corresponding to the initial board is determined to be that it passes the screening.

[0091] Optionally, the dependency acquisition module 310 is specifically used to acquire the register transfer level design requirements and, based on the register transfer level design requirements, acquire the dependency relationships between each intellectual property core.

[0092] The engineering-grade board generation apparatus provided in this embodiment of the invention can execute the engineering-grade board generation method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0093] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0094] Example 4

[0095] Figure 5 A schematic diagram of the structure of a board 40 that can be used to implement an embodiment of the present invention is shown. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0096] like Figure 5As shown, the board 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 and a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 42 or loaded from the storage unit 48 into the random access memory 43. The RAM 43 can also store various programs and data required for the operation of the board 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0097] Multiple components in board 40 are connected to I / O interface 45, including: input unit 46, output unit 47, storage unit 48, and communication unit 49. Communication unit 49 allows board 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0098] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, central processing units, graphics processing units, various special-purpose artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as the methods for generating engineering-grade boards.

[0099] In some embodiments, the method for generating an engineering-grade board can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program can be loaded and / or installed onto board 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the method for generating an engineering-grade board described above can be performed. Alternatively, in other embodiments, processor 41 can be configured to execute the method for generating an engineering-grade board by any other suitable means (e.g., by means of firmware).

[0100] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays, application-specific integrated circuits (ASICs), application-specific standard products (ASICs), systems-on-a-chip (SoCs), payload programmable logic devices, computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0101] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0102] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0103] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0104] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact via a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server.

[0105] This embodiment may also include a computer program product, which includes a computer program that, when executed by a processor, implements the method for generating engineering-grade boards provided in any embodiment of the present invention.

[0106] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0107] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for generating an engineering-grade circuit board, characterized in that, include: Obtain the health status of each intellectual property core in the initial board and obtain the dependency relationships between each intellectual property core; Based on the health status of each intellectual property core and the dependencies between each intellectual property core, the intellectual property cores are pruned together to obtain the working status of each intellectual property core. Based on the working status of each intellectual property core, the target result corresponding to each test case is obtained, and when the screening result corresponding to the initial board is detected as passing the screening based on the target result corresponding to each test case, the initial board is determined to be an engineering-level board.

2. The method according to claim 1, characterized in that, Based on the health status of each intellectual property core and the dependencies between them, the intellectual property cores are pruned together to obtain their respective working statuses, including: Obtain the engineering requirement rules, and based on the health status of each intellectual property core, the dependencies between each intellectual property core, and the engineering requirement rules, perform joint pruning on each intellectual property core to obtain the working status of each intellectual property core.

3. The method according to claim 1, characterized in that, After performing joint pruning on each intellectual property core based on its health status and the dependencies between them to obtain the working status of each intellectual property core, the process further includes: Initialize the intellectual property cores that are in a working state, and generate a mapping relationship between each intellectual property core and its corresponding working state, which is then stored in the hardware information register. Based on the working status corresponding to each intellectual property core, obtain the target results corresponding to each test case, including: Read the working status corresponding to each intellectual property core from the hardware information register, and obtain the execution requirements corresponding to each test case; Based on the working status of each intellectual property core and the execution requirements of each test case, the expected results and actual results of each test case are obtained, and based on the expected results and actual results, the target results of each test case are obtained.

4. The method according to claim 3, characterized in that, Based on the working status corresponding to each intellectual property core and the execution requirements corresponding to each test case, obtain the expected results and actual results corresponding to each test case, including: Based on the execution requirements of the current test case, obtain the current intellectual property core corresponding to the current test case; If the current working status of the intellectual property core is not working, then the expected result of the current test case is expected to be not working, and the execution of the current test case is skipped; If the current working status of the intellectual property core is "working", then the expected result of the current test case is "expected to work", and the current test case is executed through the current intellectual property core to obtain the actual result of the current test case.

5. The method according to claim 3, characterized in that, Based on the target results corresponding to each test case, the initial board was found to have passed the screening test, including: Based on the target results corresponding to each test case, determine whether there are any target test cases that are expected to work but actually do not work. If it is determined that there are none, then the screening result corresponding to the initial board is determined to be a pass.

6. The method according to claim 1, characterized in that, Obtain the dependencies between the various intellectual property cores, including: Obtain the register-transfer level design requirements, and based on the register-transfer level design requirements, obtain the dependencies between each intellectual property core.

7. An apparatus for generating engineering-grade circuit boards, characterized in that, include: The dependency acquisition module is used to obtain the health status of each intellectual property core in the initial board and to obtain the dependency relationships between each intellectual property core. The working status acquisition module is used to perform joint pruning on each intellectual property core according to the health status of each intellectual property core and the dependency relationship between each intellectual property core, and to obtain the working status of each intellectual property core. The target result acquisition module is used to acquire the target result corresponding to each test case based on the working status of each intellectual property core, and when the initial board is detected to have passed the screening result based on the target result corresponding to each test case, the initial board is identified as an engineering-level board.

8. A circuit board, characterized in that, The board includes: At least one processor, and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method for generating an engineering-grade board according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method for generating an engineering-grade board according to any one of claims 1-6.

10. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method for generating an engineering-grade board according to any one of claims 1-6.

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