System clock synchronization method and device, storage medium and electronic equipment

Abstract

The invention discloses a system clock synchronization method and device, a storage medium and electronic equipment, and the method comprises the steps: setting a master controller as a master node, setting external system equipment as a slave node, collecting the crystal oscillator frequency of the external system equipment, and transmitting the crystal oscillator frequency to the master node; performing frequency mixing on the crystal oscillator frequency and the reference frequency to obtain a heterodyne signal, and performing filtering processing on the heterodyne signal to obtain a difference frequency component; calculating transmission time delay and frequency drift time delay between the master node and the slave node, and obtaining correction time according to the transmission time delay, the frequency drift time delay and the difference frequency component; and sending the correction time to external system equipment for time synchronization.

Description

Technical Field

[0001] This invention relates to the field of gas turbine system time synchronization technology, specifically to a system clock synchronization method, device, storage medium, and electronic equipment. Background Technology

[0002] With the rapid development of computer and network communication technologies, the era of digital and networked automation systems has arrived. On the one hand, this provides a better platform for data exchange, analysis, and application between various control and information systems; on the other hand, it also places higher demands on the accuracy of time stamps for various real-time and historical data. In the field of gas turbines, precise time synchronization of the gas turbine control system is crucial to ensuring the stability and safety of the system. All components in the control system, such as sensors, actuators, controllers, and data acquisition systems, must be synchronized in time to achieve accurate control and monitoring functions.

[0003] Currently, GPS / BeiDou time synchronization systems are widely used as time references in gas turbine control systems. This system receives Coordinated Universal Clock (UTC) signals from GPS / BeiDou satellites as an external time reference, outputs a 1PPS pulse with a time accuracy of 150ns, and provides international standard time, date, and the receiver's geographical location (latitude and longitude). Utilizing GPS / BeiDou satellite-synchronized clocks covers all time-synchronized equipment in the gas turbine power plant, such as control systems TCS & SIS, DCS, plant-level monitoring information systems (SIS), and power plant management information systems (MIS), achieving unified time across the entire plant. With the development of time synchronization technology, some time synchronization system equipment supports precise time protocols such as NTP and PTP, further enhancing the accuracy of the gas turbine power plant's time synchronization system.

[0004] However, gas turbines need to adapt to various loads (no-load / full-load) and environmental conditions (external environment such as temperature and humidity) under different operating conditions, resulting in complex and variable operating conditions. This requires the control system to be able to respond quickly to changes in complex operating conditions, and the plant-wide monitoring system to monitor various parameters of the gas turbine in real time and provide timely early warnings and alarms to maintain the stable operation of the gas turbine. With the development and application of "smart operation and maintenance" technologies such as fault identification and health management systems for heavy-duty gas turbines at home and abroad, not only will the number of devices connected to the plant-wide clock synchronization system increase, but this will also form a large-scale big data system, putting enormous pressure on network load and data scheduling. This requires the plant-wide clock synchronization system to adapt to this change, and the current solution cannot meet this requirement.

[0005] Patent document CN114884602B discloses a clock synchronization control method and system, including: after the main controller acquires clock signals generated by multiple clock sources, acquiring the timing duration of each clock source when the high-precision timer in the main controller is set to a preset duration; selecting a target clock source from the multiple clock sources according to the preset duration and the timing duration of each clock source; adjusting the current time of the main controller according to the current time of the target clock source, and synchronizing the adjusted time of the main controller to the slave controller; however, this method does not solve the problems of rapid response, real-time monitoring and early warning of gas turbines under complex operating conditions, as well as the pressure of big data systems and network loads.

[0006] US patent document US20240214095A1 discloses a clock synchronization method and control system for a control system, the control system including a first controller and a second controller. In some embodiments, the first controller includes a first clock unit and a second clock unit, and the second controller includes a third clock unit. In some embodiments, the clock of the first clock unit may be different from the clock of the third clock unit, and the clock of the second clock unit may be the same as the clock of the third clock unit. In some embodiments, a method includes the first controller and the second controller adding a timestamp to sensor data using a first clock. In some embodiments, the first clock is either the clock of the first clock unit or the clock of the third clock unit, but this does not solve the problems of rapid response, real-time monitoring and early warning of gas turbines under complex operating conditions, and coping with the pressure of big data systems and network loads.

[0007] In summary, neither of the two existing patents mentioned above has solved the problems of rapid response, real-time monitoring and early warning of gas turbines under complex operating conditions, as well as the pressure of big data systems and network loads. Summary of the Invention

[0008] Based on the above-mentioned technical problems, this invention proposes a system clock synchronization method, device, storage medium, and electronic equipment to solve the problems of rapid response, real-time monitoring and early warning of gas turbines under complex operating conditions, as well as coping with the pressure of big data systems and network loads.

[0009] To achieve the above objectives, this invention proposes a system clock synchronization method.

[0010] A system clock synchronization method, comprising:

[0011] Set the main controller as the master node and the external system devices as slave nodes, and collect the crystal oscillator frequency of the external system devices and send it to the master node;

[0012] The heterodyne signal obtained by mixing the crystal oscillator frequency with the reference frequency is then filtered to obtain the difference frequency component.

[0013] Calculate the transmission delay and frequency drift delay between the master node and the slave node, and obtain the correction time based on the transmission delay, the frequency drift delay, and the difference frequency component;

[0014] The corrected time is sent to the external system device for time synchronization.

[0015] Further, the heterodyne signal obtained by mixing the crystal oscillator frequency with the reference frequency includes:

[0016] The heterodyne signal is obtained by multiplying the crystal oscillator frequency and the reference frequency. The heterodyne signal includes a sum frequency component and a difference frequency component.

[0017] Further, the heterodyne signal is filtered to obtain the difference frequency component, including:

[0018] The heterodyne signal is filtered by a filter to remove the sum frequency component and obtain the difference frequency component.

[0019] Further, the transmission delay and frequency drift delay between the master node and the slave node are calculated, including:

[0020] Based on the time synchronization messages sent and received between the master node and the slave node, the corresponding timestamps are extracted, and the transmission delay is obtained based on the timestamps.

[0021] Further, the transmission delay and frequency drift delay between the master node and the slave node are calculated, including:

[0022] The frequency drift delay is obtained based on the frequency of the master node, the frequency of the slave node, and the synchronization period.

[0023] Further, obtaining the correction time based on the transmission delay, the frequency drift delay, and the difference frequency component includes:

[0024] Frequency difference compensation is obtained based on the frequency drift delay and the difference frequency component. The correction time is then obtained using Formula Two based on the frequency difference compensation and the transmission delay. (Formula Two...)

[0025] ΔT=Δt+f(ω n ,ω0,Δt′),

[0026] Where ΔT is the correction time, Δt is the transmission delay, Δt′ is the frequency drift delay, and ω n Let f(ω) be the angular frequency of the master node, ω0 be the angular frequency of the slave node, and f(ω) be the angular frequency of the slave node. n ,ω0,Δt′) is the frequency difference compensation obtained based on the difference frequency component and the frequency drift delay.

[0027] Furthermore, the crystal oscillator frequency includes:

[0028] Frequency information, phase information, and time reference.

[0029] Furthermore, the process of acquiring the crystal oscillator frequency of external system devices and sending it to the master node also includes:

[0030] The crystal oscillator frequency of the external system device is obtained using Formula 1 based on the frequency information, the phase information, and the time reference. Formula 1...

[0031] S = sin(ωt + Φ),

[0032] Where S is the crystal oscillator frequency, ω is the frequency information, t is the time reference, and Φ is the phase information.

[0033] Furthermore, the acquisition of the crystal oscillator frequency of external system devices and its transmission to the master node includes:

[0034] The message carrying the frequency information, the phase information, and the time reference is sent to the master node.

[0035] Furthermore, sending the corrected time to the external system device for time synchronization includes:

[0036] The message carrying the corrected time is sent to the external system device, and the time of the external system device is corrected according to the time of the external system device and the corrected time.

[0037] To achieve the above objectives, the present invention also proposes a system clock synchronization device.

[0038] A system clock synchronization device, characterized in that it comprises:

[0039] The data acquisition module is used to set the main controller as the master node, set external system devices as slave nodes, and acquire the crystal oscillator frequency of the external system devices and send it to the master node.

[0040] The heterodyne processing module is used to mix the crystal oscillator frequency with the reference frequency to obtain the heterodyne signal, and then filter the heterodyne signal to obtain the difference frequency component.

[0041] The error acquisition module is used to calculate the transmission delay and frequency drift delay between the master node and the slave node, and to obtain the correction time based on the transmission delay, the frequency drift delay and the difference frequency component;

[0042] An error correction module is used to send the corrected time to the external system device for time synchronization.

[0043] Based on the above technical solution, the present invention has at least the following beneficial effects:

[0044] 1. This invention proposes a system clock synchronization method, device, storage medium, and electronic device. The main controller is designated as the master node, and external system devices are designated as slave nodes. The crystal oscillator frequencies of the slave nodes are collected and sent to the master node, achieving real-time monitoring and compensation of the slave node crystal oscillator frequencies. The difference frequency component is obtained through mixing and filtering, and the correction time is calculated by combining transmission delay and frequency drift delay. Finally, the corrected time is sent to the external system devices for time synchronization. This invention effectively solves the clock synchronization accuracy problem caused by crystal oscillator frequency differences in existing technologies, significantly improving the accuracy and stability of gas turbine system clock synchronization. By monitoring and compensating for the crystal oscillator frequencies of the slave nodes in real time, the stability and reliability of the system under different operating conditions are ensured, while the time synchronization process is optimized, improving the overall system performance.

[0045] 2. This invention proposes a system clock synchronization method, device, storage medium, and electronic equipment. It acquires the crystal oscillator frequency of slave nodes and performs real-time compensation, combining mixing and filtering to obtain the difference frequency component, and calculates and corrects transmission delay and frequency drift delay, significantly improving the accuracy and stability of clock synchronization in gas turbine systems. Specifically, this method not only effectively solves the problem of crystal oscillator frequency differences caused by environmental changes, load variations, and equipment aging, ensuring the stability and reliability of the clock synchronization system under complex operating conditions, but also enhances the system's adaptability to different operating conditions. This high-precision, high-stability, and highly adaptable clock synchronization method provides a strong guarantee for the stable operation of gas turbine systems.

[0046] 3. This invention proposes a system clock synchronization method, device, storage medium, and electronic equipment. By adopting the P2P mechanism of the gPTP protocol and the data link layer working mode, it optimizes network transmission latency and avoids the uncertainty and fluctuation of network latency in the traditional E2E mechanism, thereby significantly improving the stability and accuracy of time synchronization. This optimization is not only suitable for the complex network environment of gas turbine industrial sites, but also enhances the system's scalability and adaptability. It can effectively cope with the pressure of increased equipment access and the formation of big data systems, support large-scale equipment access, and ensure the efficient operation of the plant-wide clock synchronization system. In addition, high-precision clock synchronization provides a more accurate time reference for the plant-wide monitoring system, enabling more timely monitoring of various gas turbine parameters and issuing early warning alarms, thereby helping to quickly respond to complex operating condition changes and maintain the stable operation of the gas turbine. Attached Figure Description

[0047] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0048] Figure 1 A flowchart of a system clock synchronization method according to one embodiment is shown;

[0049] Figure 2 A schematic diagram of the structure of a system clock synchronization device according to one embodiment is shown;

[0050] Figure 3 A schematic diagram of the structure of a system clock synchronization product according to one embodiment is shown;

[0051] Figure 4 A schematic diagram of the structure of an electronic device according to an embodiment is shown. Detailed Implementation

[0052] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0053] The present invention will be further described in detail below with reference to specific embodiments, which should not be construed as limiting the scope of protection claimed by the present invention.

[0054] Example

[0055] To address the challenges of rapid response, real-time monitoring and early warning of gas turbines under complex operating conditions, as well as the pressure of big data systems and network loads, this invention proposes a system clock synchronization method, device, storage medium, and electronic equipment.

[0056] To achieve the above objectives, the present invention also proposes a system clock synchronization method.

[0057] like Figure 1 The figure illustrates a system clock synchronization method according to an embodiment of the present invention. The process mainly includes the following steps:

[0058] S101: Set the main controller as the master node, set the external system device as the slave node, and collect the crystal oscillator frequency of the external system device and send it to the master node.

[0059] Furthermore, the external system equipment includes equipment in the gas turbine control and protection system, the plant-wide MIS / SIS system, and the electrical system; in other embodiments, it may also include equipment in other gas turbine operating systems. The crystal oscillator frequency is a stable periodic clock signal, including frequency information, phase information, and a time reference, wherein the frequency information includes angular frequency.

[0060] Furthermore, the crystal oscillator frequency is obtained based on the acquired frequency information, phase information, and time reference of the external system, as expressed below:

[0061] S = sin(ωt + Φ),

[0062] Where S is the crystal oscillator frequency, ω is the frequency information, t is the time reference, and Φ is the phase information.

[0063] Specifically, the crystal oscillator frequencies of the equipment in the gas turbine control and protection system, the plant-wide MIS / SIS system, and the electrical system are calculated and denoted as S1, S2, and S3, respectively. S1, S2, and S3 are then sent to the master node via messages.

[0064] S102: The heterodyne signal obtained by mixing the crystal oscillator frequency with the reference frequency is filtered to obtain the difference frequency component.

[0065] Furthermore, a reference frequency S0 is preset, and the expression for S0 is as follows:

[0066] S0 = sin(ω0t + Φ0),

[0067] Where S0 is the reference frequency, ω0 is the reference frequency information, t is the time base, and Φ0 is the reference phase information. The preset reference frequency, reference frequency information, time base, reference phase information, and preset reference frequency are all determined based on the specific crystal oscillator used in the hardware design.

[0068] Furthermore, the heterodyne signal is obtained through the heterodyne method. The reference frequency is multiplied by the crystal oscillator frequency obtained above to obtain the heterodyne signal. The reference frequency and crystal oscillator frequency are then calculated using trigonometric identities, and the expression is as follows:

[0069]

[0070] Where S0 is the reference frequency, S1 is the crystal frequency, S1·S0 is the heterodyne signal, ω0 is the reference frequency information, ω1 is the frequency information, t is the time base, Φ0 is the reference phase information, Φ1 is the phase information, cos((ω1-ω0)t+(Φ1-Φ0)) is the difference frequency component, and cos((ω1+ω0)t+(Φ1+Φ0)) is the sum frequency component. The sum frequency component is filtered out by a filter, and the difference frequency component is retained.

[0071] Furthermore, the frequency difference |ω1-ω0| is extracted based on the difference frequency component.

[0072] S103: Calculate the transmission delay and frequency drift delay between the master node and the slave node, and obtain the correction time based on the transmission delay, the frequency drift delay and the difference frequency component.

[0073] Furthermore, based on the synchronization messages sent and received between the master node and the slave node, the corresponding timestamps are extracted to obtain the transmission delay.

[0074] Specifically, the timestamp for the master node sending a message to the slave node is t1, the timestamp for the slave node receiving a message is t2, the timestamp for the slave node sending an acknowledgment message is t3, and the timestamp for the master node receiving a message from the slave node is t4. The expression for calculating the transmission delay is as follows:

[0075]

[0076] Where Δt is the transmission delay.

[0077] Furthermore, the frequency drift delay is obtained based on the frequency of the master node, the frequency of the slave node, and the synchronization period, and its expression is as follows:

[0078]

[0079] Where Δt′ is the frequency drift delay, f1 is the frequency of the slave node, f0 is the frequency of the master node, and T is the synchronization period.

[0080] Furthermore, frequency difference compensation is obtained based on the frequency drift delay and the difference frequency component. The correction time is obtained using Formula 2 based on the frequency difference compensation and the transmission delay, and its expression is as follows:

[0081] ΔT=Δt+f(ω n ,ω0,Δt′),

[0082] Where ΔT is the correction time, Δt is the transmission delay, Δt′ is the frequency drift delay, and ω n ω0 is the angular frequency of the master node, and ω0 is the angular frequency of the slave node. n The frequency difference compensation (ω0, Δt′) is obtained based on the difference frequency component and frequency drift delay. The frequency difference compensation is calculated as follows:

[0083]

[0084] Where α∈[0,1] is an adjustable weighting factor, in this embodiment α=0.5, |ω1-ω0| is the frequency difference extracted from the difference frequency component, Δt′ is the frequency drift delay, ω0 is the reference frequency information, and ω1 is the frequency information.

[0085] S104: Send the corrected time to the external system device for time synchronization.

[0086] Furthermore, a message carrying the corrected time is sent to the external system device, and the time of the external system device is corrected according to the time of the external system device and the corrected time.

[0087] Specifically, the expression for correcting the time of external system devices is as follows:

[0088] T SYNC =ΔT+T ext ,

[0089] Where T SYNC The corrected device time is ΔT, where ΔT is the correction time. ext Use the device's local time.

[0090] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0091] Based on another aspect of the embodiments of this application, the present invention also provides a system clock synchronization device, such as... Figure 2 As shown, the device includes:

[0092] The data acquisition module 201 is used to set the main controller as the master node, set the external system devices as slave nodes, and acquire the crystal oscillator frequency of the external system devices and send it to the master node.

[0093] The heterodyne processing module 202 is used to mix the crystal oscillator frequency with the reference frequency to obtain the heterodyne signal, and to filter the heterodyne signal to obtain the difference frequency component.

[0094] Error acquisition module 203 is used to calculate the transmission delay and frequency drift delay between the master node and the slave node, and obtain the correction time based on the transmission delay, the frequency drift delay and the difference frequency component;

[0095] Error correction module 204 is used to send the corrected time to the external system device for time synchronization.

[0096] As an optional solution, the above-mentioned device is also used to: obtain a heterodyne signal by mixing the crystal oscillator frequency with the reference frequency, including: multiplying the crystal oscillator frequency and the reference frequency to obtain the heterodyne signal, wherein the heterodyne signal includes a sum frequency component and a difference frequency component.

[0097] As an optional solution, the above-mentioned device is further used to: filter the heterodyne signal to obtain the difference frequency component, including: filtering the heterodyne signal through a filter to remove the sum frequency component and obtain the difference frequency component.

[0098] As an optional solution, the above-mentioned device is also used to: calculate the transmission delay and frequency drift delay between the master node and the slave node, including: extracting the corresponding timestamps based on the time synchronization messages sent and received between the master node and the slave node, and obtaining the transmission delay based on the timestamps.

[0099] As an optional solution, the above-mentioned device is also used to: calculate the transmission delay and frequency drift delay between the master node and the slave node, including: obtaining the frequency drift delay based on the frequency of the master node, the frequency of the slave node and the synchronization period.

[0100] As an optional solution, the above-mentioned device is further configured to: obtain a correction time based on the transmission delay, the frequency drift delay, and the difference frequency component, including: obtaining frequency difference compensation based on the frequency drift delay and the difference frequency component, and obtaining the correction time based on the frequency difference compensation and the transmission delay using Formula Two, wherein Formula Two...

[0101] ΔT=Δt+f(ω n ,ω0,Δt′),

[0102] Where ΔT is the correction time, Δt is the transmission delay, Δt′ is the frequency drift delay, and ω n Let f(ω) be the angular frequency of the master node, ω0 be the angular frequency of the slave node, and f(ω) be the angular frequency of the slave node. n ,ω0,Δt′) is the frequency difference compensation obtained based on the difference frequency component and the frequency drift delay.

[0103] As an optional solution, the above-mentioned device is further used to: acquire the crystal oscillator frequency of the external system device and send it to the master node, and further includes: obtaining the crystal oscillator frequency of the external system device according to the frequency information, the phase information and the time base using Formula 1, wherein Formula 1...

[0104] S = sin(ωt + Φ),

[0105] Where S is the crystal oscillator frequency, ω is the frequency information, t is the time reference, and Φ is the phase information.

[0106] As an optional solution, the above-mentioned device is also used to: collect the crystal oscillator frequency of external system devices and send it to the master node, including: sending a message carrying the frequency information, the phase information and the time reference to the master node.

[0107] As an optional solution, the above-mentioned device is further configured to: send the corrected time to the external system device for time synchronization, including: sending a message carrying the corrected time to the external system device, and correcting the time of the external system device according to the time of the external system device and the corrected time.

[0108] In this application embodiment, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0109] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0110] According to one aspect of this application, a computer program product is provided, the computer program product comprising a computer program.

[0111] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0112] Figure 3 A schematic block diagram of a computer system architecture for implementing an electronic device according to embodiments of the present application is shown.

[0113] It should be noted that, Figure 3 The computer system 300 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0114] like Figure 3 As shown, the computer system 300 includes a central processing unit (CPU) 301, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 302 or programs loaded from storage section 308 into random access memory (RAM). The RAM 303 also stores various programs and data required for system operation. The CPU 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output interface 305 (I / O interface) is also connected to the bus 304.

[0115] The following components are connected to the input / output interface 305: an input section 306 including a keyboard, mouse, etc.; an output section 307 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 308 including a hard disk, etc.; and a communication section 309 including a network interface card such as a local area network card, modem, etc. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the input / output interface 305 as needed. A removable medium 33, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 310 as needed so that computer programs read from it can be installed into the storage section 308 as needed.

[0116] Specifically, according to embodiments of this application, the processes described in the various method flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 309, and / or installed from removable medium 33. When the computer program is executed by central processing unit 301, it performs various functions defined in the system of this application.

[0117] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 309, and / or installed from removable medium 33. When the computer program is executed by central processing unit 301, it performs various functions provided in the embodiments of this application.

[0118] According to another aspect of the embodiments of this application, an electronic device for a system clock synchronization method is also provided. This embodiment uses a terminal device as an example for illustration. Figure 4 As shown, the electronic device includes a memory 402 and a processor 404. The memory 402 stores a computer program, and the processor 404 is configured to execute the steps in any of the above method embodiments via the computer program.

[0119] Optionally, in this embodiment, the aforementioned electronic device may be located in at least one of a plurality of network devices in a computer network.

[0120] Optionally, in this embodiment, the processor may be configured to execute the methods in the embodiments of this application via a computer program.

[0121] Alternatively, as those skilled in the art will understand, Figure 4 The structure shown is for illustrative purposes only. Figure 4 This does not limit the structure of the aforementioned electronic devices. For example, the electronic device may also include components that are more... Figure 4 The more or fewer components shown (such as network interfaces, etc.), or having the same Figure 4 The different configurations shown.

[0122] The memory 402 can be used to store software programs and modules, such as the program instructions / modules corresponding to the system clock synchronization method and apparatus in this embodiment. The processor 404 executes various functional applications and data processing by running the software programs and modules stored in the memory 402, thereby realizing the aforementioned system clock synchronization method. The memory 402 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 402 may further include memory remotely located relative to the processor 404, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. Specifically, the memory 402 may be used, but is not limited to, to store collected operational data or cleaned data information. As an example, such as... Figure 4 As shown, the memory 402 may include, but is not limited to, the acquisition module 201, heterodyne processing module 202, error acquisition module 203, and error correction module 204 in the aforementioned system clock synchronization device. Furthermore, it may include, but is not limited to, other module units in the aforementioned device, which will not be elaborated upon in this example.

[0123] Optionally, the transmission device 406 described above is used to receive or send data via a network. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 406 includes a Network Interface Controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In another example, the transmission device 406 is a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0124] In addition, the aforementioned electronic device also includes: a display 408 for displaying the aforementioned operating data or cleaning data; and a connection bus 410 for connecting the various module components in the aforementioned electronic device.

[0125] In other embodiments, the aforementioned terminal device or server can be a node in a distributed system, wherein the distributed system can be a blockchain system, which is a distributed system formed by connecting multiple nodes through network communication. The nodes can form a peer-to-peer network, and any form of computing device, such as a server, terminal, or other electronic device, can become a node in the blockchain system by joining this peer-to-peer network.

[0126] According to one aspect of this application, a computer-readable storage medium is provided, wherein a processor of an electronic device reads computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the electronic device to perform a system clock synchronization method provided in one of the various alternative implementations of the above-described system clock synchronization aspect.

[0127] Optionally, in this embodiment, the computer-readable storage medium described above may be configured to store methods for performing the embodiments of this application.

[0128] Optionally, in this embodiment, those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0129] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0130] If the integrated units in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in the aforementioned computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause one or more electronic devices to execute all or part of the steps of the methods described in the various embodiments of this application.

[0131] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0132] In the several embodiments provided in this application, it should be understood that the disclosed application can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

[0133] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0134] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0135] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0136] In summary, as can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0137] 1. This invention proposes a system clock synchronization method, device, storage medium, and electronic device. The main controller is designated as the master node, and external system devices are designated as slave nodes. The crystal oscillator frequencies of the slave nodes are collected and sent to the master node, achieving real-time monitoring and compensation of the slave node crystal oscillator frequencies. The difference frequency component is obtained through mixing and filtering, and the correction time is calculated by combining transmission delay and frequency drift delay. Finally, the corrected time is sent to the external system devices for time synchronization. This invention effectively solves the clock synchronization accuracy problem caused by crystal oscillator frequency differences in existing technologies, significantly improving the accuracy and stability of gas turbine system clock synchronization. By monitoring and compensating for the crystal oscillator frequencies of the slave nodes in real time, the stability and reliability of the system under different operating conditions are ensured, while the time synchronization process is optimized, improving the overall system performance.

[0138] 2. This invention proposes a system clock synchronization method, device, storage medium, and electronic equipment. It acquires the crystal oscillator frequency of slave nodes and performs real-time compensation, combining mixing and filtering to obtain the difference frequency component, and calculates and corrects transmission delay and frequency drift delay, significantly improving the accuracy and stability of clock synchronization in gas turbine systems. Specifically, this method not only effectively solves the problem of crystal oscillator frequency differences caused by environmental changes, load variations, and equipment aging, ensuring the stability and reliability of the clock synchronization system under complex operating conditions, but also enhances the system's adaptability to different operating conditions. This high-precision, high-stability, and highly adaptable clock synchronization method provides a strong guarantee for the stable operation of gas turbine systems.

[0139] 3. This invention proposes a system clock synchronization method, device, storage medium, and electronic equipment. By adopting the P2P mechanism of the gPTP protocol and the data link layer working mode, it optimizes network transmission latency and avoids the uncertainty and fluctuation of network latency in the traditional E2E mechanism, thereby significantly improving the stability and accuracy of time synchronization. This optimization is not only suitable for the complex network environment of gas turbine industrial sites, but also enhances the system's scalability and adaptability. It can effectively cope with the pressure of increased equipment access and the formation of big data systems, support large-scale equipment access, and ensure the efficient operation of the plant-wide clock synchronization system. In addition, high-precision clock synchronization provides a more accurate time reference for the plant-wide monitoring system, enabling more timely monitoring of various gas turbine parameters and issuing early warning alarms, thereby helping to quickly respond to complex operating condition changes and maintain the stable operation of the gas turbine.

[0140] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0141] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0142] It should be noted that, in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A system clock synchronization method, characterized in that, include: Set the main controller as the master node and the external system devices as slave nodes, and collect the crystal oscillator frequency of the external system devices and send it to the master node; The heterodyne signal obtained by mixing the crystal oscillator frequency with the reference frequency is then filtered to obtain the difference frequency component. Calculate the transmission delay and frequency drift delay between the master node and the slave node, and obtain the correction time based on the transmission delay, the frequency drift delay, and the difference frequency component; The corrected time is sent to the external system device for time synchronization.

2. The method according to claim 1, characterized in that, The heterodyne signal obtained by mixing the crystal oscillator frequency with the reference frequency includes: The heterodyne signal is obtained by multiplying the crystal oscillator frequency and the reference frequency. The heterodyne signal includes a sum frequency component and a difference frequency component.

3. The method according to claim 2, characterized in that, The heterodyne signal is filtered to obtain the difference frequency component, including: The heterodyne signal is filtered by a filter to remove the sum frequency component and obtain the difference frequency component.

4. The method according to claim 1, characterized in that, Calculating the transmission delay and frequency drift delay between the master node and the slave node includes: Based on the time synchronization messages sent and received between the master node and the slave node, the corresponding timestamps are extracted, and the transmission delay is obtained based on the timestamps.

5. The method according to claim 1, characterized in that, Calculating the transmission delay and frequency drift delay between the master node and the slave node includes: The frequency drift delay is obtained based on the frequency of the master node, the frequency of the slave node, and the synchronization period.

6. The method according to claim 1, characterized in that, Obtaining the correction time based on the transmission delay, the frequency drift delay, and the difference frequency component includes: Frequency difference compensation is obtained based on the frequency drift delay and the difference frequency component. The correction time is then obtained using Formula Two based on the frequency difference compensation and the transmission delay. (Formula Two...) ΔT=Δt+f(ω n ,ω0,Δt ′ ), Where ΔT is the correction time, Δt is the transmission delay, and Δt ′ For the frequency drift delay, ω n Let f(ω) be the angular frequency of the master node, ω0 be the angular frequency of the slave node, and f(ω) be the angular frequency of the slave node. n ,ω0,Δt ′ The frequency difference compensation is obtained based on the difference frequency component and the frequency drift delay.

7. The method according to claim 1, characterized in that, The crystal oscillator frequency includes: Frequency information, phase information, and time reference.

8. The method according to claim 7, characterized in that, The process of acquiring the crystal oscillator frequency of external system devices and sending it to the master node also includes: The crystal oscillator frequency of the external system device is obtained using Formula 1 based on the frequency information, the phase information, and the time reference. Formula 1... S = sin(ωt + Φ), Where S is the crystal oscillator frequency, ω is the frequency information, and t is the time reference. Φ represents the phase information.

9. The method according to claim 7, characterized in that, The process of acquiring the crystal oscillator frequency of external system devices and sending it to the master node includes: The message carrying the frequency information, the phase information, and the time reference is sent to the master node.

10. The method according to claim 1, characterized in that, Sending the corrected time to the external system device for time synchronization includes: The message carrying the corrected time is sent to the external system device, and the time of the external system device is corrected according to the time of the external system device and the corrected time.

11. A system clock synchronization device, characterized in that, include: The data acquisition module is used to set the main controller as the master node, set external system devices as slave nodes, and acquire the crystal oscillator frequency of the external system devices and send it to the master node. The heterodyne processing module is used to mix the crystal oscillator frequency with the reference frequency to obtain the heterodyne signal, and then filter the heterodyne signal to obtain the difference frequency component. The error acquisition module is used to calculate the transmission delay and frequency drift delay between the master node and the slave node, and to obtain the correction time based on the transmission delay, the frequency drift delay and the difference frequency component; An error correction module is used to send the corrected time to the external system device for time synchronization.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein the computer program can be executed by an electronic device to perform the method described in any one of claims 1 to 10.

13. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the method described in any one of claims 1 to 10.

14. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to execute the method described in any one of claims 1 to 10 through the computer program.

Images