A high speed envelope demodulation circuit with pulse width compensation

Abstract

The application discloses a kind of pulse width compensation high-speed envelope demodulation circuit of circuit design technical field, including V-I full-wave rectification module, tail current, filter and pulse width compensation module, the first end of V-I full-wave rectification module is connected modulation voltage signal, V-I full-wave rectification module is used to convert the modulation voltage signal into current signal, or the waveform of the current signal is full-wave rectified and rectified current is output.The application can change the rectified current of V-I full-wave rectification module by introducing pulse width compensation module, and add the value to the tail current according to a certain proportion, that is, keep the difference between discharge current and rectified current during discharging close to the difference between rectified current and discharge current during charging, so as to ensure that the rising and falling time is consistent during demodulation, and the purpose of solving pulse width distortion is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, and particularly relates to a high-speed envelope demodulation circuit with pulse width compensation. BACKGROUND

[0002] Modulation and demodulation of signals is a necessary process in a communication system, and information such as language, video and data is modulated at a sending end so as to be transmitted on radio waves or a wired medium, and finally demodulated at a receiving end to restore the information. According to the characteristics of a carrier, modulation and demodulation can be divided into amplitude modulation, frequency modulation and phase modulation, and the amplitude modulation is more widely used, and the corresponding demodulation circuit is called an envelope demodulation circuit.

[0003] The envelope demodulation circuit is widely used in the fields of wireless communication, radar and radio frequency receivers, and is used to extract baseband information from a high-frequency modulated signal. The principle of envelope detection is based on the relationship between the envelope of a modulated signal and the carrier frequency, and when the modulated signal is multiplied by the carrier frequency, two upper and lower sideband signals are generated. Envelope detection obtains the envelope of the original information signal by passing the upper and lower sideband signals through a nonlinear element such as a diode and then summing the outputs of the two.

[0004] The existing envelope demodulation technology commonly uses diode envelope detection technology, which obtains an envelope signal by passing an alternating current signal through voltage stabilization, rectification and filtering, and the circuit structure is simple. In order to improve the response speed, a current-mode detection circuit is used in the prior art, which converts a high-frequency voltage signal into a current mode and can be used in high-frequency applications, but fixed-current detection causes pulse width distortion, and the use of a diode for envelope detection also has the problem of conduction voltage drop loss, and the influence of the diode junction capacitance is significant at high frequencies, which limits the application of envelope demodulation technology in high-frequency circuits. SUMMARY

[0005] The present application aims to provide a high-speed envelope demodulation circuit with pulse width compensation, which adjusts the amplitude of the current following the input signal based on a current-mode detection circuit, and solves the problem of envelope pulse width waveform distortion after ASK signal demodulation.

[0006] To achieve the above object, the present application provides the following technical scheme:

[0007] The application discloses a high-speed envelope demodulation circuit with pulse width compensation, which is used in the ASK demodulation scene of high-speed signals and comprises a V-I full-wave rectification module, a tail current, a filter and a pulse width compensation module; the first end of the V-I full-wave rectification module is connected with a modulated voltage signal; the V-I full-wave rectification module is used for converting the modulated voltage signal into a current signal or performing full-wave rectification on the waveform of the current signal to output a rectified current; when the V-I full-wave rectification module is used for performing full-wave rectification on the waveform of the current signal to output the rectified current, the upper half cycle and the lower half cycle of the current signal can be rectified, and the conversion efficiency is higher than that of the traditional half-wave rectification; the first end of the tail current is connected with the first end of the V-I full-wave rectification module; the second end of the tail current is connected with the second end of the pulse width compensation module; the third end of the tail current is grounded; the tail current is used for comparing with the rectified current and restoring the rectified current into a voltage signal for transmission; the first end of the filter is connected with the second end of the tail current; the filter is used for filtering high-frequency signals in the voltage signal and obtaining an original baseband signal; the second end of the filter is used for outputting the original baseband signal; the first end of the pulse width compensation module is connected with the second end of the V-I full-wave rectification module; the pulse width compensation module is used for detecting the change amount of the rectified current of the V-I full-wave rectification module and giving corresponding compensation to the tail current.

[0008] As a further scheme of the application, the V-I full-wave rectification module comprises a same-phase input stage circuit and an inverse-phase input stage circuit; the same-phase input stage circuit is connected with the inverse-phase input stage circuit.

[0009] As a further scheme of the application, the same-phase input stage circuit comprises a first NMOS tube M1 and a third NMOS tube M3; the inverse-phase input stage circuit comprises a second NMOS tube M2 and a fourth NMOS tube M4; the gate of the first NMOS tube M1 is connected with an input voltage Vin, the gates of the second NMOS tube M2 and the third NMOS tube M3; the source of the first NMOS tube M1 is connected with the sources of the second NMOS tube M2, the third NMOS tube M3 and the fourth NMOS tube M4; the drain of the first NMOS tube M1 is connected with the drain of the fourth NMOS tube M4; the drain of the third NMOS tube M3 is connected with the drains of the second NMOS tube M2, a sixth PMOS tube M6 and a seventh PMOS tube M7; the drain of the seventh PMOS tube M7 is connected with the gates of the seventh PMOS tube M7 and an eighth PMOS tube M8; the gate of the sixth PMOS tube M6 is connected with the gate and the drain of a fifth PMOS tube M5; the source of the sixth PMOS tube M6 is connected with the sources of the fifth PMOS tube M5, the seventh PMOS tube M7, the eighth PMOS tube M8 and a power supply VDD; the sources of the second NMOS tube M2 and the third NMOS tube M3 are respectively connected with the first end of a differential pair tail current I0.

[0010] As a further scheme of the present application, the first NMOS transistor M1 and the fourth NMOS transistor M4 have the same size, the second NMOS transistor M2 and the third NMOS transistor M3 have the same size, the size of the first NMOS transistor M1 or the fourth NMOS transistor M4 is n times the size of the second NMOS transistor M2 or the third NMOS transistor M3, n is a positive integer, the size of the first NMOS transistor M1 or the fourth NMOS transistor M4 is n*W / L, and the size of the second NMOS transistor M2 or the third NMOS transistor M3 is W / L.

[0011] As a further scheme of the present application, the fifth PMOS transistor M5, the sixth PMOS transistor M6, the seventh PMOS transistor M7 and the eighth PMOS transistor M8 have the same size.

[0012] As a further scheme of the present application, the pulse width compensation module comprises a ninth PMOS transistor M9, a tenth PMOS transistor M10 and an eleventh PMOS transistor M11, the gate of the ninth PMOS transistor M9 is connected to the gate of the eighth PMOS transistor M8, the source of the ninth PMOS transistor M9 is connected to the source of the eighth PMOS transistor M8, the tenth PMOS transistor M10 and the eleventh PMOS transistor M11, the drain of the ninth PMOS transistor M9 is connected to the drain of the tenth PMOS transistor M10, the gate of the tenth PMOS transistor M10 and the gate of the eleventh PMOS transistor M11, the drain of the eighth PMOS transistor M8 and the eleventh PMOS transistor M11 is connected to the first end of the tail current, and the ninth PMOS transistor M9 is used to copy the rectified current.

[0013] As a further scheme of the present application, the filter comprises a fourteenth NMOS transistor M14, the source of the fourteenth NMOS transistor M14 is connected to the source of the eleventh PMOS transistor M11, the gate of the fourteenth NMOS transistor M14 is connected to the drain of the eighth PMOS transistor M8, the gate of the fifteenth PMOS transistor M15 and the first end of the first capacitor C1, the drain of the fourteenth NMOS transistor M14 is connected to the first resistor R1, the first end of the second capacitor C2 and the input end of the inverter, the second end of the first resistor R1 is connected to the drain of the fifteenth PMOS transistor M15, the source of the fifteenth PMOS transistor M15, the second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded respectively, and the output end of the inverter is connected to the first input end of the AND gate, and the second input end of the AND gate is connected to the gate of the fourteenth NMOS transistor M14.

[0014] As a further scheme of the present application, the first capacitor C1 and the output node of the V-I full-wave rectifier module (101) constitute a filter structure, and the filter structure is used to filter out high-order harmonics.

[0015] As a further scheme of the present application: the second capacitor C2, the first resistor R1, the fourteenth NMOS tube M14, the fifteenth PMOS tube M15, the inverter and the AND gate constitute a deburring structure, and the deburring structure is used for removing the demodulation envelope burr.

[0016] Compared with the prior art, the present application has the following beneficial effects:

[0017] 1. The present application is aimed at the demodulation of ASK (amplitude shift keying) signal, and creatively introduces a pulse width compensation module, which can add the change value of the rectified current of the V-I full-wave rectification module to the tail current in a certain proportion, i.e. keep the difference between the discharge current and the rectified current during discharging close to the difference between the rectified current and the discharge current during charging, so as to ensure the consistency of the rising and falling time during demodulation, and achieve the purpose of solving the pulse width distortion.

[0018] 2. The present application can dynamically compensate and adjust the size of the tail current according to the size of the rectified current in real time, so as to ensure that the discharge current tracks the input signal amplitude, significantly improve the edge quality of the demodulated signal, and prevent envelope distortion.

[0019] 3. The present application can effectively improve the pulse width distortion problem by detecting the size of the full-wave rectified current and dynamically adjusting the size of the tail current.

[0020] 4. The present application is very suitable for the demodulation of high-speed signals by using current mode demodulation.

[0021] 5. The present application has simple implementation principle and is suitable for integrated circuit design, which can effectively reduce the design cost. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a high-speed envelope demodulation circuit system structure diagram of the present application;

[0023] Figure 2 It is a V-I full-wave rectification module diagram of the present application;

[0024] Figure 3 It is a connection structure diagram of the pulse width compensation, filter and tail current in the present application;

[0025] Figure 4 It is a relationship diagram of the demodulation current, discharge current and input signal of the traditional circuit;

[0026] Figure 5 It is a relationship diagram of the demodulation current, compensation discharge current and input signal of the present application.

[0027] In the figure: 101, V-I full-wave rectification module; 102, pulse width compensation module; 103, tail current; 104, filter; 105, inverter; 106, AND gate. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the protection scope of the present application.

[0029] It should be noted that when the pulse width compensation module 102 is not introduced, it is a traditional demodulation case: when the input signal of the demodulation circuit is lower than the demodulation threshold, the charging time of the node is determined by the difference |I ave1 -I1| between the average value I ave1 of the rectified current and the current I1 of the tail current 103; when the input signal of the demodulation circuit is higher than the demodulation threshold, the rectified current is reduced, the node is in a discharging state, and the discharging time is determined by the difference |I1-I ave2 | between the average value I ave2 of the rectified current and the current I1 of the tail current 103. Therefore, for the traditional fixed tail current mode, I ave1 and I ave2 vary with the change of the input signal and are affected by the amplitude of the input signal, which causes the absolute values of |I ave1 -I1| and |I ave1 -I1| to be inconsistent, which means that the charging current and the discharging current are not the same, and therefore the rising and falling times of the signal are inconsistent, which causes the demodulation pulse width to be distorted. On the other hand, in the conventional current-mode rectifier circuit, the rectified current output by the V-I full-wave rectifier module 101 is compared with the fixed current I1 of the tail current 103, and a voltage signal can be restored at the node of the two. However, the voltage signal still contains high-order harmonics, which need to be filtered out by a low-pass filter, and therefore a filter 104 is followed in the later stage to obtain the envelope signal. However, the conventional demodulation structure has a natural demodulation distortion defect. The current signal output by the V-I full-wave rectifier module 101 is related to the amplitude of the input signal, while the current I1 of the tail current 103 is a fixed current source. Therefore, the current size of the tail current 103 is certainly asymmetric during charging and discharging. Although it is not obvious in low-frequency applications, it is very obvious in the demodulation process of high-frequency signals, which causes the rising time and the falling time of the demodulation signal to be inconsistent, resulting in the problem of pulse width distortion of the finally demodulated signal.

[0030] Embodiment:

[0031] Please refer to Figure 1 and Figure 3This invention discloses a high-speed envelope demodulation circuit with pulse width compensation for ASK demodulation of high-speed signals. The high-speed envelope demodulation circuit includes a VI full-wave rectifier module 101, a tail current 103, a filter 104, and a pulse width compensation module 102. When the input voltage signal is lower than the demodulation threshold, the full-wave rectified current of the VI full-wave rectifier module 101 is large. At this time, the current at the node is determined by the difference between the average value of the rectified current and the tail current. This difference is a constant in the ASK demodulation circuit. When the input voltage signal is higher than the demodulation threshold, the full-wave rectified current of the VI full-wave rectifier module 101 is small. Therefore, the pulse width compensation module 102 detects the change in rectified current and adjusts the tail current according to a certain proportion to ensure that the current difference during discharge is equal to the current difference during charging. This tail current compensation method improves the pulse width distortion of the demodulated envelope signal. Finally, the full-wave rectified current signal at the node is converted into voltage by the filter 104, and high-order harmonics are filtered out to restore the original baseband signal.

[0032] like Figure 2 As shown, the VI full-wave rectifier module 101 is an unbalanced source-coupled pair circuit that can convert the input voltage Vin into a full-wave rectified current ΔI. rec The first terminal of the VI full-wave rectifier module 101 is connected to the modulation voltage signal. The VI full-wave rectifier module 101 is used to convert the modulation voltage signal into a current signal, or to perform full-wave rectification on the waveform of the current signal and output rectified current. When the VI full-wave rectifier module 101 is used to perform full-wave rectification on the waveform of the current signal and output rectified current, it can rectify the upper half-cycle and the lower half-cycle of the current signal, which is beneficial to the higher conversion efficiency than the traditional half-wave rectification.

[0033] The first terminal of the tail current 103 is connected to the first terminal of the VI full-wave rectifier module 101, the second terminal of the tail current 103 is connected to the second terminal of the pulse width compensation module 102, and the third terminal of the tail current 103 is grounded. The tail current 103 is used to compare with the rectified current and restore the rectified current to a voltage signal for transmission. The first terminal of the filter 104 is electrically connected to the second terminal of the tail current 103. The filter 104 is used to filter out high-frequency signals in the voltage signal and obtain the original baseband signal. The second terminal of the filter 104 is used to output the original baseband signal. The first terminal of the pulse width compensation module 102 is electrically connected to the second terminal of the VI full-wave rectifier module 101. The pulse width compensation module 102 is used to detect the change in the rectified current of the VI full-wave rectifier module 101 and provide corresponding compensation to the tail current 103.

[0034] Preferably, the VI full-wave rectifier module 101 includes a non-inverting input stage circuit and an inverting input stage circuit, with the non-inverting input stage circuit electrically connected to the inverting input stage circuit.

[0035] In this embodiment, as shown in Figure 2 , the in-phase input stage circuit includes a first NMOS transistor M1 and a third NMOS transistor M3, the anti-phase input stage circuit includes a second NMOS transistor M2 and a fourth NMOS transistor M4, the gate of the first NMOS transistor M1 is connected to an input voltage Vin, the gates of the second NMOS transistor M2 and the third NMOS transistor M3, the source of the first NMOS transistor M1 is connected to the sources of the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4, the drain of the first NMOS transistor M1 is connected to the drain of the fourth NMOS transistor M4, the drain of the third NMOS transistor M3 is connected to the drains of the second NMOS transistor M2, a sixth PMOS transistor M6 and a seventh PMOS transistor M7, the drain of the seventh PMOS transistor M7 is connected to the gates of the seventh PMOS transistor M7 and an eighth PMOS transistor M8, the gate of the sixth PMOS transistor M6 is connected to the gate and drain of a fifth PMOS transistor M5, the source of the sixth PMOS transistor M6 is connected to the sources of the fifth PMOS transistor M5, the seventh PMOS transistor M7, the eighth PMOS transistor M8 and a power supply VDD, the sources of the second NMOS transistor M2 and the third NMOS transistor M3 are respectively connected to a first end of a differential pair tail current I0, and the current of the eighth PMOS transistor M8 is the converted current Figure 1 . The converted current is therefore the result of , where W / L is the size of the MOS transistor, n is a positive integer, and I0 is the current value of the differential pair tail current: .

[0036] It can be seen that when the input voltage Vin is not input, the converted current is near the maximum value, which is higher than the tail current 103 at this time, charging the node, and the charging current is determined by the difference between the average value of the converted high-frequency current and the tail current. When Vin is large, the converted current is at a smaller value, which is lower than the current I1 of the tail current 103 at this time, discharging the node, and the discharging current is determined by the difference between the average value of the converted high-frequency current and the tail current.

[0037] The current in Figure 4 , Figure 4 is the current image of the above formula, is the amount that changes with the input Vin, Figure 4 The solid curve in the figure depicts the relationship between the two, the tail current I1 is the discharging current, which is constant in the traditional structure, and the dashed curve depicts the relationship between I1 and Vin. For the time-domain waveform of the ASK modulated signal, the input signal is either no input, represented by Vin=0 in the figure, or a pure carrier with amplitude varying within a certain range, represented by the Vin range in the shaded area. The double-headed arrow represents The difference between I1 and I2 can be seen. When Vin=0, the difference is a constant. When Vin is large, the difference varies with Vin, thus reflecting the difference in the rise and fall times of the demodulated ASK signal.

[0038] Preferably, as shown in the figure, the first NMOS transistor M1 and the fourth NMOS transistor M4 have the same size, the second NMOS transistor M2 and the third NMOS transistor M3 have the same size, the size of the first NMOS transistor M1 and the fourth NMOS transistor M4 is n times the size of the second NMOS transistor M2 or the third NMOS transistor M3, n is a positive integer, the size of the first NMOS transistor M1 and the fourth NMOS transistor M4 is n*W / L, and the size of the second NMOS transistor M2 and the third NMOS transistor M3 is W / L. Figure 2 Preferably, the fifth PMOS transistor M5, the sixth PMOS transistor M6, the seventh PMOS transistor M7, and the eighth PMOS transistor M8 have the same size.

[0039] Preferably, the pulse width compensation module 102 includes a ninth PMOS transistor M9, a tenth PMOS transistor M10, and an eleventh PMOS transistor M11. The gate of the ninth PMOS transistor M9 is connected to the gate of the eighth PMOS transistor M8. The source of the ninth PMOS transistor M9 is connected to the sources of the eighth PMOS transistor M8, the tenth PMOS transistor M10, and the eleventh PMOS transistor M11. The drain of the ninth PMOS transistor M9 is connected to the drain of the tenth PMOS transistor M10 and the gate of the eleventh PMOS transistor M11. The drains of the eighth PMOS transistor M8 and the eleventh PMOS transistor M11 are connected to the first end of the tail current 103. The ninth PMOS transistor M9 is used to copy the rectified current Δ

[0040] , which is the demodulation current. I2 needs to be set reasonably, i.e., to ensure that when the input Vin=0, Δ is large, so that the difference between I2 and the current flowing through the ninth PMOS transistor M9 is small, so that the tenth PMOS transistor M10 enters the cutoff region, and then the eleventh PMOS transistor M11 cannot copy the current, so that I1 remains constant. At this time, the difference between I1 and I2 is a constant, and the charging current of the node is unchanged. When the input Vin is large, Δ is small, so that the difference between I2 and the current flowing through the ninth PMOS transistor M9 increases, so that the tenth PMOS transistor M10 enters the saturation region, and then the difference current I2-Δ is copied by the tenth PMOS transistor M10 and the eleventh PMOS transistor M11 in proportion, and the current a(I2-Δ is supplemented to I1. At this time, the discharging current of the node decreases to I1-a(I2-Δ . ), the discharge current will change with the change of the input signal amplitude. In combination with Figure 5 the current and input signal relationship diagram, the above current image after adding the pulse width compensation. is the amount of change with the input Vin, Figure 5 the solid line curve in the figure depicts the relationship between the two, I1 is the discharge current, and after improving the current structure, it will follow the current compensation when Vin is large. For the time domain waveform of the ASK modulated signal, the input signal is either no input, Figure 5 Vin=0 in the figure, or a pure carrier with amplitude varying within a certain range, Figure 5 represented by the shaded interval Vin in the figure. The double arrow represents the difference between I1 and Vin=0, it can be seen that when Vin=0, the difference between the two is a constant, which is consistent with the traditional structure, and when Vin is large, I1 will change with the change of Vin, that is, I1- the value of I1 is approximately a constant, and is designed to keep the difference between the two equal to that when Vin=0, so it reflects that the charging and discharging currents are equal when demodulating the ASK signal, so it can keep the rising and falling times of the circuit demodulated signal equal, thereby solving the problem of ASK demodulation signal pulse width distortion.

[0041] Preferably, the filter 104 comprises a fourteenth NMOS transistor M14, a source of the fourteenth NMOS transistor M14 is connected to a source of the eleventh PMOS transistor M11, a gate of the fourteenth NMOS transistor M14 is connected to a drain of the eighth PMOS transistor M8, a gate of the fifteenth PMOS transistor M15 and a first end of the first capacitor C1, a drain of the fourteenth NMOS transistor M14 is connected to a first end of the second capacitor C2 and an input end of the inverter 105, a second end of the first resistor R1 is connected to a drain of the fifteenth PMOS transistor M15, a source of the fifteenth PMOS transistor M15, the first capacitor C1 and the second capacitor C2 are grounded respectively, an output end of the inverter 105 is connected to a first input end of the AND gate 106, and a second input end of the AND gate 106 is connected to the gate of the fourteenth NMOS transistor M14.

[0042] Preferably, the first capacitor C1 and an output node of the V-I full-wave rectification module 101 form a filtering structure, the filtering structure is used for filtering out high-order harmonics, and the output node of the V-I full-wave rectification module 101 is a second end of the V-I full-wave rectification module 101.

[0043] Preferably, the second capacitor C2, the first resistor R1, the fourteenth NMOS transistor M14, the fifteenth PMOS transistor M15, the inverter 105 and the AND gate 106 form a deburring structure, and the deburring structure is used for removing the demodulation envelope burr.

[0044] The above merely describes preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can make equivalent replacements or changes within the technical scope disclosed by the present application and according to the technical solutions and inventive concept of the present application, which should be covered within the protection scope of the present application.

Claims

1. A high speed envelope demodulation circuit with pulse width compensation, characterized by, For the ASK demodulation scenario of high-speed signals, the high-speed envelope demodulation circuit comprises: A V-I full-wave rectification module (101) has a first end connected to a modulated voltage signal, and is configured to convert the modulated voltage signal into a current signal or to perform full-wave rectification on the waveform of the current signal and output a rectified current; A tail current (103) has a first end connected to the first end of the V-I full-wave rectification module (101), a second end connected to the second end of the pulse width compensation module (102), and a third end grounded, and is configured to compare the rectified current with the tail current and restore the rectified current into a voltage signal for transmission; A filter (104) has a first end electrically connected to the second end of the tail current (103), and is configured to filter out high-frequency signals in the voltage signal and obtain an original baseband signal, and a second end configured to output the original baseband signal; A pulse width compensation module (102) has a first end electrically connected to the second end of the V-I full-wave rectification module (101), and is configured to detect the change of the rectified current of the V-I full-wave rectification module (101) and give a corresponding compensation to the tail current (103).

2. The pulse-width-compensated high-speed envelope demodulation circuit of claim 1, wherein: The V-I full-wave rectification module (101) comprises a non-inverting input stage circuit and an inverting input stage circuit.

3. The pulse-width-compensated high-speed envelope demodulation circuit of claim 2, wherein: The non-inverting input stage circuit comprises a first NMOS transistor M1 and a third NMOS transistor M3, and the inverting input stage circuit comprises a second NMOS transistor M2 and a fourth NMOS transistor M4. The gate of the first NMOS transistor M1 is connected to an input voltage Vin, and the gates of the second NMOS transistor M2 and the third NMOS transistor M3 are connected to the gate of the first NMOS transistor M1. The source of the first NMOS transistor M1 is connected to the sources of the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4. The drain of the first NMOS transistor M1 is connected to the drain of the fourth NMOS transistor M4. The drain of the third NMOS transistor M3 is connected to the drains of the second NMOS transistor M2, a sixth PMOS transistor M6, and a seventh PMOS transistor M7. The drain of the seventh PMOS transistor M7 is connected to the gates of the seventh PMOS transistor M7 and an eighth PMOS transistor M8. The gate of the sixth PMOS transistor M6 is connected to the gate and drain of a fifth PMOS transistor M5. The source of the sixth PMOS transistor M6 is connected to the sources of the fifth PMOS transistor M5, the seventh PMOS transistor M7, the eighth PMOS transistor M8, and a power supply VDD. The sources of the second NMOS transistor M2 and the third NMOS transistor M3 are respectively connected to the first ends of a differential pair of tail currents.

4. The pulse-width-compensated high-speed envelope demodulation circuit of claim 3, wherein: The first NMOS transistor M1 and the fourth NMOS transistor M4 have the same size, the second NMOS transistor M2 and the third NMOS transistor M3 have the same size, the first NMOS transistor M1 and the fourth NMOS transistor M4 have n times the size of the second NMOS transistor M2 or the third NMOS transistor M3, and n is a positive integer.

5. The pulse-width-compensated high-speed envelope demodulation circuit of claim 4, wherein: The fifth PMOS transistor M5, the sixth PMOS transistor M6, the seventh PMOS transistor M7 and the eighth PMOS transistor M8 have the same size.

6. The pulse-width-compensated high-speed envelope demodulation circuit of claim 1, wherein: The pulse width compensation module (102) comprises a ninth PMOS transistor M9, a tenth PMOS transistor M10 and an eleventh PMOS transistor M11, the gate of the ninth PMOS transistor M9 is connected to the gate of the eighth PMOS transistor M8, the source of the ninth PMOS transistor M9 is connected to the source of the eighth PMOS transistor M8, the tenth PMOS transistor M10 and the eleventh PMOS transistor M11, the drain of the ninth PMOS transistor M9 is connected to the drain of the tenth PMOS transistor M10, the gate of the tenth PMOS transistor M10 and the gate of the eleventh PMOS transistor M11, the drains of the eighth PMOS transistor M8 and the eleventh PMOS transistor M11 are connected to the first end of the tail current (103), and the ninth PMOS transistor M9 is used to copy the rectified current.

7. The pulse-width-compensated high-speed envelope demodulation circuit of claim 1, wherein: The filter (104) comprises a fourteenth NMOS transistor M14, the source of the fourteenth NMOS transistor M14 is connected to the source of the eleventh PMOS transistor M11, the gate of the fourteenth NMOS transistor M14 is connected to the drain of the eighth PMOS transistor M8, the gate of the fifteenth PMOS transistor M15 and the first end of the first capacitor C1, the drain of the fourteenth NMOS transistor M14 is connected to the first end of the first resistor R1, the first end of the second capacitor C2 and the input end of the inverter (105), the second end of the first resistor R1 is connected to the drain of the fifteenth PMOS transistor M15, the source of the fifteenth PMOS transistor M15, the second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded respectively, and the output end of the inverter (105) is connected to the first input end of the AND gate (106), and the second input end of the AND gate (106) is connected to the gate of the fourteenth NMOS transistor M14.

8. The pulse-width-compensated high-speed envelope demodulation circuit of claim 7, wherein: The first capacitor C1 and the output node of the V-I full-wave rectifier module (101) constitute a filtering structure, and the filtering structure is used to filter out high-order harmonics.

9. The pulse-width-compensated high-speed envelope demodulation circuit of claim 7, wherein: The second capacitor C2, the first resistor R1, the fourteenth NMOS transistor M14, the fifteenth PMOS transistor M15, the inverter (105) and the AND gate (106) constitute a deburring structure, and the deburring structure is used to remove the demodulation envelope burr.

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