Apparatus, method and computer program product

Abstract

An apparatus, a method, and a computer program product are provided. The apparatus includes: a corresponding address storage unit that stores data identification information for identifying a type of data in association with an address of a storage area; an acquisition unit that acquires a plurality of data segments each associated with the data identification information; a determination unit configured to determine an address of a storage area associated with the data identification information of each data segment acquired by the acquisition unit based on a storage content of the corresponding address storage unit; and a writing unit that writes each data segment acquired by the acquisition unit into a storage region of the address determined by the determination unit for the data segment.

Description

Technical Field

[0001] This invention relates to an apparatus, method, and computer program product. Background Technology

[0002] Patent Document 1 describes an image sensor tester that “takes in the image signal output from the terminal that is in contact with the image sensor to be tested…and performs image processing…to determine whether it is good or bad” (Technical Solution 1 of Patent Document 1).

[0003] [Existing Technical Documents]

[0004] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 4-3686 Summary of the Invention

[0006] In a first embodiment of the present invention, an apparatus is provided, comprising: a corresponding address storage unit for storing data identification information for identifying the type of data in association with an address of a storage area; an acquisition unit for acquiring a plurality of data segments respectively associated with the data identification information; a determination unit for determining, based on the storage content of the corresponding address storage unit, an address of a storage area associated with the data identification information of each data segment acquired by the acquisition unit; and a writing unit for writing each data segment acquired by the acquisition unit into a storage area at an address determined by the determination unit for the data segment.

[0007] In the device, the writing unit may write each data segment via direct memory access.

[0008] In the device, the corresponding address storage unit may have: a first storage unit that stores identification information of the direct memory access channel for each data identification information; and a second storage unit that stores the address of the storage area for each direct memory access channel.

[0009] In the device, the second storage unit stores logical addresses of storage areas for each direct memory access channel and stores physical addresses for each logical address of the storage area. The writing unit writes to the physical addresses determined by the determining unit based on the storage content of the second storage unit.

[0010] In any of the aforementioned devices, the acquisition unit may acquire output data from the camera element.

[0011] In the device, each piece of data may be treated as an object of image processing.

[0012] The device may further include an image processing unit that performs image processing on the data.

[0013] In the device, the imaging element may be the element to be tested, and the device further includes a determination unit that determines the quality of the element to be tested based on test results derived from image processing.

[0014] In a second embodiment of the present invention, a method is provided, comprising: a corresponding address storage stage, wherein data identification information for identifying the type of data is stored in association with the address of a storage area; an acquisition stage, wherein multiple data segments are acquired, each associated with the data identification information; a determination stage, wherein, based on the storage content of the corresponding address storage stage, the address of the storage area associated with the data identification information of each data segment acquired in the acquisition stage is determined; and a writing stage, wherein each data segment acquired in the acquisition stage is written into the storage area at the address determined by the determination stage for the data segment.

[0015] In a third embodiment of the present invention, a computer program product is provided, which, when executed by a computer, enables the computer to function as the following units: a corresponding address storage unit that stores data identification information for identifying the type of data in association with the address of a storage area; an acquisition unit that acquires a plurality of data segments respectively associated with the data identification information; a determination unit that, based on the storage content of the corresponding address storage unit, determines the address of the storage area associated with the data identification information of each data segment acquired by the acquisition unit; and a writing unit that writes each data segment acquired by the acquisition unit into the storage area at the address determined by the determination unit for the data segment.

[0016] Furthermore, the description of the invention does not list all the features required by the invention. Additionally, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0017] Figure 1 The structure of the test apparatus 10 and the test object 20 of the embodiment are shown together.

[0018] Figure 2 The structure of the capture module 200 and the image processing device 194 in the embodiment is shown.

[0019] Figure 3 The test procedure of the test apparatus 10 for the implementation method is shown.

[0020] Figure 4 The structure of the data acquisition device 300 in the embodiment is shown.

[0021] Figure 5 This indicates the action of CAPIF 280.

[0022] Figure 6This conceptually represents the action of CAPIF 280.

[0023] Figure 7 This indicates the stored content of the first storage unit 2803-1.

[0024] Figure 8 This indicates the stored content of the second storage unit 2803-2.

[0025] Figure 9 Examples of computer 2200 that demonstrate that various forms of the present invention can be implemented wholly or partially.

[0026] Explanation of icon numbers

[0027] 10: Test Apparatus

[0028] 20: Test subject

[0029] 100: Detection device

[0030] 102: Platform

[0031] 104: Probe Card

[0032] 106: Probe

[0033] 108: Light-shielding unit

[0034] 120: Connection Unit

[0035] 130: Performance Board

[0036] 140: High-fidelity test interface board

[0037] 150: Test head

[0038] 160, 160a, 160b, 160c, 160d: Test Modules

[0039] 170: Light source

[0040] 175: Lens tube

[0041] 180: Rotating device

[0042] 190: Mainframe

[0043] 192: System Controller

[0044] 194: Image processing device

[0045] 200: Capture Module

[0046] 210, 210-1, 210-2, 210-3, 210-4: Capture Blocks

[0047] 220: Image data receiving unit

[0048] 230: Capture Unit

[0049] 235: Storage Department

[0050] 240, 240a~240c: Memory bank

[0051] 250, 250-1, 250-2, 290, 290-1, 290-2~290-7, 290-8: Signal transmitters; 255: Module IF

[0052] 270: Image Processing Engine

[0053] 280, 280-1, 280-2~280-7, 280-8: CAPIF

[0054] 285: Judgment Department

[0055] 300: Data Acquisition Device

[0056] 2200: Computer

[0057] 2201: DVD-ROM

[0058] 2210: Host Controller

[0059] 2212: CPU

[0060] 2214: RAM

[0061] 2216: Graphics Controller

[0062] 2218: Display element

[0063] 2220: Input / Output Controller

[0064] 2222: Communication Interface

[0065] 2224: Hard Drive

[0066] 2226: DVD-ROM drive

[0067] 2230: ROM

[0068] 2240: Input / Output Chip

[0069] 2242: Keyboard

[0070] 2701: Image Processing Department

[0071] 2702: Memory

[0072] 2801: Acquisition Department

[0073] 2802: Determination Department

[0074] 2803: Corresponding address storage unit

[0075] 2803-1: First Storage Unit

[0076] 2803-2: Second Storage Unit

[0077] 2804: Writing Department

[0078] DUT: Component under test

[0079] S300, S310, S320, S330, S340, S350, S360, S370, S500, S510, S520, S530: Steps Detailed Implementation

[0080] The present invention will now be described through embodiments thereof; however, these embodiments are not intended to limit the scope of the claims. Furthermore, the solutions described in the embodiments do not necessarily require all combinations of the features described herein.

[0081] Figure 1 The structure of the test apparatus 10 and the test object 20 of this embodiment are shown together. The test object 20 includes one or more components with circuits formed as the test object of the test apparatus 10, which are called the device under test (DUT). In this embodiment, the DUT is a photoelectric conversion element that detects light and converts it into an electrical signal. The DUT may be a camera element such as a complementary metal-oxide-semiconductor (CMOS) image sensor or other image sensor that converts the incident optical image into image data.

[0082] The test subject 20 can be a wafer with circuitry, integrated circuit (IC) / large-scale integrated circuit (LSI) chip circuits formed on the wafer, an IC / LSI chip monolithically formed from the wafer, or an IC / LSI package formed by packaging the IC / LSI chip, etc. In the example of this figure, the test apparatus 10 is equipped with a test subject 20 having multiple camera elements formed on it, and is used to test each camera element. The test apparatus 10 can test the camera elements one by one, or it can test two or more camera elements simultaneously.

[0083] The test apparatus 10 performs optical input tests on the DUT. The test apparatus 10 can also be used to perform electrical tests on the DUT, or on a basis thereof. In this embodiment, the example of the test apparatus 10 performing a shooting test on the DUT, which is an imaging element, will be described.

[0084] The test apparatus 10 includes a detection device 100, a test head 150, a rotating device 180, and a mainframe 190. The detection device 100 has a stage 102, a probe card 104, and a connection unit 120.

[0085] The stage 102 holds the test object 20. The stage 102 may have a vacuum chuck or electrostatic chuck on its upper surface to fix the test object 20.

[0086] A probe card 104 is disposed above the stage 102. The probe card 104 includes one or more probes 106 and a light-shielding unit 108. One or more probes 106 are disposed on the stage 102 side of the probe card 104 and are connected to the electrodes of the DUT (Device Under Test) on the test object 20. On the side of the probe card 104 opposite to the stage 102, one or more connectors are included for connection to the connection unit 120. Each probe 106 is electrically connected to the performance plate 130 on the test head 150 side via the corresponding connector and the connection unit 120.

[0087] A light-shielding unit 108 is disposed on an opening provided on a probe card 104. The light-shielding unit 108 may have an opening and a light-shielding wall, wherein the opening allows test light to pass through to illuminate the DUT, and the light-shielding wall is disposed around the opening to block stray light.

[0088] A connection unit 120 is disposed above the probe card 104. The connection unit 120 has an opening for the test light to pass through. The connection unit 120 electrically connects one or more connectors of the probe card 104 to the performance board 130 of the test head 150. The probe card 104 and the connection unit 120 shown above can be replaced according to the type of test object 20 or DUT.

[0089] The test head 150 performs tests on the DUT (Device Under Test) 20, which is the test object, placed on the stage 102 of the probe device 100. The test head 150 includes a performance board 130, a high-fidelity test interface board (Hi-Fix) 140, one or more test modules 160a to 160d (also referred to as "test module 160"), a light source 170, and a lens barrel 175.

[0090] Performance board 130 and high-fidelity test interface board 140 are disposed on the side of test head 150 facing the connection unit 120. Performance board 130 and high-fidelity test interface board 140 have openings for the transmission of test light. Performance board 130 and high-fidelity test interface board 140 electrically connect the connection unit 120 to each test module 160, thereby electrically connecting the terminals of each test module 160 to the corresponding electrodes of the DUT via the connection unit 120, probe card 104, and each probe 106. Performance board 130 includes one or more connectors connected to the connection unit 120, and one or more connectors on the high-fidelity test interface board 140 side. High-fidelity test interface board 140 houses cables, etc., that connect the multiple terminals of the connectors on the high-fidelity test interface board 140 side of performance board 130 to the terminals of the corresponding test modules 160.

[0091] One or more test modules 160 are inserted into slots within the test head 150 and are detachably connected to the backplane (upper side) of the test head 150. Test modules 160 may also be referred to as "pinelectronics cards" or "tester boards," etc. Each test module 160 is electrically connected to the device under test (DUT) 20 via a high-fidelity test interface board 140 and performance board 130 mounted on the test head 150, and a connection unit 120 and probe card 104 mounted on the probe device 100. One or more test modules 160 input / output signals between themselves and the DUT, and check the signals input from the DUT, thereby testing the DUT.

[0092] At least one test module 160 transmits and receives signals between itself and the DUT, which serves as an imaging element, via an electrical signal line to set up the DUT and capture test light. At least one test module 160 acquires output data from the DUT and supplies it to the image processing device 194 within the mainframe 190. Additionally, at least one test module 160 can function as a power supply for the DUT.

[0093] The light source 170 is disposed on the side of the test head 150 opposite to the side on which the performance plate 130 and the high-fidelity test interface plate 140 are mounted. The light source 170 emits test light to illuminate the DUT. The lens 175 is positioned within the range from the light source 170 to the performance plate 130 and guides the test light from the light source 170 to the opening of the performance plate 130.

[0094] The rotating device 180 holds the test head 150 in a manner that allows it to rotate around the rotation axis as a center. When testing the DUT, as shown in this figure, the rotating device 180 rotates and moves the test head 150 to the test position where the performance board 130 of the test head 150 is electrically connected to the connection unit 120 of the probe device 100. Furthermore, when installing or replacing the performance board 130 and the high-fidelity test interface board 140, or inserting or removing the test module 160, the rotating device 180 rotates and moves the test head 150 to a maintenance position where the surface of the test head 150 housing the performance board 130 and the high-fidelity test interface board 140 is on top.

[0095] The mainframe 190 is connected to the probe 100 and the test head 150. The mainframe 190 includes a system controller 192 and an image processing unit 194. The system controller 192 is connected to the probe 100, the test head 150, and the image processing unit 194, and controls the testing of the DUT. In response to receiving a signal from the probe 100 indicating that the DUT 20 has been brought into contact with one or more probes 106, the system controller 192 controls various parts of the test head 150, including one or more test modules 160, to perform the DUT test.

[0096] The system controller 192 can be a personal computer (PC), workstation, server computer, general-purpose computer, or other computer, or a computer system composed of multiple connected computers. This computer system is also a computer in a broad sense. Alternatively, the system controller 192 can be constructed within a computer using one or more executable virtual computer environments. Alternatively, the system controller 192 can also be a dedicated computer designed for experimental control, or dedicated hardware implemented using dedicated circuitry.

[0097] The image processing device 194 is connected to the system controller 192 and the test head 150. The image processing device 194 receives output data containing image data from the DUT (Device Under Test) from the test module 160 within the test head 150. The image data included in the output data can be image data of an image captured by the DUT under test light, or image data of an image captured by the DUT in a state without light. The image processing device 194 processes the data contained in the output data to determine the quality of the DUT. In this embodiment, as an example, the image processing device 194 can perform image processing on the image data in the output data to determine whether the captured image meets the image quality standards of the imaging element of the DUT.

[0098] Furthermore, the image processing device 194 can be connected to one test head 150 as shown in this figure, or it can be connected to multiple test heads 150. When the image processing device 194 is connected to multiple test heads 150, the image processing device 194 receives image data from each DUT (Device Under Test) as the test subject from the multiple test heads 150 and checks the image data.

[0099] The image processing apparatus 194 can be a PC (personal computer), workstation, server computer, general-purpose computer, or other computer, or a computer system composed of multiple interconnected computers. Such a computer system is also a computer in a broad sense. Alternatively, the image processing apparatus 194 can be constructed within a computer using one or more executable virtual computer environments. Alternatively, the image processing apparatus 194 can be a dedicated computer designed for image processing, or dedicated hardware implemented using dedicated circuitry.

[0100] Figure 2 This illustrates the structure of the capture module 200 and the image processing apparatus 194 in this embodiment. The capture module 200 is configured as... Figure 1 The test module 160 (e.g., test module 160c) among the multiple test modules 160 shown functions to acquire output data from the DUT. The test head 150 may be equipped with one or more capture modules 200.

[0101] Here, the DUT can share a single physical output line across multiple virtual channels, or it can send different data on each virtual channel. Each virtual channel can discretely send data that needs to be aggregated for data processing (for example, image processing) in the form of data segments, or it can insert data segments sent by one or more other virtual channels between data segments sent by one virtual channel. Thus, the output data from the DUT can be segmented, containing each data segment. The data contained in the output data can be one or more image data (e.g., image data for each color, such as RGB), or metadata such as focus information. Furthermore, each virtual channel sending image data can send image data corresponding to its respective pixel format, or it can send image data with different image sizes or data volumes. Each data segment can be associated with data identification information (also represented as a data ID) used to identify the type of data; in this embodiment, for example, a data ID can also be attached to each data segment.

[0102] The capture module 200 includes one or more capture blocks 210 (referred to as "capture block 210-1 to capture block 210-4" in this example), one or more signal transmitters 250 (referred to as "signal transmitter 250-1 to signal transmitter 250-2" in this example), and a module interface (module IF (interface)) 255.

[0103] Each capture block 210 is provided corresponding to one or more DUTs (Distributed Under Tests) used as test subjects. The capture block 210 is electrically connected to the DUT used as test subjects and acquires output data from the DUT. The capture block 210 includes an image data receiving unit 220, a capture unit 230, and a storage unit 235.

[0104] The image data receiving unit 220 is electrically connected to the DUT (Distributed Under Test) as the test subject. The image data receiving unit 220 receives output data from the DUT. The image data receiving unit 220 can receive output data containing image data captured by the DUT. The image data receiving unit 220 has an image input interface suitable for the image output interface installed in the DUT as the test subject. The image data receiving unit 220 can be a PHY chip or PHY board conforming to physical layer (PHY) standards such as Mobile Industry Processor Interface (MIPI, registered trademark). In this case, the image data receiving unit 220 can receive image data from the DUT having an interface conforming to such a PHY standard.

[0105] The capture unit 230 is connected to the image data receiving unit 220 and the storage unit 235. The capture unit 230 receives output data from the DUT from the image data receiving unit 220 and temporarily stores it in the storage unit 235. The output data stored in the storage unit 235 can be segmented into multiple data segments of a predetermined bit width, and each data segment can be appended with a data ID to identify the type of data. The capture unit 230 can sequentially receive multiple data segments containing multiple captured images of the DUT under the same or different test light, and store them in the storage unit 235. In response to a request from the image processing device 194, the capture unit 230 can read the multiple data segments stored in the storage unit 235 and transmit them to the image processing device 194 via the signal transmitter 250. The capture unit 230 can read data segments regardless of the type of data. For example, it can read them in the order they are stored in the storage unit 235, or in the reverse order of storage, or in the order of storage addresses in the storage unit 235, or in the reverse order of storage addresses in the storage unit 235.

[0106] Storage unit 235 stores output data from the DUT. Each storage unit 235 can store data segments of output data from different DUTs. Storage unit 235 may have one or more memory banks 240a to 240c (also referred to as "memory bank 240"). One or more memory banks 240 are connected to capture unit 230. Each memory bank 240 may be a memory element or memory module such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Each memory bank 240 may include two or more memory elements or memory modules.

[0107] One or more signal transmitters 250 are connected to one or more capture blocks 210. Each signal transmitter 250 may be connected to all capture blocks 210 within the capture module 200, to two or more capture blocks 210 within the capture module 200, or to one capture block 210. In the example of this figure, the capture module 200 has four capture blocks 210 and two signal transmitters 250, each signal transmitter 250 being connected to the four capture blocks 210.

[0108] Signal transmitter 250 is connected to signal transmitter 290 within the image processing device 194, which is connected in opposite directions, via a communication cable, and transmits and receives signals such as electrical or optical signals between the two. As an example, signal transmitter 250 may be a quad small form-factor pluggable (QSFP) standard optical transceiver. In the case where signal transmitter 250 is a QSFP standard optical transceiver, signal transmitter 250 is connected to the opposite signal transmitter 290 via a four-lane optical fiber.

[0109] Module IF 255 is connected to each capture block 210 and other circuits within capture module 200, as well as system controller 192. Module IF 255 enables control of the circuits within capture module 200 by system controller 192 through relaying access from system controller 192 to the circuits within capture module 200.

[0110] The image processing apparatus 194 includes an image processing engine 270, one or more Common Application Program Interface Frameworks (CAPIF) 280-1 to 280-8 (also referred to as "CAPIF 280"), and a determination unit 285. The image processing engine 270 performs data processing on data generated from multiple data segments supplied from the capture module 200. In this embodiment, the image processing engine 270 is described as performing image processing on image data generated from multiple data segments; however, it may also perform different data processing on data of a different type than image data. Furthermore, the method for generating image data from multiple data segments will be described in detail later.

[0111] Here, image processing can refer to the process of extracting certain information from image data. For example, image processing can be the process of calculating the average pixel value, the process of calculating a sensitivity index of the DUT, the process of calculating a uniformity index of pixel values, the process of calculating a noise characteristic index of the DUT, the process of calculating the standard deviation of pixel values ​​in at least a portion of the image data, or the process of detecting points or lines with unintended pixel values. The image processing engine 270 can supply data representing the result of image processing to the determination unit 285.

[0112] The image processing engine 270 may be a computer mainframe including a central processing unit (CPU), memory, and input / output devices, and optionally external storage devices. Alternatively, the image processing engine 270 may be an image processing accelerator such as a graphics processing unit (GPU) mounted on the computer mainframe. The image processing engine 270 may, for example, be one or more image processing accelerators mounted on a peripheral bus such as PCI Express (registered trademark). Alternatively, the image processing engine 270 may be a dedicated computer or dedicated circuit designed specifically for image processing in the experimental setup 10.

[0113] CAPIF (Capture Interface) 280 is an interface device for communicatively connecting image processing engine 270 to capture block 210 within capture module 200. CAPIF 280 can be mounted on a peripheral bus such as PCI Express (registered trademark) of image processing engine 270. Each of one or more CAPIFs 280-1 to 280-8 includes one or more signal transmitters 290-1 to 290-8, and communicates with capture unit 230 within capture block 210 via corresponding signal transmitter 290 and signal transmitter 250 connected to signal transmitter 290.

[0114] The judgment unit 285 determines the quality of the DUT based on test results derived from the image processing results. The judgment unit 285 can derive test results from data representing the image processing results. The judgment unit 285 can perform predetermined calculations on the image processing results (e.g., comparison with a benchmark value) to derive test results (e.g., pass / fail). The judgment unit 285 can determine the quality of the DUT based on whether the test results of each test item meet a pre-set pass / fail benchmark (e.g., a benchmark where all test results are pass). The judgment unit 285 can perform a judgment for each DUT.

[0115] also, Figure 1 and Figure 2 The structure of the test apparatus 10 shown is an example. The test apparatus 10 can be structured according to the test method (wafer testing, chip testing, IC / LSI testing, etc.), the type of test (functional testing, parameter testing, etc.), and the scale of the test. Alternatively, for example, the image processing device 194 can be located separately from the main body of the test apparatus 10 instead of being housed within the mainframe 190, and connected to the main body of the test apparatus 10 via a communication network. The image processing device 194 can also be implemented using a cloud server capable of communicating with the main body of the test apparatus 10 via the Internet.

[0116] Figure 3 The test procedure of the test apparatus 10 according to this embodiment is shown. In step 300 (S300), the test apparatus 10 is configured according to the DUT. Specifically, the rotating device 180 rotates and moves the test head 150 to the maintenance position. A light source 170 corresponding to the DUT is mounted on the test head 150. Various test modules 160 selected according to the type and quantity of the DUT are inserted into the test head 150 from the upper surface side at the maintenance position. In addition, a high-fidelity test interface board 140 and a performance board 130 corresponding to the DUT are mounted and fixed on the upper surface of the test head 150. A probe card 104 and a connection unit 120 corresponding to the DUT are mounted on the probe device 100. After the test apparatus 10 is configured, the rotating device 180 rotates and moves the test head 150 to the test position.

[0117] In S310, the detection device 100 connects one or more DUTs (Device Under Test) formed on the test object 20 to the probe card 104 of the testing device 10. Specifically, the detection device 100 transports and places the test object 20 onto the stage 102. After aligning the DUTs on the test object 20 with the probe card 104 by moving the stage 102 in the horizontal direction (also referred to as the "XY direction"), the detection device 100 moves the stage 102 upward in the vertical direction (also referred to as the "Z direction") to electrically connect each electrode of the DUT to each probe 106 of the probe card 104.

[0118] In S320, the light source 170 emits test light under the control of the system controller 192. The test light passes through the lens tube 175, the high-fidelity test interface board 140, the performance board 130, the connection unit 120, and the probe card 104. Thus, the test apparatus 10 illuminates the DUT with test light.

[0119] In S330, the test module 160, which controls the DUT, is controlled by the system controller 192 to instruct the DUT to perform image capture settings and capture images of the test light. Thus, the DUT captures an image of the test light.

[0120] In S340, the test module 160, used to control the DUT, is controlled by the system controller 192 to output data segments such as image data or metadata of the captured images from the DUT. The capture block 210 within the capture module 200 acquires the output data from the DUT. When the test is performed in the image processing device 194 by image processing of multiple captured images, the test device 10 repeats the processing from S320 to S340 while changing at least one of the light intensity, color, or emission pattern of the test light as needed.

[0121] In S350, the image processing device 194 acquires and examines the image data captured by the capture module 200, thereby testing the DUT.

[0122] Specifically, CAPIF 280 acquires multiple data segments and supplies them to image processing engine 270. Image processing engine 270 performs image processing on one or more image data generated from the acquired multiple data segments according to a predetermined algorithm such as a test program. Then, judgment unit 285 determines the quality of DUT based on the test results derived from the image processing results. Judgment unit 285 can determine the quality of DUT by judging whether the image processing result for the captured image meets the image quality standard. In addition, the test apparatus 10 can perform electrical tests on DUT in addition to optical input tests.

[0123] In S360, the testing device 10 determines whether the test of the DUT, which is the test subject, has ended. If the test of the DUT has not ended (S360 "NO"), the testing device 10 moves the process to S320 and performs the test process from S320 to S350 for the next test item. If the test of the DUT has ended (S360 "YES"), the testing device 10 moves the process to S370.

[0124] In S370, the testing apparatus 10 determines whether the testing of all DUTs of the test object 20 has been completed. If the testing of all DUTs has not been completed (S370 "No"), the testing apparatus 10 proceeds to S310, performing the testing process from S310 to S360. If the testing of all DUTs has been completed (S370 "Yes"), the testing apparatus 10 terminates the testing process of the test object 20. Furthermore, the detection device 100 can remove the completed test object 20 and place the next test object 20 onto the stage 102. Correspondingly, the testing apparatus 10 can perform the testing process shown in this figure on the next test object 20.

[0125] Figure 4 This illustrates the structure of the data acquisition device 300 in this embodiment. The data acquisition device 300 of this embodiment can be configured as including... Figure 2 The data acquisition device 300 is used in conjunction with the structure of the CAPIF 280 and image processing engine 270 shown. Alternatively, the data acquisition device 300 can be applied to various application areas that acquire and store multiple data segments. The data acquisition device 300 can be implemented by one or more components such as ICs or LSIs, or by executing a computational program in a general computer, digital signal processor (DSP), or microcontroller. The data acquisition device 300 includes the CAPIF 280 and the image processing engine 270.

[0126] CAPIF 280 is an interface device for acquiring multiple data segments from the capture module 200 and supplying them to the image processing engine 270. It writes data to the memory 2702 (described later) in the image processing engine 270 via direct memory access (DMA). The data acquisition device 300 includes an acquisition unit 2801, a corresponding address storage unit 2803, a determination unit 2802, and a writing unit 2804.

[0127] The acquisition unit 2801 acquires multiple data segments, each associated with a data ID. The acquisition unit 2801 can acquire output data from the DUT. In this embodiment, as an example, the acquisition unit 2801 acquires output data from the DUT via the capture module 200. Here, the data ID can be an ID used to identify the type of data being processed, or it can be appended to each data segment. The acquisition unit 2801 can sequentially supply each acquired data segment to the determination unit 2802.

[0128] The corresponding address storage unit 2803 stores the data ID in association with the address of the storage area. The corresponding address storage unit 2803 may have a first storage unit 2803-1 and a second storage unit 2803-2.

[0129] The first storage unit 2803-1 stores the identification information (also referred to as channel ID) of the DMA channel for each data ID. The channel ID of the stored DMA channel can be the channel ID of the DMA channel to be used in writing the data segment, or it can be the channel ID of the DMA channel pre-selected for each data ID from multiple DMA channels that can be used in the DMA.

[0130] The second storage unit 2803-2 stores the address of a storage region for each DMA channel. The stored address of the storage region can be the starting address of the storage region to be written to, or it can be the address of the memory 2702 described later (e.g., a logical address). The address stored in the second storage unit 2803-2 can be different for each DMA channel. Therefore, the address stored in the second storage unit 2803-2 is different for each data ID, that is, for each type of data.

[0131] The determining unit 2802 determines the address of the storage region associated with the data ID of each data segment acquired by the acquiring unit 2801 based on the storage content of the corresponding address storage unit 2803. The determining unit 2802 may determine the channel ID of the DMA channel associated with the data ID of each acquired data segment based on the storage content of the first storage unit 2803-1, and determine the address associated with the determined channel ID based on the storage content of the second storage unit 2803-2. The determining unit 2802 may supply the determined address and channel ID to the writing unit 2804.

[0132] The writing unit 2804 writes each data segment acquired by the acquisition unit 2801. The writing unit 2804 can write each data segment via DMA, or it can write to the memory 2702 of the image processing engine 270 without going through the CPU (not shown) of the image processing engine 270.

[0133] The writing unit 2804 can write each data segment acquired by the acquisition unit 2801 into a storage area at an address determined by the determination unit 2802 for that data segment. The writing unit 2804 can write to the address determined by the determination unit 2802 via the DMA channel indicated by the channel ID determined by the determination unit 2802. If a data segment has already been written to the determined address, the writing unit 2804 can write a new data segment immediately after the address has been written. Thus, each data segment is summarized and stored individually, resulting in the reproduction of image data or metadata contained in the output data from the DUT within the memory 2702. Writing based on individual DMA channels can be performed in parallel.

[0134] The image processing engine 270 performs image processing on image data generated from multiple data segments. The image processing engine 270 includes a memory 2702 and an image processing unit 2701.

[0135] The memory 2702 stores image data that is the object of image processing. The memory 2702 may store data segments summarized by the write unit 2804, or it may store image data or metadata.

[0136] The image processing unit 2701 performs image processing on each piece of data. As an example, the image processing unit 2701 may be an image processing accelerator such as a GPU. The image processing unit 2701 can read image data from the memory 2702 according to the instructions from the system controller 192, perform image processing, and output the processing result to the determination unit 285.

[0137] Based on the data acquisition device 300 described above, the address of the storage area associated with the data ID of each acquired data segment is determined, and each data segment is written to the storage area at the determined address. Therefore, each data segment is summarized and written according to the type of data. Thus, compared with the case where the acquired data segments are temporarily stored and rearranged according to type before storage, the time from receiving the data segments to providing them for data processing (for example, image processing) can be shortened.

[0138] Furthermore, since data segments are written via DMA, data segments can be stored without waiting for CPU processing. Therefore, the time from receiving a data segment to providing it for processing can be further reduced.

[0139] Furthermore, since a channel ID for each DMA channel is stored for each data ID, and an address for a storage area is stored for each DMA channel, each data segment can be stored at the address corresponding to the DMA channel through the DMA channel corresponding to the data ID of the data segment. Therefore, by using multiple DMA channels, the time from receiving a data segment to providing it for data processing can be further reduced.

[0140] Furthermore, since the output data from the camera element is acquired, the data contained in the output data from the camera element can be quickly provided to the data processing.

[0141] Furthermore, since each piece of data is treated as an object of image processing, the data contained in the output data from the camera element can be quickly provided to the image processing.

[0142] Furthermore, since the image processing unit 2701 of the experimental device 10 performs image processing on each data, the data can be provided to the image processing unit more quickly compared to the case where image processing is performed using an external device.

[0143] Furthermore, the quality of the camera element under test is determined based on the test results derived from image processing. Therefore, the quality of the camera element can be determined quickly.

[0144] Figure 5 This describes the operation of CAPIF 280. CAPIF 280 writes data into memory 2702 by performing the processes S500 to S530. Furthermore, in this operation, it is assumed that the data ID is stored in the corresponding address storage unit 2803 in association with the address of the storage area beforehand.

[0145] In S500, the acquisition unit 2801 acquires multiple data segments, each associated with a data ID. The acquisition unit 2801 can acquire output data from the DUT.

[0146] In S510, the determination unit 2802 determines the channel ID of the DMA channel associated with the data ID of each acquired data segment based on the storage contents of the first storage unit 2803-1.

[0147] In S520, the determining unit 2802 determines the address associated with the determined channel ID based on the storage content of the second storage unit 2803-2. Here, the second storage unit 2803-2 may store a logical address of a storage area for each DMA channel, and a physical address for each logical address of the storage area. In this case, the determining unit 2802 may determine the logical address of the memory 2702 associated with the determined channel ID, and further determine the physical address associated with the logical address. Through the above S510 and S520, based on the storage content of the corresponding address storage unit 2803, the address of the storage area associated with the data ID of each data segment acquired by the acquiring unit 2801 is determined.

[0148] Then, in S530, the writing unit 2804 writes each data segment acquired in S500 into a storage area corresponding to the address determined in S520 for that data segment. The writing unit 2804 can write to the physical address determined in S520. The writing unit 2804 can write via the DMA channel determined in S510.

[0149] Based on the above operations, the second storage unit 2803-2 stores the logical address of the storage area for each DMA channel, and stores the physical address for each logical address of the storage area. The writing unit 2804 writes to the determined physical address based on the stored content. Therefore, even when the physical addresses to be stored are discrete, data in each data segment can be written continuously. That is, distributed aggregation is possible.

[0150] Figure 6 This diagram conceptually represents the operation of CAPIF 280. Furthermore, each data segment is illustrated in a different shading pattern according to its data ID in this diagram.

[0151] As shown in the figure, CAPIF 280 stores each data segment sent from the capture module 200, regardless of the type of data, in a storage area associated with the data ID of the data segment within the storage area of ​​the memory 2702.

[0152] Figure 7 This represents the stored content of the first storage unit 2803-1. As shown in the figure, the first storage unit 2803-1 can be a data table that stores channel IDs and data IDs in association. Furthermore, in this figure, the number of DMA channels can be up to 32, and the channel IDs can be numbers from 1 to 32, represented by 5 bits. The number of data types can be up to 65536, and the data IDs can be numbers from 1 to 65536, represented by 16 bits.

[0153] Figure 8 This represents the stored content of the second storage unit 2803-2. As shown in the figure, the second storage unit 2803-2 can be a data table that stores channel IDs, the starting address of logical addresses, and data sizes in association. The data size can be the size of each data segment written by the corresponding DMA channel. Furthermore, although not shown in this figure, the second storage unit 2803-2 can also store subsequent addresses of logical addresses sequentially, or it can store their physical addresses in association with each logical address.

[0154] Furthermore, in the above embodiments, the data was described as image data, but other types of data may also be used. In this case, the test apparatus 10 may include a processing unit that processes the data file instead of the image processing engine 270.

[0155] Furthermore, while the description assumes that a corresponding address storage unit 2803 is included in CAPIF 280, at least a portion of the corresponding address storage unit 2803 may also be provided in the memory 2702 of the image processing engine 270. As an example, a second storage unit 2803-2 may be provided in the memory 2702.

[0156] Various embodiments of the present invention can be described with reference to flowcharts and block diagrams, where blocks may represent: (1) a stage of an operation being executed, or (2) a segment of a device having the function of performing an operation. Specific stages and segments may be constructed as follows: dedicated circuitry, programmable circuitry supplied together with computer-readable instructions stored on a computer-readable medium, and / or a processor supplied together with computer-readable instructions stored on a computer-readable medium. Dedicated circuitry may contain digital and / or analog hardware circuitry, or integrated circuits (ICs) and / or discrete circuitry. Programmable circuitry may contain reconfigurable hardware circuitry, including logical AND, logical OR, logical XOR, logical NAND, logical NOR, and other logical operations, flip-flops, registers, field-programmable gate arrays (FPGAs), and memory components such as programmable logic arrays (PLAs).

[0157] A computer-readable medium can contain any tangible element capable of storing instructions executable by a suitable device. As a result, a computer-readable medium having instructions stored therein constitutes a product containing executable instructions necessary to create the operations specified in a flowchart or block diagram. Examples of computer-readable media include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, etc. More specific examples of computer-readable media may include: floppy disks, diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electrically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital video disc (DVD), Blu-ray discs, memory sticks, integrated circuit cards, etc.

[0158] Computer-readable instructions may comprise any source code or object code described in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or object-oriented programming languages ​​such as Smalltalk, Java, and C++, and conventional sequential programming languages ​​such as the "C" programming language or similar programming languages.

[0159] Compared to the processor or programmable circuitry of a programmable data processing device such as a general-purpose computer, a special-purpose computer, or another computer, computer-readable instructions can be provided locally or via a wide area network (WAN) such as a local area network (LAN) or the Internet, and executing computer-readable instructions creates the means required to perform the operations specified in a flowchart or block diagram. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, and microcontrollers.

[0160] Figure 9 Examples of computer 2200 that can be wholly or partially implemented in various forms of the present invention are shown. A program installed on computer 2200 enables computer 2200 to function as an operation of a device associated with an embodiment of the present invention or one or more segments of said device; or, to execute said operation or said one or more segments, and / or to enable computer 2200 to execute a process or stage of an embodiment of the present invention. Such a program can be executed by computer 2200 via CPU 2212 to perform specific operations associated with some or all of the blocks in the flowcharts and block diagrams described in this specification.

[0161] The computer 2200 of this embodiment includes a CPU 2212, RAM 2214, a graphics controller 2216, and a display element 2218, which are interconnected via a host controller 2210. The computer 2200 also includes input / output units such as a communication interface 2222, a hard disk drive 2224, a DVD-ROM drive 2226, and an IC card driver, which are connected to the host controller 2210 via an input / output controller 2220. The computer also includes conventional input / output units such as a ROM 2230 and a keyboard 2242, which are connected to the input / output controller 2220 via an input / output chip 2240.

[0162] The CPU 2212 operates according to the program stored in the ROM 2230 and RAM 2214, thereby controlling the various units. The graphics controller 2216 acquires image data generated by the CPU 2212 from the frame buffer provided in RAM 2214 or itself, and the image data can be displayed on the display element 2218.

[0163] Communication interface 2222 communicates with other electronic components via a network. Hard disk drive 2224 stores programs and data to be used by CPU 2212 within computer 2200. DVD-ROM drive 2226 reads programs or data from DVD-ROM 2201 and provides programs or data to hard disk drive 2224 via RAM 2214. IC card drive reads programs and data from IC card and / or writes programs and data to IC card.

[0164] ROM 2230 stores boot programs to be executed by computer 2200 at startup, and / or programs dependent on the hardware of computer 2200. Input / output chip 2240 can also connect various input / output units to input / output controller 2220 via parallel ports, serial ports, keyboard ports, mouse ports, etc.

[0165] The program is provided via a computer-readable medium such as a DVD-ROM 2201 or an IC card. The program is read from the computer-readable medium and installed on a hard disk drive 2224, RAM 2214, or ROM 2230, which are also examples of computer-readable media, and executed by the CPU 2212. The information processing described within these programs is read into the computer 2200, causing cooperation between the program and the various types of hardware resources. The apparatus or method can be configured to perform information manipulation or processing based on the use of the computer 2200.

[0166] For example, when communication is performed between computer 2200 and external components, CPU 2212 executes the communication program loaded in RAM 2214, and based on the processing described in the communication program, it can perform communication processing on the commands of communication interface 2222. Under the control of CPU 2212, communication interface 2222 reads transmission data stored in the transmission buffer processing area provided in the recording medium such as RAM 2214, hard disk drive 2224, DVD-ROM 2201, or IC card, and sends the read transmission data to the network, or writes received data received from the network into the receive buffer processing area provided on the recording medium, etc.

[0167] In addition, CPU 2212 can read all or necessary portions of files or databases stored in external recording media such as hard disk drive 2224, DVD-ROM drive 2226 (DVD-ROM 2201), and IC cards into RAM 2214, and perform various types of processing on the data in RAM 2214. CPU 2212 then writes the processed data back to the external recording media.

[0168] Various types of information, such as programs, data, tables, and databases, can be stored in the recording medium and processed. The CPU 2212 can execute various types of processing described in this disclosure on data read from RAM 2214, including various types of operations, information processing, conditional judgments, conditional branches, unconditional branches, and information retrieval / replacement specified by a sequence of instructions, and write the results back to RAM 2214. Furthermore, the CPU 2212 can retrieve information from files, databases, etc., within the recording medium. For example, when multiple entries with attribute values ​​of a first attribute each associated with an attribute value of a second attribute are stored in the recording medium, the CPU 2212 retrieves entries from the multiple entries that meet the conditions specified by the attribute value of the first attribute, and reads the attribute value of the second attribute stored in those entries. Thus, the attribute value of the second attribute associated with the first attribute that satisfies predetermined conditions can be obtained.

[0169] The programs or software modules described above can be stored on computer 2200 or on a computer-readable medium near computer 2200. Alternatively, a recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet can be used as a computer-readable medium, thereby providing the program to computer 2200 via the network.

[0170] The present invention has been described above using embodiments, but the scope of the present invention is not limited to the scope described in the embodiments. Those skilled in the art will understand that various modifications or improvements can be made to the embodiments. As will be apparent from the claims, such modifications or improvements can also be included within the scope of the present invention.

[0171] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specification, and drawings can be implemented in any order unless specifically stated as "before" or "before," and unless the output of the previous process is used in the subsequent process. The action flow in the claims, specification, and drawings is described using terms such as "firstly," "secondly," etc., for convenience, but this does not imply that the actions must be performed in the stated order.

Claims

1. An apparatus comprising: The corresponding address storage unit stores data identification information used to identify the type of data in association with the address of the storage area; The acquisition unit acquires multiple data segments that are associated with data identification information. The determining unit, based on the storage content of the corresponding address storage unit, determines the address of the storage region associated with the data identification information of each data segment acquired by the acquiring unit; and The writing unit writes each data segment acquired by the acquisition unit into a storage area at an address determined by the determination unit for the data segment.

2. The apparatus according to claim 1, wherein the writing unit writes each data segment via direct memory access.

3. The apparatus according to claim 2, wherein the corresponding address storage unit comprises: The first storage unit stores the identification information of the direct memory access channel for each data identification information; and The second storage section stores the addresses of storage areas for each direct memory access channel.

4. The apparatus of claim 3, wherein the second storage unit stores a logical address of a storage region for each direct memory access channel, and stores a physical address for each logical address of the storage region. The writing unit writes to the physical address determined by the determining unit based on the stored content of the second storage unit.

5. The apparatus according to any one of claims 1 to 4, wherein the acquisition unit acquires output data from the imaging element.

6. The apparatus of claim 5, wherein each piece of data is the object of image processing.

7. The apparatus according to claim 6 further includes an image processing unit, which performs image processing on each piece of data.

8. The apparatus according to claim 7, wherein the imaging element is the element under test. The device also includes a determination unit. The determination unit determines the quality of the tested component based on the test results derived from the image processing results.

9. A method comprising: During the address storage phase, data identification information used to identify the type of data is stored in association with the address of the storage area; In the acquisition phase, multiple data segments associated with data identification information are acquired. In the determination phase, based on the storage content of the corresponding address storage phase, the address of the storage area associated with the data identification information of each data segment obtained through the acquisition phase is determined; as well as During the write phase, each data segment acquired in the acquisition phase is written into the storage area at the address determined in the determination phase for that data segment.

10. A computer program product, executed by a computer, causes the computer to function as the following components: The corresponding address storage unit stores data identification information used to identify the type of data in association with the address of the storage area; The acquisition unit acquires multiple data segments that are associated with data identification information. The determining unit, based on the storage content of the corresponding address storage unit, determines the address of the storage region associated with the data identification information of each data segment acquired by the acquiring unit; and The writing unit writes each data segment acquired by the acquisition unit into a storage area at an address determined by the determination unit for the data segment.

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