Power level comparator with switch input

Abstract

An integrated circuit is disclosed that includes a power multiplexer for selecting between a first supply voltage and a second supply voltage to provide the selected supply voltage to a memory. The controller includes a comparator stage having a comparator with a switchable input such that the comparator stage can control a binary state of the first output signal in response to whether the first supply voltage is greater than the second supply voltage plus a voltage offset of the comparator. Similarly, the comparator stage may control a binary state of the second output signal in response to whether the first supply voltage is greater than the second supply voltage minus the voltage offset. The controller controls selection of the power multiplexers in response to binary states of the first output signal and the second output signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Patent Application No. 18 / 306,167, filed April 24, 2023, the disclosure of which is fully set forth below and incorporated herein by reference for all applicable purposes. Technical Field

[0003] This application relates to integrated circuit memories, and more specifically to a power level comparator having a switching input for selecting a power supply voltage for an integrated circuit memory. Background Technology

[0004] Integrated circuits with digital cores, such as processors, typically have various operating modes, where the core domain power supply voltage for the digital core varies depending on the operating mode. In high-performance mode, the core domain power supply voltage increases. In contrast, for low-performance or quiescent modes, the core domain power supply decreases. During high-performance mode, it is advantageous for the memory to be powered by the increased core domain power supply voltage, thus enhancing memory performance. In low-performance mode, the core domain power supply voltage decreases to conserve power. The memory can continue to be powered by this reduced core domain power, which must not only power the memory bit cell array but also the associated peripheral logic components used for the write and read paths of the bit cell array.

[0005] If the power supply voltage to peripheral logic components drops below a minimum voltage, the peripheral logic components may fail to function correctly. If the core domain power supply voltage drops below this minimum voltage and the memory continues to be powered by the core domain power supply voltage, the memory may fail. Therefore, integrated circuits typically include a power multiplexer that selects between the core domain power supply voltage and the memory domain power supply voltage to provide a selected power supply voltage to power the bit cell array. This selection by the power multiplexer is prone to inaccuracies, which can lead to memory performance problems. Summary of the Invention

[0006] According to one aspect of this disclosure, an integrated circuit is provided, comprising: a memory including a bit cell array; a first voltage rail for a first power supply voltage; a second voltage rail for a second power supply voltage; a power multiplexer configured to select between the first power supply voltage and the second power supply voltage to provide the selected power supply voltage to power the bit cell array; and a controller including a comparator stage configured to switch between the first configuration and the second configuration, wherein in the first configuration, a first input terminal of a comparator in the comparator stage is coupled to the first voltage rail and a second input terminal of a comparator is coupled to the second voltage rail, and in the second configuration, the first input terminal is coupled to the second voltage rail and the second input terminal is coupled to the first voltage rail, the controller being configured to control the power multiplexer to select between the first power supply voltage and the second power supply voltage in response to a first output signal and a second output signal of the comparator stage during operation in the first and second configurations.

[0007] According to another aspect of this disclosure, a method for selecting a power supply voltage is provided, the method occurring during a transition of a first power supply voltage from less than a second power supply voltage to greater than the second power supply voltage, the method comprising: asserting a first output signal in response to the first power supply voltage being greater than the sum of the second power supply voltage and a comparator offset voltage; asserting a second output signal in response to the first power supply voltage being greater than the second power supply voltage minus the comparator offset voltage; and controlling a power multiplexer to select the first power supply voltage in response to the assertions of both the first and second output signals, so as to power a bit cell array in a memory with the first power supply voltage.

[0008] According to another aspect of this disclosure, an integrated circuit is provided, comprising: a power multiplexer; and a controller configured to control the power multiplexer to select between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage in response to determining whether a first power supply voltage is greater than a second power supply voltage plus a voltage offset and in response to determining whether the first power supply voltage is greater than a second power supply voltage minus the voltage offset.

[0009] These and other advantageous features can be better understood through the detailed description below. Attached Figure Description

[0010] Figure 1 An integrated circuit including a power multiplexer and a controller according to one aspect of this disclosure is illustrated.

[0011] Figure 2 Examples Figure 1 The transition of the first power supply voltage in the integrated circuit from being greater than the sum of the second power supply voltage and the comparator offset voltage to being less than the second power supply voltage minus the comparator offset voltage.

[0012] Figure 3 Examples Figure 1 The transition of the first power supply voltage in the integrated circuit from less than the second power supply voltage minus the comparator offset voltage to greater than the second power supply voltage plus the comparator offset voltage.

[0013] Figure 4 Examples Figure 1 The transition of the first power supply voltage in the integrated circuit from less than the second power supply voltage minus the comparator offset voltage to greater than the second power supply voltage but less than the second power supply voltage plus the comparator offset voltage.

[0014] Figure 5 An example of a comparator level according to one aspect of this disclosure is shown.

[0015] Figure 6 An example of a pre-logic level according to one aspect of this disclosure is shown.

[0016] Figure 7 The final logic level according to one aspect of this disclosure is illustrated.

[0017] Figure 8 This is a flowchart of a method for selecting a memory power supply voltage according to one aspect of this disclosure.

[0018] Figure 9 Examples of electronic systems according to one aspect of this disclosure include integrated circuits having a power multiplexer and a controller.

[0019] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0020] A power multiplexer is provided, which is controlled by a controller to improve performance and prevent undervoltage conditions or selection of voltages below optimal for embedded memories in integrated circuits. During a high-performance mode where the core domain power supply voltage is greater than the memory domain power supply voltage, the controller controls the power multiplexer to select the core domain power supply voltage, allowing for higher operating speeds of the bit cell array (and associated peripheral logic units) in the memory. However, during a low-power mode where the memory domain power supply voltage is greater than the core domain power supply voltage, the controller controls the power multiplexer to select the memory domain power supply voltage.

[0021] To perform this selection, the controller includes a comparator stage that compares the core domain supply voltage with the memory domain supply voltage to determine which voltage is greater than the other. Like any comparator, the comparator is not ideal but operates with a certain voltage offset. In other words, suppose the comparator receives a first voltage at its non-inverting input and a second voltage at its inverting input. Given this input coupling, an ideal comparator would assert its output signal when it detects that the first voltage is greater than the second voltage. However, due to real-world limitations, the comparator can be considered to be formed from an ideal comparator where the first voltage is offset by this offset voltage. For example, suppose the offset voltage is a positive offset voltage equal to 30mV. Therefore, when the first voltage is greater than the second voltage minus 30mV, the resulting comparator will assert its output terminal. Conversely, if the offset voltage is a negative offset voltage equal to -30mV, the comparator will only assert its output signal if the first voltage is greater than the second voltage plus 30mV.

[0022] Offset voltages for real-world comparators are problematic and can lead to undervoltage in memory or performance issues. However, these issues are addressed as discussed further in this article. Now turning to the accompanying figures, in Figure 1 An example integrated circuit 100 with a controller 110 for controlling a power multiplexer 105 is shown. The power multiplexer 105 selects between a core domain (CX) power supply voltage and a memory domain (MX) power supply voltage to provide a selected vmx power supply voltage to an embedded memory 115 (such as static random access memory (SRAM)) in the integrated circuit 100. The CX power supply voltage is also referred to herein as the first power supply voltage. Similarly, the MX power supply voltage is also referred to herein as the second power supply voltage. The memory 115 includes a bit cell array 120 and associated peripheral logic components (e.g., write drivers, write column multiplexers, read column multiplexers, sense amplifiers, etc.). The peripheral logic components are divided into a CX domain portion (Peri-Cx) 130 and a vmx domain portion (Peri-vmx) 125. The CX power supply voltage always powers the CX domain portion 130 of the peripheral logic components, while the vmx power supply voltage selected by the power multiplexer 105 powers the vmx domain portion 125 of the peripheral logic components. The vmx power supply voltage powers the bit cell array 120, while the CX power supply voltage powers the digital core 135 (e.g., the processor).

[0023] As will be explained further, controller 110 includes a comparator ( Figure 1(Not illustrated) to detect which of the MX and CX supply voltages is greater than the other. Controller 110 then instructs power multiplexer 105 to select the larger of the two supply voltages to generate the VMX supply voltage. Like any real-world comparator, the comparator in controller 110 will have a voltage offset that affects the comparison between the MX and CX supply voltages. This voltage offset can then cause power multiplexer 105 to make an undesirable supply voltage selection. For example, consider... Figure 2 The CX and MX power waveforms are shown. The MX power does not change but remains constant. This is due to the mode transition for the digital core 135 (see reference). Figure 1 (Discussion) The CX power supply transitions from a relatively high value greater than a constant value relative to the MX power supply voltage to a relatively low value less than the MX power supply voltage. The offset voltage used for the comparison between the CX and MX power supply voltages can be positive (+offset) or negative (-offset). If the offset voltage is negative, the comparator will de-assert its output signal at time t1 when the sum of the CX power supply voltage and the offset voltage is less than the MX power supply voltage. Then, at time t1, a transition will occur from a selected power supply voltage vmx equal to the CX power supply voltage to a selected power supply voltage equal to the MX power supply voltage.

[0024] Conversely, if the offset voltage is positive, the comparator will assert its output signal at time t2 when the CX supply voltage equals the difference between the MX supply voltage and the positive offset voltage. Such a positive offset voltage could lead to an undervoltage (Vmin) violation for memory 115, because the selection of the MX voltage will not occur until time t2 in this case. The vmx supply voltage will then continue to be equal to the CX supply voltage as it falls below the MX supply voltage, until it eventually falls below the positive offset voltage below the MX supply voltage. If the minimum operating voltage for the bit cell array 120 is some value between the MX supply voltage and the difference between the MX supply voltage and the positive offset voltage, an undervoltage violation occurs for memory 115, potentially causing bits stored in the bit cell array 120 to be lost or corrupted. Then, the transition from the selected supply voltage vmx equal to the CX supply voltage to the selected supply voltage equal to the MX supply voltage will not occur until time t2. From time t1 to time t2, the selected supply voltage vmx can therefore be equal to either the CX supply voltage or the MX supply voltage, depending on whether the offset voltage is positive or negative. Before time t1, the selected power supply voltage vmx is equal to the CX power supply voltage, while after time t2, the selected power supply voltage vmx is equal to the MX power supply voltage.

[0025] When the CX power supply voltage changes from low to high, a similar Vmin violation issue may occur, such as... Figure 3As shown. If the offset voltage is positive, then at time t1, the CX supply voltage plus the positive offset voltage equals the MX supply voltage. Before time t1, the selected supply voltage vmx equals the MX supply voltage, but with a positive offset, at time t1, the selected supply voltage vmx will equal the CX supply voltage, which may cause a Vmin violation until the CX supply voltage eventually rises to equal the MX supply voltage. If the offset voltage is negative, the selected supply voltage vmx will not become equal to the CX supply voltage until time t2, at which time the absolute value of the CX supply voltage minus the negative offset voltage finally equals the MX supply voltage. Therefore, after time t2, the selected supply voltage vmx will equal the CX supply voltage. From time t1 to time t2, the selected supply voltage vmx can equal either the MX supply voltage or the CX supply voltage, depending on whether the offset voltage is positive or negative.

[0026] In addition to Vmin violations, offset voltage can also cause performance violations in memory 115. Figure 4 The diagram illustrates an example low-to-high transition for the CX power supply voltage. Before time t1, the CX power supply voltage is low enough that the selected power supply voltage vmx equals the MX power supply voltage. If the offset voltage is positive, the selected power supply voltage vmx will transition to equal the CX power supply voltage at time t1. Then, when the CX power supply voltage transitions to a high value less than the sum of the absolute values ​​of the MX power supply voltage and the negative offset voltage, no performance violation will occur. However, if the offset voltage equals the negative offset voltage, the selected power supply voltage vmx will not transition to equal the CX power supply voltage because the CX power supply voltage will not rise above the sum of the absolute values ​​of the MX power supply voltage and the negative offset voltage. Therefore, a performance violation begins to occur at time t2 when the selected power supply voltage vmx equals the MX power supply voltage, because the transition to the CX power supply will provide better performance for memory 115.

[0027] It should be understood that similar Vmin violations and performance violations may occur for high-to-low or low-to-high transitions of the MX power supply voltage. However, controller 110 addresses these issues caused by offset voltage. For example, in response to... Figure 2 In the high-to-low transition of the CX power supply voltage discussed, controller 110 controls power multiplexer 105 to select the MX power supply voltage at time t1, regardless of whether the offset voltage is positive or negative. This prevents any Vmin violation in memory 115. Similarly, in response to... Figure 3 During the low-to-high transition of the CX power supply voltage discussed, controller 110 controls power multiplexer 105 to select the CX power supply voltage at time t2, regardless of whether the offset voltage is positive or negative. This again prevents any Vmin violation in memory 115. Furthermore, controller 110 is used to prevent reference violations by controlling power multiplexer 105 to select the CX power supply voltage at time t2. Figure 4 The performance violation being discussed is regardless of whether the offset voltage is positive or negative.

[0028] Example specific implementations of controller 110 include Figure 5 The comparator section 500 is shown. Comparator 501 has a non-inverting terminal (+) and an inverting terminal (-). The non-inverting terminal is also referred to herein as the first input terminal, and the inverting terminal is also referred to herein as the second input terminal. If comparator 501 is ideal, comparator 501 will assert its output signal whenever the voltage at the non-inverting terminal exceeds the voltage at the inverting terminal. As used herein, the "assertion" signal is considered true regardless of whether a high-level active convention or a low-level active convention is used. In the high-level active convention, comparator 501 asserts its output signal by charging the output signal to the supply voltage. In the deassertion state, the output signal is therefore grounded. The following discussion will assume that controller 110 uses the high-level active convention; however, it should be understood that a low-level active convention can also be implemented.

[0029] Due to process, voltage and temperature variations, and other non-ideals, comparator 501 may have a positive or negative voltage offset in its comparison with respect to its input terminal voltages. To prevent such voltage offsets from causing Vmin violations or performance violations in memory 115, comparator 501 switches its input terminals in response to the period of a clock from clock source 520. Clock source 520 generates a clock signal represented as an even clock signal (clk-even). Inverter 525 inverts the even clock signal to produce an odd clock signal (clk-odd). The even and odd clock signals control a pair of switches at each input terminal of comparator 501. These switches will now be described. Switch S1 is coupled between the node for the MX power supply voltage and the non-inverting terminal. Another switch S2 is coupled between the node for the MX power supply voltage and the inverting input terminal. Similarly, switch S3 is coupled between the node for the CX power supply voltage and the non-inverting terminal, while switch S4 is coupled between the node for the CX power supply voltage and the inverting input terminal. The node used for the CX power supply voltage can also be referred to as the first voltage rail in this document. Similarly, the node used for the MX power supply voltage can also be referred to as the second voltage rail in this document. Switches S3 and S2 are configured to close when an even clock signal is asserted. Similarly, switches S1 and S4 are configured to close when an odd clock signal is asserted. Switches S1, S2, S3, and S4 can also be referred to as the first switch, the second switch, the third switch, and the fourth switch in this document, respectively.

[0030] Given this switch configuration, comparator 501 asserts its output signal when the CX power supply voltage is greater than the MX power supply voltage plus an offset voltage (which can be positive or negative) and an odd clock signal is asserted. Switch S5, configured to close when an odd clock signal is asserted, is coupled between latch 505 and the output terminal of comparator 501. Latch 505 inverts the latched output signal obtained from comparator 501 to form output signal A. Latch 505 can be formed by a first pair of cross-coupled inverters. Therefore, when the CX power supply voltage is less than the sum of the MX power supply voltage and the voltage offset for comparator 501, output signal A is binary 0. Similarly, when the CX power supply voltage is greater than the sum of the MX power supply voltage and the voltage offset for comparator 501, output signal A is binary 1.

[0031] A switch S6, configured to close when an even-numbered clock signal is asserted, is coupled between the output terminals of latch 510 and comparator 501. Latch 510 inverts the latched output signal obtained from comparator 501 to form a signal that is inverted by inverter 515 to form output signal B. Latch 510 may be formed by a second pair of cross-coupled inverters. Therefore, when the CX power supply voltage is less than the difference between the MX power supply voltage and the voltage offset for comparator 501, output signal B is binary 0. Similarly, when the CX power supply voltage is greater than the difference between the MX power supply voltage and the voltage offset for comparator 501, output signal B is binary 1. Switches S5 and S6 may also be referred to herein as a fifth switch and a sixth switch, respectively. Similarly, latches 505 and 510 may also be referred to herein as a first latch and a second latch, respectively.

[0032] Note the advantage of the switching inputs of comparator 501: output signal A is the comparison result when the offset voltage is applied to the MX power supply, while output signal B is the comparison result when the offset voltage is subtracted from the MX power supply voltage. By properly processing output signals A and B, controller 110 can thus force the offset to effectively have the correct sign for the corresponding CX (or MX) power supply voltage transition. For example, consider again… Figure 2 The high-to-low transition of the CX power supply voltage. By appropriately processing output signals A and B, controller 110 can control power supply multiplexer 105 to always select the MX power supply at time t1, regardless of whether the offset voltage is actually positive or negative. Therefore, such selection avoids any Vmin violation during the high-to-low transition of the CX power supply voltage. For example, controller 110 may include Figure 6 The pre-logic stage 600 shown includes first logic gates, such as NAND gate 605, for processing output signals A and B. See again... Figure 2 and Figure 5Note that before time t1 when the CX supply voltage minus the offset voltage is greater than the MX supply voltage, both output signals A and B are binary zero. Regardless of whether the offset voltage is negative or positive, NAND gate 605 will assert the output signal PreGoto Mx at time t1 when the CX supply voltage transitions from high to low. For example, suppose the offset voltage is positive. In this case, the CX supply voltage will be less than the MX supply voltage minus the positive offset at time t1, causing output signal B to be deasserted (reset to zero). This zero value of output signal B causes NAND gate 605 to assert the PreGoto MX signal. It should be understood that... Figure 5 The set of logic gates shown for pre-logic level 600 is merely exemplary, and alternative combinations of logic gates can be used to implement pre-logic level 600.

[0033] like Figure 7 As shown, the final logic stage 700 for controller 110 includes logic gates, such as AND gate 705 for processing the Pre Goto MX signal. The final logic stage 700 also receives a Target_CX signal as binary one when the CX supply voltage is asserted to be greater than a threshold. In this example, the CX supply voltage transitions to a low value, so the Target_CX signal is binary zero. Inverter 710 inverts the Target_CX signal to drive AND gate 705 with the inverted output signal. Therefore, regardless of whether the offset voltage is positive or negative, when the CX supply voltage drops below the sum of the absolute values ​​of the MX supply voltage and the offset voltage (which corresponds to...), the Target_CX signal is... Figure 2 At time t1), the output signal Goto MX of the AND gate 705 will be asserted. See again Figure 1 The assertion of the Goto MX signal by controller 110 causes power multiplexer 105 to select the MX power supply voltage to generate a selected power supply voltage vmx for powering the bit cell array 120 and the vmx domain peripheral logic unit 125. The Pre Goto MX signal can also be referred to herein as the first selection signal. It should also be understood that... Figure 7 The set of logic gates shown for final logic level 700 is merely exemplary, and alternative combinations of logic gates can be used to implement final logic level 700.

[0034] Referring again to pre-logic stage 600, inverter 615 inverts the PreGoto MX signal to form an inverted signal received by OR gate 625. Therefore, when the PreGoto MX signal is de-asserted, the PreGoto CX output signal of the OR gate will be asserted. Thus, the PreGoto CX output signal is asserted whenever the CX supply voltage is greater than both the MX supply voltage plus the offset voltage and the MX supply voltage minus the offset voltage. In final logic stage 700, logic gates (such as AND gate 715) can perform an AND operation between the Target_CX signal and the PreGoto CX signal to form the Goto CX signal. See again Figure 1 The controller 110 asserts the Goto CX signal, and the power multiplexer 105 selects the CX power supply voltage. Figure 3 As shown in the low-to-high transition of the CX power supply voltage, it can be understood that the controller 110 will only switch the power multiplexer 105 from selecting the MX power supply voltage to selecting the CX power supply voltage at time t2, thereby avoiding any Vmin violation during the low-to-high transition of the CX power supply voltage. The Pre-Goto CX signal can also be referred to herein as the second selection signal.

[0035] To prevent reference Figure 4 Regarding the performance violation discussed, pre-logic level 600 may include a second logic gate, such as OR gate 610, which performs an OR operation between output signal A and output signal B. Therefore, the output signal of OR gate 610 will be asserted when the CX supply voltage is greater than the MX supply voltage plus an offset voltage, or when the CX supply voltage is greater than the MX supply voltage minus the offset voltage. When the low-to-high transition of the CX supply voltage is complete, the power management circuitry (not illustrated) controlling the transition of the CX supply voltage asserts an acknowledgment signal (ACK). See also... Figure 4 The acknowledgment signal is therefore asserted at time t3. The pre-logic stage 600 may also include logic gates, such as AND gate 620, which performs an AND operation between the output signal from OR gate 610 and the acknowledgment signal. Therefore, the output signal from AND gate 620 is asserted only if the acknowledgment signal is true and the CX supply voltage is greater than the MX supply voltage plus the offset voltage, or the CX supply voltage is greater than the MX supply voltage minus the offset voltage. OR gate 625 performs an OR operation between the output signal from inverter 615 and the output signal from AND gate 620. Therefore, the PreGoto CX signal will only be asserted if the acknowledgment signal is true and the CX supply voltage is greater than the MX supply voltage minus the offset voltage. Figure 4 The assertion is made at time t3, which in turn causes the Goto CX signal to be asserted so that the CX power supply voltage is selected at the power supply multiplexer 105.

[0036] Now refer to Figure 8The flowchart below discusses a method for selecting a power supply voltage. This method occurs during the transition from a first power supply voltage that is less than a second power supply voltage to a voltage greater than the second power supply voltage. An example of the first power supply voltage is the CX power supply voltage, while the MX power supply voltage is a reference voltage. Figure 2 An example of a second power supply voltage during the transition discussed. The method includes action 800: asserting a first output signal in response to a first power supply voltage being greater than the sum of the second power supply voltage and the comparator offset voltage. An assertion of output signal A is an example of action 800. Therefore, output signal A can also be represented herein as the first output signal. The method also includes action 805: asserting a second output signal in response to a first power supply voltage being greater than the second power supply voltage minus the comparator offset voltage. An assertion of output signal B is an example of action 805. Therefore, output signal B can also be represented herein as the second output signal. Finally, the method includes action 810: controlling a power multiplexer to select a first power supply voltage in response to assertions of both the first and second output signals, to power a bit cell array in the memory with the first power supply voltage. Control of power multiplexer 105 by controller 110 is an example of action 810.

[0037] Integrated circuits having power multiplexers and controllers as disclosed herein can be advantageously used in a wide variety of electronic systems. For example, such as Figure 9 As shown, cellular phone 900, laptop computer 9505, and tablet computer 910 may all include an integrated circuit having a power multiplexer and controller according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with an integrated circuit having a power multiplexer and controller constructed according to the present disclosure.

[0038] This disclosure will now be outlined in the following series of provisions:

[0039] Clause 1. An integrated circuit, said integrated circuit comprising:

[0040] The memory includes a bit cell array;

[0041] First voltage rail for the first power supply voltage;

[0042] Second voltage rail for second power supply voltage;

[0043] A power multiplexer configured to select between a first power supply voltage and a second power supply voltage to provide the selected power supply voltage to power the bit cell array; and

[0044] A controller includes a comparator stage configured to switch between the first and second configurations. In the first configuration, a first input terminal of a comparator in the comparator stage is coupled to a first voltage rail, and a second input terminal of the comparator is coupled to a second voltage rail. In the second configuration, the first input terminal is coupled to the second voltage rail, and the second input terminal is coupled to the first voltage rail. The controller is configured to control a power multiplexer to select between a first power supply voltage and a second power supply voltage in response to a first output signal and a second output signal of the comparator stage during operation in both the first and second configurations.

[0045] Clause 2. The integrated circuit according to Clause 1, further comprising:

[0046] A clock source, configured to provide a clock signal; and

[0047] A first inverter, configured to invert the clock signal to provide an inverted clock signal, wherein the comparator stage is configured to switch to the first configuration in response to an assertion of the clock signal, and to switch to the second configuration in response to an assertion of the inverted clock signal.

[0048] Clause 3. The integrated circuit according to Clause 2, further comprising:

[0049] A first switch is coupled between the first voltage rail and the first input terminal;

[0050] A second switch is coupled between the first voltage rail and the second input terminal;

[0051] A third switch, coupled between the second voltage rail and the first input terminal; and

[0052] A fourth switch, coupled between the second voltage rail and the second input terminal, wherein the first switch and the fourth switch are configured to close in response to the assertion of the inverted clock signal, and wherein the second switch and the third switch are configured to close in response to the assertion of the clock signal.

[0053] Clause 4. The integrated circuit according to any one of Clauses 2 to 3, wherein the comparator stage further comprises:

[0054] First latch;

[0055] Second latch;

[0056] A fifth switch, coupled between the output terminal of the comparator and the input terminal of the first latch, wherein the fifth switch is configured to close in response to the assertion of the inverted clock signal, so that the first latch outputs the first output signal;

[0057] A sixth switch, coupled between the output terminal of the comparator and the input terminal of the second latch, wherein the sixth switch is configured to close in response to an assertion of the clock signal; and

[0058] The second inverter is configured to invert the latch signal from the second latch to form the second output signal.

[0059] Clause 5. The integrated circuit according to Clause 4, wherein the first latch includes a first pair of cross-coupled inverters, and wherein the second latch includes a second pair of cross-coupled inverters.

[0060] Clause 6. The integrated circuit according to any one of Clauses 1 to 5, wherein the comparator stage is configured to assert the first output signal in response to the first supply voltage being greater than the sum of the second supply voltage and the offset voltage of the comparator, and to assert the second output signal in response to the first supply voltage being greater than the second supply voltage minus the offset voltage.

[0061] Clause 7. The integrated circuit according to any one of Clauses 1 to 6, wherein the comparator stage is further configured to de-assert the first output signal in response to the first supply voltage being less than the sum of the second supply voltage and the offset voltage of the comparator, and to de-assert the second output signal in response to the first supply voltage being less than the second supply voltage minus the offset voltage.

[0062] Clause 8. The integrated circuit according to Clause 7, wherein the controller further comprises:

[0063] A first logic gate is configured to process the first output signal and the second output signal to form a first selection signal, and wherein the controller is further configured to control the power multiplexer to select the second power supply voltage in response to the binary value of the first selection signal.

[0064] Clause 9. The integrated circuit as described in Clause 8, wherein the first logic gate includes a NAND gate.

[0065] Clause 10. The integrated circuit according to Clause 8, further comprising:

[0066] An inverter, configured to invert the first selection signal to form an inverted output signal, and

[0067] A second logic gate is configured to process the inverted output signal to form a second selection signal, wherein the controller is further configured to control the power multiplexer to select the first power supply voltage in response to the binary value of the second selection signal.

[0068] Clause 11. The integrated circuit according to Clause 10, wherein the second logic gate includes an OR gate.

[0069] Clause 12. The integrated circuit according to any one of Clauses 1 to 11, wherein the integrated circuit further comprises:

[0070] A digital core, which is configured to be powered by the first power supply voltage.

[0071] Clause 13. An integrated circuit according to any one of Clauses 1 to 11, wherein the integrated circuit is included in a cellular phone.

[0072] Clause 14. The integrated circuit according to any one of Clauses 1 to 11, wherein the controller is further configured to control the power multiplexer to select between a first power supply voltage and a second power supply voltage in response to an acknowledgment signal asserted in response to the first power supply voltage completing a voltage level transition.

[0073] Clause 15. A method for selecting a power supply voltage, the method comprising:

[0074] During the transition of the first power supply voltage from being less than the second power supply voltage to being greater than the second power supply voltage:

[0075] The first output signal is asserted in response to the first power supply voltage being greater than the sum of the second power supply voltage and the comparator offset voltage.

[0076] A second output signal is asserted in response to the first power supply voltage being greater than the second power supply voltage minus the comparator offset voltage; and

[0077] In response to an assertion on both the first output signal and the second output signal, the power supply multiplexer is controlled to select the first power supply voltage to power the bit cell array in the memory.

[0078] Clause 16. The method described in Clause 15, further comprising:

[0079] In a comparator having the comparator offset voltage, the first power supply voltage is determined to be greater than the sum of the second power supply voltage and the comparator offset voltage by coupling the first input terminal of the comparator to a first voltage rail for the first power supply voltage and by coupling the second input terminal of the comparator to a second voltage rail for the second power supply voltage.

[0080] Clause 17. The method described in Clause 16 further comprises:

[0081] In the comparator having the comparator offset voltage, the first power supply voltage is determined to be greater than the second power supply voltage minus the comparator offset voltage by coupling the first input terminal of the comparator to the first voltage and by coupling the second input terminal of the comparator to the second voltage rail.

[0082] Clause 18. The method described in Clause 16, further comprising:

[0083] The power multiplexer is controlled to select the second power supply voltage before the assertion of both the first output signal and the second output signal, so as to use the second power supply voltage to power the bit cell array in the memory.

[0084] Clause 19. An integrated circuit, said integrated circuit comprising;

[0085] Power multiplexer; and

[0086] A controller configured to control a power multiplexer to select between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage in response to determining whether a first power supply voltage is greater than a second power supply voltage plus a voltage offset and in response to determining whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset.

[0087] Clause 20. The integrated circuit according to Clause 19, the integrated circuit further comprising a comparator for comparing the first supply voltage and the second supply voltage, wherein the voltage offset is a comparator voltage offset of the comparator.

[0088] Clause 21. The integrated circuit according to any one of Clauses 19 to 20, wherein the integrated circuit further comprises:

[0089] The memory includes an array of bit cells configured to be powered by a selected power supply voltage.

[0090] Clause 22. The integrated circuit according to any one of Clauses 19 to 20, wherein the integrated circuit further comprises:

[0091] A digital core, which is configured to be powered by the first power supply voltage.

[0092] Clause 23. The integrated circuit as described in Clause 22, wherein the digital core includes a processor.

[0093] Clause 24. The integrated circuit according to Clause 21, wherein the memory includes static random access memory.

[0094] It should be understood that many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the equipment disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. An integrated circuit, the integrated circuit comprising: The memory includes a bit cell array; First voltage rail for the first power supply voltage; Second voltage rail for second power supply voltage; A power multiplexer configured to select between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage to power the bit cell array; and A controller includes a comparator stage configured to switch between the first and second configurations. In the first configuration, a first input terminal of a comparator in the comparator stage is coupled to a first voltage rail, and a second input terminal of the comparator is coupled to a second voltage rail. In the second configuration, the first input terminal is coupled to the second voltage rail, and the second input terminal is coupled to the first voltage rail. The controller is configured to control a power multiplexer to select between a first power supply voltage and a second power supply voltage in response to a first output signal and a second output signal of the comparator stage during operation in both the first and second configurations.

2. The integrated circuit according to claim 1, further comprising: A clock source, configured to provide a clock signal; and A first inverter, configured to invert the clock signal to provide an inverted clock signal, wherein the comparator stage is configured to switch to the first configuration in response to an assertion of the clock signal, and to switch to the second configuration in response to an assertion of the inverted clock signal.

3. The integrated circuit according to claim 2, further comprising: A first switch is coupled between the first voltage rail and the first input terminal; A second switch is coupled between the first voltage rail and the second input terminal; A third switch is coupled between the second voltage rail and the first input terminal; and A fourth switch, coupled between the second voltage rail and the second input terminal, wherein the first switch and the fourth switch are configured to close in response to the assertion of the inverted clock signal, and wherein the second switch and the third switch are configured to close in response to the assertion of the clock signal.

4. The integrated circuit of claim 2, wherein the comparator stage further comprises: First latch; Second latch; A fifth switch, coupled between the output terminal of the comparator and the input terminal of the first latch, wherein the fifth switch is configured to close in response to the assertion of the inverted clock signal, so that the first latch outputs the first output signal; A sixth switch, coupled between the output terminal of the comparator and the input terminal of the second latch, wherein the sixth switch is configured to close in response to the assertion of the clock signal; and The second inverter is configured to invert the latch signal from the second latch to form the second output signal.

5. The integrated circuit of claim 4, wherein the first latch includes a first pair of cross-coupled inverters, and wherein the second latch includes a second pair of cross-coupled inverters.

6. The integrated circuit of claim 1, wherein the comparator stage is configured to assert the first output signal in response to the first power supply voltage being greater than the sum of the second power supply voltage and the offset voltage of the comparator, and to assert the second output signal in response to the first power supply voltage being greater than the second power supply voltage minus the offset voltage.

7. The integrated circuit of claim 1, wherein the comparator stage is further configured to de-assert the first output signal in response to the first power supply voltage being less than the sum of the second power supply voltage and the offset voltage of the comparator, and to de-assert the second output signal in response to the first power supply voltage being less than the second power supply voltage minus the offset voltage.

8. The integrated circuit of claim 7, wherein the controller further comprises: A first logic gate is configured to process the first output signal and the second output signal to form a first selection signal, and wherein the controller is further configured to control the power multiplexer to select the second power supply voltage in response to the binary value of the first selection signal.

9. The integrated circuit of claim 8, wherein the first logic gate comprises a NAND gate.

10. The integrated circuit according to claim 8, further comprising: An inverter, configured to invert the first selection signal to form an inverted output signal, and A second logic gate is configured to process the inverted output signal to form a second selection signal, wherein the controller is further configured to control the power multiplexer to select the first power supply voltage in response to the binary value of the second selection signal.

11. The integrated circuit of claim 10, wherein the second logic gate includes an OR gate.

12. The integrated circuit according to claim 1, further comprising: A digital core, which is configured to be powered by the first power supply voltage.

13. The integrated circuit of claim 1, wherein the integrated circuit is included within a cellular phone.

14. The integrated circuit of claim 1, wherein the controller is further configured to control the power multiplexer to select between the first power supply voltage and the second power supply voltage in response to an acknowledgment signal, the acknowledgment signal being asserted in response to the first power supply voltage completing a voltage level transition.

15. A method for selecting a power supply voltage, the method comprising: During the transition of the first power supply voltage from being less than the second power supply voltage to being greater than the second power supply voltage: The first output signal is asserted in response to the first power supply voltage being greater than the sum of the second power supply voltage and the comparator offset voltage. A second output signal is asserted in response to the first power supply voltage being greater than the second power supply voltage minus the comparator offset voltage; as well as In response to an assertion on both the first output signal and the second output signal, the power supply multiplexer is controlled to select the first power supply voltage to power the bit cell array in the memory.

16. The method according to claim 15, further comprising: In a comparator having the comparator offset voltage, the first power supply voltage is determined to be greater than the sum of the second power supply voltage and the comparator offset voltage by coupling the first input terminal of the comparator to a first voltage rail for the first power supply voltage and by coupling the second input terminal of the comparator to a second voltage rail for the second power supply voltage.

17. The method according to claim 16, further comprising: In the comparator having the comparator offset voltage, the first power supply voltage is determined to be greater than the second power supply voltage minus the comparator offset voltage by coupling the first input terminal of the comparator to the first voltage and by coupling the second input terminal of the comparator to the second voltage rail.

18. The method according to claim 16, further comprising: The power multiplexer is controlled to select the second power supply voltage before the assertion of both the first output signal and the second output signal, so as to use the second power supply voltage to power the bit cell array in the memory.

19. An integrated circuit, said integrated circuit comprising; Power multiplexer; and A controller configured to control a power multiplexer to select between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage in response to determining whether a first power supply voltage is greater than a second power supply voltage plus a voltage offset and in response to determining whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset.

20. The integrated circuit of claim 19, further comprising a comparator for comparing the first power supply voltage and the second power supply voltage, wherein the voltage offset is a comparator voltage offset of the comparator.

21. The integrated circuit of claim 19, further comprising: The memory includes an array of bit cells configured to be powered by a selected power supply voltage.

22. The integrated circuit according to claim 19, further comprising: A digital core, which is configured to be powered by the first power supply voltage.

23. The integrated circuit of claim 22, wherein the digital core comprises a processor.

24. The integrated circuit of claim 21, wherein the memory comprises static random access memory.

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