Memory controller, storage system, device and write merging method

Abstract

The application discloses a memory controller, a storage system, a device and a write merging method. The memory controller comprises a preparation module and a cache module; the preparation module is configured to send a first indication instruction to the cache module in the case that an address overlap condition is met between a first write address and a second write address; and the cache module is configured to merge the first write address and the second write address to obtain a third write address and merge first write data and second write data to obtain third write data in the case that the first indication instruction is received. From the perspective of write data correctness, the write merging mechanism is designed in the memory controller to merge write data, the data write correctness of the write request of address overlap is improved, the problem that the memory controller needs to be forced to suspend to ensure the data write correctness of the write request of address overlap is solved, and therefore the bandwidth utilization of the memory controller is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory controller, storage system, device, and write merging method. Background Technology

[0002] In a storage system, the memory controller is used to manage data read and write operations between memory and processing units (such as GPUs or CPUs).

[0003] In related technologies, when a processing unit needs to write data to memory, it sends a write request to the memory controller, which then caches the write request. When an idle transmission channel exists between the memory and the memory controller, the memory controller sends the write request to the memory, which then processes the request to write the corresponding data.

[0004] However, the memory controller in the related technology has low bandwidth utilization. Summary of the Invention

[0005] This application provides a memory controller, a memory system, a device, and a write merging method, the technical solution of which is as follows:

[0006] On one hand, a memory controller is provided, the memory controller including: a preparation module and a cache module, the preparation module being connected to the cache module;

[0007] The preparation module is configured to receive a first write request and a second write request. The first write request corresponds to a first write address and a first write data, and the second write request corresponds to a second write address and a second write data. The second write request is an unprocessed write request received before the first write request. The second write address and the second write data are cached in the cache module. If the first write address and the second write address meet the address overlap condition, a first indication instruction is sent to the cache module. The first indication instruction is used to indicate merging the first write request and the second write request.

[0008] The cache module is configured to, upon receiving the first instruction, merge the first write address and the second write address to obtain a third write address, merge the first write data and the second write data to obtain third write data, and send a third write request to the memory device based on the third write address and the third write data.

[0009] On the other hand, a storage system is provided, the storage system comprising: a memory controller as described above and a memory device, the memory controller being connected to the memory device.

[0010] On the other hand, a computer device is provided, the computer device comprising: a storage system as described above, and a host coupled to the storage system.

[0011] On the other hand, a write merging method is provided, applied in a memory controller, the memory controller including a preparation module and a cache module; the method includes:

[0012] The preparation module receives a first write request and a second write request. The first write request corresponds to a first write address and a first write data, and the second write request corresponds to a second write address and a second write data. The second write request is an unprocessed write request received before the first write request. The second write address and the second write data are cached in the cache module. If the first write address and the second write address meet the address overlap condition, a first indication instruction is sent to the cache module. The first indication instruction is used to indicate merging the first write request and the second write request.

[0013] Upon receiving the first instruction, the cache module merges the first write address and the second write address to obtain a third write address, merges the first write data and the second write data to obtain third write data, and sends a third write request to the memory device based on the third write address and the third write data.

[0014] On the other hand, a computer-readable storage medium is provided, wherein at least one computer program is stored in the storage medium, and the at least one computer program is loaded and executed by a memory controller to implement the above-described write-merge method.

[0015] On the other hand, a computer program is provided that includes computer instructions stored in a computer-readable storage medium. A memory controller reads the computer instructions from the computer-readable storage medium and executes the computer instructions to perform the write-merge method described above.

[0016] The beneficial effects of the technical solutions provided in this application include at least the following:

[0017] On the one hand, the memory controller reduces the number of write requests that the memory device needs to process by merging write requests, thereby reducing the computational burden on the memory device. On the other hand, from the perspective of write data correctness, this application improves the data writing correctness of write requests with overlapping addresses by designing a write merging mechanism in the memory controller to merge write data, solving the problem of needing to forcibly suspend the memory controller to ensure the data writing correctness of write requests with overlapping addresses, thereby improving the bandwidth utilization of the memory controller. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a computer system provided in an exemplary embodiment of this application;

[0020] Figure 2 This is a schematic diagram of a memory controller provided in an exemplary embodiment of this application;

[0021] Figure 3 This is a schematic diagram of write data merging provided in an exemplary embodiment of this application;

[0022] Figure 4 This is a schematic diagram of write data merging provided in another exemplary embodiment of this application;

[0023] Figure 5 This is a schematic diagram of write data merging provided in yet another exemplary embodiment of this application;

[0024] Figure 6 This is a schematic diagram of a memory controller provided in another exemplary embodiment of this application;

[0025] Figure 7 This is a schematic diagram of a memory controller provided in yet another exemplary embodiment of this application;

[0026] Figure 8 This is a schematic diagram of an HBM controller provided in an exemplary embodiment of this application;

[0027] Figure 9 This is a schematic diagram of a queue preparation module provided in an exemplary embodiment of this application;

[0028] Figure 10 This is a schematic diagram of a queue caching module provided in an exemplary embodiment of this application;

[0029] Figure 11 This is a schematic diagram of a queue request module provided in an exemplary embodiment of this application;

[0030] Figure 12 This is a flowchart of a write merging method provided in an exemplary embodiment of this application;

[0031] Figure 13 This is a flowchart of a write merging method provided in another exemplary embodiment of this application;

[0032] Figure 14 This is a flowchart of a write merging method provided in yet another exemplary embodiment of this application;

[0033] Figure 15 This is a structural block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0035] First, the computer system involved in this application will be described.

[0036] The computer system provided in the embodiments of this application may include a host and a storage system. Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application. Figure 1 As shown, the computer system 100 includes a storage system 102 and a host 108 coupled to the storage system 102. The storage system 102 includes a memory device 104 and a memory controller 106 connected to the memory device 104, wherein the memory controller 106 is used to control the memory device 104.

[0037] In some embodiments, the computer system 100 can be integrated into various types of computer devices. These computer devices may be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, etc. In some embodiments, the host 108 includes a processor, which may include at least one of a CPU and a GPU.

[0038] In some embodiments, the memory device 104 may be implemented as main memory. Schematically, the main memory may be implemented as at least one of DRAM (Dynamic Random Access Memory), HBM, and DDR (Double Data Rate Synchronous DRAM). This application embodiment primarily uses HBM (High Bandwidth Memory) as an example for illustration. HBM is a type of memory for high-performance computing based on 3D stacking technology. Multiple DRAM chips are vertically stacked to form HBM. HBM uses a high-bandwidth serial interface to directly connect to the GPU or CPU in the host 108, thereby providing bandwidth far exceeding that of traditional DRAM, meeting the needs of high-performance computing. In some embodiments, HBM is mainly applied to scenarios with high data throughput requirements, such as AI (Artificial Intelligence) chips (e.g., GPUs), high-performance computing, and data center acceleration cards. AI chips can be used for training large models such as LLM (Large Language Model).

[0039] In some embodiments, the memory controller 106 manages data read and write operations in the memory device 104, optimizing data allocation and transmission paths to ensure efficient data transmission and storage. Illustratively, if the memory device 104 is implemented as an HBM, the memory controller 106 may be implemented as an HBM controller.

[0040] This application designs a memory controller 106, in which a preparation module, upon receiving a first write request, determines whether the write address of the first write request matches the write address of a second write request (an unprocessed write request received before the first write request) already cached in the cache module, meeting the address overlap condition. If they match, the preparation module instructs the cache module to merge the first and second write requests. Upon receiving this instruction, the cache module merges the write addresses of the first and second write requests to obtain a third write address and merges the write data of the first and second write requests to obtain third write data. Then, the cache module sends a third write request to the memory device based on the third write address and the third write data. This third write request is the write request obtained by merging the first and second write requests. On one hand, by merging write requests, the memory controller reduces the number of write requests that the memory device needs to process, thus reducing the computational burden on the memory device.

[0041] On the other hand, from the perspective of write data correctness, this application improves the data write correctness of write requests with overlapping addresses by designing a write merging mechanism in the memory controller to merge write data. This solves the problem of needing to forcibly suspend the memory controller to ensure the data write correctness of write requests with overlapping addresses, thereby improving the bandwidth utilization of the memory controller. Specifically: For the first and second write requests that meet the address overlap conditions, if they are not merged, the memory controller 106 may suspend (switch to an invalid state) and wait for the second write request to be completed before the suspension can be lifted, thus solving the data consistency problem in memory. During the suspension period, the memory controller 106 cannot receive new write or read requests, thereby reducing bandwidth utilization. However, the memory controller 106 provided in this application reduces the suspension of the memory controller 106 by merging the first and second write requests that meet the address overlap conditions, thereby improving the bandwidth utilization of the memory controller.

[0042] Furthermore, if the first and second write requests that meet the address overlap condition are not merged, they may access the same memory address or adjacent rows multiple times in a short period of time, thereby increasing the risk of row hammering. However, the memory controller 106 provided in this application can merge the first and second write requests that meet the address overlap condition into a single operation, reducing the number of accesses and thus reducing the risk of row hammering.

[0043] Next, the memory controller 106 in this application will be described. The write merging method involved in the embodiments of this application is executed by the memory controller 106.

[0044] Figure 2 This is a schematic diagram of a memory controller 106 provided in an embodiment of this application. Figure 2 As shown, the memory controller 106 includes a preparation module 1061 and a cache module 1062, with the preparation module 1061 connected to the cache module 1062.

[0045] The preparation module 1061 is configured to: receive a first write request and a second write request, wherein the first write request corresponds to a first write address and a first write data, and the second write request corresponds to a second write address and a second write data; and, if the first write address and the second write address meet the address overlap condition, send a first indication instruction to the cache module, wherein the first indication instruction is used to indicate merging the first write request and the second write request.

[0046] In some embodiments, the first write request is a request sent by the host 108 to the memory controller 106 to request the writing of first write data into the memory device 104. Indicatively, the first write request may be a request sent by the processor (such as a CPU or GPU) in the host 108 to the memory controller 106. The first write address points to a first storage region in the memory device 104; that is, the first write request is used to request the writing of first write data into the first storage region in the memory device 104. It should be noted that, in this application, the specific operation of writing write data into a certain storage region is as follows: if the storage region does not contain data, the write data is directly stored in the storage region; if the storage region contains original data, the original data is updated to write data. For example, if the storage region contains original data, the original data is deleted, and then the write data is written into the storage region.

[0047] The second write request is an unprocessed write request received prior to the first write request. In some embodiments, the second write request is a request sent by the host 108 to the memory controller 106 to request the writing of second write data into the memory device 104. Indicatively, the second write request may be a request sent by a processor (such as a CPU or GPU) in the host 108 to the memory controller 106. The second write address points to a second storage region in the memory device 104; that is, the second write request is used to request the writing of second write data into the second storage region in the memory device 104.

[0048] The second write address and the second write data are cached in the cache module. In other words, the second write request is a write request cached in the cache module 1062. Write requests cached in the cache module 1062 are also write requests that have not yet been sent to the memory device 104, i.e., unprocessed write requests. Illustratively, after receiving the first write request, the preparation module 1061 obtains the write addresses of all write requests cached in the current cache module 1062. If there is a second write address that overlaps with the first write address of the first write request (belonging to the second write request), then the memory controller 106 triggers a write merging process for the first and second write requests.

[0049] In some embodiments, the first write address corresponds to a first address range, which is used to indicate the address range corresponding to the first write data; the second write address corresponds to a second address range, which is used to indicate the address range corresponding to the second write data.

[0050] In some embodiments, the first written data includes at least two sub-data, with different sub-data corresponding to different address units within a first address range. In some embodiments, the second written data includes at least two sub-data, with different sub-data corresponding to different address units within a second address range. In some embodiments, at least one of the following conditions exists among the at least two sub-data corresponding to the first written data (or the at least two sub-data corresponding to the second written data):

[0051] (1) Two sub-data with adjacent and consecutive address units, such as sub-data 1 written to address 100-105 (a total of 6 address units), and the next sub-data 2 written to address 106-110 (the next address after 105), then the address units of these two sub-data are adjacent and consecutive.

[0052] (2) Two sub-data with adjacent but non-contiguous address units, such as sub-data 3 written to address 100-105 (a total of 6 address units), and the next sub-data 4 written to address 107-112, then the address units of these two sub-data are adjacent but non-contiguous.

[0053] In some embodiments, the first write data corresponds to the first mask data, which is used to indicate the valid address units corresponding to the first write data within a first address range. The second write data corresponds to the second mask data, which is used to indicate the valid address units corresponding to the second write data within a second address range. For example, if the address units corresponding to the first address range are A1, A2, A3, and A4, and the first mask data is 1111, it indicates that all address units corresponding to the first address range are valid, and the corresponding first write data are the sub-data corresponding to A1, A2, A3, and A4 respectively; or if the address units corresponding to the first address range are A1, A2, A3, and A4, and the first mask data is 1010, it indicates that address units A1 and A3 are valid, and the corresponding first write data are the sub-data corresponding to A1 and A3 respectively.

[0054] In some embodiments, the first write request corresponds to a first virtual address. Indicatively, the first virtual address is the logical address allocated in the virtual address space by the processor in host 108 for the first write data when generating the first write request.

[0055] In some embodiments, the preparation module 1061 is configured to: convert the first virtual address corresponding to the first write request into the first physical address corresponding to the memory device 104; and convert the data format of the first physical address into a bitmap format to obtain the first write address.

[0056] Here, the first physical address is different from the first virtual address. The first physical address is the actual storage address in the memory device 104. The address space corresponding to the memory device 104 can be called the actual address space. There is an address mapping relationship between the actual address space and the virtual address space. The first virtual address in the virtual address space is converted into the first physical address in the actual address space through the address mapping relationship.

[0057] In some embodiments, after obtaining the first physical address, the data format of the first physical address is converted into a bitmap format to obtain the first write address. The data format of the first write address is a bitmap format, and the data bits in the first write address correspond to address units in the memory device 104. The value of the data bits indicates the occupancy status of the address units by the first data. Schematic, the values ​​of the data bits in the first write address include a first preset value (e.g., 1) and a second preset value (e.g., 0). When the value of the data bit in the first write address is the first preset value, the address unit corresponding to that data bit is in an occupied state, meaning that the first write request requests the first write data to occupy that address unit. When the value of the data bit in the first write address is the second preset value, the address unit corresponding to that data bit is in an idle state, meaning that the first write request does not request the first write data and does not occupy that address unit.

[0058] The method for converting the data format of the first physical address into a bitmap format to obtain the first write address is as follows: In some embodiments, an address mapping table is obtained. The address mapping table records the correspondence between each physical address unit in the memory device 104 and the data bits in the bitmap. For example, if the memory device includes N address units (such as bytes, blocks, or pages), then a bitmap of length N bits can be created, where each bit corresponds to a unique address unit, i.e., the i-th bit corresponds to the i-th address unit, where N and i are positive integers, and i ≤ N. The address mapping table is queried to traverse each address unit in the memory device 104 pointed to by the first physical address. If the first write data occupies a certain address unit (that is, a sub-data of the first write data needs to be written to this address unit), then the value of the data bit corresponding to that address unit in the bitmap is set to 1. If the first write data does not occupy a certain address unit (that is, a sub-data of the first write data does not need to be written to this address unit), then the value of the data bit corresponding to that address unit in the bitmap is set to 0. Finally, a continuous binary number is formed as the first write address, such as "1110". In some embodiments, the bitmap data represented by the first write address may represent the address unit corresponding to the entire memory device 104; or, the bitmap data represented by the first write address may represent the address unit corresponding to the first memory block, wherein the first memory block refers to the memory block corresponding to the first physical address.

[0059] It should be noted that the above description only uses the first write request as an example. In this application, in the preparation module 1061, the addresses of all received read and write requests (such as the first write address of the first write request, the first read address of the first read request, the second write address of the second write request, etc.) are converted into bitmap format data to facilitate subsequent write merging operations. For example, if the first write address of the first write request is "1101" and the second write address of the second write request is "0011", then the operation of merging the first write address and the second write address can be achieved through bitwise operations. For example, by performing a bitwise OR operation, the third address obtained after merging the first write address and the second write address is "1111".

[0060] In the above scheme, by converting the data format of the write address of the write request into a bitmap format, the computational complexity of write merging is reduced and the processing efficiency of the memory controller is improved.

[0061] In some embodiments, the preparation module 1061 is configured to determine that the first write address and the second write address meet the address overlap condition if there is at least a partial identical address between the first write address and the second write address corresponding to the second write request.

[0062] In some embodiments, if there is at least one common address between the first write address of the first write request and the second write address of the second write request, it is determined that the first write address and the second write address meet the address overlap condition. Schematic, if the address range corresponding to the first write address is ABC, the address range corresponding to the second write address is BCD, and the overlapping area is BC, then the first write address and the second write address meet the address overlap condition. In some embodiments, if there is no common address between the first write address of the first write request and the second write address of the second write request, it is determined that the first write address and the second write address do not meet the address overlap condition.

[0063] In some embodiments, the start and end addresses of the address range of the first write address and the second write address are used to determine whether the first write address and the second write address meet the address overlap condition. Illustratively, if the end address of the first write address is greater than or equal to the start address of the second write address and the end address of the second write address is greater than or equal to the start address of the first write address, then the first write address and the second write address meet the address overlap condition; otherwise, the first write address and the second write address do not meet the address overlap condition.

[0064] In some embodiments, if the data format of the first write address and the second write address is implemented as a bitmap format, performing a bitwise AND operation on the first write address and the second write address, if the result is not 0, then it is determined that the first write address and the second write address meet the address overlap condition. For example, if the first write address is "1100" and the second write address is "0011", performing a bitwise AND operation on the two write addresses results in "0000", which is 0, indicating that the first write address and the second write address do not overlap, that is, they do not meet the address overlap condition. For example, if the first write address is "1101" and the second write address is "0011", performing a bitwise AND operation on the two write addresses results in "0001", which is not 0, indicating that the first write address and the second write address overlap, that is, they meet the address overlap condition.

[0065] In the above scheme, determining whether to merge write requests by judging whether there are partial identical addresses can merge multiple write operations targeting the same or partially overlapping storage areas into a single write operation, thereby reducing the number of writes to the memory device, reducing memory wear, extending the memory's lifespan, and also helping to optimize the memory's write process, improve the speed and efficiency of data writing, and enable the memory device to process data write requests more efficiently.

[0066] In some embodiments, the preparation module 1061 is further configured to: determine an overlap ratio threshold based on the current load of the memory device; and determine that the first write address and the second write address meet the address overlap condition if the address overlap ratio between the first write address and the second write address is greater than the overlap ratio threshold. Herein, the current load and the overlap ratio threshold are negatively correlated.

[0067] Wherein, the first write address corresponds to the first address range, the second write address corresponds to the second address range, and the size of the intersection of the first address range and the second address range / the size of the union of the first address range and the second address range = the address overlap ratio of the first write address and the second write address.

[0068] In some embodiments, the current load of the memory device is determined by at least one of bandwidth utilization, response latency, etc. Bandwidth utilization represents the proportion of actual data transfer volume at the interface between the memory controller and the memory device relative to the maximum bandwidth; response latency is the average time taken for the memory device to complete a read / write request from receiving it over a historical period.

[0069] In the above scheme, the overlap ratio threshold is dynamically adjusted according to the current load of the memory device, enabling the memory controller to flexibly control the degree of write request merging. When the memory device load is high, lowering the overlap ratio threshold can more aggressively merge write requests to reduce the number of write operations; when the memory device load is low, increasing the overlap ratio threshold can reduce unnecessary write request merging, maintain the independence and timeliness of write operations, and reduce write latency caused by excessive merging of write requests.

[0070] In some embodiments, when the current load of the memory device is less than or equal to a preset load, if the address overlap ratio between the first write address and the second write address is greater than a preset overlap ratio threshold, it is determined that the first write address and the second write address meet the address overlap condition. When the current load of the memory device is greater than the preset load, if there is at least a partial overlap between the first write address and the second write address, it is determined that the first write address and the second write address meet the address overlap condition.

[0071] Schematic representation: When the current load of the memory device is light (less than or equal to a preset load), the two write addresses are determined to meet the address overlap condition only if the address overlap ratio of the first write address and the second write address is greater than a preset overlap ratio threshold. When the current load of the memory device is heavy (greater than the preset load), the first write address and the second write address are determined to meet the address overlap condition as long as there is at least a partial overlap between them.

[0072] In some embodiments, the preparation module 1061 is further configured to: send a first indication instruction to the caching module if the address overlap condition is met between the first write address and the second write address corresponding to the second write request, and the priority of the first write request is greater than or equal to the priority of the second write request; and send a second indication instruction to the caching module 1062 if the address overlap condition is met between the first write address and the second write address corresponding to the second write request, and the priority of the first write request is less than the priority of the second write request. The second indication instruction is used to instruct the caching module 1062 to cache the first write address and the first write data corresponding to the first write request upon receiving the second indication instruction.

[0073] In some embodiments, the priority of a write request is associated with the urgency (or real-time requirement) of that write request. A higher priority write request indicates that it needs to be processed first. Illustratively, a first write request includes a first priority identifier (e.g., high, medium, low), and a second write request includes a second priority identifier (e.g., high, medium, low). If the first priority identifier is "high" and the second priority identifier is "medium," it means that the first write request has a higher priority than the second write request. If the first priority identifier is "low" and the second priority identifier is "high," it means that the first write request has a lower priority than the second write request.

[0074] In some embodiments, the priority of the third write request obtained by merging the first write request and the second write request is the same as the priority of the first write request.

[0075] In the above scheme, when the first write address and the second write address meet the address overlap condition, the preparation module will further compare the priorities of the first write request and the second write request, and merge the first write request and the second write request only when the priority of the first write request is greater than or equal to the priority of the second write request, so as to prevent the low-priority write request from blocking the timely processing of the high-priority write request.

[0076] In some embodiments, the determination of whether the first write address and the second write address meet the address overlap condition needs to be further combined with the address of the read request in order to avoid data conflicts or inconsistencies.

[0077] In some embodiments, the preparation module 1061 is configured to determine that the first write address and the second write address meet the address overlap condition when there is at least a partial common address between the first write address and the second write address, and when there is no common address between the first write address and the first read address corresponding to the first read request.

[0078] The first read request is an unprocessed read request received prior to the first write request. In some embodiments, the first read request is a request sent by the host 108 to the memory controller 106 to request the reading of first read data from the memory device 104. Indicatively, the first read request may be a request sent by a processor (such as a CPU or GPU) in the host 108 to the memory controller 106. The first read address points to a third storage area in the memory device 104; that is, the first read address is used to request the reading of currently stored data from the third storage area in the memory device 104. In some embodiments, the first read request is a read request cached in the cache module 1062. A read request cached in the cache module 1062 is a read request that has not yet been sent to the memory device 104, i.e., an unprocessed read request. Schematic, after receiving the first write request, the preparation module 1061 obtains the read addresses of all read requests and the write addresses of all write requests cached in the current cache module 1062. If there is a second write address that overlaps with the first write address of the first write request (belonging to the second write request), and there is no first read address that overlaps with the first write address of the first write request (belonging to the first read request), then it is determined that the first write address and the second write address meet the address overlap condition, and the write merging process for the first write request and the second write request is triggered in the memory controller 106.

[0079] The above solution combines the address of the read request with the write address overlap judgment to ensure that no data conflict occurs with unprocessed read requests during write merging. This resolves the problem of data inconsistency or errors caused by write operations overwriting data required by read requests, ensuring data accuracy and reliability.

[0080] In some embodiments, the preparation module 1061 is configured to switch the preparation state of the first write request from a valid state to an invalid state when there is at least a partial overlap between the first write address and the second write address, and when there is an overlap between the first write address and the first read address corresponding to the first read request. When the preparation state of the first write request is valid, the first write request can participate in subsequent processes; when the preparation state of the first write request is invalid, the first write request cannot participate in subsequent processes. In some embodiments, after the first read request is completed, it is determined whether there is a write address in the cache module 1062 that overlaps with the first write address of the first write request. If so, a write merging process is triggered.

[0081] In other embodiments, the preparation module 1061 is configured to send a second instruction to the caching module 1062 if there is no common address between the first write address and the second write address. The second instruction is used to instruct the caching module 1062 to cache the first write request. The caching module 1062 is configured to cache the first write address and the first write data corresponding to the first write request upon receiving the second instruction.

[0082] Indicatively, if there is no common address between the first write address and the second write address, the preparation module 1061 sends a second instruction to the cache module 1062 for the first write request. Upon receiving the second instruction, the cache module 1062 caches the first write address and the first write data corresponding to the first write request.

[0083] The cache module 1062 is configured to: cache the second write address and the second write data corresponding to the second write request; upon receiving an instruction to merge the first write request and the second write request, merge the first write address and the second write address to obtain a third write address, merge the first write data and the second write data to obtain the third write data; and send a third write request to the memory device 104 based on the third write address and the third write data.

[0084] Upon receiving a third write request, the memory device 104 processes the third write request, that is, writes the third write data into the memory area indicated by the third write address.

[0085] The method for merging the first and second write addresses to obtain the third write address is explained.

[0086] In some embodiments, the cache module 1062 is configured to perform a union operation on the first address range corresponding to the first write address and the second address range corresponding to the second write address to obtain a third address range, which also represents the third address.

[0087] In some embodiments, the cache module 1062 is configured to: if the data format of the first write address and the second write address is implemented as a bitmap format, perform a bitwise OR operation on the first write address and the second write address to obtain a third address.

[0088] The method for merging the first and second write data to obtain the third write data is explained.

[0089] In some embodiments, the first write data includes at least two sub-data, the second write data includes at least two sub-data, the first write address includes at least two address units, and the second write address includes at least two address units; the cache module 1062 is configured to merge the first write data and the second write data in at least one of the following ways:

[0090] Replacement operation: Replace the second sub-data in the second written data with the first sub-data in the first written data. The second sub-data and the first sub-data correspond to the same address unit.

[0091] Combination operation: Combine the third sub-data in the first written data and the fourth sub-data in the second written data. The third sub-data and the fourth sub-data correspond to different address units.

[0092] (1) The first write address and the second write address are exactly the same.

[0093] Assume the first write addresses are A1 to A3, where A1 corresponds to valid sub-data 1, A2 corresponds to invalid first-write data (i.e., there is no corresponding sub-data for first-write data on A2), and A3 corresponds to valid sub-data 2. Assume the second write addresses are A1 to A3, where A1 corresponds to valid sub-data 3, A2 corresponds to valid sub-data 4, and A3 corresponds to invalid second-write data (i.e., there is no corresponding sub-data for second-write data on A3). Then, when merging the first and second write data, a replacement operation is triggered for A1, replacing valid sub-data 3 with valid sub-data 1; a combination operation is triggered for A2 and A3, combining valid sub-data 2 and valid sub-data 4. The final third write data is: sub-data 1 (A1), sub-data 4 (A2), and sub-data 2 (A3).

[0094] (2) The first and second write addresses are the same.

[0095] Assume the first write addresses are A1 to A3, where A1 corresponds to valid sub-data 1, A2 corresponds to invalid first-write data, and A3 corresponds to valid sub-data 2. Assume the second write addresses are A2 to A4, where A2 corresponds to valid sub-data 3, A3 corresponds to valid sub-data 4, and A4 corresponds to invalid second-write data. Then, when merging the first and second write data, a replacement operation is triggered for A3, replacing valid sub-data 4 with valid sub-data 2; a combination operation is triggered for A1 and A2, combining valid sub-data 1 and valid sub-data 3. The resulting third write data consists of sub-data 1 (A1), sub-data 3 (A2), and sub-data 2 (A3).

[0096] In some embodiments, when merging the first written data and the second written data, at least one of a replacement operation and a combination operation is performed to obtain the third written data.

[0097] In the above scheme, the correctness of the merged data is ensured through reasonable data merging and replacement operations.

[0098] In some embodiments, the first write data is valid data obtained by masking the first original data with first mask data. The first original data refers to the original write data corresponding to the first write request, and the address range corresponding to the first original data is also the first address range. The second write data is valid data obtained by masking the second original data with second mask data. The second original data refers to the original write data corresponding to the second write request, and the address range corresponding to the second original data is also the second address range. The operation of merging the first write data and the second write data refers to the overwrite operation of the second original data by the first original data. Schematic, if the first address range and the second address range completely overlap or partially overlap, in the overlapping area, the first original data overwrites the second original data. The coverage conditions include at least one of the following: (1) If the first original data on the address units corresponding to the overlapping area are all valid, then after merging, the third written data corresponding to the overlapping area is also the first original data corresponding to the overlapping area; (2) If the first original data on some address units in the overlapping area is valid and the first original data on other address units is invalid, then after merging, the third written data corresponding to the overlapping area includes the first original data on some address units and the data corresponding to other address units (either empty or the corresponding valid second original data); (3) If the first original data on the address units corresponding to the overlapping area are all invalid, then after merging, the third written data corresponding to the overlapping area does not include the first original data, and the third written data corresponding to the overlapping area is empty or the corresponding valid second original data.

[0099] Wherein, "first original data valid" on a specified address unit means that the first mask data corresponding to the specified address unit is a third preset value (e.g., 1); wherein, "first original data invalid" on a specified address unit means that the first mask data corresponding to the specified address unit is a fourth preset value (e.g., 0). The third preset value indicates that the address unit is valid, and the fourth preset value indicates that the address unit is invalid.

[0100] In some embodiments, there is a common storage row address between the first write address and the second write address, the storage row address indicating a first storage row in the memory device 104; the first write request is used to request the writing of first write data to a first portion region of the first storage row.

[0101] Schematic, the memory device 104 includes at least one bank, each bank being divided into at least one row and at least one column. The terms "Bank, Row, Column" specifically represent a storage location within the memory device 104. In related technologies, HBM typically performs read and write operations on a row-by-row basis. For example, when a write request is received that only modifies a portion of the data in a row, the HBM needs to first read the entire row of data stored in the row, adjust the read row according to the write request, and then write the adjusted row back to the row. However, the memory controller 106 provided in this application can merge write requests targeting the same row, thereby eliminating the need for additional read operations during write operations and improving the overall system bandwidth. The following describes three scenarios for merging write requests targeting the same row.

[0102] Case 1: Cache module 1062 is configured to combine the first write data and the second write data to obtain the third write data when the second write request is used to request the writing of the second write data in the second part of the first storage line.

[0103] The first part and the second part constitute the first storage row, and the first part and the second part do not overlap.

[0104] Schematic, the goal of the first write request is to write first write data to a first portion of the first storage line. The goal of the second write request is to write second write data to a second portion of the same first storage line, wherein this second portion does not overlap with the first portion and forms a complete first storage line. In this case, the cache module 1062 combines the first and second write data together to form a third write data.

[0105] Please refer to Figure 3 , Figure 3 A schematic diagram of write data merging is shown. For example... Figure 3 As shown, the first write request is used to write the first write data 301 into the first part area 304 of the first storage line 303, and the second write request is used to write the second write data 302 into the second part area 305 of the first storage line 303. The first part area 304 and the second part area 305 together constitute the complete first storage line 303, and there is no overlapping area between the first part area 304 and the second part area 305. Therefore, the method to obtain the third data is: combine the first write data 301 and the second write data 302 to obtain the third write data, which is also known as... Figure 3 The data portion filled with slashes will be directly written to the first storage line 303.

[0106] Case 2: Cache module 1062 is configured to, in the case of a second write request requesting the writing of second write data in the third part of the first storage line, combine the first write data and the second write data except for the overlapping data to obtain the third write data.

[0107] The first part and the third part constitute the first storage line. There is an overlapping area between the first part and the third part. The overlapping data is the data in the second write data that corresponds to the overlapping area.

[0108] Schematic, the goal of the first write request is to write first write data to a first portion of a first storage line. The goal of the second write request is to write second write data to a third portion of the same first storage line, and this third portion overlaps with the first portion and forms a complete first storage line. In this case, the cache module 1062 extracts the non-overlapping data from the first and second write data, respectively. In the overlapping region, the first write data (the first write request is the newer request) is retained first. The non-overlapping data is combined with the data in the non-overlapping region to form the third write data.

[0109] Please refer to Figure 4 , Figure 4 A schematic diagram of write data merging is shown. For example... Figure 4 As shown, the first write request is used to write the first write data 401 into the first part region 404 of the first storage line 403, and the second write request is used to write the second write data 402 into the third part region 405 of the first storage line 403. The first part region 404 and the third part region 405 together constitute the complete first storage line 403, and there is an overlapping region 406 between the first part region 404 and the third part region 405. Therefore, the method to obtain the third data is to combine the data from the first write data 401 and the second write data 402, excluding the overlapping data 407, to obtain the third write data. The third write data is... Figure 4 The data portion filled with slashes will be directly written to the first storage line 403.

[0110] Case 3: Cache module 1062 is configured to: when the second write request is used to request the writing of the second write data to the entire area of ​​the first storage line, replace the data in the second write data corresponding to the first part of the area with the first write data to obtain the third write data.

[0111] Schematic, the goal of the first write request is to write first write data to a first portion of the first storage line. The goal of the second write request is to write second write data, overwriting the entire first storage line. In this case, the cache module 1062 replaces the data corresponding to the first portion of the second write data with the first write data to obtain the third write data.

[0112] Please refer to Figure 5 , Figure 5 A schematic diagram of write data merging is shown. For example... Figure 5 As shown, the first write request is used to write the first write data 501 into the first part of the storage area 504 of the first storage line 503, and the second write request is used to write the second write data 502 into the entire storage area of ​​the first storage line 503. The method for merging to obtain the third data is as follows: replace the data in the second write data 502 corresponding to the first part of the storage area 504 with the first write data 501 to obtain the third write data. The third write data is also... Figure 5 The data portion filled with slashes will be directly written to the first storage line 503.

[0113] In some embodiments, such as Figure 6 As shown, the memory controller 106 also includes a request module 1063, and a cache module 1062 connected to the request module 1063.

[0114] The cache module 1062 is configured to send a third write request to the request module 1063 based on the third write address and the third write data.

[0115] Schematic, the third write request can be regarded as a write request obtained by merging the first write request and the second write request. The third write request is used to request the writing of third write data in the memory device 104 to the memory area corresponding to the third write address.

[0116] In some embodiments, the caching module 1062 is configured to: upon receiving the first instruction, switch the cache state of the second write request from an active state to an invalid state; merge the first write address and the second write address to obtain a third write address, merge the first write data and the second write data to obtain third write data, and then switch the cache state of the second write request from an invalid state to an active state; and, if the cache state of the second write request is active, send a third write request to the request module 1063 based on the third write address and the third write data.

[0117] Specifically, when the cached state of a write request is valid, the write request can participate in subsequent processes; when the cached state of a write request is invalid, the write request cannot participate in subsequent processes. It should be noted that after merging the first and second write requests to obtain the third write request, the fact that the cached state of the second write request is valid actually means that the cached state of the third write request is valid (the cached state of the third write request is inherited from the valid state of the second write request). In other words, the third write request can participate in subsequent processes, so the cache module 1062 can send the third write request to the request module 1063.

[0118] In the above scheme, by managing the cache state of the second write request, it is ensured that the second write request will not be processed during the merging of the first and second write requests, so that the memory controller can correctly process the write requests in the cache.

[0119] The request module 1063 is configured to send a third write request to the memory device 104 if the third write request meets the write conditions.

[0120] Schematic, the request module 1063 stores at least one write request, including a third write request. At the current moment, the request module 1063 selects a write request that meets the write conditions from the at least one write request and sends it to the memory device 104.

[0121] In some embodiments, a third write request meeting the write conditions includes at least one of the following:

[0122] (1) Among the multiple data transmission channels between the memory device 104 and the memory controller 106, there is an idle data transmission channel. Among them, the idle data transmission channel is sufficient to carry the data transmission amount corresponding to the third write request.

[0123] (2) The priority of the third write request meets the priority requirements. Illustratively, the priority of the third write request is higher than that of other requests stored in the current request module 1063 (such as read requests, write requests, etc.).

[0124] (3) The memory device 104 is in a state where it can receive write requests.

[0125] It should be noted that the examples of writing conditions above are merely illustrative and this application does not impose any limitations on them.

[0126] In some embodiments, the request module 1063 includes at least one storage block, each storage block corresponding to a storage block (Bank) in the memory device 104, and a third write request is written to the target storage block in the request module 1063 according to the third write address, wherein the target storage block corresponds to the target Bank in the memory device 104, and the third write address belongs to (points to) the target Bank.

[0127] Schematic, the HBM (i.e., memory device 104) typically consists of multiple independent banks (e.g., 16 banks). Each bank can independently receive read / write requests, therefore a corresponding read / write request needs to be generated for each bank. Each bank may have at least one read / write request, which is cached in the request module 1063. The request module 1063 stores the read / write requests of a specified bank in a specified storage block. The request module 1063 selects the highest priority request from each storage block. Assuming the HBM includes 16 banks, and the request module 1063 selects a total of 16 requests, then each request corresponds to one bank. At the current moment, the request module 1063 selects one request from these 16 requests and sends it to the HBM, such as determining the request to be sent to the HBM at the current moment based on at least one of the following: bank load, bank priority, or preset order of banks in the HBM.

[0128] In the above scheme, the request module arbitrates the third write request and ensures that it meets the write conditions before sending it to the memory device, thereby improving the validity and correctness of the write request sent to the memory device and improving the reliability of the write operation.

[0129] In some embodiments, such as Figure 7 As shown, the memory controller 106 also includes a write merging module 1064, and a preparation module 1061, a cache module 1062 and a request module 1063 are respectively connected to the write merging module 1064.

[0130] The preparation module 1061 is configured to send a first write request to the write merging module 1064 if the address overlap condition is met between the first write address and the second write address. The write merging module 1064 is configured to send a first instruction to the caching module 1062 if the first write request meets the write merging condition.

[0131] The cache module 1062 is configured to, upon receiving a first instruction, merge the first write address and the second write address to obtain a third write address, and merge the first write data and the second write data to obtain the third write data.

[0132] Schematic, when the address overlap condition is met between the first write address and the second write address, the preparation module 1061 sends a first write request to the write merging module 1064. After receiving the first write request, the write merging module 1064 determines whether the first write request meets the write merging condition. If it does, the write merging module 1064 sends a first indication instruction to the cache module 1062. The first indication instruction is used to indicate merging the first write request and the second write request.

[0133] The above scheme resolves potential conflicts between write merging and subsequent scheduling by setting write merging conditions, while also reducing the number of logic levels (LOL), which is beneficial for physical implementation.

[0134] The following explains how to write merge conditions.

[0135] In some embodiments, the write merging module 1064 is configured to determine that the first write request meets the write merging conditions if the write process corresponding to the second write request has not been started.

[0136] The writing process refers to the process of writing the second write data into the memory device 104.

[0137] In some embodiments, if the second write request is not selected by the request module 1063, a first instruction is sent to the cache module 1062. Indicatively, if the second write request is not loaded into the request module 1063, or if the second write request is not on the pipeline between the cache module 1062 and the request module 1063, it is determined that the second write request was not selected by the request module 1063, meaning the write process corresponding to the second write request has not started.

[0138] In some embodiments, the write merging module 1064 is configured to send a first instruction to the cache module 1062 when the first write request meets the write merging conditions and the second write data has been cached in the cache module 1062.

[0139] In this application, the write data transmission channel and the write address transmission channel in the storage system are separate. Therefore, there is a situation where the write data and the write address are not synchronized. In this case, the process of merging the first write request and the second write request can only be started when the second write data has arrived (and has been cached in the cache module 1062).

[0140] In some embodiments, the write merging module 1064 is configured to: send a wait indication to the cache module 1062 when the first write request meets the write merging conditions and the second write data has not been cached in the cache module 1062. The cache module 1062 is configured to: upon receiving the wait indication, switch the cache state of the first write request from an active state to an inactive state; and when the second write data has been cached in the cache module 1062, switch the cache state of the first write request from an inactive state to an active state. The write merging module 1064 is configured to: send a first indication instruction to the cache module 1062 when the second write data has been cached in the cache module 1062.

[0141] In other embodiments, the write merging module 1064 is configured to send a second instruction to the cache module 1062 if the first write request does not meet the write merging conditions.

[0142] The second instruction is used to instruct the cache to handle the first write request.

[0143] The cache module 1062 is configured to cache the first write address and the first write data corresponding to the first write request when a second instruction is received.

[0144] In some embodiments, when the write process corresponding to the second write request is started, it is determined that the first write request does not meet the write merging condition. Illustratively, when the second write request is selected by the request module 1063, a second instruction is sent to the cache module 1062. For example, if the second write request is loaded into the request module 1063, or if the second write request is on the pipeline between the cache module 1062 and the request module 1063, and it is determined that the second write request has been selected by the request module 1063, i.e., the write process corresponding to the second write request has started, then a second instruction is sent to the cache module 1062.

[0145] In the above scheme, the decision to merge is made by determining whether the write process of the second write request has not started. When the first write request meets the write merging conditions, the write merging module can instruct the cache module to merge the write request. When the write merging conditions are not met, the write merging module can instruct the cache module to cache the first write request separately, thereby avoiding merging operations when the second write request has already started writing to memory, and preventing write conflicts and data inconsistency problems caused by merging.

[0146] In some embodiments, as long as the third write request has not yet started the write process (i.e., it has not been selected by the request module 1063), if there are other new write requests that meet the merging requirements with the third write request, then these other write requests can be merged with the third write request, and so on. The following explanation uses the implementation of other write requests as a fourth write request as an example:

[0147] In some embodiments, the preparation module 1061 is configured to: receive a fourth write request, the fourth write request corresponding to a fourth write address and fourth write data; and send the fourth write request to the write merging module if the fourth write address and the third write address meet the address overlap condition. The write merging module 1064 is configured to: instruct the cache module 1062 to send a third instruction if the write process corresponding to the third write request has not been started, the third instruction being used to instruct the merging of the third write request and the fourth write request. The cache module 1062 is configured to: upon receiving the third instruction, merge the fourth write address and the third write address to obtain a fifth write address, merge the fourth write data and the third write data to obtain fifth write data, and send a fifth write request to the memory device 104 based on the fifth write address and the fifth write data. In some embodiments, the cache module 1062 is configured to: send a fifth write request to the request module 1063 based on the fifth write address and the fifth write data. The request module 1063 is configured to: send a fifth write request to the memory device 104 if the fifth write request meets the write condition.

[0148] In some embodiments, the memory device includes high-bandwidth memory (HBM), and the memory controller includes an HBM controller.

[0149] HBM (High-Performance Memory) is a type of memory used for high-performance computing. Compared to traditional memory, HBM uses a high-bandwidth serial interface to directly connect to a GPU (Graphics Processing Unit) or CPU (Central Processing Unit), thus providing bandwidth far exceeding that of traditional memory and meeting the demands of high-performance computing. In related technologies, the HBM controller manages data read and write operations within the HBM. Illustratively, when the GPU or CPU needs to write data to the HBM, it sends a write request to the HBM controller, which caches the request. When an idle channel exists between the HBM and the HBM controller, the HBM controller sends the write request to the HBM, which processes the request to write the corresponding data. However, the bandwidth utilization of the HBM controller in related technologies is low. Therefore, this application provides an HBM controller, which is described below... Figure 8 Let me introduce it.

[0150] Figure 8 This is a schematic diagram of an HBM controller provided in an embodiment of this application. Figure 8As shown, the HBM controller includes: a queue preparation module 810, a queue cache module 820, a queue request module 830, and a write merging module 840. The queue preparation module 810, the queue cache module 820, and the queue request module 830 are respectively connected to the write merging module 840. The queue preparation module 810 is connected to the queue cache module 820, and the queue cache module 820 is connected to the queue request module 830.

[0151] Please refer to Figure 9 , Figure 9 This is a schematic diagram of a queue preparation module provided in an embodiment of this application. Figure 9 As shown, the queue preparation module 810 is used to receive write requests from the CPU or GPU, and perform the following preprocessing:

[0152] (1) Address translation. The virtual address sent by the CPU or GPU is mapped to the physical address (Bank, Row, Column) of HBM and used as part of the tag content. Wherein Bank represents the storage block (or storage block address), Row represents the storage row in the storage block (or row address), and Column represents the storage column in the storage block (or column address).

[0153] (2) Length processing. The format of the write address is converted into Bitmap format according to the length, which facilitates subsequent write merging.

[0154] (3) Determine whether the write address overlaps with the write address of an existing write request in the queue cache module 820, and determine whether the write address overlaps with the read address of an existing read request in the queue cache module 820. When the write address overlaps with the write address of an existing write request in the queue cache module 820, and the write address does not overlap with the read address of an existing read request in the queue cache module 820, a write merge signal is generated. When the write address does not overlap with the write address of an existing write request in the queue cache module 820, a write request signal is generated. The write request signal is used to pass the write request to the queue cache module 820. For a single write request, the write merge signal and the write request signal cannot be generated simultaneously.

[0155] Among them, the write request channel 1 of the queue preparation module 810 is used to receive write request signals, the address channel 1 is used to receive write addresses, the validity channel 1 is used to receive validity data, the validity data indicates whether the write request is valid, the data channel 1 is used to receive write data, and the mask channel 1 is used to receive mask data.

[0156] Specifically, the write request channel 2 between the queue preparation module 810 and the queue cache module 820 is used for the queue preparation module 810 to send a write request signal to the queue cache module 820; the write merge channel 2 is used for the queue preparation module 810 to send a write merge signal to the queue cache module 820; the identifier channel 2 is used for the queue preparation module 810 to send identifier content to the queue cache module 820; and the data channel 2 is used for the queue preparation module 810 to send write data to the queue cache module 820.

[0157] In some embodiments, the queue preparation module 810 is configured to: receive a first write request and a second write request; convert the first virtual address corresponding to the first write request into a first physical address corresponding to the memory device 104; convert the data format of the first physical address into a bitmap format to obtain a first write address; determine that the first write address and the second write address meet the address overlap condition when there is at least a partial common address between the first write address and the second write address corresponding to the second write request, and there is no common address between the first write address and the first read address corresponding to the first read request; and send the first write request to the write merging module 840.

[0158] The second write request is an unprocessed write request received before the first write request.

[0159] Schematic representation: The first write request corresponds to the first write data. The queue preparation module 810 receives the write request signal corresponding to the first write request through write request channel 1; receives the first virtual address in the first write request through address channel 1; receives the first write data in the first write request through data channel 1; receives the validity data corresponding to the first write request through validity channel 1, the validity data indicating whether the first write request is valid; and receives the first mask data corresponding to the first write data through mask channel 1.

[0160] After receiving the first write request, the queue preparation module 810 maps the first virtual address in the first write request to the first physical address corresponding to HBM, and uses the mapped first physical address as part of the tag content. Then, it converts the data format of the first physical address in the tag content into Bitmap format, and the converted first physical address is the first write address. The data bits in the first write address (bitmap data) correspond to address units in the memory device 104, and the value of the data bits indicates the occupancy status of the address units by the first data. Indicatively, the values ​​of the data bits in the first write address include a first preset value (e.g., 1) and a second preset value (e.g., 0). When the data bit in the first write address is the first preset value, the address unit corresponding to that data bit is in an occupied state, meaning the first write request requests the first write data to occupy that address unit. When the data bit in the first write address is the second preset value, the address unit corresponding to that data bit is in an idle state, meaning the first write request does not request the first write data and does not occupy that address unit.

[0161] After obtaining the first write address, the queue preparation module 810 determines whether the first write address overlaps with the write address of an existing write request (i.e., the second write request) in the queue cache module 820, and whether the first write address overlaps with the read address of an existing read request (i.e., the first read request) in the queue cache module 820. When the first write address overlaps with the write address of an existing write request in the queue cache module 820, and the first write address does not overlap with the read address of an existing read request in the queue cache module 820, a write merge signal is generated. When the write merge signal is generated, the queue preparation module 810 sends the write merge signal to the queue cache module 820 through write merge channel 2; sends an identifier, including the first write address, to the queue cache module 820 through identifier channel 2; sends the first write data to the queue cache module 820 through data channel 2; and sends the first write request to the write merge module 840.

[0162] In other embodiments, if there is no common address between the first write address and the second write address corresponding to the second write request, a second indication instruction is sent to the queue cache module 820. The second indication instruction is used to indicate that the first write request should be cached.

[0163] Schematic, a write request signal is generated when the first write address does not overlap with the write address of an existing write request in the queue cache module 820. When a write request signal is generated, the queue preparation module 810 sends the write request signal to the queue cache module 820 through the write request channel 2; sends an identification content, including the first write address, to the queue cache module 820 through the identification channel 2; and sends the first write data to the queue cache module 820 through the data channel 2.

[0164] Schematic, the write merge module 840 includes the following functions:

[0165] (1) Determine whether the write request currently passed to the queue preparation module 810 meets the write merging condition.

[0166] (2) For write requests that meet the write merging conditions, complete the process of merging them into the queue cache module 820.

[0167] (3) For cache blocks that are about to enter write merging in queue cache module 820, temporarily prevent them from entering queue request module 830.

[0168] (4) Write requests in the filter queue request module 830 are not included in write merging.

[0169] In some embodiments, the write merging module 840 is configured to: upon receiving a first write request, if the second write data has been cached in the queue cache module 820, send a first instruction to the queue cache module 820 if the first write request meets the write merging conditions.

[0170] The first instruction is used to instruct the merging of the first write request and the second write request.

[0171] Schematic, if the second write request is not loaded into the queue request module 830, or if the second write request is not on the pipeline between the queue buffer module 820 and the queue request module 830, it is determined that the second write request was not selected by the queue request module 830, that is, it is determined that the first write request meets the write merging condition. If the first write request meets the write merging condition, the write merging module 840 sends a first indication instruction to the queue buffer module 820. For example, if the first write request meets the write merging condition, the write merging module 840 sets the write merging signal of the queue buffer module 820 to a high level, indicating that the first write request and the second write request need to be merged.

[0172] In other embodiments, the write merging module 840 is configured to: upon receiving a first write request, if the first write request does not meet the write merging conditions, send a second instruction to the queue caching module 820, the second instruction being used to instruct the caching of the first write request.

[0173] Schematic, if the second write request is loaded into the queue request module 830, or if the second write request is on the pipeline between the queue buffer module 820 and the queue request module 830, it is determined that the second write request is selected by the queue request module 830, that is, it is determined that the first write request does not meet the write merging condition. In the case that the first write request does not meet the write merging condition, the write merging module 840 sends a second indication instruction to the queue buffer module 820. For example, in the case that the first write request does not meet the write merging condition, the write merging module 840 sets the write request signal of the queue buffer module 820 to a high level, indicating that the first write request needs to be buffered.

[0174] Please refer to Figure 10 , Figure 10 This is a schematic diagram of a queue caching module provided in an embodiment of this application. Figure 10 As shown, the queue caching module 820 is used to cache multiple write / read requests and includes the following features:

[0175] (1) The queue cache module 820 can cache multiple (e.g., 128) write requests.

[0176] (2) The content cached in the queue cache module 820 includes the write address / service attribute / other and transmission-related attributes of the write request, collectively referred to as the tag content.

[0177] (3) The queue caching module 820 includes valid logic and invalid logic. Valid logic: Determines when a cache request becomes effective (cache status is valid), i.e., it can be sent to the next level. Invalid logic: Determines when a cache request needs to be invalidated (cache status is invalid). If the request has already been sent to HBM, it does not need to be cached again. Or, if the cache request is in the write merging process, it needs to be suspended (determined to be invalid) and wait for the write merging process to be completed before it can be sent to the next level.

[0178] (4) The queue cache module 820 supports write merging operations. After the relevant cache is suspended, the tag content is updated and the write data is updated.

[0179] Specifically, the identification channel 3 between the queue cache module 820 and the queue request module 830 is used for the queue cache module 820 to send identification content to the queue request module 830; the validity channel 3 is used for the queue cache module 820 to send validity data to the queue request module 830, and the validity data indicates whether the write request is valid; the write request channel 3 is used for the queue cache module 820 to send a write request signal to the queue request module 830; and the data channel 3 is used for the queue cache module 820 to send write data to the queue request module 830.

[0180] In some embodiments, the queue caching module 820 is configured to: upon receiving a first instruction, merge the first write address and the second write address to obtain a third write address, merge the first write data and the second write data to obtain third write data; and send a third write request to the queue request module 830 based on the third write address and the third write data.

[0181] Schematic, regarding the first instruction: In the queue cache module 820, assuming that cache block 1 caches the identifier content containing the second write address and the second write data, when the queue cache module 820 receives a write merge signal and the write merge signal is high, it first switches the cache state of the second write request (or the cache state of cache block 1) from the valid state to the invalid state. Then, it merges the first write request and the second write request. The specific merging process includes: merging the identifier content containing the first write address and the identifier content containing the second write address in cache block 1 to obtain the identifier content containing the third write address; merging the first write data and the second write data to obtain the third write data. After the merging process is completed, the cache state of the second write request (or the third write request) is switched from the invalid state to the valid state. Finally, when the cached state of the second write request (or the third write request) is valid, the queue cache module 820 sends the write request signal corresponding to the third write request to the queue request module 830 through the write request channel 3; sends validity data to the queue request module 830 through the validity channel 3, the validity data indicating whether the third write request is valid; sends the identifier content containing the third write address to the queue request module 830 through the identifier channel 3; and sends the third write data to the queue request module 830 through the data channel 3.

[0182] In other embodiments, the queue caching module 820 is configured to: cache the first write address and the first write data corresponding to the first write request upon receiving a second instruction; and send the first write request to the queue request module 830.

[0183] Schematic, regarding the second instruction: When the queue cache module 820 receives a write request signal and the write request signal is high, it caches the identifier content of the first write address and the first write data, for example, caching the identifier content of the first write address and the first write data in cache block 2. Then, when the cache state of the first write request (or the cache state of cache block 2) is valid, the queue cache module 820 sends the write request signal corresponding to the first write request to the queue request module 830 through the write request channel 3; sends validity data to the queue request module 830 through the validity channel 3, the validity data indicating whether the first write request is valid; sends the identifier content containing the first write address to the queue request module 830 through the identifier channel 3; and sends the first write data to the queue request module 830 through the data channel 3.

[0184] Please refer to Figure 11 , Figure 11 This is a schematic diagram of a queue request module provided in an embodiment of this application. Figure 11 As shown, the queue request module 830 is used to generate write requests to be transmitted to HBM, and its responsibilities are as follows:

[0185] (1) Filter and determine the write requests required for each storage block of HBM.

[0186] (2) For each storage block, arbitration comes from multiple requests in the queue request module 830.

[0187] (3) Arbitration is based on write requests from multiple storage blocks. One write request is selected and sent to HBM at the current time.

[0188] Specifically, the identification channel 4 between the queue request module 830 and the memory device 104 is used for the queue request module 830 to send identification content to the memory device 104; the request channel 4 is used for the queue request module 830 to send write requests to the memory device 104; and the data channel 4 is used for the queue request module 830 to send write data to the memory device 104.

[0189] The queue request module 830 is configured to send a third write request to the memory device 104 if the third write request meets the write conditions.

[0190] Upon receiving a third write request, the memory device 104 executes the third write request to write the third write data into the memory area indicated by the third write address.

[0191] Schematic, the queue request module 830 includes multiple storage blocks, each corresponding to a Bank in the HBM. Assuming storage block 1 corresponds to Bank 1 in the HBM, and the third write address corresponding to the third write request belongs to (points to) Bank 1, after receiving the third write request, the queue request module 830 stores the write request signal corresponding to the third write request in Bank 1. The queue request module 830 selects the highest priority request from each storage block. Assuming the queue request module 830 selects a total of 128 requests, each request corresponds to a Bank. At the current moment, the queue request module 830 selects one request from these 16 requests based on information provided by the HBM, including but not limited to at least one of the following: Bank load, Bank priority, and preset order of Banks in the HBM. Specifically, if the queue request module 830 selects the third write request to send to the HBM, the queue request module 830 will send the write request signal corresponding to the third write request to the HBM through request channel 4; send an identifier containing the third write address to the HBM through identifier channel 4; and send the third write data to the HBM through data channel 4. Upon receiving a third write request, the HBM executes the third write request to write the third write data to the storage area in Bank1 indicated by the third write address. When the HBM receives the third write request, it indicates that the third write request has been completed, and at this point, the third write request can be deleted from the queue cache module 820 and the queue request module 830. Optionally, when the queue request module 830 receives a request completion notification from the HBM, it indicates that the third write request has been completed, and at this point, the third write request can be deleted from the queue cache module 820 and the queue request module 830.

[0192] It should be noted that the aforementioned queue preparation module 810 is also known as the preparation module 1061, the queue cache module 820 is also known as the cache module 1062, the queue request module 830 is also known as the request module 1063, and the write merging module 840 is also known as the write merging module 1064. For details not disclosed in the descriptions of "queue preparation module 810, queue cache module 820, queue request module 830, and write merging module 840," please refer to the above descriptions of "preparation module 1061, cache module 1062, request module 1063, and write merging module 1064," which will not be repeated here.

[0193] Schematic, a write-merge operation performed in the HBM controller in this application includes the following procedures:

[0194] (a) The queue preparation module 810 receives a write request from the host (CPU / GPU) and determines how to process the write request, hereinafter referred to as WR0:

[0195] (1) If the write address (WR0) and the addresses cached in the current queue cache module 820 (including write / read addresses) do not overlap, then WR0 is cached in the queue cache module 820, where the write address (WR0) is cached in the queue cache module 820 in the form of tag content. WR0 is also the first write request mentioned above. The queue preparation module 810 sends a write request signal to the queue cache module 820, which is used to directly cache WR0 in the queue cache module 820.

[0196] It should be noted that the addresses cached in the current queue caching module 820 must be the addresses corresponding to requests (including write / read requests) that are in a valid state.

[0197] (2) If the write address (WR0) overlaps with the write address in the current queue cache module 820 (hereinafter referred to as WR1, the existing write request overlapping with the address WR0 in the queue cache module 820), and does not overlap with the read address in the current queue cache module 820, then WR0 is transmitted to the write merging module 840. The queue preparation module 810 also sends a write merging signal to the queue cache module 820, which is used to merge WR0 and WR1 in the queue cache module 820. WR0 is also the second write request mentioned above.

[0198] (3) If the write address (WR0) overlaps with the read address in the current queue cache module 820, to ensure that the initial purpose of the read request in the queue cache module 820 is to read the value in the current HBM, WR0 in the current queue preparation module 810 is suspended (that is, WR0 is set to invalid). After the read request is processed, WR0 in the queue preparation module 810 is set to a valid state, and then it is determined whether the write address (WR0) overlaps with the cached address (including write / read address) in the current queue cache module 820, that is, the above processing process is repeated. In some embodiments, after the read request is processed, the read address corresponding to the read request cached in the queue cache module 820 is deleted, or the cached state of the read request cached in the queue cache module 820 is set to an invalid state.

[0199] (ii) After receiving WR0 from queue preparation module 810, write merging module 840 performs the following processing:

[0200] (1) Write merging module - queue preparation module processing: The write merging module 840 first determines whether WR1 is complete, that is, whether the write data (WR1) of WR1 has arrived. If the write data (WR1) has not yet arrived at HBM (or has not yet arrived at the queue buffer module 820), the write merging module 840 tells the queue preparation module 810 to suspend after receiving WR0 and wait for the write data (WR1) to arrive. When WR1 is complete (that is, the write data (WR1) has arrived), the write merging module 840 sends WR0 to the queue buffer module 820 and pulls up the write merging signal received by the queue buffer module 820, indicating that WR1 and WR0 need to be written merging processed.

[0201] (2) Write merge module - queue cache module processing: The write merge module 840 first determines whether WR1 has been selected by the queue request module 830 and is waiting to be sent. If WR1 has been selected by the queue request module 830, the write merge module 840 stops the write merge process of WR1 and WR0, and places WR0 in the queue cache module 820, occupying a new cache block. If WR1 is not in the queue request module 830, the write merge process of WR0 and WR1 is started:

[0202] First, change the cache state of WR1 from Valid to Invalid. Then, use WR0's data / strobe to overwrite (merge) WR1's data / strobe. WR0's data / strobe is not required to arrive at the current time and is allowed to arrive later. Once WR0's data / strobe arrives and WR1's data / strobe has been updated, change WR1's cache state back from Invalid to Valid. This completes the write merging process. The merged WR1 (i.e., the third write request) can then participate in the selection process of the subsequent queue request module 830. It should be noted that if a new WR2 arrives before the merged WR1 is selected by the queue request module 830, WR2 can then be written and merged with the merged WR1, and so on.

[0203] (3) Write merging module - queue request module processing: The write merging module 840 filters out loaded requests from the requests cached by the queue cache module 820, preventing them from participating in the write merging process. Loaded requests refer to requests already loaded into the queue request module 830. The write merging module 840 filters out requests in the pipeline between the queue cache module and the queue request module, preventing them from participating in the write merging process. These two filtering methods resolve potential conflicts between write merging and subsequent scheduling, while also reducing the number of logical levels (LOL), which benefits the physical implementation.

[0204] In summary, the HBM controller provided in this application achieves the following technical effects:

[0205] (1) In response to multiple write requests with overlapping addresses sent by the host (CPU / GPU) within a short period of time, this application can merge multiple write requests into one write request, thereby improving the overall bandwidth of the system.

[0206] (2) In view of the fact that HBM does not support masked writing and has to implement masked writing by reading first and then writing, this application can merge two masked write requests, so that the system no longer needs to send a read request or perform a read-write conversion, thereby improving the overall bandwidth of the system.

[0207] (3) By merging multiple write requests, the repeated ACT (row activation)-PRE (precharge) operations on a storage block are solved to a certain extent, avoiding excessive row activation (ACT) and precharge (PRE) operations caused by frequent row switching, which would lead to increased latency, increased power consumption and decreased bandwidth utilization.

[0208] (4) By merging multiple write requests, the address conflict blocking problem is solved to some extent. That is, if the system is configured to block the new write request and wait for the write request in the cache block to finish executing first when the new write request and the write request in the cache block point to the same block address, the solution provided in this application can merge the two write requests, no longer blocking the host, and improving system efficiency.

[0209] Next, the specific process of the write merging method involved in this application will be introduced.

[0210] Figure 12 This is a flowchart of a write merging method provided in an exemplary embodiment of this application. In some embodiments, the method is applied to any of the memory controllers described above, such as... Figure 12 As shown, the memory controller includes a preparation module 1061 and a cache module 1062. The method includes the following steps 1210 to 1250.

[0211] Step 1210: Preparation module 1061 receives the second write request.

[0212] The second write request corresponds to a second write address and a second write data, which are cached in the cache module.

[0213] Step 1220: Preparation module 1061 receives the first write request.

[0214] The first write request corresponds to the first write address and the first write data. The second write request is an unprocessed write request received before the first write request.

[0215] In some embodiments, the first write request corresponds to a first virtual address. The preparation module 1061 converts the first virtual address corresponding to the first write request into a first physical address corresponding to the memory device; it converts the data format of the first physical address into a bitmap format to obtain the first write address, wherein the data bits in the first write address correspond to the address units in the memory device, and the values ​​of the data bits indicate the occupancy of the address units by the first write data.

[0216] Step 1230: If the address overlap condition is met between the first write address and the second write address, the preparation module 1061 sends a first instruction to the cache module 1062.

[0217] The first instruction is used to instruct the merging of the first write request and the second write request.

[0218] In some embodiments, if the preparation module 1061 determines that the first write address and the second write address meet the address overlap condition when there is at least a partial identical address between the first write address and the second write address.

[0219] In some embodiments, the preparation module 1061 determines that the first write address and the second write address meet the address overlap condition when there is at least a partial common address between the first write address and the second write address, and when there is no common address between the first write address and the first read address corresponding to the first read request.

[0220] In step 1240, upon receiving the first instruction, the cache module 1062 merges the first write address and the second write address to obtain the third write address, and merges the first write data and the second write data to obtain the third write data.

[0221] In some embodiments, the first written data includes at least two sub-data, the second written data includes at least two sub-data, the first written address includes at least two address units, and the second written address includes at least two address units; the cache module 1062 merges the first written data and the second written data in at least one of the following ways:

[0222] Replacement operation: Replace the second sub-data in the second written data with the first sub-data in the first written data. The second sub-data and the first sub-data correspond to the same address unit.

[0223] Combination operation: Combine the third sub-data in the first written data and the fourth sub-data in the second written data. The third sub-data and the fourth sub-data correspond to different address units.

[0224] In some embodiments, the first write address and the second write address share the same storage row address, the storage row address indicating a first storage row in the memory device; the first write request is used to request the writing of first write data to a first portion region of the first storage row. The method by which the cache module 1062 merges the first write data and the second write data to obtain the third write data includes at least one of the following:

[0225] Scenario 1: When a second write request is used to request writing second write data to the second part of the first storage line, the first write data and the second write data are combined to obtain the third write data. The first part and the second part constitute the first storage line, and there is no overlapping area between the first part and the second part.

[0226] Scenario 2: When the second write request is used to request writing second write data to the third part of the first storage line, the data in the first and second write data, excluding overlapping data, are combined to obtain the third write data. The first and third parts constitute the first storage line, and there is an overlapping area between the first and third parts. The overlapping data is the data in the second write data corresponding to the overlapping area.

[0227] Scenario 3: When the second write request is used to request the writing of the second write data to the entire area of ​​the first storage line, the data corresponding to the first part of the second write data is replaced with the first write data to obtain the third write data.

[0228] Step 1250: The cache module 1062 sends a third write request to the memory device based on the third write address and the third write data.

[0229] The third write request is used to write third write data to the memory area corresponding to the third write address in the memory device.

[0230] Figure 13 This is a flowchart of a write merging method provided in an exemplary embodiment of this application. In some embodiments, the method is applied to any of the memory controllers described above, such as... Figure 13 As shown, the memory controller 106 includes a preparation module 1061, a cache module 1062, a request module 1063, and a write merging module 1064. The method includes steps 1310 to 1370.

[0231] Step 1310: Preparation module 1061 receives the second write request.

[0232] Step 1320: Preparation module 1061 receives the first write request.

[0233] The second write request is an unprocessed write request received before the first write request.

[0234] Step 1330: If the address overlap condition is met between the first write address and the second write address, the preparation module 1061 sends a first write request to the write merging module 1064.

[0235] Step 1340: If the first write request meets the write merging conditions, the write merging module 1064 sends a first instruction to the cache module 1062.

[0236] In some embodiments, the write merging module 1064 determines that the first write request meets the write merging conditions if the write process corresponding to the second write request has not been started; wherein, the write process refers to the process of writing the second write data into the memory device.

[0237] In other embodiments, if the write merging module 1064 does not meet the write merging conditions, it sends a second instruction to the caching module 1062. The second instruction is used to instruct the caching module 1062 to cache the first write request. The caching module 1062 is configured to cache the first write address and the first write data corresponding to the first write request upon receiving the second instruction.

[0238] In step 1350, upon receiving the first instruction, the cache module 1062 merges the first write address and the second write address to obtain the third write address, and merges the first write data and the second write data to obtain the third write data.

[0239] Step 1360: The cache module 1062 sends a third write request to the request module 1063 based on the third write address and the third write data.

[0240] In some embodiments, when the caching module 1062 receives a first merge instruction, it switches the cache state of the second write request from an active state to an inactive state; after merging the first write address and the second write address to obtain a third write address, and merging the first write data and the second write data to obtain third write data, it switches the cache state of the second write request from an inactive state to an active state; when the cache state of the second write request is in the active state, it sends a third write request to the request module 1063 based on the third write address and the third write data.

[0241] Step 1370: If the third write request meets the write conditions, the request module 1063 sends a third write request to the memory device.

[0242] In some embodiments, the memory device includes high-bandwidth memory (HBM), and the memory controller includes an HBM controller. Figure 14 This is a flowchart of a write merging method provided in an exemplary embodiment of this application. In some embodiments, the method is applied in an HBM controller, such as... Figure 14As shown, the HBM controller 800 includes: a queue preparation module 810, a queue buffer module 820, a queue request module 830, and a write merging module 840. The method includes steps 1410 to 1470.

[0243] Step 1410: The queue preparation module 810 receives and caches the second write request.

[0244] Step 1420: The queue preparation module 810 receives the first write request; converts the first virtual address corresponding to the first write request into the first physical address corresponding to the memory device; and converts the data format of the first physical address into a bitmap format to obtain the first write address.

[0245] In step 1430, if the queue preparation module 810 meets the address overlap condition between the first write address and the second write address, it sends a first write request to the write merging module 840.

[0246] In some embodiments, the queue preparation module 810 determines that the first write address and the second write address meet the address overlap condition when there is at least a partial common address between the first write address and the second write address corresponding to the second write request, and there is no common address between the first write address and the first read address corresponding to the first read request.

[0247] In other embodiments, if there is no common address between the first write address and the second write address corresponding to the second write request, the queue preparation module 810 sends a second indication instruction to the queue caching module 820. The second indication instruction is used to indicate that the first write request should be cached.

[0248] Step 1440: The write merging module 840 receives the first write request; if the first write request meets the write merging conditions, it sends a first instruction to the queue cache module 820.

[0249] The first instruction is used to instruct the merging of the first write request and the second write request.

[0250] In other embodiments, if the first write request does not meet the write merging conditions, the write merging module 840 sends a second instruction to the queue caching module 820, the second instruction being used to instruct the cache of the first write request.

[0251] In step 1450, upon receiving the first instruction, the queue cache module 820 merges the first write address and the second write address to obtain the third write address, and merges the first write data and the second write data to obtain the third write data.

[0252] Step 1460: The queue cache module 820 sends a third write request to the queue request module 830 based on the third write address and the third write data.

[0253] In other embodiments, upon receiving a second instruction, the queue caching module 820 caches the first write address and the first write data corresponding to the first write request and sends the first write request to the queue request module 830.

[0254] Step 1470: If the third write request meets the write conditions, the queue request module 830 sends a third write request to HBM.

[0255] It should be noted that the apparatus and method embodiments provided in the above embodiments belong to the same concept. For details of the specific implementation process of the method embodiments, please refer to the apparatus embodiments, which will not be repeated here.

[0256] This application provides a computer device, which includes a storage system 102 as described in any of the above embodiments, and a host 108 coupled to the storage system 102. The computer device may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, etc.

[0257] Indicatively, Figure 15 This is a structural block diagram of a computer device 1500 provided in an exemplary embodiment of this application. In some embodiments, the computer device 1500 includes a memory controller 106, a memory device 104, and a processor 110. The memory controller 106 and the memory device 104 are connected, and the memory controller 106 and the processor 110 are connected.

[0258] Processor 110 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 110 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Processor 110 may also include a main processor and a coprocessor. The main processor, also known as a central processing unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 110 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 110 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0259] In some embodiments, the computer device 1500 further includes an input interface and an output interface. The memory controller 106, memory device 104, processor 110, and the input and output interfaces can be connected via a bus or signal lines. Various peripheral devices can be connected to the input and output interfaces via a bus, signal lines, or a circuit board. The input and output interfaces are used to connect at least one input / output (I / O) related peripheral device to the processor 110, memory controller 106, and memory device 104. In some embodiments, the processor 110, memory controller 106, memory device 104, and the input and output interfaces are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 110, memory controller 106, memory device 104, and the input and output interfaces can be implemented on separate chips or circuit boards, and this application embodiment does not limit this.

[0260] Those skilled in the art will understand that Figure 15 The structure shown does not constitute a limitation on the computer device 1500, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0261] This application provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a memory controller to implement any of the write merging methods described in the above embodiments.

[0262] This application provides a computer program including computer instructions stored in a computer-readable storage medium. A memory controller reads the computer instructions from the computer-readable storage medium and executes the computer instructions to perform the write-merge method described above.

[0263] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0264] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The above descriptions are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory controller, characterized in that, The memory controller includes a preparation module and a cache module, wherein the preparation module is connected to the cache module; The preparation module is configured to receive a first write request and a second write request. The first write request corresponds to a first write address and a first write data, and the second write request corresponds to a second write address and a second write data. The second write request is an unprocessed write request received before the first write request. The second write address and the second write data are cached in the cache module. If the first write address and the second write address meet the address overlap condition, a first indication instruction is sent to the cache module. The first indication instruction is used to indicate merging the first write request and the second write request. The cache module is configured to, upon receiving the first instruction, merge the first write address and the second write address to obtain a third write address; and merge the first write data and the second write data to obtain third write data. The method for merging the first write data and the second write data includes at least one of the following: replacing a second sub-data in the second write data with a first sub-data in the first write data, wherein the second sub-data and the first sub-data correspond to the same address unit; and combining a third sub-data in the first write data and a fourth sub-data in the second write data, wherein the third sub-data and the fourth sub-data correspond to different address units. The cache module is configured to send a third write request to the memory device based on the third write address and the third write data.

2. The controller according to claim 1, characterized in that, The preparation module is configured to determine that the first write address and the second write address meet the address overlap condition if there is at least a partial overlap between the first write address and the second write address.

3. The controller according to claim 1, characterized in that, The preparation module is configured to determine that the address overlap condition is met between the first write address and the second write address when there is at least a partial common address between the first write address and the second write address, and there is no common address between the first write address and the first read address corresponding to the first read request. The first read request is an unprocessed read request received before the first write request.

4. The controller according to any one of claims 1 to 3, characterized in that, There is a common storage row address between the first write address and the second write address, the storage row address indicating a first storage row in the memory device; the first write request is used to request that the first write data be written in a first portion region of the first storage row; The caching module is configured to combine the first write data and the second write data to obtain the third write data when the second write request is used to request the writing of the second write data in the second part of the first storage line, wherein the first part and the second part constitute the first storage line and do not overlap. The caching module is configured to, when the second write request is used to request the writing of the second write data in the third part of the first storage line, combine the first write data and the data in the second write data excluding overlapping data to obtain the third write data, wherein the first part and the third part constitute the first storage line, and there is an overlapping area between the first part and the third part, and the overlapping data is the data in the second write data corresponding to the overlapping area; The caching module is configured to, when the second write request requests to write the second write data in the entire area of ​​the first storage line, replace the data in the second write data corresponding to the first part of the area with the first write data to obtain the third write data.

5. The controller according to any one of claims 1 to 3, characterized in that, The memory controller includes: a write merging module; the preparation module and the cache module are respectively connected to the write merging module; The preparation module is configured to send the first write request to the write merging module if the address overlap condition is met between the first write address and the second write address. The write merging module is configured to send the first instruction to the cache module when the first write request meets the write merging conditions.

6. The controller according to claim 5, characterized in that, The write merging module is configured to determine that the first write request meets the write merging conditions when the write process corresponding to the second write request has not been started; wherein, the write process refers to the process of writing the second write data into the memory device.

7. The controller according to claim 5, characterized in that, The write merging module is further configured to send a second instruction to the caching module if the first write request does not meet the write merging conditions. The second instruction is used to instruct the caching module to cache the first write request. The caching module is further configured to cache the first write address and the first write data corresponding to the first write request when the second instruction is received.

8. The controller according to any one of claims 1 to 3, characterized in that, The first write request corresponds to a first virtual address; The preparation module is configured to convert the first virtual address corresponding to the first write request into the first physical address corresponding to the memory device. The preparation module is configured to convert the data format of the first physical address into a bitmap format to obtain the first write address. The data bits in the first write address correspond to the address units in the memory device, and the values ​​of the data bits indicate the occupancy of the address units by the first write data.

9. The controller according to any one of claims 1 to 3, characterized in that, The memory controller includes: a request module; the cache module is connected to the request module; The caching module is configured to send a third write request to the request module based on the third write address and the third write data; The request module is configured to send the third write request to the memory device if the third write request meets the write conditions.

10. The controller according to claim 9, characterized in that, The caching module is configured to, upon receiving the first instruction to merge, switch the cache state of the second write request from the valid state to the invalid state; after merging the first write address and the second write address to obtain the third write address, and merging the first write data and the second write data to obtain the third write data, switch the cache state of the second write request from the invalid state to the valid state. The caching module is configured to send a third write request to the request module based on the third write address and the third write data when the cache state of the second write request is in the valid state.

11. The controller according to any one of claims 1 to 3, characterized in that, The memory device includes high-bandwidth memory (HBM), and the memory controller includes an HBM controller.

12. A storage system, characterized in that, The storage system includes a memory controller and a memory device as described in any one of claims 1 to 11, wherein the memory controller is connected to the memory device.

13. A computer device, characterized in that, The computer device includes: the storage system as described in claim 12, and a host coupled to the storage system.

14. A write merging method, characterized in that, Applied in a memory controller, the memory controller includes: a preparation module and a cache module; the method includes: The preparation module receives a first write request and a second write request. The first write request corresponds to a first write address and a first write data, and the second write request corresponds to a second write address and a second write data. The second write request is an unprocessed write request received before the first write request. The second write address and the second write data are cached in the cache module. If the first write address and the second write address meet the address overlap condition, a first indication instruction is sent to the cache module. The first indication instruction is used to indicate merging the first write request and the second write request. Upon receiving the first instruction, the cache module merges the first write address and the second write address to obtain a third write address; it also merges the first write data and the second write data to obtain third write data. The method for merging the first write data and the second write data includes at least one of the following: replacing the second sub-data in the second write data with the first sub-data in the first write data, where the second sub-data and the first sub-data correspond to the same address unit; and combining the third sub-data in the first write data and the fourth sub-data in the second write data, where the third sub-data and the fourth sub-data correspond to different address units. The cache module is configured to send a third write request to the memory device based on the third write address and the third write data.

15. The method according to claim 14, characterized in that, The method further includes: The preparation module determines that the address overlap condition is met between the first write address and the second write address if there is at least a partial overlap between the first write address and the second write address, and if there is no overlap between the first write address and the first read address corresponding to the first read request. The first read request is an unprocessed read request received before the first write request.

16. The method according to claim 14 or 15, characterized in that, The memory controller includes: a write merging module; If the preparation module receives a first indication instruction from the cache module when the address overlap condition is met between the first write address and the second write address, the instruction includes: If the address overlap condition is met between the first write address and the second write address, the preparation module sends the first write request to the write merging module. If the first write request meets the write merging conditions, the write merging module sends the first instruction to the cache module.

17. The method according to claim 16, characterized in that, The method further includes: If the first write request does not meet the write merging conditions, the write merging module sends a second instruction to the caching module. The second instruction is used to instruct the caching of the first write request. Upon receiving the second instruction, the caching module caches the first write address and the first write data corresponding to the first write request.

18. The method according to claim 14 or 15, characterized in that, The memory controller includes: a request module; The cache module sends a third write request to the memory device based on the third write address and the third write data, including: The caching module sends a third write request to the request module based on the third write address and the third write data; If the third write request meets the write conditions, the request module sends the third write request to the memory device.

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