Large-scale timer management system based on systolic array and shift register
By using an architecture based on pulsating arrays and shift registers, the performance bottleneck of traditional hardware timer management in large-scale concurrent scenarios is solved, and the scalability and low latency characteristics of the timer management system are realized.
Patent Information
- Application Number
- CN202510989303.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-17
- Publication Date
- 2025-11-14
AI Technical Summary
Traditional hardware timer management solutions struggle to meet power consumption, area constraints, and packet processing rate requirements in large-scale concurrent scenarios, and existing solutions cannot effectively manage large-scale timers, impacting system performance.
An architecture based on systolic arrays and shift registers is adopted. Through hardware primitive decoding, shift mask generation, shift register module and temporary register module, the abstract actions of the timer are defined, including registration, deletion and update, to achieve efficient management of the timer.
It achieves good scalability and low latency characteristics of a large-scale timer management system, and can increase the number of timers without affecting the system fan-out and logic levels, with an operation time interval of up to 5 clock cycles.
Smart Images
Figure CN120950124A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of network processing, specifically relating to a large-scale timer management system based on a systolic array and a shift register. Background Technology
[0002] In hardware offloading scenarios such as network switching, network offloading, and acceleration, efficient management of large-scale concurrent timers has become a key factor restricting system performance. The design of the timer management architecture must simultaneously meet the real-time scheduling requirements of massive timers and the line-rate requirements of network forwarding / processing. However, traditional hardware timer management solutions have significant bottlenecks in terms of hardware scalability or operational complexity, making it difficult to adapt to power consumption, area (PPA) constraints, and packet processing rate requirements in large-scale scenarios.
[0003] In the field of programmable switching architectures, such as PSA (Programmable Switch Architecture) and PNA (Packet Processing Network Architecture), a time-to-live (TTL) mechanism can be configured for each matching action entry—the entry is automatically deleted if it does not match a target flow within its TTL; if it matches, the timer is refreshed. Real-world testing data from Tofino commercial switches shows that the size of such matching entries typically exceeds 8K. In network service offloading scenarios such as RDMA (Remote Direct Data Access) and TOE (TCP Offload Engine), reliable service flows rely on retransmission counters to ensure service reliability: each flow initializes a retransmission timer when sending a request, refreshes the counter upon receiving a response, deletes the timer upon completion of the response, and triggers a retransmission request upon timeout. Taking the CX6 network adapter as an example, it supports up to 8K concurrent flows. In such scenarios, how to maintain line-rate flow processing and forwarding rates while achieving efficient management of large-scale timers becomes a core challenge in hardware architecture design. Summary of the Invention
[0004] To address the aforementioned problems in the prior art, this invention provides a large-scale timer management system based on a systolic array and a shift register. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a large-scale timer management system based on systolic arrays and shift registers. It employs a systolic array architecture to define abstract actions for the timers, comprising: several cascaded systolic array sub-units; wherein, Each pulsating array sub-unit includes: The hardware primitive decoding module is used to parse the instructions received by the pulsating array sub-unit and output shift signals and control signals; A shift mask generation module is used to output a control mask according to the control signal; The shift register module is used to complete the time sorting of the timer inside the pulsating array sub-unit according to the shift signal and the control mask, and transmit the shift signal and the control mask to the hardware primitive generation module; The temporary register module is used to store the last element in the shift register module; The hardware primitive generation module is used to generate new hardware primitives based on shift signals and control signals, and pass the new hardware primitives to the next level of pulsating array sub-units connected in series with the current pulsating array sub-unit. The output of the first systolic array subunit in a series of systolic array subunits is used as the output of the large-scale timer management system.
[0005] In one embodiment of the present invention, the abstract action of the timer includes: Registration, deletion, and updating; among them, The registration is used to generate new timer events; The deletion is used to delete the original timer event; The update is used to reset the original timer events.
[0006] In one embodiment of the present invention, the shift register module includes M shift register sub-units, the large-scale timer management system includes N systolic array sub-units, and the maximum count value that the large-scale timer management system can store is N×M.
[0007] In one embodiment of the present invention, the hardware primitives supported by the pulsating array sub-unit include: Push_ID, Push_first, Delete_ID, Pop; among them, Pop and Push_ID can be valid simultaneously.
[0008] In one embodiment of the present invention, the data format stored internally in the pulsating array sub-unit is ID+DATA; where ID represents a timer event and DATA represents the absolute time of the timer.
[0009] In one embodiment of the present invention, the operation process of Push_ID includes: Inject ID and Data into the current pulsating array sub-cell. Compare the ID and Data with the elements of each shift register sub-cell in the current pulsating array sub-cell by broadcasting. Obtain the ID comparison result and Data comparison result. Use the ID comparison result to confirm the deletion position and use the Data comparison result to determine the insertion position to complete the shift enable.
[0010] In one embodiment of the present invention, the operation process of Delete_ID includes: The current systolic array sub-unit searches for the target ID in its own shift register module and deletes it. If the target ID is not found, the current systolic array sub-unit does not move and outputs Delete_ID to the next level systolic array sub-unit.
[0011] In one embodiment of the present invention, the operation process of Pop includes: Shift all elements of the shift register module in the current systolic array subcell to the right and output Pop to the next systolic array subcell after the current systolic array subcell.
[0012] In one embodiment of the present invention, the Push_first operation process includes: The last element of the shift register module in the current systolic array sub-unit is used as the first element of the shift register module in the next systolic array sub-unit.
[0013] The beneficial effects of this invention are: In the solution provided by this invention, each systolic array sub-unit is independent of each other. When expanding the number of timers managed by the system, the added sub-units will not affect the fan-out and logic level of the system, thus giving the large-scale timer management system good scalability. By using a systolic array architecture to define abstract actions for the timers, the operation time between each abstract action only needs to be spaced at most 5 clock cycles before the next operation can be performed. Compared with traditional methods, this invention has lower latency characteristics. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of a large-scale timer management system based on a systolic array and a shift register, provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the hardware primitives supported by the pulse array subunit in a large-scale timer management system based on a pulse array and shift register provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of a pulse array subunit in a large-scale timer management system based on a pulse array and a shift register, provided in an embodiment of the present invention. Figure 4 This is a precise schematic diagram of a sample clock in a large-scale timer management system based on a systolic array and shift register provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the first case of Push_ID in a large-scale timer management system based on systolic array and shift register provided in an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the second case of Push_ID in a large-scale timer management system based on a systolic array and shift register, as provided in an embodiment of the present invention. Figure 7 This is a schematic diagram illustrating the third case of Push_ID in a large-scale timer management system based on a systolic array and shift register provided in an embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the fourth case of Push_ID in a large-scale timer management system based on a systolic array and shift register provided in an embodiment of the present invention. Figure 9 This is a schematic diagram illustrating the fifth case of Push_ID in a large-scale timer management system based on a systolic array and shift register provided in an embodiment of the present invention. Figure 10 This is a schematic diagram illustrating the sixth case of Push_ID in a large-scale timer management system based on a systolic array and shift register provided in an embodiment of the present invention. Figure 11 This is a schematic diagram illustrating the seventh case of Push_ID in a large-scale timer management system based on a systolic array and shift register provided in an embodiment of the present invention. Figure 12 This is a schematic diagram illustrating a case where Push and Pop do not need to be compared in a large-scale timer management system based on a systolic array and shift register, as provided in an embodiment of the present invention. Figure 13 This is a schematic diagram illustrating the situation where Push and Pop need to be compared in a large-scale timer management system based on a systolic array and shift register, as provided in an embodiment of the present invention. Figure 14 This is a schematic diagram of the precise clock period of a large-scale timer management system based on a systolic array and a shift register, provided in an embodiment of the present invention. Figure 15 This is a schematic diagram illustrating the first case of finding the element insertion position in a large-scale timer management system based on a systolic array and a shift register, as provided in an embodiment of the present invention. Figure 16 This is a schematic diagram illustrating the second case of finding the element insertion position in a large-scale timer management system based on a systolic array and a shift register, provided as an embodiment of the present invention. Detailed Implementation
[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0016] A general-purpose timer management system should have the following basic functionalities: 1. Timer registration mechanism: Assign a unique ID to each timer and initialize the timer value (Data) to complete the creation and state initialization of the counting event; 2. Timer retrieval mechanism: Quickly locate the target timer by ID, and realize dynamic refresh and status update of the timer value; 3. Timer cancellation mechanism: Search and delete the corresponding timer based on its ID to release system resources; 4. Timed triggering mechanism: When the timer expires, the event is popped from the queue and delivered to the processing module for event processing.
[0017] Furthermore, to meet the management needs of large-scale timers, the system architecture must possess good scalability to avoid processing latency jitter caused by resource contention and to meet the dual requirements of network hardware for real-time performance and throughput. The design of this system needs to balance hardware resource consumption (such as storage capacity and power consumption) with processing performance, achieving coordinated optimization of timer management and high-speed forwarding under PPA (power consumption, area, performance) constraints.
[0018] There are two common implementation schemes for large-scale timer management: The Simple Cycle Check Timer (SCC) decrements each timer in the list by 1. If a timer reaches 0, a corresponding event is triggered. If a system has a large number of timers, such as 1 million, then 1 million subtractions need to be performed, and a priority encoder is required to encode the results. This process can affect timing accuracy and consume too many resources.
[0019] Multilevel Queue Timer (MQT) divides timers into different levels. When adding a timer, it is first inserted into the largest granularity queue. If it expires, it is inserted into the next level. Each timer, except for the first one in the queue, only retains its relative value to the previous timer, so only the head of the queue needs to be checked. However, this approach consumes significant computational resources when adding timers, and the frequent addition operations can potentially become a bottleneck for the entire system.
[0020] Furthermore, neither of the above two solutions can fully support the basic functional system required by the timer management system.
[0021] To address the aforementioned problems, this invention provides a large-scale timer management system based on systolic arrays and shift registers. This system uses a systolic array architecture to define abstract actions for the timers, such as... Figure 1 As shown, it may include: Several cascaded pulsating array sub-units; among which, Each pulsating array sub-unit includes: The hardware primitive decoding module is used to parse the instructions received by the pulsating array sub-unit and output shift signals and control signals; The shift mask generation module is used to output a control mask based on the control signal; The shift register module is used to complete the time sorting of the timer inside the pulsating array sub-unit according to the shift signal and control mask, and transmit the shift signal and control mask to the hardware primitive generation module. The temporary register module is used to store the last element in the shift register module; The hardware primitive generation module is used to generate new hardware primitives based on shift signals and control signals, and pass the new hardware primitives to the next level of pulsating array sub-units connected in series with the current pulsating array sub-unit. The output of the first systolic array subunit in a series of systolic array subunits is used as the output of the large-scale timer management system.
[0022] This invention provides a large-scale timer management system based on systolic arrays and shift registers. It adopts a systolic array architecture, defines three abstract actions for the timer, and the overall architecture is composed of several systolic array sub-units. Each systolic array sub-unit has four basic hardware primitives. The systolic array sub-units use shift registers as a local sorting architecture. It is designed with a hybrid architecture of shift registers and systolic arrays and supports update operations.
[0023] Specifically, embodiments of the present invention introduce the systolic array and shift register used in priority queue management into the management of large-scale timer values. This large-scale timer management system, such as... Figure 1 As shown, it is mainly composed of N pulsating array sub-units connected in series.
[0024] Hardware primitives supported by the pulsating array sub-cell, such as Figure 2 As shown, it may include: Push_ID, Push_first, Delete_ID, Pop; among them, Pop and Push_ID can be valid simultaneously.
[0025] Pulsating array sub-cells, such as Figure 3 As shown, it may include: The module includes a hardware primitive decoding module, a shift register module, a shift mask generation module, a temporary register module, and a hardware primitive generation module.
[0026] The shift register module may include M shift register sub-units, and the large-scale timer management system may include N systolic array sub-units. The maximum number of count values that the large-scale timer management system can store may be N×M. The data format stored internally by each systolic array sub-unit is ID+DATA; where ID represents the timer event and DATA represents the absolute time of the timer.
[0027] The temporary register module is used to store a copy of the first element in the next-level shift register module. The elements in the temporary register module and the shift register module in the current systolic array sub-unit can be shifted to the right within the range of M+1. When the last element in the shift register module in the current systolic array sub-unit, i.e. the M-1th shift register sub-unit, is shifted to the left, its element will be directly pushed into the first shift register sub-unit in the next shift register module.
[0028] Based on the expiration times stored in the systolic array sub-units, the shift register modules within the systolic array are arranged sequentially from smallest to largest, with larger expiration times stored to the left of smaller ones. Therefore, a maximum of N×M count values can be stored, corresponding to N×M timing tasks. Multiple parallel queues can be designed and implemented to manage timers with different counting precisions. An absolute timer can be set outside the systolic array to retain the current time, updating at the microsecond or millisecond level depending on the application scenario. Only a comparison with the head element of the systolic array sub-unit at the beginning of the systolic array is needed to determine whether a pop operation is required, thus completing the next action; there is no need to compare or update the timing value of each individual entry.
[0029] In the systolic array sub-unit, after receiving the hardware primitive signals passed from the top level or upper level, it decodes them into two parts: DATA and ID (shift signals) used for indexing are passed to the shift register module to determine the control signals for each shift register sub-unit; the individual control signals from the upper level are passed to the shift mask generation module to generate a control mask (control signals), which is then returned to the shift register module. After the shift register module completes its operation, it backs up the last element of the current systolic array sub-unit in a temporary register and passes ID+DATA and the individual control signals to the hardware primitive generation module to generate the hardware primitive signals for the next-level systolic array sub-unit.
[0030] The advantage of using a systolic array and shift register in this embodiment of the invention is that each systolic array sub-unit only needs to transmit actions, and by increasing the number of systolic array sub-units, it can be ensured that while increasing the number of manageable timer events, there will be no load problem caused by broadcast comparison.
[0031] The abstract actions of a timer can include: Registration, deletion, and updating; among them, Registered to generate new timer events; Delete, used to delete the existing timer event; Update, used to reset the existing timer events.
[0032] Depending on the application scenario of the data stream, this embodiment of the invention abstracts three operations for the timer queue in this architecture: registration, deletion, and update. Timer registration mechanism: Assign a unique ID to each timer and initialize the timer value to complete the creation and state initialization of counting events; Timer cancellation mechanism: Search for and delete the corresponding timer based on its ID to release system resources; Timer retrieval mechanism: Quickly locate the target timer by ID to achieve dynamic refresh and status update of the timer value.
[0033] The hardware primitives supported by the pulsating array subcell may include: Push_ID, Push_first, Delete_ID, Pop; among them, Pop and Push_ID can be valid simultaneously.
[0034] To implement the three abstract actions for queues mentioned above, specific hardware actions need to be designed for systolic arrays. In addition to the common Push, Pop, and Delete operations, this invention also proposes a Push_first operation, the precise clock of which is illustrated in the following diagram. Figure 4 As shown, this is used to directly push elements into the first shift register sub-unit of the next level systolic array sub-unit, without comparing them with other elements.
[0035] Users only need to connect to the first systolic array sub-unit. When a new timing event needs to be registered, the event is registered from the first-level systolic array sub-unit. When an event needs to be deleted or refreshed, the event is pushed to the first-level systolic array sub-unit. When it is necessary to observe whether there are any timing tasks that have expired, it is only necessary to PEEK the first-level systolic array sub-unit. When it is found that the expired event it carries is less than or equal to the global time, the POP primitive can be used on the first-level systolic array sub-unit.
[0036] The meaning of ID match is: find the ID in the current shift register subcell; the meaning of DATA match is: find the appropriate insertion position in the current shift register subcell, that is, there are elements greater than DATA and elements less than DATA at the same time.
[0037] The Push_ID operation process may include: Inject ID and Data into the current pulsating array sub-cell. Compare the ID and Data with the elements of each shift register sub-cell in the current pulsating array sub-cell by broadcasting. Obtain the ID comparison result and Data comparison result. Use the ID comparison result to confirm the deletion position and use the Data comparison result to determine the insertion position to complete the shift enable.
[0038] Specifically, Push_ID: This operation injects ID and Data into the systolic array sub-cell. Since it doesn't distinguish whether the ID already exists in the queue, both registration and update operations can be implemented by this action. That is, after the ID and Data enter, they are compared with the elements in each shift register sub-cell via broadcast. The deletion position is determined by the ID comparison result, and the insertion position is determined by the Data comparison result, i.e., shift enable. Because ID and Data need to be compared simultaneously, there are four possible cases: 1. If both the target ID and Data are found in the current shift register module, or if there is a free space in this stage, then no action is propagated to the next stage. Figure 5 , Figure 6 As shown, when Push_id=9 and Data=3, the element can be inserted in systolic array sub-cell 0, so there is no need to continue passing commands to subsequent systolic array sub-cells; 2. If only the target ID is found in the current shift register module, but not the Data value (i.e., the Data value of the target ID has increased), then this stage needs to perform a left shift and continue propagating the Push operation to the next stage. Therefore, Push_ID and Pop operations are propagated to the next stage. It can be proven that when Push_ID is valid, the Pop operation will no longer propagate to the next stage. Figure 7 , Figure 8 As shown, when Push_id=9 and Data=16, although the corresponding ID is found at the pulsating array sub-cell 0, it is smaller than the head element of the lower sub-cell. Therefore, it is necessary to push the element to the lower level and at the same time pop the head element of the lower level to the pulsating array sub-cell 0. 3. If only Data is found in the current shift register module but not ID, it means that the element can be inserted into the current shift register module. This means all elements after the ID at this level are shifted left. However, it cannot be determined whether the same ID exists in subsequent systolic array sub-cells. Therefore, a Delete operation needs to be passed to the next level to delete the element with the target ID, and the last element of this level is pushed into the next level. Figure 9 , Figure 10 As shown; 4. If the target ID and Data are not found in the current shift register module, then only the Push_ID action is propagated to the next stage, such as... Figure 11 As shown.
[0039] The process of deleting ID may include: The current systolic array sub-unit searches for the target ID in its own shift register module and deletes it. If the target ID is not found, the current systolic array sub-unit does not move and outputs Delete_ID to the next level systolic array sub-unit.
[0040] Specifically, Delete: This operation searches for the target ID in the queue and deletes it. If not found, the current level does not move, but outputs the Delete operation to the next level. If the target ID is found, the elements after the target ID are shifted to the right, and a Pop operation is issued to the next level. Figure 10 The left-side pulsating array sub-unit 1 is shown.
[0041] The operation process of Pop, such as Figure 8 As shown, it may include: Shift all elements of the shift register module in the current systolic array subcell to the right and output Pop to the next systolic array subcell after the current systolic array subcell.
[0042] The Push_first operation process may include: The last element of the shift register module in the current systolic array sub-unit is used as the first element of the shift register module in the next systolic array sub-unit.
[0043] Specifically, Push_first: In the third case of Push_ID, there is a possibility of pushing the last element of the current systolic array sub-unit into the next level. Since the order in the queue is known to be arranged in ascending order of Data, the last element of this level must be the first element stored in the next level shift register module. Therefore, there is no need to perform broadcast comparison again. The next level shift register module can be set and shifted directly.
[0044] Based on the above analysis of various operations, it can be statistically determined that when a push operation occurs in the current pulsating array sub-unit, two operations may occur simultaneously in the next level, as shown in Table 1. These two situations may lead to left shift and right shift occurring simultaneously in the same pulsating array sub-unit. According to the encoding, the shift can be completed within one cycle, thereby ensuring the correctness of the simultaneous execution of the two operations.
[0045] Table 1 Situation Table
[0046] It can be seen that when a push operation occurs, there are two situations that can cause two operations to occur simultaneously in the queue: When ID matches but DATA does not match, push and pop operations may occur simultaneously in the subsequent stage. Since ID matching has already occurred in this stage, push in the subsequent stage can only cause the element to shift left, and pop can only cause the element to shift right. The two shifts can cancel each other out, simplifying the control logic for resolving conflicts. If the ID does not match, but the DATA does match, then the subsequent operations may both delete and push_first occur simultaneously. In the design of this embodiment, it is specified that the above four actions need to be completed in four cycles, which is aligned with the push operation. The push operation completes the four steps of enabling, comparing, shifting or setting, and ending, and outputs the delete, pop or push_first operation to the next stage in the fourth cycle.
[0047] The pop operation does not require a comparison process and, in principle, can be completed in fewer cycles. Figure 12 As shown, however, since the pop operation may occur simultaneously with the push operation during the propagation of the shift register sub-units, and the push operation requires all elements in the current shift register sub-unit to be in a stable position during the comparison phase, while the pop operation may be in the shifting or incomplete shifting phase at this time, causing the push to fail, a null operation is added to the pop operation process in the design to align to 4 cycles; during the compare phase of the push, it is compared with the first element in the next level shift register sub-unit to determine whether the currently inserted DATA should be placed in the next level or the last element of the current level, so as to avoid the situation where the DATA is not found in a suitable position in the current level, and due to the pop operation, it is mistakenly placed in the first element of the next level instead of the last shift block of the current level, such as... Figure 13 As shown, this situation is illustrated.
[0048] When delete and push_first occur simultaneously, it is only necessary to ensure that all elements after the matched ID remain unchanged, while all elements before the matched ID are shifted to the left and overwrite the position of the matched ID.
[0049] The architecture of this invention requires that there be at least four cycles between any two adjacent operations, and their timing relationship is as follows: Figure 14 As shown, from Figure 14 It can be seen that push or pop operations are issued to the next level in the finish stage of level N-1. After the finish stage of level N, the first element of this level needs to be stabilized before the compare process in the push operation can be correctly executed in level N-1. This requires at least 4 cycles, that is, 5 cycles are needed to complete each operation.
[0050] The key to the internal control logic of the systolic array sub-unit lies in correctly finding the element insertion position and shifting. This invention employs centralized control of all shift register sub-units within a single systolic array sub-unit, and then introduces an encoding calculation method to solve for shifts and set points, simplifying the implementation logic and reducing resource overhead.
[0051] The ID retrieval process involves broadcasting and comparing it with the ID stored in each shift register subunit. If they are equal, the corresponding position is set to 1. After forming a bit code table, the corresponding ID position is found through priority encoding.
[0052] When performing Delete or Push_ID operations, if the ID matches successfully, the result will be represented as a one-hot code; if the Data comparison succeeds, the result will consist of consecutive 0s and consecutive 1s. The set signal and shift control signal determine the position of 0 or 1 through Boolean operations. Solving the control commands of shift register sub-cells using priority encoding consumes significant resources. When the Push_ID operation successfully matches both ID and Data within a systolic array sub-cell, this can lead to left or right shifts in other elements, which will be illustrated with examples here.
[0053] Given an element with ID=2 and Data=21, this diagram illustrates how to find the element's insertion position. Figure 15 As shown, the ID matching result is: push_id_flag, and the data comparison result is: push_data_flag. The set signal is calculated based on the data comparison result. Since the insertion position is to the left of the ID matching position, it needs to be shifted to the right. A 1 is added to the highest bit of the data comparison result. ; Subtract 1 from it and invert it to get the set signal set_en: ; The calculation of the right-shift enable signal `right_en` requires combining the ID matching result with the data comparison result. Subtract 1 from the ID matching result and XOR it with `push_data_flag_lp` to obtain the right-shift enable signal `right_en`. ; Therefore, after inputting an element ID=2, Data=21, the set signal is: 8'b00100000, and the shift signal is: 8'b00011100.
[0054] If an element is input with ID=9 and Data=9, here is a diagram illustrating how to find the element's insertion position, as shown below. Figure 16As shown, the matching ID position is to the left of the matching Data position, therefore some elements need to be shifted left. Subtracting 1 from the data comparison result and inverting it yields the set signal: ; The left-shift enable signal left_en is obtained by subtracting 1 from the id matching result, performing a bitwise OR operation with the data comparison result, and then padding the right side with 0.
[0055] ; Therefore, after inputting an element ID=9 and Data=9, the set signal is: 8'b0000 0100, and the shift signal is: 8'b0111 1000. The set and shift signals for Push_first, Delete, and Pop are calculated using the same method.
[0056] This invention proposes a large-scale timer management system based on systolic arrays and shift registers for smart network interface cards (NICs) and programmable switches. Addressing the challenge of traditional hardware structures failing to meet the demands of large-scale concurrent timer usage in hardware offloading scenarios such as network switching, network offloading, and acceleration, this invention provides a hardware system for managing large-scale timers using systolic arrays and shift registers. It defines three abstract actions for timers: registration, deletion, and update, and designs four hardware actions. Through timer value comparison and transmission, it achieves unified management of timer events. The systolic array structure provides excellent scalability for large-scale timer management scenarios. By increasing the number of systolic array sub-units, the number of elements can be increased without increasing the load on the broadcast signal. The use of shift registers for accelerated sorting within the systolic array sub-units reduces hardware latency caused by sorting.
[0057] In this embodiment of the invention, each systolic array subunit is independent of the others. When expanding the number of timers managed by the system, the added subunits will not affect the fan-out and logic levels of the system, thus enabling the large-scale timer management system to have good scalability. By using a systolic array architecture to define abstract actions for the timers, the operation time between each abstract action only needs to be spaced at most 5 clock cycles before the next operation can be performed. Compared with traditional methods, this invention has lower latency characteristics.
[0058] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0059] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A large-scale timer management system based on systolic arrays and shift registers, characterized in that, a systolic array architecture is used to define abstract actions for timers. include: Several cascaded pulsating array sub-units; among which, Each pulsating array sub-unit includes: The hardware primitive decoding module is used to parse the instructions received by the pulsating array sub-unit and output shift signals and control signals; A shift mask generation module is used to output a control mask according to the control signal; The shift register module is used to complete the time sorting of the timer inside the pulsating array sub-unit according to the shift signal and the control mask, and transmit the shift signal and the control mask to the hardware primitive generation module; The temporary register module is used to store the last element in the shift register module; The hardware primitive generation module is used to generate new hardware primitives based on shift signals and control signals, and pass the new hardware primitives to the next level of pulsating array sub-units connected in series with the current pulsating array sub-unit. The output of the first systolic array subunit in a series of systolic array subunits is used as the output of the large-scale timer management system.
2. The large-scale timer management system based on systolic array and shift register according to claim 1, characterized in that, The abstract actions of the timer include: Registration, deletion, and updating; among them, The registration is used to generate new timer events; The deletion is used to delete the original timer event; The update is used to reset the original timer events.
3. A large-scale timer management system based on a systolic array and shift register as described in claim 1, characterized in that, The shift register module includes M shift register sub-units, the large-scale timer management system includes N systolic array sub-units, and the maximum count value that the large-scale timer management system can store is N×M.
4. A large-scale timer management system based on a systolic array and shift register as described in claim 1, characterized in that, The hardware primitives supported by the pulse array sub-unit include: Push_ID, Push_first, Delete_ID, Pop; among them, Pop and Push_ID can be valid simultaneously.
5. A large-scale timer management system based on a systolic array and shift register according to claim 4, characterized in that, The data format stored internally in the pulse array subunit is ID+DATA; where ID represents the timer event and DATA represents the absolute time of the timer.
6. A large-scale timer management system based on a systolic array and shift register according to claim 5, characterized in that, The operation process for Push_ID includes: Inject ID and Data into the current pulsating array sub-cell. Compare the ID and Data with the elements of each shift register sub-cell in the current pulsating array sub-cell by broadcasting. Obtain the ID comparison result and Data comparison result. Use the ID comparison result to confirm the deletion position and use the Data comparison result to determine the insertion position to complete the shift enable.
7. A large-scale timer management system based on a systolic array and shift register according to claim 5, characterized in that, The operation process of Delete_ID includes: The current systolic array sub-unit searches for the target ID in its own shift register module and deletes it. If the target ID is not found, the current systolic array sub-unit does not move and outputs Delete_ID to the next level systolic array sub-unit.
8. A large-scale timer management system based on a systolic array and shift register according to claim 4, characterized in that, The Pop operation process includes: Shift all elements of the shift register module in the current systolic array subcell to the right and output Pop to the next systolic array subcell after the current systolic array subcell.
9. A large-scale timer management system based on a systolic array and shift register according to claim 4, characterized in that, The Push_first operation process includes: The last element of the shift register module in the current systolic array sub-unit is used as the first element of the shift register module in the next systolic array sub-unit.