Instruction execution method and device and processor

Abstract

The invention relates to an instruction execution method and device and a processor. The method comprises the steps that whether a to-be-executed instruction comprises an extension instruction prefix or not is recognized; if yes, extracting a first field used for marking operation code mapping of a to-be-executed instruction from the to-be-executed instruction; judging whether a second field related to a variable-length vector register and a third field related to a variable-length mask register are extracted from the to-be-executed instruction or not according to the first field; if the second field and the third field are extracted from the to-be-executed instruction, executing the to-be-executed instruction according to the first field, the second field, the third field and an operation code and an addressing mode field included in the to-be-executed instruction; and if the second field and the third field are not extracted from the instruction to be executed, executing the instruction to be executed according to the first field, the operation code and the addressing mode field. Therefore, the portability of software can be improved, and the x86 instruction can be easily expanded.

Description

Technical Field

[0001] This disclosure relates to the field of computers, and more particularly to an instruction execution method, apparatus and processor. Background Technology

[0002] Due to its historical compatibility design, the x86 vector instruction set architecture faces challenges in achieving cross-platform software portability. The instruction extension mechanism is limited by the x86 variable-length instruction encoding system, and the introduction of new instructions requires complex decoding logic. As the SIMD bit width has expanded from 128 bits to 512 bits, the instruction encoding space is nearing saturation. Summary of the Invention

[0003] In view of this, the present disclosure proposes an instruction execution method, apparatus and processor, thereby improving software portability and facilitating the extension of x86 instructions.

[0004] According to a first aspect of this disclosure, an instruction execution method is provided, comprising: identifying whether an instruction to be executed includes an extended instruction prefix; if the instruction to be executed includes the extended instruction prefix, extracting a first field from the instruction to be executed for marking the opcode mapping of the instruction to be executed; determining, based on the first field, whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the instruction to be executed, wherein the variable-length vector register is used for vector operations and the variable-length mask register is used for mask control; if it is determined that the second field and the third field should be extracted from the instruction to be executed, executing the instruction to be executed based on the first field, the second field, the third field, and the opcode and addressing mode field included in the instruction to be executed; if it is determined that the second field and the third field should not be extracted from the instruction to be executed, executing the instruction to be executed based on the first field, the opcode, and the addressing mode field.

[0005] In one possible implementation, the first field includes a first bit field for marking the opcode mapping of the instruction to be executed. Determining whether to extract the second field and the third field from the instruction to be executed based on the first field includes: determining whether the first bit field is a first value; if the first bit field is determined to be the first value, then determining not to extract the second field and the third field from the instruction to be executed; if the first bit field is determined to be a value other than the first value, then determining to extract the second field and the third field from the instruction to be executed.

[0006] In one possible implementation, executing the instruction to be executed based on the first field, the second field, the third field, and the opcode and addressing mode fields included in the instruction to be executed includes: determining information related to the variable-length vector register and the variable-length mask register based on the first field, the second field, and the third field; determining the function of the instruction to be executed based on the opcode; determining the source register and destination register of the instruction to be executed based on the addressing mode fields; and performing operations on the instruction to be executed corresponding to the function of the instruction to be executed based on the information, the source register, and the destination register.

[0007] In one possible implementation, the first field further includes a second bit field for accessing extended register resources, the second field including a third bit field for accessing extended register resources and a fourth bit field for identifying the processing to be performed on an inactive variable-length mask register, the third field including a fifth bit field for identifying the index of the variable-length mask register, and determining information related to the variable-length vector register and the variable-length mask register based on the first field, the second field, and the third field, including: determining addressable variable-length vector registers based on the second bit field and the third bit field; determining masking operations to be performed on inactive variable-length mask registers based on the fourth bit field; and determining active variable-length mask registers based on the fifth bit field.

[0008] In one possible implementation, based on the information, the source register, and the destination register, the operation corresponding to the function of the instruction to be executed is performed on the instruction to be executed, including: obtaining the source operand based on the source register; loading multiple data elements in parallel according to the addressed variable-length vector register; performing the operation corresponding to the function of the instruction to be executed on the data elements that need to participate in the operation from the source operand and the loaded multiple data elements that correspond to the activated variable-length mask register; and performing the masking operation on the inactive variable-length mask register.

[0009] In one possible implementation, performing an operation on the instruction to be executed corresponding to the function of the instruction to be executed includes: if the opcode is a predetermined operation value, then determining that the function of the instruction to be executed is a predetermined function, and performing a predetermined operation corresponding to the predetermined function on the instruction to be executed. The predetermined operation includes addition, subtraction, multiplication, division, shift operation, logical AND, logical NAND, logical OR, logical XNOR, logical XOR, bitwise NOT, bitwise OR operation, bitwise OR operation on two source operands and setting a flag bit according to the result, left shift operation, right shift operation, operation of packing bit test mask and setting flag bit, or unpacking operation.

[0010] In one possible implementation, when the predetermined operation is the move operation, the operation corresponding to the function of the instruction to be executed is performed on the instruction to be executed, including: if the opcode is a first operation value, then the instruction to be executed is moved from memory to the activated variable-length mask register; if the opcode is a second operation value, then the instruction to be executed is moved from the activated variable-length mask register to memory; if the opcode is a third operation value, then the instruction to be executed is moved from a general-purpose vector register to the activated variable-length mask register; if the opcode is a fourth operation value, then the instruction to be executed is moved from the activated variable-length mask register to a general-purpose vector register.

[0011] In one possible implementation, the above instruction execution method further includes: determining the bit width of the shift operation of the variable-length mask register based on the flag bit of the first bit field and whether the instruction to be executed includes a prefix of the third field having a preset value.

[0012] In one possible implementation, the bit width of the move operation of the variable-length mask register is determined based on the flag bit and whether the instruction to be executed includes a prefix with a preset value in the third field. This includes: if the flag bit is 0 and includes a prefix with a preset value, the bit width of the move operation is 1 byte; if the flag bit is 0 and does not include a prefix with a preset value, the bit width of the move operation is 2 bytes; if the flag bit is 1 and includes a prefix with a preset value, the bit width of the move operation is 4 bytes; and if the flag bit is 1 and does not include a prefix with a preset value, the bit width of the move operation is 8 bytes.

[0013] In one possible implementation, the first field further includes a second bit field for accessing extended register resources. Executing the instruction to be executed based on the first field, the opcode, and the addressing mode field includes: determining an addressable variable-length vector register based on the second bit field; determining the function of the instruction to be executed based on the opcode; determining the source register and destination register of the instruction to be executed based on the addressing mode field; and performing an operation on the instruction to be executed corresponding to the function of the instruction to be executed based on the addressed variable-length vector register, the source register, and the destination register.

[0014] In one possible implementation, the first field includes a first bit field for marking the opcode mapping of the instruction to be executed, and the instruction execution method further includes: if the flag bit of the first bit field is a first flag value, then the instruction to be executed is determined to be a private variable-length vector instruction; if the flag bit of the first bit field is a second flag value different from the first flag value, then the instruction to be executed is determined to be not the private variable-length vector instruction.

[0015] In one possible implementation, the instruction execution method further includes: loading and operation instructions for updating the variable-length mask register, as well as mask operations.

[0016] In one possible implementation, the instruction execution method further includes: if an exception occurs during the execution of the instruction to be executed, reporting the exception to a system register.

[0017] According to a second aspect of this disclosure, an instruction execution apparatus is provided, comprising: a decoding unit configured to identify whether an instruction to be executed includes an extended instruction prefix; if the instruction to be executed includes the extended instruction prefix, extracting a first field from the instruction to be executed for marking an opcode mapping of the instruction to be executed; determining, based on the first field, whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the instruction to be executed, wherein the variable-length vector register is used for vector operations and the variable-length mask register is used for mask control; and an execution unit configured to, if it is determined that the second field and the third field are extracted from the instruction to be executed, execute the instruction to be executed based on the first field, the second field, the third field, and an opcode and an addressing mode field included in the instruction to be executed; and if it is determined that the second field and the third field are not extracted from the instruction to be executed, execute the instruction to be executed based on the first field, the opcode, and the addressing mode field.

[0018] In one possible implementation, the first field includes a first bit field for marking the opcode mapping of the instruction to be executed, and the decoding unit is configured to: determine whether the first bit field is a first value; if the first bit field is the first value, then determine not to extract the second field and the third field from the instruction to be executed; if the first bit field is a value other than the first value, then determine to extract the second field and the third field from the instruction to be executed.

[0019] In one possible implementation, the execution unit is configured to: determine information related to the variable-length vector register and the variable-length mask register based on the first field, the second field, and the third field; determine the function of the instruction to be executed based on the opcode; determine the source register and destination register of the instruction to be executed based on the addressing mode field; and perform operations on the instruction to be executed corresponding to the function of the instruction to be executed based on the information, the source register, and the destination register.

[0020] In one possible implementation, the first field further includes a second bit field for accessing extended register resources. The second field includes a third bit field for identifying the addressing range and a fourth bit field for identifying the processing to be performed on an inactive variable-length mask register. The third field includes a fifth bit field for identifying the index of the variable-length mask register. The execution unit is configured to: determine an addressable variable-length vector register based on the second bit field and the third bit field; determine a masking operation to be performed on an inactive variable-length mask register based on the fourth bit field; and determine an active variable-length mask register based on the fifth bit field.

[0021] In one possible implementation, the execution unit is configured to: obtain a source operand from the source register; load multiple data elements in parallel from the addressed variable-length vector register; perform operations corresponding to the function of the instruction to be executed on the source operand and the data elements among the loaded multiple data elements that correspond to the activated variable-length mask register; and perform the masking operation on the inactive variable-length mask register.

[0022] In one possible implementation, the execution unit is configured to: if the opcode is a predetermined operation value, determine that the function of the instruction to be executed is a predetermined function, and perform a predetermined operation corresponding to the predetermined function on the instruction to be executed, wherein the predetermined operation includes addition, subtraction, multiplication, division, shift operation, logical AND, logical NAND, logical OR, logical XNOR, logical XOR, bitwise NOT, bitwise OR operation, bitwise OR operation on two source operands and setting a flag bit according to the result, left shift operation, right shift operation, bitwise test mask and flag bit setting operation, or unpacking operation.

[0023] In one possible implementation, when the predetermined operation is the move operation, the execution unit is configured to: if the opcode is a first operation value, move the source operand of the instruction to be executed from memory to the activated variable-length mask register; if the opcode is a second operation value, move the source operand of the instruction to be executed from the activated variable-length mask register to memory; if the opcode is a third operation value, move the source operand of the instruction to be executed from a general-purpose vector register to the activated variable-length mask register; and if the opcode is a fourth operation value, move the source operand of the instruction to be executed from the activated variable-length mask register to a general-purpose vector register.

[0024] In one possible implementation, the execution unit is configured to: determine the bit width of the shift operation of the variable-length mask register based on the flag bit of the first bit field and whether the instruction to be executed includes a prefix of the third field having a preset value.

[0025] In one possible implementation, the execution unit is configured to: determine the bit width of the move operation as 1 byte if the flag bit is 0 and includes a prefix with a preset value; determine the bit width of the move operation as 2 bytes if the flag bit is 0 and does not include a prefix with a preset value; determine the bit width of the move operation as 4 bytes if the flag bit is 1 and includes a prefix with a preset value; and determine the bit width of the move operation as 8 bytes if the flag bit is 1 and does not include a prefix with a preset value.

[0026] In one possible implementation, the first field further includes a second bit field for accessing extended register resources, and the execution unit is configured to: determine an addressable variable-length vector register based on the second bit field; determine the function of the instruction to be executed based on the opcode; determine the source register and destination register of the instruction to be executed based on the addressing mode field; and perform an operation on the instruction to be executed corresponding to the function of the instruction to be executed based on the addressed variable-length vector register, the source register, and the destination register.

[0027] In one possible implementation, the first field includes a first bit field for marking the opcode mapping of the instruction to be executed, and the decoding unit is configured to: determine that the instruction to be executed is a private variable-length vector instruction if the flag bit of the first bit field is a first flag value; and determine that the instruction to be executed is not the private variable-length vector instruction if the flag bit of the first bit field is a second flag value different from the first flag value.

[0028] In one possible implementation, the instruction execution device further includes an update unit for updating the loading and operation instructions and mask operations of the variable-length mask register.

[0029] In one possible implementation, the execution unit is configured to report an exception to a system register if an exception occurs during the execution of the instruction to be executed.

[0030] According to a third aspect of this disclosure, a processor is provided, comprising: 32 variable-length vector registers; 8 variable-length mask registers; 6 variable-length control registers; and the aforementioned instruction execution means.

[0031] The instruction execution method, apparatus, and processor disclosed herein improve the instruction set architecture and provide a variable-length vector architecture. Using this architecture, x86 vector instructions can be extended in a new variable-length vector form through the vec_len control register, ele_len control register, and vrnd control register, thereby improving software portability. Based on this, a new extended instruction format is defined, and the design of an independent instruction space encoding is completed, thus enabling simpler instruction extension. Furthermore, matrix tensor operation extensions can be implemented through the vgpr_len and vmtx_len control registers.

[0032] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0033] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0034] Figure 1 A flowchart of an instruction execution method 100 according to an embodiment of the present disclosure is shown.

[0035] Figure 2 A schematic diagram of a variable-length vector architecture 200 according to an embodiment of the present disclosure is shown.

[0036] Figure 3 A schematic diagram of the format of a variable-length vector according to an embodiment of the present disclosure is shown.

[0037] Figure 4 A schematic diagram illustrating a format extension of a general instruction according to an embodiment of the present disclosure is shown.

[0038] Figure 5 A schematic diagram illustrating the format of a vector instruction extension according to an embodiment of the present disclosure is shown.

[0039] Figure 6 A schematic diagram of an ISA extension method according to an embodiment of the present disclosure is shown.

[0040] Figure 7 A schematic diagram of a microarchitecture SIMD according to an embodiment of the present disclosure is shown.

[0041] Figure 8 A schematic diagram of a microarchitecture decoder according to an embodiment of the present disclosure is shown.

[0042] Figure 9 An example of variable-length mask register loading and operation instructions according to an embodiment of the present disclosure is shown.

[0043] Figure 10 The MOV instruction for a variable-length mask register according to an embodiment of the present disclosure is shown.

[0044] Figure 11 A block diagram of an instruction execution apparatus according to an embodiment of the present disclosure is shown.

[0045] Figure 12 A block diagram of a processor according to an embodiment of the present disclosure is shown. Detailed Implementation

[0046] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0047] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0048] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0049] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0050] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0051] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0052] A preferred embodiment

[0053] Figure 1 A flowchart of an instruction execution method 100 according to an embodiment of the present disclosure is shown. In some embodiments, the instruction execution method 100 can be applied to a processor, such as... Figure 12 The processor is 1200. For example... Figure 12 As shown, the processor 1200 may include a register 1210, a decoding unit 1220, and an execution unit 1230.

[0054] Register 1210 can be Figure 2The variable-length vector architecture shown, i.e., register 1210 may include control register 210, variable-length mask register 220, and variable-length vector register 230. Control register 210 may include the following six control registers: vimp_len control register 211, vec_len control register 212, ele_len control register 213, vgpr_len control register 214, vmtx_len control register 215, and vrnd control register 216.

[0055] The `vimp_len` control register 211 indicates the maximum length supported by the vector machine, which can be set to 128 bits, 256 bits, or 512 bits. The `vec_len` control register 212 indicates the length of the vector machine that can be processed in a single operation, which can be set to 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits, 512 bits, 1024 bits, 2048 bits, 4096 bits, 8192 bits, 16348 bits, or 32768 bits. The `ele_len` control register 213 indicates the length of each element in a vector, such as 4 bits, 8 bits, 16 bits, 32 bits, or 64 bits. The length and size of a Length Variable Vector (LVV) can be controlled through the `vimp_len`, `vec_len`, and `ele_len` control registers 211, 212, and 213.

[0056] The `vgpr_len` control register 214 indicates the number of operations in the vector machine. For example, if the number is 2, the operation is performed twice. The first operation is sent to group 0, and the second operation is sent to group 1. The operation is then performed by the two groups. The `vmtx_len` control register 215 indicates the length and width of the matrix. For example, if the length is 2... 4.2 8. If matrix operations are to be performed, the length and width of the matrix must be specified. Matrix tensor operations can be performed using the vgpr_len control register 214 and the vmtx_len control register 215.

[0057] The vrnd control register (Rounding mode) 216 is used to indicate the rounding mode. The rounding mode can be controlled through the vrnd control register 216.

[0058] like Figure 2As shown, the variable-length mask register 220 can include eight variable-length mask registers, from Ln0 register 221 to Ln7 register 228. For a given instruction, one of these eight registers is selected, for example, Ln0 register 221. The length of the variable-length mask register 220 is equal to the value set in vec_len control register 212 / the value set in ele_len control register 213. For example, if vec_len control register 212 is set to 128 bits and ele_len control register 213 is set to 16 bits, then the length of the variable-length mask register 220 is 128 / 16 = 8. Bit 0 controls element 0, bit 1 controls element 1, bit 2 controls element 2, ..., bit 7 controls element 8. When a corresponding bit is 1, the value of the element corresponding to that bit is sent out for computation. If it's addition, the value of the element corresponding to that bit is added; if it's subtraction, the value of the element corresponding to that bit is subtracted. When a corresponding bit is 0, the value of the element corresponding to that bit is not used in the computation.

[0059] Define a new set of register types: for example, 0101 represents that the variable-length mask register 220 needs to be accessed. There are 8 variable-length mask registers 220, each 64 bits. The specific encoding will be determined later and synchronized with the RAT.

[0060] like Figure 2 As shown, the variable-length vector register 230 can include 32 variable-length vector registers, from V0 register 231 to ... V31 register 262. The length of the variable-length vector register 230 is equal to the value set in the vimp_len control register 211. A new set of register type definitions is given: for example, 1010 represents that the variable-length vector register 230 needs to be accessed. There are 32 variable-length vector registers 230, each 128 bits, which can be set via the vimp_len control register 211.

[0061] In a preferred embodiment, such as Figure 1 As shown, the instruction execution method 100 may include the following steps:

[0062] In step S110, it is determined whether the instruction to be executed includes the extended instruction prefix D6.

[0063] In some embodiments, the instruction to be executed can be a vector extension instruction or a regular extension instruction, such as... Figure 3As shown, the extended instruction 300 can include a vector extended instruction 310 and a normal extended instruction 320. The vector extended instruction 310 includes a prefix, an extended instruction prefix D6, a P0 field, a P1 field, a P2 field, an opcode, a Mod M / R field, an immediate value, and a shift. The normal extended instruction 320 includes a prefix, an extended instruction prefix D6, a P0 field, an opcode, a Mod M / R field, an immediate value, and a shift. Therefore, the extended instruction 300 has a D6 prefix, and the only difference between the two extended instructions is whether or not the P1 and P2 fields are included.

[0064] Considering that instruction execution method 100 targets extended instructions, while non-extended instructions should be executed according to existing instruction execution methods, the decoding unit 1220 can identify the instruction to be executed to determine whether it has a D6 prefix, thereby determining whether the instruction to be executed is an extended instruction. If it is determined that the instruction to be executed has a D6 prefix, then the instruction to be executed is an extended instruction and needs to be executed according to instruction execution method 100, and the process proceeds to step S130 below. If it is determined that the instruction to be executed does not have a D6 prefix, then the instruction to be executed is not an extended instruction, and it is not necessary to execute the instruction to be executed according to instruction execution method 100. The instruction to be executed can be executed according to existing instruction execution methods. For example, for this instruction to be executed, instruction execution method 100 can be terminated.

[0065] In step S130, a first field (P0 field) for marking the opcode mapping of the instruction to be executed is extracted from the instruction to be executed.

[0066] In some embodiments, the decoding unit 1220 can decode the instruction to be executed in order to extract the P0 field from the instruction to be executed.

[0067] like Figure 3 As shown, the P0 field may include an opmap bit field for marking opcode mapping, a W bit field for defining the granularity (size) of data types, and an RXB bit field. The opmap bit field has a width of 4 bits, the W bit field has a width of 1 bit, and the RXB (Register eXtension Bits) bit field has a width of 3 bits. It is used to access extended register resources. The R bit is used to extend the destination register index, and the X / B bits are used to extend the base / index register index. By combining the RXB bits, 4-bit addressing of a total of 16 general-purpose registers (GPRs) can be achieved. Therefore, the P0 field has a total of 8 bits, of which P0[7:4] is the opmap bit field, P0[3] is the W bit field, and P0[2:0] is the RXB bit field.

[0068] If P0[7:4] is 0000, it represents a 1-byte opcode with only the P0 field and no P1 or P2 fields; if P0[7:4] is 0001, the instruction is 0x0F, which is not a proprietary variable-length vector instruction, such as being compatible with Intel instructions; if P0[7:4] is 0010, the instruction is 0x0F 38, which is not a proprietary variable-length vector instruction, such as being compatible with Intel instructions; if P0[7:4] is 0011, the instruction is 0x0F 3A, which is not a proprietary variable-length vector instruction, such as being compatible with Intel instructions; if P0[7:4] is 1000, it represents a 1-byte opcode with complete P0, P1, and P2 fields, and the instruction is an extended instruction and a vector extended instruction; if P0[7:4] is 1001, the instruction is 0x0F, and the instruction is an LVV instruction; if P0[7:4] is 1010, the instruction is 0x0F. 38, at this time the instruction is LVV instruction; if P0[7:4] is 1011, the instruction is 0x0F 3A, at this time the instruction is LVV instruction; if P0[7:4] is any other value, the instruction is a reserved value.

[0069] For example, such as Figure 6 As shown, the instruction extension method is determined by the value of P0[7]. If P0[7] is 1, the instruction is the instruction extension of this embodiment. The extended instruction can be determined by the value of P0[6:4]. For example, if P0[6:4] is 000, it represents 1 byte opcode; if P0[6:4] is 001, it represents 2 bytes 0fxx; if P0[6:4] is 010, it represents 3 bytes 0f38; if P0[6:4] is 011, it represents 3 bytes 0f3A. If P0[7] is 0, then the instruction is not a private variable-length vector instruction, such as a compatible Intel instruction, and the compatible instruction can be determined according to the value of P0[6:4]. For example, if P0[6:4] is 001, it means 2 bytes 0fxx; if P0[6:4] is 010, it means 3 bytes 0f38; if P0[6:4] is 011, it means 3 bytes 0f3A.

[0070] In step S150, it is determined whether to extract the second field (P1 field) related to the variable-length vector register and the third field (P2 field) related to the variable-length mask register from the instruction to be executed based on the first field (P0 field). The variable-length vector register is used for vector operations, and the variable-length mask register is used for mask control. The variable-length mask register contains flag bits with the same number of data stored in the variable-length vector register, which are used to indicate whether the corresponding data in the variable-length vector register participates in the calculation execution.

[0071] In some embodiments, such as Figure 4 As shown, P0[7:4] is 0000, and the extended instruction 400 only has the P0 field but not the P1 and P2 fields; for example Figure 5 As shown, P0[7:4] is 1000 or 1001, and the extended instruction 500 has P0, P1, and P2 fields. Therefore, the value of P0[7:4] can be used to determine whether to extract the P1 and P2 fields from the instruction to be executed.

[0072] In some embodiments, the decoding unit 1220 can determine whether the first field P0[7:4] is a first value based on whether one or more bits of the first field (P0[7:4]) included in the first field (P0 field) are 1; if it is determined that one or more bits of the first field are not 1, then the first field is determined to be a first value; if it is determined that one or more bits of the first field are all 1, then the first field is determined to be a value other than the first value.

[0073] For example, the decoding unit 1220 can determine whether P0[7:4] is the first value based on whether P0[4] is 1. If P0[4] is 1, it is determined that P0[7:4] is a value other than the first value; if P0[4] is 0, it is determined that P0[7:4] is the first value.

[0074] For example, the decoding unit 1220 can determine whether P0[7:4] is the first value based on whether P0[7] and P0[4] are both 1. If P0[7] and P0[4] are both 1, then P0[7:4] is determined to be a value other than the first value; if P0[7] and P0[4] are both 0, then P0[7:4] is determined to be the first value.

[0075] In one possible implementation, the decoding unit 1220 can determine whether P0[7:4] is a first value (e.g., 0000); if it is determined that P0[7:4] is a first value, then it is determined that the P1 field and P2 field will not be extracted from the instruction to be executed, and step S150 is determined to be "no", and the following step S190 is executed; if it is determined that P0[7:4] is a value other than the first value (e.g., 1000 or 1001), then it is determined that the P1 field and P2 field will be extracted from the instruction to be executed, and step S150 is determined to be "yes", and the following step S170 is executed.

[0076] In step S170, the instruction to be executed is executed according to the first field (P0 field), the second field (P1 field), the third field (P2 field), and the opcode and addressing mode field (ModR / M field) included in the instruction to be executed.

[0077] In some embodiments, the decoding unit 1220 can determine information related to the variable-length vector register 230 and the variable-length mask register 220 based on the P0, P1, and P2 fields; determine the function of the instruction to be executed based on the opcode; determine the operation to be performed on the instruction to be executed based on the ModR / M field; and perform the operation corresponding to the function of the instruction to be executed based on this information, the source register, and the destination register. The method by which the decoding unit 1220 determines the function of the instruction to be executed based on the opcode and determines the source register and destination register based on the ModR / M field will not be described in detail here.

[0078] like Figure 3 As shown, the P1 field includes the VVVV bit field, the R'X' bit field, and the M / Z bit field. The VVVV bit field has a width of 5 bits and is used to define the third operand. With the help of the VVVV bit field, the existing two operands, such as the first operand and the second operand, can be extended to three operands, such as the first operand, the second operand, and the third operand. The R'X' bit field has a width of 2 bits. By combining the R'X' bits, 5-bit addressing of a total of 32 general-purpose registers (GPRs) can be achieved. The M / Z bit field has a width of 1 bit and is used to define the masking operation of the inactive variable-length mask registers in the variable-length mask register 220. If the M / Z bit field is set to 1, the value of the inactive variable-length mask register corresponding to the original destination register is maintained. If the M / Z bit field is set to 0, the value of the inactive variable-length mask register corresponding to the original destination register is cleared. Therefore, the P1 field has a total of 8 bits, of which P1[7:3] is the VVVV bit field, P1[2:1] is the R'X' bit field, and P1[0] is the M / Z bit field.

[0079] like Figure 3 As shown, the P2 field includes the Ln bit field, the pref bit field, the app bit field, and the RSV bit field. The Ln bit field has a width of 3 bits and is used to define which variable-length mask register in the variable-length mask register 220 is used. The pref bit field has a width of 2 bits and represents the compressed bit field. The app bit field has a width of 1 bit and represents the divisor processing bit field. The RSV bit field has a width of 2 bits and represents the reserved bit field. Therefore, the P2 field has a total of 8 bits, of which P2[7:5] is the Ln bit field, P2[4:3] is the pref bit field, P2[2] is the app bit field, and P2[1:0] is the RSV bit field. If P2[4:3] is set to 00, no compression is performed. If P2[4:3] is set to 01, the compressed bit field takes the value 66. If P2[4:3] is set to 10, the compressed bit field takes the value F3. If P2[4:3] is set to 11, the compressed bit field takes the value F2.

[0080] The decoding unit 1220 can determine the addressable variable-length vector registers based on the RXB bit field and the R'X' bit field; determine which variable-length mask register in the variable-length mask register 220 will be activated based on the Ln bit field; and determine the masking operation to be performed on the inactive variable-length mask register in the variable-length mask register 220 based on the M / Z bit field. Thus, it can determine the register extension of the vector instruction (i.e., the addressable variable-length vector register), mask control (clearing or keeping the original value), and the variable-length mask register to be used, thereby determining the information related to the variable-length vector register 230 and the variable-length mask register 220.

[0081] The decoding unit 1220 can send this information to the execution unit 1230. Accordingly, the execution unit 1230 can use this information, the source operand obtained from the source register, and the destination register to perform operations corresponding to the function of the instruction to be executed.

[0082] In one possible implementation, the execution unit 1230 can obtain the source operand from the source register; load multiple data elements in parallel according to the addressed variable-length vector register; perform operations corresponding to the function of the instruction to be executed on the source operand and the data elements that need to participate in the operation from the multiple loaded data elements and the data elements corresponding to the activated variable-length mask register; and perform masking operations on the inactive variable-length mask register.

[0083] In step S190, the instruction to be executed is performed based on the first field (P0 field), the opcode, and the addressing mode field (ModR / M field).

[0084] In some embodiments, the execution unit 1230 may determine the addressable variable-length vector register based on the RXB bit field; determine the function of the instruction to be executed based on the opcode to determine the operation to be performed on the instruction to be executed; determine the source register and destination register of the instruction to be executed based on the ModR / M field; and perform the operation corresponding to the function of the instruction to be executed based on the addressable variable-length vector register, source register, and destination register.

[0085] In one possible implementation, the execution unit 1230 can obtain the source operand from the source register; load multiple data elements in parallel from the addressed variable-length vector register; and perform operations on the source operand and the loaded multiple data elements corresponding to the function of the instruction to be executed.

[0086] In some embodiments, such as Figure 7 As shown, the execution unit 1230 can perform coordinated operations on the variable-length vector register 230 and the variable-length mask register 220 to achieve efficient parallel computing. During the vector operation phase, the variable-length vector register 230 supports multiple data types by configuring its bit width. For example, a single 2048-bit register can store 32 64-bit double-precision floating-point numbers or 256 8-bit integers. The execution unit 1230 reads multiple data elements from the variable-length vector register 230 in parallel and performs SIMD operations according to the opcode type (such as ADD / MUL). The register file adopts a multi-bank design, providing sufficient bandwidth to meet the parallel data requirements through cross-access. During the mask control phase, each bit of the variable-length mask register 220 corresponds to a data element of the variable-length vector register 230. 1 indicates that the operation at that position is activated, and 0 indicates that it is suppressed. The mask operation supports conditional execution, such as performing arithmetic operations only on elements that meet the comparison conditions. The dynamic mask length is automatically synchronized with the bit width of the variable-length vector register 230 to ensure operation alignment.

[0087] In some embodiments, such as Figure 8 As shown, matrix tensor operations can be extended through the vgpr_len control register 214 and the vmtx_len control register 215. When a vector group is used, if the original encoding register is not divisible by the number of the corresponding group, a report needs to be submitted for general exception handling.

[0088] According to this embodiment, the instruction system architecture is improved, and provides... Figure 2 The variable-length vector architecture shown, with the help of this architecture, such as Figure 7As shown, through the vec_len control register 212, ele_len control register 213, and vrnd control register 216, x86 vector instructions can be extended in a new variable-length vector form, thereby improving software portability (Write Once, Run Anywhere). Based on this, the following is defined: Figure 3 The new extended instruction format 300 shown completes the design of an independent instruction space encoding, thereby enabling simpler instruction extension. Additionally, as... Figure 8 As shown, matrix tensor operations can be extended through the vgpr_len control register 214 and the vmtx_len control register 215.

[0089] In one possible implementation, performing an operation corresponding to the function of the instruction to be executed includes: if the opcode is a predetermined operation value, then determining that the function of the instruction to be executed is a predetermined function, and performing a predetermined operation corresponding to the predetermined function on the instruction to be executed. The predetermined operation includes addition (LNADD), subtraction (LNSUB), multiplication (LNMUL), division (LNDIV), shift operation (LNMOV), logical AND operation (LNAND), logical NAND NOT operation (LNANDN), logical OR operation (LNOR), logical XNOR operation (LNXNOR), logical XOR operation (LNXOR), bitwise NOT operation (LNNOT), bitwise OR operation on two source operands and setting a flag based on the result (LNORTEST), left shift operation (LNSHIFTL), right shift operation (LNSHIFTR), packing bit test mask and flag setting operation (LNTEST), or unpacking operation (LNUNPCK).

[0090] In some embodiments, the instructions to be executed may include, but are not limited to, those mentioned above. Figure 9 The instructions shown include one or more of the following arithmetic instructions: LNADD, LNSUB, LNMUL, LNDIV, LNMOV, LNAND, LNANDN, LNOR, LNXNOR, LNXOR, LNNOT, LNORTEST, LNSHIFTL, LNSHIFTR, LNTEST, and LNUNPCK. Each arithmetic instruction has a corresponding opcode, which uniquely identifies the type of arithmetic instruction. Therefore, the opcode value can be used to determine which of the above arithmetic instructions the instruction to be executed is, and the corresponding operation can be performed on the instruction to be executed.

[0091] For example, if the opcode is the op value corresponding to the LNADD instruction, then the instruction to be executed is determined to be an LNADD instruction, and an ADD operation (addition operation, such as adding two source operands, ADDTwo Masks) can be performed on the instruction to be executed. The LNADD instructions include LNADDW, LNADDB, LNADDQ, and LNADDD instructions. These instructions respectively represent adding two 16-bit, 8-bit, 64-bit, and 32-bit source operands. It can be seen that W / B / D / Q represent operands of different bit widths: W represents 2 bytes (16 bits), B represents 1 byte (8 bits), D represents 8 bytes (64 bits), and Q represents 4 bytes (32 bits).

[0092] If the opcode is the op value corresponding to the LNSUB instruction, then the instruction to be executed is determined to be an LNSUB instruction, which can be used to perform SUB operations (subtraction operations, such as subtracting two source operands, SUB TwoMasks). The LNSUB instructions include LNSUBW, LNSUBB, LNSUBQ, and LNSUBD instructions, which respectively represent subtracting two 16-bit, 8-bit, 64-bit, and 32-bit source operands.

[0093] If the opcode is the op value corresponding to the LNMUL instruction, then the instruction to be executed is determined to be an LNMUL instruction, and a MUL operation (multiplication operation, such as multiplying two source operands, MUL TwoMasks) can be performed on the instruction to be executed. The LNMUL instructions include LNMULW, LNMULB, LNMULQ, and LNMULD, which respectively represent multiplying two 16-bit, 8-bit, 64-bit, and 32-bit source operands.

[0094] If the opcode is the op value corresponding to the LNDIV instruction, then the instruction to be executed is determined to be an LNDIV instruction, and a DIV operation (division operation, such as dividing two source operands, DIV TwoMasks) can be performed on the instruction to be executed. The LNDIV instructions include LNDIVW, LNDIVB, LNDIVQ, and LNDIVD instructions, which respectively represent dividing two 16-bit, 8-bit, 64-bit, and 32-bit source operands.

[0095] If the opcode is the op value corresponding to the LNMOV instruction, then the instruction to be executed is determined to be an LNMOV instruction, and MOV operations (shift operations, such as shifting the source operand, Move From and to Mask Registers) can be performed on the instruction to be executed. The LNMOV instructions include LNMOVW, LNMOVB, LNMOVQ, and LNMOVD instructions, which respectively represent shifting 16-bit, 8-bit, 64-bit, and 32-bit source operands.

[0096] If the opcode is the op value corresponding to the LNAND instruction, then the instruction to be executed is determined to be an LNAND instruction, and an AND operation (logical AND operation, such as performing a logical AND operation on two source operands, Bitwise Logical AND Masks) can be performed on the instruction to be executed. The LNAND instructions include LNANDW, LNANDB, LNANDQ, and LNANDD instructions, which respectively represent performing a logical AND operation on 16-bit source operands, 8-bit source operands, 64-bit source operands, and 32-bit source operands.

[0097] If the opcode is the op value corresponding to the LNANDN instruction, then the instruction to be executed is determined to be an LNANDN instruction, and ANDN operations (logical AND NOT operations, such as performing logical AND NOT operations on two source operands, Bitwise Logical AND NOT Masks) can be performed on the instruction to be executed. The LNANDN instructions include LNANDNW, LNANDNB, LNANDNQ, and LNANDND instructions, which respectively represent logical AND NOT operations on 16-bit, 8-bit, 64-bit, and 32-bit source operands.

[0098] If the opcode is the operand value corresponding to the LNOR instruction, then the instruction to be executed is determined to be an LNOR instruction, which can perform an OR operation (logical OR operation, such as performing a logical OR operation on two source operands, Bitwise Logical OR Masks) on the instruction to be executed. The LNOR instructions include LNORW, LNORB, LNORQ, and LNORD, which respectively represent performing a logical OR operation on 16-bit source operands, 8-bit source operands, 64-bit source operands, and 32-bit source operands.

[0099] If the opcode is the op value corresponding to the LNXNOR instruction, then the instruction to be executed is determined to be an LNXNOR instruction, and an XNOR operation (logical XNOR operation, such as performing a logical XNOR operation on two source operands, Bitwise Logical XNOR Masks) can be performed on the instruction to be executed. The LNXNOR instructions include LNXNORW, LNXNORB, LNXNORQ, and LNXNORD instructions, which respectively represent performing a logical XNOR operation on 16-bit source operands, 8-bit source operands, 64-bit source operands, and 32-bit source operands.

[0100] If the opcode is the op value corresponding to the LNXOR instruction, then the instruction to be executed is determined to be an LNXOR instruction, which can perform an XOR operation (logical XOR operation, such as performing a logical XOR operation on two source operands, Bitwise Logical XOR Masks) on the instruction to be executed. The LNXOR instructions include LNXORW, LNXORB, LNXORQ, and LNXORD instructions, which respectively represent performing a logical XOR operation on 16-bit source operands, 8-bit source operands, 64-bit source operands, and 32-bit source operands.

[0101] If the opcode is the op value corresponding to the LNNOT instruction, then the instruction to be executed is determined to be an LNNOT instruction, and a NOT operation (bitwise inversion, such as bitwise inversion of the source operand, NOTMask Register) can be performed on the instruction to be executed. The LNNOT instructions include LNNOTW, LNNOTB, LNNOTQ, and LNNOTD, which respectively represent bitwise inversion of a 16-bit source operand, a 8-bit source operand, a 64-bit source operand, and a 32-bit source operand.

[0102] If the opcode is the op value corresponding to the LNORTEST instruction, then the instruction to be executed is determined to be the LNORTEST instruction. The ORTEST operation (OR Masks and Set Flags) can then be performed on the instruction to be executed. The LNORTEST instructions include LNORTESTW, LNORTESTB, LNORTESTQ, and LNORTESTD. These instructions respectively represent performing a bitwise OR operation on two 16-bit source operands and setting flags based on the result; performing a bitwise OR operation on two 8-bit source operands and setting flags based on the result; performing a bitwise OR operation on two 64-bit source operands and setting flags based on the result; and performing a bitwise OR operation on two 32-bit source operands and setting flags based on the result.

[0103] If the opcode is the op value corresponding to the LNSHIFTL instruction, then the instruction to be executed is determined to be an LNSHIFTL instruction, and a SHIFTL operation (Shift Left Mask Registers) can be performed on the instruction to be executed. The LNSHIFTL instructions include LNSHIFTLW, LNSHIFTLB, LNSHIFTLQ, and LNSHIFTLD instructions, which respectively represent left shift operations on 16-bit, 8-bit, 64-bit, and 32-bit source operands.

[0104] If the opcode is the op value corresponding to the LNSHIFTR instruction, then the instruction to be executed is determined to be an LNSHIFTR instruction, and a SHIFTR operation (Shift Right Mask Registers) can be performed on the instruction to be executed. The LNSHIFTR instructions include LNSHIFTRW, LNSHIFTRB, LNSHIFTRQ, and LNSHIFTRD instructions, which respectively represent right shift operations on 16-bit, 8-bit, 64-bit, and 32-bit source operands.

[0105] If the opcode is the op value corresponding to the LNTEST instruction, then the instruction to be executed is determined to be the LNTEST instruction, and a TEST operation (Packed BitTest Masks and Set Flags) can be performed on the instruction to be executed. The LNTEST instructions include LNTESTW, LNTESTB, LNTESTQ, and LNTESTD instructions. These instructions respectively represent performing a packed bit test operation on a 16-bit source operand and setting flags based on the result; performing a packed bit test operation on an 8-bit source operand and setting flags based on the result; performing a packed bit test operation on a 64-bit source operand and setting flags based on the result; and performing a packed bit test operation on a 32-bit source operand and setting flags based on the result.

[0106] If the opcode is the op value corresponding to an LNUNPCK instruction, then the instruction to be executed is determined to be an LNUNPCK instruction, and UNPCK (Unpack for Mask Registers) operations can be performed on the instruction to be executed. The LNUNPCK instructions include LNUNPCKBW, LNUNPCKWD, and LNUNPCKDQ instructions, which respectively unpack an 8-bit source operand into a 16-bit destination operand, unpack a 16-bit source operand into a 32-bit destination operand, and unpack a 32-bit source operand into a 64-bit destination operand.

[0107] In one possible implementation, when the predetermined operation is the move operation (MOV instruction), the instruction to be executed is subjected to an operation corresponding to the function of the instruction to be executed, including: if the opcode is a first op value (0x90), the instruction to be executed is subjected to a move operation from memory to the active variable-length mask register; if the opcode is a second op value (0x91), the instruction to be executed is subjected to a move operation from the active variable-length mask register to memory; if the opcode is a third op value (0x92), the instruction to be executed is subjected to a move operation from a general-purpose vector register to the active variable-length mask register; if the opcode is a fourth op value (0x93), the instruction to be executed is subjected to a move operation from the active variable-length mask register to the general-purpose vector register.

[0108] In some embodiments, such as Figure 10As shown, if the executable instruction is 0xd6 p0 p1 p2 0x90, the corresponding arithmetic instruction is Mov mem / LNreg to LNreg, where Modrm:r / m specifies the source register and Modrm:reg specifies the destination register. If the executable instruction is 0xd6 p0 p1 p2 0x91, the corresponding arithmetic instruction is Mov LNreg to mem, where Modrm:r / m specifies the source register and Modrm:reg specifies the destination register. If the executable instruction is 0xd6 p0 p1 p2 0x92, the corresponding arithmetic instruction is MovGreg to LNreg, where Modrm:r / m specifies the source register and Modrm:reg specifies the destination register. If the executable instruction is 0xd6 p0 p1 p2 0x93, then the corresponding arithmetic instruction is Mov LNreg to Greg, where Modrm:r / m specifies the source register and Modrm:reg specifies the destination register.

[0109] In one possible implementation, the instruction execution method 100 may further include: determining the bit width of the shift operation of the variable-length mask register based on the flag bit (bit 3) of the first bit field and whether the instruction to be executed includes a prefix of the third field with a preset value.

[0110] In x86 architecture assembly language, MOV class instructions are used for data transfer operations. Based on the different operand bit widths, they are divided into the following types: MOVB (byte transfer), which operates on 8-bit data (1 byte); MOVW (word transfer), which operates on 16-bit data (2 bytes); MOVD (double word transfer), which operates on 32-bit data (4 bytes); and MOVQ (quad word transfer), which operates on 64-bit data (8 bytes).

[0111] In some embodiments, for LNmov type instructions, the operand width can be determined as 1 byte, 2 bytes, 4 bytes, or 8 bytes based on whether P0[7] and P2[4:3] are set to 01.

[0112] In one possible implementation, if P0[7] is 0 and the compressed bit field is 66, the bit width of the move operation is 1 byte, and the instruction is LNmovB; if P0[7] is 0 and the compressed bit field is not 66, the bit width of the move operation is 2 bytes, and the instruction is LNmovW; if P0[7] is 1 and the compressed bit field is 66, the bit width of the move operation is 4 bytes, and the instruction is LNmovD; if P0[7] is 1 and the compressed bit field is not 66, the bit width of the move operation is 8 bytes, and the instruction is LNmovQ.

[0113] In one possible implementation, the instruction execution method 100 may further include: loading and operation instructions for updating the variable-length mask register, as well as mask operations.

[0114] In some embodiments, the loading and operation instructions of the variable-length mask register 220, as well as the updates of the mask operations, may include, but are not limited to, the following: Figure 9 The example shown.

[0115] In one possible implementation, the instruction execution method 100 may further include: if an exception occurs during the execution of the instruction to be executed, reporting the exception to a system register.

[0116] In some embodiments, if an exception, such as a precision error, occurs during the execution of an instruction by the execution unit 1230, the execution unit 1230 can generate an Ldlvcsr instruction. The Ldlvcsr instruction has a 32-bit width, where [6:0] indicates the cause of the exception, [12:7] indicates whether to perform a masking operation on the exception, [14:13] indicates rounding control, and [31:15] indicates preserving RSV. Thus, the Ldlvcsr instruction is used to report the exception to the system register, and the cause of the exception can be determined based on [6:0] of the instruction. Therefore, the exception can be handled in a corresponding manner; the specific handling method will not be elaborated further.

[0117] A preferred embodiment

[0118] Figure 11 A block diagram of an instruction execution apparatus 1100 according to an embodiment of the present disclosure is shown. Figure 11 As shown, the instruction execution device 1100 may include a decoding unit 1110 and an execution unit 1120.

[0119] The decoding unit 1110 is used to identify whether the instruction to be executed includes an extended instruction prefix; if the instruction to be executed includes an extended instruction prefix, a first field for marking the opcode mapping of the instruction to be executed is extracted from the instruction to be executed; based on the first field, it is determined whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the instruction to be executed, wherein the variable-length vector register is used for vector operations, the variable-length mask register is used for mask control, and the variable-length mask register contains a number of flag bits equal to the number of data stored in the variable-length vector register, for marking whether the corresponding data in the variable-length vector register participates in the calculation execution.

[0120] The execution unit 1120 is configured to execute the instruction to be executed based on the first field, the second field, the third field, and the opcode and addressing mode field included in the instruction to be executed if the second field and the third field are extracted from the instruction to be executed; and to execute the instruction to be executed based on the first field, the opcode, and the addressing mode field if the second field and the third field are not extracted from the instruction to be executed.

[0121] In one possible implementation, the first field includes a first bit field for marking the opcode mapping of the instruction to be executed, and the decoding unit 1110 is configured to: determine whether the first bit field is a first value; if the first bit field is the first value, then determine not to extract the second field and the third field from the instruction to be executed; if the first bit field is a value other than the first value, then determine to extract the second field and the third field from the instruction to be executed.

[0122] In one possible implementation, the execution unit 1120 is configured to: determine information related to the variable-length vector register and the variable-length mask register based on the first field, the second field, and the third field; determine the function of the instruction to be executed based on the opcode; determine the source register and destination register of the instruction to be executed based on the addressing mode field; and perform operations on the instruction to be executed corresponding to the function of the instruction to be executed based on the information, the source register, and the destination register.

[0123] In one possible implementation, the first field further includes a second bit field for accessing extended register resources. The second field includes a third bit field for accessing extended register resources and a fourth bit field for identifying the processing to be performed on an inactive variable-length mask register. The third field includes a fifth bit field for identifying the index of the variable-length mask register. The execution unit 1120 is configured to: determine an addressable variable-length vector register based on the second bit field and the third bit field; determine a masking operation to be performed on an inactive variable-length mask register based on the fourth bit field; and determine an active variable-length mask register based on the fifth bit field.

[0124] In one possible implementation, the execution unit 1120 is configured to: obtain a source operand from the source register; load multiple data elements in parallel from the addressed variable-length vector register; perform operations corresponding to the function of the instruction to be executed on the source operand and the data elements among the loaded multiple data elements that need to participate in the operation and correspond to the activated variable-length mask register; and perform the masking operation on the inactive variable-length mask register.

[0125] In one possible implementation, the execution unit 1120 is configured to: if the opcode is a predetermined operation value, determine that the function of the instruction to be executed is a predetermined function, and perform a predetermined operation corresponding to the predetermined function on the instruction to be executed, wherein the predetermined operation includes addition, subtraction, multiplication, division, shift operation, logical AND, logical NAND, logical OR, logical XNOR, logical XOR, bitwise NOT, bitwise OR operation, bitwise OR operation on two source operands and setting a flag bit according to the result, left shift operation, right shift operation, bitwise AND test mask and flag bit setting operation, or unpacking operation.

[0126] In one possible implementation, when the predetermined operation is the move operation, the execution unit 1120 is configured to: if the opcode is a first operation value, move the source operand of the instruction to be executed from memory to the active variable-length mask register; if the opcode is a second operation value, move the source operand of the instruction to be executed from the active variable-length mask register to memory; if the opcode is a third operation value, move the source operand of the instruction to be executed from a general-purpose vector register to the active variable-length mask register; and if the opcode is a fourth operation value, move the source operand of the instruction to be executed from the active variable-length mask register to a general-purpose vector register.

[0127] In one possible implementation, the execution unit 1120 is configured to: determine the bit width of the move operation of the variable-length mask register based on the flag bit of the first bit field and whether the instruction to be executed includes a prefix of the third field with a preset value.

[0128] In one possible implementation, the execution unit 1120 is configured to: determine the bit width of the move operation as 1 byte if the flag bit is 0 and includes a prefix with a preset value; determine the bit width of the move operation as 2 bytes if the flag bit is 0 and does not include a prefix with a preset value; determine the bit width of the move operation as 4 bytes if the flag bit is 1 and includes a prefix with a preset value; and determine the bit width of the move operation as 8 bytes if the flag bit is 1 and does not include a prefix with a preset value.

[0129] In one possible implementation, the first field further includes a second bit field for accessing extended register resources, and the execution unit 1120 is configured to: determine an addressable variable-length vector register based on the second bit field; determine the function of the instruction to be executed based on the opcode; determine the source register and destination register of the instruction to be executed based on the addressing mode field; and perform an operation on the instruction to be executed corresponding to the function of the instruction to be executed based on the addressed variable-length vector register, the source register, and the destination register.

[0130] In one possible implementation, the first field includes a first bit field for marking the opcode mapping of the instruction to be executed, and the decoding unit 1110 is configured to: if the flag bit of the first bit field is a first flag value, then determine that the instruction to be executed is a private variable-length vector instruction; if the flag bit of the first bit field is a second flag value different from the first flag value, then determine that the instruction to be executed is not the private variable-length vector instruction.

[0131] In one possible implementation, the instruction execution device 1100 further includes an update unit (not shown) for updating the loading and operation instructions and mask operations of the variable-length mask register.

[0132] In one possible implementation, the execution unit 1120 is configured to report an exception to a system register if an exception occurs during the execution of the instruction to be executed.

[0133] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0134] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for executing instructions, characterized in that, include: Identify whether the instruction to be executed includes an extended instruction prefix; If the instruction to be executed includes the extended instruction prefix, then extract the first field from the instruction to be executed to identify the opcode mapping of the instruction to be executed; Based on the first field, determine whether to extract the second field related to the variable-length vector register and the third field related to the variable-length mask register from the instruction to be executed, wherein the variable-length vector register is used for vector operations and the variable-length mask register is used for mask control; If it is determined that the second field and the third field are extracted from the instruction to be executed, then the instruction to be executed is executed according to the first field, the second field, the third field, and the opcode and addressing mode fields included in the instruction to be executed; If it is determined that the second field and the third field will not be extracted from the instruction to be executed, then the instruction to be executed will be executed based on the first field, the opcode, and the addressing mode field.

2. The instruction execution method according to claim 1, characterized in that, The first field includes a first bit field used to identify the opcode mapping of the instruction to be executed. Determining whether to extract the second and third fields from the instruction to be executed based on the first field includes: Determine whether the first bit field is the first value; If it is determined that the first bit field is the first value, then it is determined that the second field and the third field will not be extracted from the instruction to be executed; If it is determined that the first bit field is a value other than the first value, then it is determined that the second field and the third field are extracted from the instruction to be executed.

3. The instruction execution method according to claim 1, characterized in that, Executing the instruction to be executed based on the first field, the second field, the third field, and the opcode and addressing mode fields included in the instruction to be executed includes: Based on the first field, the second field, and the third field, determine information related to the variable-length vector register and the variable-length mask register; The function of the instruction to be executed is determined based on the opcode; The source register and destination register of the instruction to be executed are determined based on the addressing mode field; Based on the information, the source register, and the destination register, the instruction to be executed is subjected to an operation corresponding to the function of the instruction to be executed.

4. The instruction execution method according to claim 3, characterized in that, The first field also includes a second bit field for accessing extended register resources, the second field including a third bit field for accessing extended register resources and a fourth bit field for identifying the processing to be performed on an inactive variable-length mask register, the third field including a fifth bit field for identifying the index of the variable-length mask register. Based on the first field, the second field, and the third field, information related to the variable-length vector register and the variable-length mask register is determined, including: The addressable variable-length vector register is determined based on the second bit field and the third bit field; The masking operation to be performed by the inactive variable-length mask register is determined based on the fourth bit field. The activated variable-length mask register is determined based on the fifth bit field.

5. The instruction execution method according to claim 4, characterized in that, Based on the information, the source register, and the destination register, perform operations on the instruction to be executed corresponding to the function of the instruction to be executed, including: Obtain the source operand from the source register; Multiple data elements are loaded in parallel based on the addressable variable-length vector register; For the source operand and the data elements among the loaded data elements that need to participate in the operation and correspond to the activated variable-length mask register, perform the operation corresponding to the function of the instruction to be executed, and perform the mask operation on the inactive variable-length mask register.

6. The instruction execution method according to claim 3, characterized in that, Performing operations on the instruction to be executed corresponding to the function of the instruction to be executed, including: If the opcode is a predetermined operation value, then the function of the instruction to be executed is determined to be a predetermined function, and the predetermined operation corresponding to the predetermined function is performed on the instruction to be executed. The predetermined operations include addition, subtraction, multiplication, division, shift operation, logical AND, logical NAND, logical OR, logical XNOR, logical XOR, bitwise NOT, bitwise OR operation, bitwise OR operation on two source operands and setting a flag bit according to the result, left shift operation, right shift operation, operation of packing bit test mask and setting flag bit, or unpacking operation.

7. The instruction execution method according to claim 6, characterized in that, When the predetermined operation is the move operation, performing an operation on the instruction to be executed corresponding to the function of the instruction to be executed includes: If the opcode is the first op value, then the source operand of the instruction to be executed is moved from memory to the active variable-length mask register. If the opcode is the second op value, then the source operand of the instruction to be executed is moved from the activated variable-length mask register to memory; If the opcode is a third op value, then the source operand of the instruction to be executed is moved from the general vector register to the activated variable-length mask register. If the opcode is the fourth op value, then the source operand of the instruction to be executed is moved from the active variable-length mask register to the general vector register.

8. The instruction execution method according to claim 7, characterized in that, The first field includes a first bit field used to identify the opcode mapping of the instruction to be executed. The instruction execution method further includes: The bit width of the shift operation of the variable-length mask register is determined based on the flag bit of the first bit field and whether the instruction to be executed includes a prefix of the third field with a preset value.

9. The instruction execution method according to claim 8, characterized in that, The bit width of the shift operation of the variable-length mask register is determined based on the flag bit and whether the instruction to be executed includes a prefix with a preset value for the third field, including: If the flag bit is 0 and includes a prefix with a preset value, then the bit width of the move operation is 1 byte; If the flag bit is 0 and does not include a prefix with a preset value, then the bit width of the move operation is 2 bytes; If the flag bit is 1 and includes a prefix with a preset value, then the bit width of the move operation is 4 bytes; If the flag bit is 1 and does not include a prefix with a preset value, then the bit width of the move operation is 8 bytes.

10. The instruction execution method according to claim 1, characterized in that, The first field also includes a second bit field for accessing extended register resources. Executing the instruction to be executed based on the first field, the opcode, and the addressing mode field includes: The addressable variable-length vector register is determined based on the second bit field; The function of the instruction to be executed is determined based on the opcode; The source register and destination register of the instruction to be executed are determined based on the addressing mode field; Based on the addressed variable-length vector register, the source register, and the destination register, the instruction to be executed is subjected to an operation corresponding to the function of the instruction to be executed.

11. The instruction execution method according to claim 1, characterized in that, The first field includes a first bit field used to identify the opcode mapping of the instruction to be executed. The instruction execution method further includes: If the flag bit of the first bit field is the first flag value, then the instruction to be executed is determined to be a private variable-length vector instruction. If the flag bit of the first bit field is a second flag value that is different from the first flag value, then the instruction to be executed is determined to be not the private variable-length vector instruction.

12. The instruction execution method according to claim 1, characterized in that, Also includes: Update the loading and operation instructions of the variable-length mask register, as well as the mask operation.

13. The instruction execution method according to claim 1, characterized in that, Also includes: If an exception occurs during the execution of the instruction to be executed, the exception is reported to the system register.

14. An instruction execution device, characterized in that, include: The decoding unit is used to identify whether the instruction to be executed includes an extended instruction prefix; if the instruction to be executed includes the extended instruction prefix, then extracts a first field from the instruction to be executed to mark the opcode mapping of the instruction to be executed; and determines whether to extract a second field related to a variable-length vector register and a third field related to a variable-length mask register from the instruction to be executed based on the first field, wherein the variable-length vector register is used for vector operations and the variable-length mask register is used for mask control. An execution unit is configured to, if it is determined that the second field and the third field are extracted from the instruction to be executed, execute the instruction to be executed based on the first field, the second field, the third field, and the opcode and addressing mode field included in the instruction to be executed; and if it is determined that the second field and the third field are not extracted from the instruction to be executed, execute the instruction to be executed based on the first field, the opcode, and the addressing mode field.

15. The instruction execution apparatus according to claim 14, characterized in that, The first field includes a first bit field used to identify the opcode mapping of the instruction to be executed. The decoding unit is configured as follows: Determine whether the first bit field is the first value; If it is determined that the first bit field is the first value, then it is determined that the second field and the third field will not be extracted from the instruction to be executed; If it is determined that the first bit field is a value other than the first value, then it is determined that the second field and the third field are extracted from the instruction to be executed.

16. The instruction execution apparatus according to claim 14, characterized in that, The execution unit is configured as follows: Based on the first field, the second field, and the third field, determine information related to the variable-length vector register and the variable-length mask register; The function of the instruction to be executed is determined based on the opcode; The source register and destination register of the instruction to be executed are determined based on the addressing mode field; Based on the information, the source register, and the destination register, the instruction to be executed is subjected to an operation corresponding to the function of the instruction to be executed.

17. The instruction execution apparatus according to claim 16, characterized in that, The first field also includes a second bit field for accessing extended register resources, the second field including a third bit field for accessing extended register resources and a fourth bit field for identifying the processing to be performed on an inactive variable-length mask register, the third field including a fifth bit field for identifying the index of the variable-length mask register. The execution unit is configured as follows: The addressable variable-length vector register is determined based on the second bit field and the third bit field; The masking operation to be performed by the inactive variable-length mask register is determined based on the fourth bit field. The activated variable-length mask register is determined based on the fifth bit field.

18. The instruction execution apparatus according to claim 17, characterized in that, The execution unit is configured as follows: Obtain the source operand from the source register; Multiple data elements are loaded in parallel based on the addressable variable-length vector register; For the source operand and the data elements among the loaded data elements that need to participate in the operation and correspond to the activated variable-length mask register, perform the operation corresponding to the function of the instruction to be executed, and perform the mask operation on the inactive variable-length mask register.

19. The instruction execution apparatus according to claim 16, characterized in that, The execution unit is configured as follows: If the opcode is a predetermined operation value, then the function of the instruction to be executed is determined to be a predetermined function, and the predetermined operation corresponding to the predetermined function is performed on the instruction to be executed. The predetermined operations include addition, subtraction, multiplication, division, shift operation, logical AND, logical NAND, logical OR, logical XNOR, logical XOR, bitwise NOT, bitwise OR operation, bitwise OR operation on two source operands and setting a flag bit according to the result, left shift operation, right shift operation, operation of packing bit test mask and setting flag bit, or unpacking operation.

20. The instruction execution apparatus according to claim 19, characterized in that, When the predetermined operation is the move operation, the execution unit is configured as follows: If the opcode is the first op value, then the source operand of the instruction to be executed is moved from memory to the active variable-length mask register. If the opcode is the second op value, then the source operand of the instruction to be executed is moved from the activated variable-length mask register to memory; If the opcode is a third op value, then the source operand of the instruction to be executed is moved from the general vector register to the activated variable-length mask register. If the opcode is the fourth op value, then the source operand of the instruction to be executed is moved from the active variable-length mask register to the general vector register.

21. The instruction execution apparatus according to claim 20, characterized in that, The first field includes a first bit field used to identify the opcode mapping of the instruction to be executed. The execution unit is configured as follows: The bit width of the shift operation of the variable-length mask register is determined based on the flag bit of the first bit field and whether the instruction to be executed includes a prefix of the third field with a preset value.

22. The instruction execution apparatus according to claim 21, characterized in that, The execution unit is configured as follows: If the flag bit is 0 and includes a prefix with a preset value, then the bit width of the move operation is determined to be 1 byte; If the flag bit is 0 and does not include a prefix with a preset value, then the bit width of the move operation is determined to be 2 bytes; If the flag bit is 1 and includes a prefix with a preset value, then the bit width of the move operation is determined to be 4 bytes; If the flag bit is 1 and does not include a prefix with a preset value, then the bit width of the move operation is determined to be 8 bytes.

23. The instruction execution apparatus according to claim 14, characterized in that, The first field also includes a second bit field for accessing extended register resources. The execution unit is configured as follows: The addressable variable-length vector register is determined based on the second bit field; The function of the instruction to be executed is determined based on the opcode; The source register and destination register of the instruction to be executed are determined based on the addressing mode field; Based on the addressed variable-length vector register, the source register, and the destination register, the instruction to be executed is subjected to an operation corresponding to the function of the instruction to be executed.

24. The instruction execution apparatus according to claim 14, characterized in that, The first field includes a first bit field used to identify the opcode mapping of the instruction to be executed. The decoding unit is configured as follows: If the flag bit of the first bit field is the first flag value, then the instruction to be executed is determined to be a private variable-length vector instruction. If the flag bit of the first bit field is a second flag value that is different from the first flag value, then the instruction to be executed is determined to be not the private variable-length vector instruction.

25. The instruction execution apparatus according to claim 14, characterized in that, Also includes: The update unit is used to update the loading and operation instructions and mask operations of the variable-length mask register.

26. The instruction execution apparatus according to claim 14, characterized in that, The execution unit is configured as follows: If an exception occurs during the execution of the instruction to be executed, the exception is reported to the system register.

27. A processor, characterized in that, include: The registers include 32 variable-length vector registers, 8 variable-length mask registers, and 6 variable-length control registers; The decoding unit in the instruction execution apparatus according to any one of claims 14 to 26, The processor also includes: The execution unit in the instruction execution apparatus according to any one of claims 14 to 26.

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