Server heterogeneous computing resource dynamic partition scheduling method, system and device

Abstract

The application discloses a server heterogeneous computing resource dynamic partition scheduling method, system and device, and belongs to the server field. The server in the application contains multiple heterogeneous computing resources, each resource provides a computing partition and is connected with a CPU and a main memory through multiple high-speed interconnection channels. The eye diagram parameters of the high-speed interconnection channels connecting the CPU, the main memory and each computing resource partition are acquired and input into a variational autoencoder model, and the quality scores of the channels are determined through reconstruction errors. The main memory, the CPU and the resource partition are taken as nodes, the high-speed channels are taken as edge channels, and the quality scores are taken as weights to construct a topology graph. When a computing task is received, the candidate computing resource partitions are screened and adjusted according to the load demand of the computing task. The data transmission path quality scores from the main memory to each candidate partition are calculated in the topology graph, the candidate partition with the highest path quality score is selected, and the task is assigned to the partition for execution, so that the throughput rate and stability can be improved in a large-scale data-intensive computing scenario.

Description

Technical Field

[0001] This application belongs to the field of servers, and in particular relates to a method, system and device for dynamic partitioning and scheduling of heterogeneous computing resources on servers. Background Technology

[0002] Dynamic partitioning and scheduling of heterogeneous computing resources on servers is a key technology aimed at fully utilizing various computing hardware such as CPUs and GPUs to improve overall processing performance and resource utilization. With the rapid development of applications such as artificial intelligence and big data analytics, the demand for efficient heterogeneous computing resource management methods is increasing, and this technology has broad application prospects in modern data centers and high-performance computing.

[0003] Existing heterogeneous computing resource scheduling methods typically monitor and allocate resources at the logical or application level. Scheduling systems primarily make decisions based on macroscopic indicators such as the usage status and memory capacity of heterogeneous computing resources, aiming to allocate computing tasks to logically available and performance-matched resources to achieve load balancing or improve throughput.

[0004] However, in large-scale data-intensive computing scenarios, existing technologies that rely solely on the aforementioned logical performance metrics for scheduling face limitations in improving processing performance. For example, during the training of large AI models, massive amounts of data need to be frequently exchanged between main memory and multiple GPUs. In this case, the actual transmission efficiency of the data path becomes a key bottleneck determining performance. Existing methods for dynamic partitioning and scheduling of heterogeneous server computing resources lack the ability to perceive the real-time status of data transmission paths within the server. This may lead to problems such as poor data transmission or mismatched allocation of computing resources, resulting in poor throughput and stability in large-scale data-intensive computing scenarios. Summary of the Invention

[0005] This application provides a method, system, device, and computer storage medium for dynamic partitioning and scheduling of heterogeneous computing resources on servers, which can improve throughput and stability in large-scale data-intensive computing scenarios.

[0006] In a first aspect, this application provides a method for dynamic partitioning and scheduling of heterogeneous computing resources in a server. The server includes multiple heterogeneous computing resources, each heterogeneous computing resource provides an independently schedulable computing resource partition, and each heterogeneous computing resource is connected to the central processing unit and main memory through multiple high-speed interconnect channels. The method includes:

[0007] Obtain the eye diagram parameters of the differential signal for each high-speed interconnect channel. The eye diagram parameters include eye height, eye width, and jitter component.

[0008] The eye diagram parameters are input as input vectors to the trained variational autoencoder model to obtain the reconstruction vector. The channel quality score of each high-speed interconnect channel is determined by calculating the reconstruction error between the input vector and the reconstruction vector.

[0009] A topology graph is constructed using main memory, central processing unit, and computing resource partitions as nodes, high-speed interconnect channels as edges, and channel quality scores as edge weights.

[0010] Receive computing tasks, determine multiple candidate computing resource partitions from all computing resource partitions based on the load requirements of the computing tasks, and dynamically adjust the capacity of the candidate computing resource partitions.

[0011] In the topology graph, the node corresponding to the main memory is determined as the main memory node, and the node corresponding to the candidate computing resource partition is determined as the candidate partition node. For each candidate partition node, a data transmission path is determined in the topology graph with the main memory node as the starting point and the candidate partition node as the ending point. The path quality score of the data transmission path is calculated based on the weight of the edges in the data transmission path.

[0012] The candidate partition node in the data transmission path with the highest path quality score is identified as the target partition node, and the computing tasks are assigned to the computing resource partition corresponding to the target partition node.

[0013] In one feasible implementation, load requirements include the type of computing resources and the amount of resources required.

[0014] Based on the load requirements of the computing tasks, multiple candidate computing resource partitions are identified from all computing resource partitions, and the capacity of the candidate computing resource partitions is dynamically adjusted, including:

[0015] Based on the type of computing resources, resource demand, and channel quality score, multiple candidate computing resource partitions are identified from all computing resource partitions, and the capacity of the candidate computing resource partitions is dynamically adjusted.

[0016] In one feasible implementation, multiple candidate computing resource partitions are determined from all computing resource partitions based on computing resource type, resource demand, and channel quality score, and the capacity of the candidate computing resource partitions is dynamically adjusted, including:

[0017] Based on the type of computing resources, multiple candidate computing resources are identified from heterogeneous computing resources;

[0018] The accessibility value of each candidate computing resource is calculated by weighted summation based on the computing power index of the candidate computing resources and the channel quality score corresponding to the candidate computing resources.

[0019] All candidate computing resources are sorted in descending order based on their accessibility values. The top N candidate computing resources are determined as the target computing resources, and the computing resource partitions in the target computing resources are determined as candidate computing resource partitions.

[0020] Adjust the capacity of each candidate computing resource partition based on resource demand.

[0021] In one feasible implementation, for each candidate partition node, a data transmission path is determined in the topology graph, starting from the main memory node and ending at the candidate partition node. The path quality score of the data transmission path is then calculated based on the weights of the edges within the path, including:

[0022] For each candidate partition node, a first link from the main memory node to the corresponding node of the central processing unit is determined in the topology graph, and a second link from the corresponding node of the central processing unit to the candidate partition node. The first link and the second link together constitute the data transmission path.

[0023] The minimum weight between the weights of the edges corresponding to the first link and the weights of the edges corresponding to the second link is determined as the path quality score of the data transmission path.

[0024] In one feasible implementation, the attributes of the node corresponding to the computing resource partition in the topology graph include the capacity of the computing resource partition;

[0025] After identifying multiple candidate computing resource partitions from all computing resource partitions based on the load requirements of the computing tasks, and dynamically adjusting the capacity of the candidate computing resource partitions, the method further includes:

[0026] Based on the adjusted capacity of the computing resource partition, update the attributes of the nodes corresponding to the computing resource partition in the topology graph.

[0027] In one feasible implementation, the method further includes:

[0028] By calling the transceivers of the endpoint devices associated with the high-speed interconnect channel, the eye diagram parameters of the differential signal of the high-speed interconnect channel are collected in real time during server operation. The endpoint devices include heterogeneous computing resources and central processing units.

[0029] In one feasible implementation, before inputting the eye diagram parameters as input vectors into the trained variational autoencoder model to obtain the reconstructed vectors, the method further includes:

[0030] Obtain the training sample set, which includes multiple training samples, each of which consists of raw eye diagram parameters collected under the server's baseline operating conditions;

[0031] For each training sample, perform the following steps: input the original eye diagram parameters from each training sample into a preset variational autoencoder model to obtain the reconstructed eye diagram parameters;

[0032] The loss function value of the variational autoencoder model is determined based on the difference between the original eye diagram parameters and the reconstructed eye diagram parameters in the training samples.

[0033] If the loss function value does not meet the training stopping condition, adjust the model parameters of the variational autoencoder model to obtain the updated variational autoencoder model, and return to execute the step of inputting the original eye diagram parameters of each training sample into the preset variational autoencoder model until the training stopping condition is met, and obtain the trained variational autoencoder model.

[0034] Secondly, this application provides a dynamic partitioning and scheduling system for heterogeneous computing resources in a server. The server includes multiple heterogeneous computing resources, each heterogeneous computing resource provides an independently schedulable computing resource partition, and each heterogeneous computing resource is connected to the central processing unit and main memory through multiple high-speed interconnect channels. The system includes:

[0035] The acquisition module is used to acquire the eye diagram parameters of the differential signal of each high-speed interconnect channel. The eye diagram parameters include eye height, eye width and jitter component.

[0036] The calculation module is used to input eye diagram parameters as input vectors into the trained variational autoencoder model to obtain reconstruction vectors, and to determine the channel quality score of each high-speed interconnect channel by calculating the reconstruction error between the input vector and the reconstruction vector.

[0037] The building module is used to construct a topology graph with main memory, central processing unit and computing resource partitions as nodes, high-speed interconnect channels as edges and channel quality scores as edge weights;

[0038] The adjustment module is used to receive computing tasks, determine multiple candidate computing resource partitions from all computing resource partitions based on the load requirements of the computing tasks, and dynamically adjust the capacity of the candidate computing resource partitions.

[0039] The computing module is also used to determine the node corresponding to the main memory as the main memory node in the topology graph, determine the node corresponding to the candidate computing resource partition as the candidate partition node, and for each candidate partition node, determine a data transmission path in the topology graph with the main memory node as the starting point and the candidate partition node as the ending point, and calculate the path quality score of the data transmission path based on the weight of the edges in the data transmission path.

[0040] The allocation module is used to identify the candidate partition node in the data transmission path with the highest path quality score as the target partition node, and to allocate the computing tasks to the computing resource partition corresponding to the target partition node.

[0041] Thirdly, this application provides an electronic device, the device including: a processor, and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the server heterogeneous computing resource dynamic partitioning scheduling method as described in any embodiment of the first aspect.

[0042] Fourthly, this application provides a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the server heterogeneous computing resource dynamic partitioning scheduling method as described in any embodiment of the first aspect.

[0043] This application discloses a method, system, device, and computer storage medium for dynamic partitioning and scheduling of heterogeneous computing resources in servers. By real-time acquisition of eye diagram parameters—a physical layer signal quality indicator—of high-speed interconnect channels, and quantifying them into channel quality scores using a variational autoencoder model, the actual transmission capabilities of each data path within the server are perceived. By constructing a topology graph weighted by channel quality, the scheduler, when allocating computing tasks, no longer relies solely on the logical state of computing resources but can comprehensively evaluate the resource allocation and scheduling quality of the complete data path from main memory to candidate computing partitions. This allows computing tasks to be preferentially allocated to computing resource partitions that not only have matching computing power but also the smoothest and most stable data transmission paths, effectively avoiding performance degradation caused by data transmission bottlenecks. Therefore, it improves the overall data throughput and system stability of the server when handling large-scale data-intensive tasks.

[0044] Furthermore, by defining an accessibility value that integrates the computing power of computing units and the physical quality of data channels, the selection logic for candidate computing resource partitions is further optimized. In the initial stage of resource selection, both computing and communication capabilities are comprehensively evaluated, preemptively eliminating resources with sufficient computing power but poor data transmission path quality, thus bringing the consideration of physical transmission bottlenecks forward. This ensures that resource partitions entering the final path optimization stage all possess good computing and data access capabilities. Therefore, the foresight and effectiveness of scheduling decisions are improved, efficiently matching optimal resources for large-scale data-intensive tasks, further enhancing system throughput and stability. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating a method for dynamic partitioning and scheduling of heterogeneous computing resources on servers, provided in one embodiment of this application.

[0047] Figure 2 This is a schematic diagram of a constructed topology provided in one embodiment of this application;

[0048] Figure 3 This is a flowchart illustrating a method for adjusting the capacity of a dynamic partition of computing resources according to an embodiment of this application;

[0049] Figure 4 This is a schematic diagram of the structure of a server heterogeneous computing resource dynamic partitioning and scheduling system provided in one embodiment of this application;

[0050] Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0051] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0053] Existing heterogeneous computing resource scheduling methods typically monitor and allocate resources at the logical or application level. Scheduling systems primarily make decisions based on macroscopic indicators such as the usage status and memory capacity of heterogeneous computing resources, aiming to allocate computing tasks to logically available and performance-matched resources to achieve load balancing or improve throughput. However, in large-scale data-intensive computing scenarios, existing technologies relying solely on these logical performance indicators for scheduling have limitations in improving processing performance. For example, during large-scale AI model training, massive amounts of data need to be frequently exchanged between main memory and multiple GPUs; in this case, the actual transmission efficiency of the data path becomes a key bottleneck determining performance. Existing dynamic partitioning and scheduling methods for heterogeneous server computing resources lack the ability to perceive the real-time status of data transmission paths within the server, which may lead to problems such as poor data transmission or mismatched computing resource allocation. Therefore, existing technologies suffer from poor throughput and stability in large-scale data-intensive computing scenarios.

[0054] To address the problems of existing technologies, embodiments of this application provide a method, system, device, and computer storage medium for dynamic partitioning and scheduling of heterogeneous computing resources on servers. The method for dynamic partitioning and scheduling of heterogeneous computing resources on servers provided in this application embodiment will be described first below.

[0055] Figure 1 This illustration shows a flowchart of a server heterogeneous computing resource dynamic partitioning and scheduling method according to an embodiment of this application. The server includes multiple heterogeneous computing resources, each providing an independently schedulable computing resource partition. Each heterogeneous computing resource is connected to the central processing unit and main memory via multiple high-speed interconnect channels, such as... Figure 1 As shown, the method includes steps S110 to S160.

[0056] In large-scale data-intensive computing scenarios such as training large-scale artificial intelligence models, a single computing hardware cannot meet the enormous demands for parallel computing. Therefore, servers are typically configured with multiple physically heterogeneous computing resources, such as multiple graphics processing units (GPUs). Heterogeneous computing resources refer to physical hardware entities within a server, other than the central processing unit (CPU), that possess specific computing acceleration capabilities, such as GPUs, field-programmable gate arrays (FPGAs), or application-specific integrated circuits (ASICs). A computing resource partition is the basic logical unit for resource allocation and task assignment; it is a portion of computing resources divided from the heterogeneous computing resource physical entities. In this application, each heterogeneous computing resource physical entity provides a corresponding computing resource partition, and these partitions collectively constitute a schedulable resource pool. When a computing task needs to be executed, the scheduling system selects the most suitable partition from this resource pool for allocation. The allocatable resource capacity within each computing resource partition, such as the percentage of computing power or the size of video memory, can be adjusted. High-speed interconnect channels refer to the physical data links connecting main memory, central processing unit (CPU), and various heterogeneous computing resources. They mainly include two types: one is the I / O interconnect bus used to connect CPU and heterogeneous computing resources, such as the PCIe bus; the other is the memory interconnect bus used to connect main memory and CPU.

[0057] For example, in large-scale data-intensive computing scenarios such as training large-scale artificial intelligence models, the architecture of a high-performance server includes a large-capacity main memory and a high-performance multi-core central processing unit (CPU). To meet the computing needs of mixed workloads, the server is also configured with seven heterogeneous computing resources, all connected via the CPU's PCIe controller. Specifically, this may include three high-performance graphics processing units (GPU0, GPU1, and GPU2), two field-programmable gate arrays (FPGA0 and FPGA1) for low-latency streaming data processing, and two application-specific integrated circuits (ASIC0 and ASIC1) for accelerating specific AI inference. Each heterogeneous computing resource provides a logically independently schedulable computing resource partition, and each computing resource partition is initially allocated a specific computing resource capacity. For example, GPU0 provides a computing resource partition (GPU0 partition), and the initial capacity of GPU0 partition can be 24GB of high-speed video memory. FPGA0 provides a computing resource partition (FPGA0 partition), and the initial capacity of FPGA0 partition can be 80% of its internal logic units. This continues, forming seven computing resource partitions. When a data-intensive computing task is issued, the raw data for the task is loaded from main memory and transferred to the central processing unit (CPU) via a high-speed memory bus. The CPU, acting as the data distribution hub, transmits the data to a computing resource partition for processing through its directly connected PCIe high-speed interconnect channels.

[0058] S110: Obtain the eye diagram parameters of the differential signal for each high-speed interconnect channel. The eye diagram parameters include eye height, eye width, and jitter component.

[0059] Eye diagram parameters are a set of key metrics used to quantitatively evaluate the signal integrity of the physical layer in high-speed interconnect channels. High-speed digital signals are subject to interference from various physical factors during transmission. By superimposing a large number of consecutive signal bits on the time axis, a shape resembling an eye can be formed, hence the eye diagram. Eye height refers to the widest distance of the eye diagram in the vertical direction, representing the noise margin of the signal; eye width refers to the widest distance of the eye diagram in the horizontal direction, representing the timing margin of the signal; jitter components are various statistical measures of the signal's deviation from its ideal position on the time axis, such as deterministic jitter and random jitter.

[0060] The diagnostic module is invoked via software commands to access the physical layer transceiver diagnostic module built into the endpoint device associated with each high-speed interconnect channel. These endpoint devices can be central processing units (CPUs) or heterogeneous computing resources. This diagnostic module uses internal high-precision sampling circuitry to scan the differential signal and perform bit error rate statistics during normal server operation, thereby logically reconstructing the eye diagram and calculating a set of quantized eye diagram parameters. The memory bus connecting main memory and the CPU also obtains its eye diagram parameters by invoking the diagnostic function built into the memory controller. Ultimately, for each high-speed interconnect channel within the server, an eye diagram parameter set containing multiple dimensions such as eye height, eye width, and various jitter components is output.

[0061] For example, a command is sent via the driver interface to the transceiver of the PCIe channel connected to GPU0 to activate its internal self-test diagnostic function. This function module continuously samples the received data signals without interrupting the normal operation of GPU0, measuring and calculating the current eye height of the channel (e.g., 400 mV), eye width (e.g., 0.6 unit intervals), and deterministic jitter (e.g., 0.1 unit intervals). A command is then sent to the CPU's memory controller to obtain the eye diagram parameters of the memory bus channel connected to main memory, for example, its eye height (e.g., 500 mV) and eye width (e.g., 0.7 unit intervals). The same operation is repeated for all high-speed interconnect channels connected to the other six heterogeneous computing resources, resulting in a set of eye diagram parameters reflecting the real-time health of the physical layer of all data paths within the server.

[0062] S120: The eye diagram parameters are input as input vectors to the trained variational autoencoder model to obtain the reconstruction vector. The channel quality score of each high-speed interconnect channel is determined by calculating the reconstruction error between the input vector and the reconstruction vector.

[0063] Channel quality score is a numerical indicator used to characterize the current physical health of a high-speed interconnect channel; a higher score indicates better channel quality.

[0064] First, the eye diagram parameters of each high-speed interconnect channel are organized into a multi-dimensional input vector. For example, the eye diagram parameters of the PCIe channel connected to GPU0 can be constructed as an input vector, which can be [400, 0.6, 0.1]. Then, this input vector is sent to a pre-trained variational autoencoder model. The model, through its internal encoder and decoder networks, outputs a reconstruction vector with the same dimension as the input vector; the model output reconstruction vector can be [398, 0.61, 0.09]. By calculating the Euclidean distance between the input vector and the reconstruction vector in multi-dimensional space, a scalar reconstruction error value is obtained. Finally, this reconstruction error value is processed to generate a channel quality score ranging from 0 to 1. This processing can utilize a sigmoid function, such as an exponential decay function or a logistic function, to establish a non-linear mapping between the reconstruction error and the channel quality score. In this mapping relationship, the reconstruction error value is inversely proportional to the channel quality score value. That is, a lower reconstruction error value will result in a higher channel quality score after function transformation, reflecting a high similarity between the current channel state and its health state during training. Conversely, a higher reconstruction error value indicates anomalies in the channel signal, resulting in a lower channel quality score. The calculated lower reconstruction error, after this function transformation, yields a high score close to 1, ultimately determining that the channel quality score for the high-speed interconnect channel connecting to GPU0 can be 0.98. This process is applied to all acquired eye diagram parameters, generating a real-time, quantized channel quality score for each data path within the server.

[0065] S130: Construct a topology graph using main memory, central processing unit, and computing resource partitions as nodes, high-speed interconnect channels as edges, and channel quality scores as edge weights.

[0066] First, a topology graph data structure is created. Then, based on the server's physical configuration, corresponding node objects are created for the large main memory, CPU, and each computing resource partition. Next, edge objects are created between the corresponding nodes according to the hardware connectivity, with each edge representing a unique high-speed interconnect channel. Finally, the channel quality score calculated for each high-speed interconnect channel is assigned as a weight to the corresponding edge in the graph. This construction process is executed periodically or updated as needed to ensure that the topology graph always reflects the latest channel health status.

[0067] Figure 2 A schematic diagram of a constructed topology provided in one embodiment of this application is shown.

[0068] For example, such as Figure 2As shown, a server configured with one central processing unit (CPU) and seven heterogeneous computing resources is used to construct a topology graph consisting of nine nodes. The nodes are the main memory node, the CPU node, and the GPU0, GPU1, GPU2, FPGA0, FPGA1, ASIC0, and ASIC1 partition nodes. Eight edges are created based on physical connections: one edge connects the main memory node and the CPU node, and the other seven edges connect the CPU node to each of the seven computing resource partition nodes. Finally, the calculated channel quality scores are assigned to the corresponding edges in the graph as their weights. Specifically, the weight of the edge connecting the main memory node is 0.99; the weights of the edges connecting the GPU0, GPU1, and GPU2 partition nodes are 0.98, 0.95, and 0.97, respectively; the weights of the edges connecting the FPGA0 and FPGA1 partition nodes are 0.99 and 0.96, respectively; and the weights of the edges connecting the ASIC0 and ASIC1 partition nodes are 0.94 and 0.98, respectively. Through this process, a weighted graph of the current server resource topology and link status is constructed.

[0069] S140: Receive computing tasks, determine multiple candidate computing resource partitions from all computing resource partitions based on the load requirements of the computing tasks, and dynamically adjust the capacity of the candidate computing resource partitions.

[0070] Load requirements are the hardware resource demands of a computing task, used for resource selection and configuration. Load requirements mainly include the type of computing resources and the amount of resources required. The type of computing resources specifies the type of hardware required to execute the task; for example, a task might specify that it needs a graphics processing unit (GPU) for parallel computing. The amount of resources required defines the scale of the resources needed; for example, a task might require at least 20GB of video memory and a certain level of computing power.

[0071] Upon receiving a new computing task, the system first parses the computing resource type in its load requirements and then iterates through all computing resource partitions on the server, filtering out all partitions that match the type to form an initial candidate list of computing resource partitions. Then, based on the resource requirements in the load requirements, the resource capacity of each partition in the initial candidate list is dynamically adjusted or reserved to ensure that they can all meet the task's execution requirements.

[0072] For example, when a computational task requiring AI model inference arrives, its load requirements are first analyzed. These requirements could be for GPUs as the computing resource type and 16GB of high-speed video memory as the resource requirement. Then, all seven computing resource partitions in the server are traversed. By comparing the computing resource types, GPU0, GPU1, and GPU2 are identified as meeting the requirements and are designated as candidate computing resource partitions. The capacity of these three candidate computing resource partitions is then dynamically adjusted; for example, the allocatable capacity of GPU0 is adjusted to 16GB, the allocatable capacity of GPU1 is adjusted to 16GB, and the allocatable capacity of GPU2 is also adjusted to 16GB.

[0073] S150: In the topology graph, the node corresponding to the main memory is determined as the main memory node, and the node corresponding to the candidate computing resource partition is determined as the candidate partition node. For each candidate partition node, a data transmission path is determined in the topology graph with the main memory node as the starting point and the candidate partition node as the ending point. The path quality score of the data transmission path is calculated based on the weight of the edges in the data transmission path.

[0074] A data transmission path is a complete route used to represent computing task data from main memory, through the central processing unit, and finally to the target computing resource partition. In a topology graph, it is represented as a sequence of edges connected end-to-end. Path quality is a quantitative indicator used to evaluate the overall health and transmission capacity of the entire data transmission path.

[0075] First, for each partition in a set of capacity-adjusted candidate compute resource partitions, its corresponding candidate partition node is identified in the constructed topology graph. Next, based on the server's fixed physical architecture, a unique data transfer path is determined from the main memory node to the candidate partition node. This path includes the link from main memory to the CPU and the link from the CPU to the partition. Finally, the weights of all edges constituting this path, i.e., the channel quality score, are extracted, and a pre-defined mathematical method, such as bottleneck analysis or weighted averaging, is applied to calculate the final path quality score. Specifically, based on the bottleneck principle, the smaller value between the weights of the main memory to CPU and the CPU to the candidate partition constituting the data transfer path is determined as the final path quality score.

[0076] S160: Identify the candidate partition node in the data transmission path with the highest path quality score as the target partition node, and assign the computing task to the computing resource partition corresponding to the target partition node.

[0077] First, the path quality scores calculated for all candidate partition nodes are compared. For example, if the path quality score for GPU0 is 0.98, for GPU1 it's 0.95, and for GPU2 it's 0.97, a maximum value search process identifies the candidate partition node with the highest path quality score. By comparing these three values, 0.98 is determined as the maximum, and GPU0 is selected as the sole target partition node for this scheduling. Finally, the corresponding instructions are generated and executed, formally allocating the computation task to the computational resource partition physically corresponding to the target partition node. Specifically, this may include loading the task's execution code into the GPU0's computational core and transferring the data required by the task to GPU0's memory via its corresponding high-speed interconnect channel. The task then begins execution on GPU0.

[0078] This embodiment acquires eye diagram parameters—a physical layer signal quality indicator—of high-speed interconnect channels in real time and quantifies them into channel quality scores using a variational autoencoder model, thereby perceiving the true transmission capabilities of each data path within the server. By constructing a topology graph weighted by channel quality, the scheduler, when allocating computing tasks, no longer relies solely on the logical state of computing resources but can comprehensively evaluate the resource allocation and scheduling quality of the complete data path from main memory to candidate computing partitions. This allows computing tasks to be preferentially allocated to computing resource partitions that not only have matching computing power but also the smoothest and most stable data transmission paths, effectively avoiding performance degradation caused by data transmission bottlenecks. Therefore, it improves the overall data throughput and system stability of the server when handling large-scale data-intensive tasks.

[0079] In one feasible implementation, load requirements include the type of computing resources and the amount of resources required.

[0080] In step S140, based on the load requirements of the computing tasks, multiple candidate computing resource partitions are determined from all computing resource partitions, and the capacity of the candidate computing resource partitions is dynamically adjusted, including:

[0081] Based on the type of computing resources, resource demand, and channel quality score, multiple candidate computing resource partitions are identified from all computing resource partitions, and the capacity of the candidate computing resource partitions is dynamically adjusted.

[0082] First, after a computing task is issued, its load requirements are extracted to obtain the type and quantity of computing resources needed. Next, all computing resource partitions in the server whose hardware types match the task requirements are initially screened. Then, for each initially screened partition, a comprehensive accessibility score is calculated for each partition through a weighted summation process, combining its inherent hardware performance indicators, such as computing power, and the channel quality score of its corresponding high-speed interconnect channel. The accessibility score quantifies both the partition's computing power and data path quality. Subsequently, all initially screened partitions are sorted in descending order based on this accessibility score, and the top-ranked partitions are selected as the final candidate computing resource partitions. Finally, the capacity of these final selected candidate computing resource partitions is dynamically adjusted according to the resource requirements, resulting in an optimized and configured list of candidate computing resource partitions.

[0083] Figure 3 A flowchart illustrating a method for adjusting the capacity of a dynamic partition of computing resources according to an embodiment of this application is shown. Figure 3 As shown, the method includes steps S310 to S340.

[0084] In one feasible implementation, multiple candidate computing resource partitions are determined from all computing resource partitions based on computing resource type, resource demand, and channel quality score, and the capacity of the candidate computing resource partitions is dynamically adjusted, including:

[0085] S310: Based on the type of computing resource, identify multiple candidate computing resources among heterogeneous computing resources.

[0086] Upon receiving a computing task, the first step is to parse the computing resource type from its load requirements; for example, for an AI model training task, the computing resource type could be GPU. Then, all the physical heterogeneous computing resources configured on the server are traversed, and the hardware type of each resource is compared with the type required by the task. All heterogeneous computing resources that match the type are identified and collectively form a candidate computing resource list; physical hardware GPU0, GPU1, and GPU2 are identified as candidate computing resources.

[0087] S320: The accessibility value of each candidate computing resource is calculated by weighted summation based on the computing power index of the candidate computing resources and the channel quality score corresponding to the candidate computing resources.

[0088] Computing power metrics are numerical values ​​that quantify the theoretical computing performance of heterogeneous computing resources. These can be metrics such as peak floating-point operations, core frequency, or memory bandwidth. Accessibility metrics are quantitative values ​​that evaluate the suitability of computing resources for data-intensive tasks; higher scores indicate better overall performance of the computing resources.

[0089] First, for each identified candidate computing resource, predefined computing power metrics are extracted from its hardware specifications, and the channel quality score corresponding to the high-speed interconnect channel connecting that candidate computing resource is obtained. The computing power metrics can be obtained from the hardware's technical manual or configuration information, specifically its peak half-precision floating-point performance (FPS). For example, this performance for a GPU might be 90 TFLOPS. This value is then linearly mapped to obtain the quantized computing power metric. For instance, for candidate computing resources GPU0, GPU1, and GPU2, the computing power metrics obtained through this method could be 100, 100, and 120, respectively, while the corresponding channel quality scores would be 0.98, 0.95, and 0.97.

[0090] Next, the values ​​of these two different dimensions are normalized to eliminate the difference in dimensions, and the normalized computing power index and channel quality score are merged into a single accessibility value through a weighted summation calculation with a non-linear penalty term. Specifically, the accessibility value can be calculated using a function as shown in formula (1).

[0091] (1)

[0092] Where V is the accessibility value; S is the normalized computing power index; and C is the channel quality score. and These are preset weighting coefficients; is the preset penalty weight coefficient, and |S_norm-C_q| is the absolute value of the difference between the computing power index and the channel quality score. This term is used as a penalty term to reduce the final score of candidate computing resources that are unbalanced between the two.

[0093] S330: Sort all candidate computing resources in descending order based on their accessibility values, determine the top N candidate computing resources as target computing resources, and determine the computing resource partitions in the target computing resources as candidate computing resource partitions.

[0094] First, based on the accessibility values ​​of all candidate computing resources, a descending sort operation is performed on these candidate computing resources; the three candidate computing resources are sorted into the order GPU2, GPU0, and GPU1. Then, according to a preset parameter N, the top N candidate computing resources in the sorted results are selected and determined as target computing resources. Finally, the computing resource partitions that uniquely correspond to the physical entities of these N target computing resources are collectively determined as the final candidate computing resource partition list of this embodiment; if the preset parameter N is 2, then GPU2 and GPU0, which rank higher, are selected as target computing resources, and their corresponding GPU2 and GPU0 partitions are determined as the final candidate computing resource partitions.

[0095] S340: Adjust the capacity of each candidate computing resource partition according to resource demand.

[0096] First, the specific resource requirements are extracted from the workload of the computing task; for example, for another AI model training task, the resource requirement could be 40GB of high-speed video memory. Then, for each identified candidate computing resource partition, its allocable capacity is adjusted to meet the resource requirements by calling the underlying resource management interface; that is, the available video memory capacity of both GPU2 and GPU0 partitions is dynamically adjusted to 40GB, ultimately generating a list of two filtered and configured high-quality candidate computing resource partitions.

[0097] This embodiment further optimizes the selection logic for candidate computing resource partitions by defining an accessible value that integrates the computing power of a computing unit with the physical quality of the data channel. In the initial stage of resource selection, both computing and communication capabilities are comprehensively evaluated, preemptively eliminating resources with sufficient computing power but poor data transmission path quality, thus prioritizing the consideration of physical transmission bottlenecks. This ensures that resource partitions entering the final path optimization stage all possess good computing and data access capabilities. Therefore, it improves the foresight and effectiveness of scheduling decisions, efficiently matching optimal resources for large-scale data-intensive tasks, and further enhancing system throughput and stability.

[0098] In one feasible implementation, step S150 involves determining a data transmission path in the topology graph for each candidate partition node, starting from the main memory node and ending at the candidate partition node, and calculating the path quality score of the data transmission path based on the weights of the edges in the data transmission path, including:

[0099] For each candidate partition node, a first link is determined in the topology graph from the main memory node to the node corresponding to the central processing unit, and a second link is determined from the node corresponding to the central processing unit to the candidate partition node. The first link and the second link together constitute the data transmission path.

[0100] The first link specifically refers to the path through which data is transferred from the source main memory to the distribution hub, the central processing unit (CPU), and corresponds to the edge connecting the main memory node and the CPU node in the topology graph. The second link specifically refers to the path through which data is further transferred from the CPU to a specific computing resource partition, and corresponds to the edge connecting the CPU node and the candidate partition node in the topology graph.

[0101] For each candidate compute resource partition, the first link representing data flow from main memory to the central processing unit (CPU) is first identified in the constructed topology graph. This link is unique and fixed in a single-CPU architecture. Then, a second link representing data flow from the CPU to that specific candidate compute resource partition is identified. Finally, these two logically connected links are combined to form a complete data transmission path from the data source to the processing terminal. For example, for the candidate compute resource partition GPU0, its data transmission path consists of the first link from main memory to the CPU and the second link from the CPU to GPU0.

[0102] The minimum weight between the weights of the edges corresponding to the first link and the weights of the edges corresponding to the second link is determined as the path quality score of the data transmission path.

[0103] First, for the data transmission path determined for each candidate partition node in the previous step, the weights of the edges corresponding to the first and second links constituting the path are extracted respectively. These two weights are their respective channel quality scores. Taking the aforementioned GPU0 partition as an example, from... Figure 2 In the topology diagram shown, the weight of the first link is assigned as 0.99, and the weight of the second link as 0.98. Then, a numerical comparison operation is performed to find the minimum of these two weight values. Finally, this minimum value is taken as the final path quality score for this data transmission path; in the example of the GPU0 partition, by comparing 0.99 and 0.98, the smaller value of 0.98 is determined as the path quality score leading to the GPU0 partition. Through the above process, the corresponding path quality score can be calculated for each candidate partition node.

[0104] In one feasible implementation, the attributes of the node corresponding to the computing resource partition in the topology graph include the capacity of the computing resource partition.

[0105] The attributes of a compute resource partition node can include information about the currently available resource capacity of that compute resource partition.

[0106] In step S140: After determining multiple candidate computing resource partitions from all computing resource partitions based on the load requirements of the computing tasks and dynamically adjusting the capacity of the candidate computing resource partitions, the method further includes:

[0107] Based on the adjusted capacity of the computing resource partition, update the attributes of the nodes corresponding to the computing resource partition in the topology graph.

[0108] First, after S140 is completed, all candidate computing resource partitions and their adjusted new capacity values ​​are obtained; for example, it is known that the capacity of GPU0 partition and GPU2 partition has been dynamically adjusted to 40GB of high-speed video memory. Then, for each candidate computing resource partition, its corresponding node is located in the topology graph. Finally, through an assignment operation, the adjusted new capacity value of the partition is updated to the capacity attribute of its corresponding node; for example, the capacity attribute value of the GPU0 partition node is updated from its initial 24GB to the adjusted 40GB, and similarly, the capacity attribute value of the GPU2 partition node is also updated to 40GB.

[0109] In one feasible implementation, the method further includes:

[0110] By calling the transceivers of the endpoint devices associated with the high-speed interconnect channel, the eye diagram parameters of the differential signal of the high-speed interconnect channel are collected in real time during server operation. The endpoint devices include heterogeneous computing resources and central processing units.

[0111] Endpoint devices refer to hardware entities located at both ends of a high-speed interconnect channel; these entities are central processing units (CPUs) and various heterogeneous computing resources. Transceivers are physical layer interface circuits built into these endpoint devices, responsible for transmitting and receiving high-speed signals. With continuous improvements in chip technology and integration, modern high-performance CPUs, graphics processing units (GPUs), and FPGAs commonly integrate built-in self-test functions for signal integrity diagnostics into their physical layer interfaces. These functions enable the acquisition of physical layer parameters such as eye diagrams during system runtime via software instructions.

[0112] Through the underlying hardware driver interface or management firmware, a function call instruction is sent to the endpoint device associated with a specified high-speed interconnect channel. For example, to obtain the eye diagram parameters of the high-speed interconnect channel connecting the heterogeneous computing resource GPU1, a system call is executed, which is ultimately translated into an instruction sent to the GPU1 chip. This instruction activates the diagnostic module integrated in the physical layer transceiver inside the endpoint device chip. This module then begins internal sampling and statistical analysis of the received high-speed differential signals without interrupting the device's normal computing tasks. After completing the analysis, the module calculates the eye diagram parameters, including eye height, eye width, and jitter components, and returns these parameters to the upper-layer software through registers or predefined memory areas. For example, this diagnostic function can determine that the eye height of the corresponding channel of GPU1 is 380 millivolts and the eye width is 0.55 unit intervals, and write these parameters to a memory area accessible by its driver. At the same time, the diagnostic function of the memory controller built into the central processing unit can also be invoked to obtain the status of the memory bus connected to main memory, ultimately enabling the complete collection of physical layer health data of all critical data links within the entire server.

[0113] In one feasible implementation, before inputting the eye diagram parameters as input vectors into the trained variational autoencoder model to obtain the reconstructed vectors, the method further includes:

[0114] Obtain the training sample set, which includes multiple training samples, each of which consists of raw eye diagram parameters collected under the server's baseline operating conditions.

[0115] The server baseline operating state refers to the reference operating conditions under which all hardware physical links are in good working order. Under this baseline operating state, the training samples in the training sample set represent the original eye diagram parameters under these conditions. The original eye diagram parameters of the differential signals of high-speed interconnect channels collected from all servers with no physical layer defects in their high-speed interconnect channels are integrated to form a training sample set containing multiple training samples. For example, one could collect and aggregate hundreds of thousands of sets of eye diagram parameters of the differential signals of high-speed interconnect channels from servers with no physical layer defects in their high-speed interconnect channels under different high-load applications to form the training sample set.

[0116] For each training sample, perform the following steps: input the original eye diagram parameters from each training sample into a preset variational autoencoder model to obtain the reconstructed eye diagram parameters.

[0117] Based on the difference between the original eye diagram parameters and the reconstructed eye diagram parameters in the training samples, the loss function value of the variational autoencoder model is determined. If the loss function value does not meet the training stopping condition, the model parameters of the variational autoencoder model are adjusted to obtain an updated variational autoencoder model. Then, the process of inputting the original eye diagram parameters from each training sample into the preset variational autoencoder model is repeated until the training stopping condition is met, resulting in a trained variational autoencoder model.

[0118] First, the variational autoencoder model is initialized. Then, a training sample is taken one by one or in batches from the training sample set, and its original eye diagram parameters are input into the model. The model outputs a reconstructed eye diagram parameter through its encoder and decoder networks. For example, inputting a set of original eye diagram parameters [500, 0.7, 0.05] into a randomly initialized model may result in a reconstructed eye diagram parameter [450, 0.6, 0.1] that varies considerably. Next, the Euclidean distance between the original and reconstructed eye diagram parameters is calculated to determine the current model's loss function value on that sample. Subsequently, it is determined whether the loss function value or cumulative loss meets the training stopping condition. If not, the gradient of the loss function with respect to all parameters within the model is calculated using the backpropagation algorithm, and these parameters are finely adjusted using optimization algorithms such as gradient descent. The adjusted model is an updated model, which will continue to process the next training sample. This process is repeated hundreds of times, until the total loss function of the model converges to a very low level and remains stable. At this point, the training stopping condition is met. For example, the training stopping condition can be that when the decrease in the total loss function of the model in multiple consecutive training cycles is less than a preset convergence threshold, such as one ten-thousandth, the training stopping condition can be determined to be met, thus finally obtaining a fully trained variational autoencoder model.

[0119] Based on the same concept, this application provides a dynamic partitioning and scheduling system for heterogeneous computing resources on servers. The following is a detailed description... Figure 4 This application provides a detailed description of the server heterogeneous computing resource dynamic partitioning and scheduling system provided in the embodiments.

[0120] Figure 4 This is a structural block diagram of a server heterogeneous computing resource dynamic partitioning and scheduling system shown in an embodiment of this application.

[0121] The server comprises multiple heterogeneous computing resources, each providing an independently schedulable computing resource partition. Each heterogeneous computing resource is connected to the central processing unit and main memory via multiple high-speed interconnect channels. For example... Figure 4 As shown, the server heterogeneous computing resource dynamic partitioning and scheduling system may include:

[0122] The acquisition module 410 is used to acquire the eye diagram parameters of the differential signal of each high-speed interconnect channel. The eye diagram parameters include eye height, eye width and jitter component.

[0123] The calculation module 420 is used to input the eye diagram parameters as input vectors into the trained variational autoencoder model to obtain the reconstruction vector, and to determine the channel quality score of each high-speed interconnect channel by calculating the reconstruction error between the input vector and the reconstruction vector.

[0124] Module 430 is used to construct a topology graph with main memory, central processing unit and computing resource partitions as nodes, high-speed interconnect channels as edges and channel quality scores as edge weights.

[0125] The adjustment module 440 is used to receive computing tasks, determine multiple candidate computing resource partitions from all computing resource partitions according to the load requirements of the computing tasks, and dynamically adjust the capacity of the candidate computing resource partitions.

[0126] The computing module 420 is also used to determine the node corresponding to the main memory as the main memory node in the topology graph, determine the node corresponding to the candidate computing resource partition as the candidate partition node, and for each candidate partition node, determine a data transmission path in the topology graph with the main memory node as the starting point and the candidate partition node as the ending point, and calculate the path quality score of the data transmission path based on the weight of the edge in the data transmission path.

[0127] The allocation module 450 is used to determine the candidate partition node in the data transmission path with the highest path quality score as the target partition node, and to allocate the computing tasks to the computing resource partition corresponding to the target partition node.

[0128] In one embodiment, the load requirement includes the type of computing resource and the amount of resource required; the adjustment module 440 is specifically used to determine multiple candidate computing resource partitions among all computing resource partitions based on the type of computing resource, the amount of resource required and the channel quality score, and to dynamically adjust the capacity of the candidate computing resource partitions.

[0129] In one embodiment, the adjustment module 440 is specifically used to determine multiple candidate computing resources among heterogeneous computing resources according to the type of computing resources; calculate the accessibility value of each candidate computing resource by weighted summation based on the computing power index of the candidate computing resources and the channel quality score corresponding to the candidate computing resources; sort all candidate computing resources in descending order according to the accessibility value, determine the top N candidate computing resources as target computing resources, and determine the computing resource partitions in the target computing resources as candidate computing resource partitions; and adjust the capacity of each candidate computing resource partition according to the resource demand.

[0130] In one embodiment, the computing module 420 is specifically used to determine, for each candidate partition node, a first link from the main memory node to the node corresponding to the central processing unit in the topology graph, and a second link from the node corresponding to the central processing unit to the candidate partition node, wherein the first link and the second link together constitute a data transmission path; and to determine the path quality score of the data transmission path as the minimum weight between the weight of the edge corresponding to the first link and the weight of the edge corresponding to the second link.

[0131] In one embodiment, the attributes of the node corresponding to the computing resource partition in the topology graph include the capacity of the computing resource partition; the adjustment module 440 is further configured to, after determining multiple candidate computing resource partitions among all computing resource partitions according to the load requirements of the computing task and dynamically adjusting the capacity of the candidate computing resource partitions, update the attributes of the node corresponding to the computing resource partition in the topology graph based on the adjusted capacity of the computing resource partition.

[0132] In one embodiment, the acquisition module 410 is further configured to acquire eye diagram parameters of the differential signal of the high-speed interconnect channel in real time during server operation by calling the transceiver of the endpoint device associated with the high-speed interconnect channel, the endpoint device including heterogeneous computing resources and a central processing unit.

[0133] In one embodiment, the computing module 420 is further configured to acquire a training sample set, which includes multiple training samples, each of which consists of original eye diagram parameters collected under server baseline operating conditions. For each training sample, the following steps are performed: inputting the original eye diagram parameters from each training sample into a preset variational autoencoder model to obtain reconstructed eye diagram parameters; determining the loss function value of the variational autoencoder model based on the difference between the original eye diagram parameters and the reconstructed eye diagram parameters in the training sample; adjusting the model parameters of the variational autoencoder model if the loss function value does not meet the training stopping condition, obtaining an updated variational autoencoder model, and returning to execute the step of inputting the original eye diagram parameters from each training sample into the preset variational autoencoder model until the training stopping condition is met, thereby obtaining a trained variational autoencoder model.

[0134] Figure 4 Each module in the system shown has an implementation Figure 1 and Figure 3 The functions of each step in the process and their corresponding technical effects are described in detail here for the sake of brevity.

[0135] Figure 5 A schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application is shown.

[0136] The electronic device may include a processor 510 and a memory 520 storing computer program instructions.

[0137] Specifically, the processor 510 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0138] Memory 520 may include mass storage for data or instructions. For example, and not limitingly, memory 520 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 520 may include removable or non-removable (or fixed) media. Where appropriate, memory 520 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 520 is non-volatile solid-state memory.

[0139] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to the first aspect of this disclosure.

[0140] The processor 510 reads and executes computer program instructions stored in the memory 520 to implement any of the server heterogeneous computing resource dynamic partitioning scheduling methods in the above embodiments.

[0141] In one example, the electronic device may also include a communication interface 530 and a bus 540. Wherein, such as Figure 5 As shown, the processor 510, memory 520, and communication interface 530 are connected through bus 540 and complete communication with each other.

[0142] The communication interface 530 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0143] Bus 540 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 540 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0144] This electronic device can execute the server heterogeneous computing resource dynamic partitioning scheduling method in the embodiments of this application, thereby achieving a combination of Figure 1 and Figure 3 The method described is a dynamic partitioning and scheduling method for heterogeneous computing resources on servers.

[0145] Furthermore, in conjunction with the server heterogeneous computing resource dynamic partitioning and scheduling method in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the server heterogeneous computing resource dynamic partitioning and scheduling methods in the above embodiments.

[0146] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0147] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0148] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0149] The aspects of this application have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0150] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for dynamic partitioning and scheduling of heterogeneous computing resources on servers, characterized in that, The server includes multiple heterogeneous computing resources, each of which provides an independently schedulable computing resource partition. Each heterogeneous computing resource is connected to the central processing unit and main memory via multiple high-speed interconnect channels. The method includes: Eye diagram parameters of the differential signal for each of the high-speed interconnect channels are obtained. The eye diagram parameters include eye height, eye width, and jitter components. The eye diagram parameters are a set of key indicators for quantitatively evaluating the signal integrity of the differential signal based on the eye diagram. The eye diagram is a shape resembling an eye formed by superimposing a large number of consecutive signal bits of the differential signal on the time axis. The eye height is the longest distance of the eye diagram in the vertical direction, the eye width is the longest distance of the eye diagram in the horizontal direction, and the jitter components are a statistical measure of the deviation of the differential signal from the ideal position on the time axis. The jitter components include deterministic jitter and random jitter. The eye diagram parameters are input as input vectors to the trained variational autoencoder model to obtain the reconstruction vector, and the channel quality score of each high-speed interconnect channel is determined by calculating the reconstruction error between the input vector and the reconstruction vector. A topology graph is constructed using main memory, central processing unit, and the computing resource partition as nodes, the high-speed interconnect channel as edges, and the channel quality score as the edge weights. Receive computing tasks, determine multiple candidate computing resource partitions from all the computing resource partitions according to the load requirements of the computing tasks, and dynamically adjust the capacity of the candidate computing resource partitions; In the topology graph, the node corresponding to the main memory is determined as the main memory node, and the node corresponding to the candidate computing resource partition is determined as the candidate partition node. For each candidate partition node, a data transmission path is determined in the topology graph with the main memory node as the starting point and the candidate partition node as the ending point. The path quality score of the data transmission path is calculated based on the weight of the edges in the data transmission path. The candidate partition node in the data transmission path with the highest path quality score is determined as the target partition node, and the computing task is assigned to the computing resource partition corresponding to the target partition node; For each candidate partition node, a data transmission path is determined in the topology graph, starting from the main memory node and ending at the candidate partition node. The path quality score of the data transmission path is then calculated based on the weights of the edges in the data transmission path, including: For each candidate partition node, a first link from the main memory node to the node corresponding to the central processing unit is determined in the topology graph, and a second link from the node corresponding to the central processing unit to the candidate partition node. The first link and the second link together constitute the data transmission path. The minimum weight between the weight of the edge corresponding to the first link and the weight of the edge corresponding to the second link is determined as the path quality score of the data transmission path.

2. The method according to claim 1, characterized in that, The load requirements include the type of computing resources and the amount of resources required. The step of determining multiple candidate computing resource partitions from all the computing resource partitions based on the load requirements of the computing task, and dynamically adjusting the capacity of the candidate computing resource partitions, includes: Based on the computing resource type, the resource requirement, and the channel quality score, multiple candidate computing resource partitions are determined from all the computing resource partitions, and the capacity of the candidate computing resource partitions is dynamically adjusted.

3. The method according to claim 2, characterized in that, The step of determining multiple candidate computing resource partitions from all the computing resource partitions based on the computing resource type, the resource demand, and the channel quality score, and dynamically adjusting the capacity of the candidate computing resource partitions, includes: Based on the computing resource type, multiple candidate computing resources are determined from the heterogeneous computing resources; The accessibility value of each candidate computing resource is calculated by weighted summation based on the computing power index of the candidate computing resource and the channel quality score corresponding to the candidate computing resource. All candidate computing resources are sorted in descending order according to the accessibility value, the top N candidate computing resources are determined as target computing resources, and the computing resource partitions in the target computing resources are determined as candidate computing resource partitions. Adjust the capacity of each candidate computing resource partition according to the resource demand.

4. The method according to claim 1, characterized in that, The attributes of the nodes corresponding to the computing resource partitions in the topology diagram include the capacity of the computing resource partitions; After determining multiple candidate computing resource partitions from all the computing resource partitions based on the load requirements of the computing task, and dynamically adjusting the capacity of the candidate computing resource partitions, the method further includes: Based on the adjusted capacity of the computing resource partition, update the attributes of the node corresponding to the computing resource partition in the topology graph.

5. The method according to claim 1, characterized in that, The method further includes: By invoking the transceiver of the endpoint device associated with the high-speed interconnect channel, the eye diagram parameters of the differential signal of the high-speed interconnect channel are acquired in real time during server operation. The endpoint device includes the heterogeneous computing resources and the central processing unit.

6. The method according to claim 1, characterized in that, Before inputting the eye diagram parameters as input vectors into the trained variational autoencoder model to obtain the reconstructed vector, the method further includes: Obtain a training sample set, which includes multiple training samples, each of which consists of raw eye diagram parameters collected under the server's baseline operating conditions; For each training sample, the following steps are performed: the original eye diagram parameters in each training sample are input into the preset variational autoencoder model to obtain the reconstructed eye diagram parameters; The loss function value of the variational autoencoder model is determined based on the difference between the original eye map parameters and the reconstructed eye map parameters in the training samples. If the loss function value does not meet the training stopping condition, the model parameters of the variational autoencoder model are adjusted to obtain the updated variational autoencoder model. Then, the process of inputting the original eye diagram parameters of each training sample into the preset variational autoencoder model is repeated until the training stopping condition is met, and the trained variational autoencoder model is obtained.

7. A dynamic partitioning and scheduling system for heterogeneous computing resources in a server, wherein the server includes multiple heterogeneous computing resources, each heterogeneous computing resource provides an independently schedulable computing resource partition, and each heterogeneous computing resource is connected to a central processing unit and main memory through multiple high-speed interconnect channels, characterized in that, The system includes: The acquisition module is used to acquire eye diagram parameters of the differential signal of each of the high-speed interconnect channels. The eye diagram parameters include eye height, eye width, and jitter components. The eye diagram parameters are a set of key indicators for quantitatively evaluating the signal integrity of the differential signal based on the eye diagram. The eye diagram is a shape resembling an eye formed by superimposing a large number of consecutive signal bits of the differential signal on the time axis. The eye height is the longest distance of the eye diagram in the vertical direction, the eye width is the longest distance of the eye diagram in the horizontal direction, and the jitter components are a statistical measure of the deviation of the differential signal from the ideal position on the time axis. The jitter components include deterministic jitter and random jitter. The calculation module is used to input the eye diagram parameters as input vectors into the trained variational autoencoder model to obtain the reconstruction vector, and to determine the channel quality score of each of the high-speed interconnect channels by calculating the reconstruction error between the input vector and the reconstruction vector. The construction module is used to construct a topology graph with main memory, central processing unit and computing resource partition as nodes, high-speed interconnect channel as edge and channel quality score as edge weight; An adjustment module is used to receive computing tasks, determine multiple candidate computing resource partitions from all the computing resource partitions according to the load requirements of the computing tasks, and dynamically adjust the capacity of the candidate computing resource partitions. The computing module is further configured to determine the node corresponding to the main memory as the main memory node and the node corresponding to the candidate computing resource partition as the candidate partition node in the topology graph. For each candidate partition node, a data transmission path is determined in the topology graph starting from the main memory node and ending at the candidate partition node. The module also calculates the path quality score of the data transmission path based on the weights of the edges in the data transmission path. Specifically, for each candidate partition node, the module determines a first link from the main memory node to the node corresponding to the central processing unit (CPU) and a second link from the CPU node to the candidate partition node in the topology graph. The first link and the second link together constitute the data transmission path. The minimum weight between the weights of the edges corresponding to the first link and the weights of the edges corresponding to the second link is determined as the path quality score of the data transmission path. The allocation module is used to determine the candidate partition node in the data transmission path with the highest path quality score as the target partition node, and to allocate the computing task to the computing resource partition corresponding to the target partition node.

8. An electronic device, characterized in that, The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the server heterogeneous computing resource dynamic partitioning scheduling method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the server heterogeneous computing resource dynamic partitioning scheduling method as described in any one of claims 1-6.

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