Method of data transmission, receiving unit, chip, readable medium, program product

Abstract

The present disclosure provides a data transmission method, a receiving unit, a chip, a computer readable medium and a computer program product, and belongs to the technical field of cross-die data transmission, and can solve the problem of long delay in existing cross-die data transmission. The data transmission method of the present disclosure is used for a receiving unit, the receiving unit and a sending unit are packaged in the same chip and are connected through an inter-die connection, the receiving unit receives a data signal from the sending unit through an RX FIFO, a local clock of the sending unit and a local clock of the receiving unit are generated according to a same reference clock, a read clock of the RX FIFO is the local clock of the receiving unit, a write clock is a feedforward clock generated according to the local clock of the sending unit, and a read period of the RX FIFO is greater than a write period. The method of the present disclosure comprises at least determining an adjusted write pointer according to a read clock and a write clock of the RX FIFO, and determining a read enable of the RX FIFO according to the adjusted write pointer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of cross-die data transmission, and in particular to a data transmission method, a receiving unit, a sending unit, a chip, a computer readable medium, and a computer program product. BACKGROUND

[0002] The delay of data transmission between different dies in a chip is large. SUMMARY

[0003] The present disclosure provides a data transmission method, a receiving unit, a sending unit, a chip, a computer readable medium, and a computer program product.

[0004] In a first aspect, the present disclosure provides a data transmission method, which is used in a receiving unit, the receiving unit and a sending unit are packaged in the same chip and connected through an inter-die connection, the receiving unit receives a data signal from the sending unit through a receiving side first-in-first-out buffer RX FIFO, a local clock of the sending unit and a local clock of the receiving unit are generated according to a same reference clock, a read clock of the RX FIFO is the local clock of the receiving unit, a write clock of the RX FIFO is a feedforward clock generated according to the local clock of the sending unit, and a read period of the RX FIFO is greater than a write period; the method comprises the following steps.

[0005] According to at least the read clock and the write clock of the RX FIFO, an adjusted write pointer is determined, and a read enable of the RX FIFO is determined according to the adjusted write pointer.

[0006] In some embodiments, the step of determining the adjusted write pointer according to at least the read clock and the write clock of the RX FIFO, and determining the read enable of the RX FIFO according to the adjusted write pointer comprises the following steps.

[0007] An offset between the write clock and the read clock of the RX FIFO is detected.

[0008] According to the offset and the write clock of the RX FIFO, a sample write pointer signal is generated.

[0009] The sample write pointer signal is sampled at a sampling edge of the read clock of the RX FIFO, and a read enable of the RX FIFO is determined according to a sampling result.

[0010] In some embodiments, the sampling edge of the read clock of the RX FIFO is located in a preset central interval of a write pointer range of the sample write pointer signal.

[0011] In some embodiments, the generating a sample write pointer signal according to the offset and a write clock of the RX FIFO comprises:

[0012] generating the sample write pointer signal delayed relative to a write pointer of the RX FIFO according to the offset; wherein a delay amount of the sample write pointer signal relative to the write pointer of the RX FIFO is nt / 2, t is a write period of the RX FIFO, and n is an integer greater than or equal to 0 and less than a multiple of 2, the multiple of period being a ratio of a read period to a write period of the RX FIFO.

[0013] In some embodiments, the method of the present disclosure further comprises:

[0014] in response to the RX FIFO being reset, setting the write pointer of the RX FIFO to a maximum position and setting the read pointer of the RX FIFO to a minimum position.

[0015] the determining an adjusted write pointer according to at least the read clock and the write clock of the RX FIFO and determining a read enable of the RX FIFO according to the adjusted write pointer comprises: generating a local high-frequency clock; synchronizing the write pointer of the RX FIFO to a read clock domain of the RX FIFO according to the local high-frequency clock; sampling the synchronized write pointer of the RX FIFO at a sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO according to a sampling result; wherein a period of the local high-frequency clock is equal to a write period of the RX FIFO, a total period of the high-frequency clock after synchronization is less than 2 times a read period of the RX FIFO, and the write pointer of the RX FIFO is in a Gray code form.

[0016] In some embodiments, the multiple of period is 4, the multiple of period being a ratio of a read period to a write period of the RX FIFO.

[0017] the total period of the high-frequency clock after synchronization is 4 to 6 periods.

[0018] In some embodiments, the method of the present disclosure further comprises:

[0019] in response to the RX FIFO being reset, setting the write pointer of the RX FIFO to a maximum position and setting the read pointer of the RX FIFO to a minimum position.

[0020] In some embodiments, the method of the present disclosure further comprises:

[0021] when there is no data signal to be received, the feedforward clock is not received from the sending unit.

[0022] When the time of continuously receiving the feedforward clock reaches a preset time threshold, the feedforward clock is received from the sending unit, and the write pointer of the RX FIFO is adjusted according to at least the read clock of the RX FIFO.

[0023] In some embodiments, the method of the embodiments of the present disclosure further comprises:

[0024] In response to the amount of data stored in the RX FIFO reaching a preset data amount threshold, a full signal is sent to the sending unit; the data amount threshold is less than the maximum capacity of the RX FIFO, and the full signal is used to control the sending unit to suspend sending the data signal.

[0025] In some embodiments, the method of the embodiments of the present disclosure further comprises:

[0026] In response to the number of write cycles of the RX FIFO continuously receiving the data signal reaching a predetermined cycle number threshold, a full signal is sent to the sending unit; the full signal is used to control the sending unit to suspend sending the data signal.

[0027] In some embodiments, the receiving unit receives multiple data signals from the sending unit through multiple RX FIFOs, wherein one RX FIFO is a target RX FIFO.

[0028] The method further comprises: determining the adjusted write pointer according to at least the read clock and the write clock of the target RX FIFO, and determining the read enable of all the RX FIFOs according to the adjusted write pointer.

[0029] In a second aspect, the embodiments of the present disclosure provide a receiving unit, comprising an RX FIFO, a memory and a processor; the memory stores a computer program executable by the processor, and the computer program is executed by the processor to implement any one of the data transmission methods of the embodiments of the present disclosure.

[0030] In a third aspect, the embodiments of the present disclosure provide a chip, comprising:

[0031] a reference clock;

[0032] a sending unit;

[0033] a receiving unit implementing any one of the receiving units of the embodiments of the present disclosure.

[0034] In a fourth aspect, the embodiments of the present disclosure provide a computer readable medium, which stores a computer program. The computer program is executed by a processor to implement any of the data transmission methods of the embodiments of the present disclosure.

[0035] In a fifth aspect, the embodiments of the present disclosure provide a computer program product, which includes a computer program. The computer program is executed by a processor to implement any of the data transmission methods of the embodiments of the present disclosure.

[0036] In the embodiments of the present disclosure, the receiving unit can generate an adjusted write pointer according to a read clock of the locally generated RX FIFO and a write clock of the RX FIFO generated by the sending unit, and determine the read enable of the RX FIFO according to the adjusted write pointer, so as to shorten the read-write distance and greatly reduce the delay of cross-die data transmission. BRIEF DESCRIPTION OF DRAWINGS

[0037] In the drawings of the embodiments of the present disclosure:

[0038] Figure 1 is a block diagram of a chip in the related art;

[0039] Figure 2 is a flowchart of a data transmission method provided by the embodiments of the present disclosure;

[0040] Figure 3 is a flowchart of another data transmission method provided by the embodiments of the present disclosure;

[0041] Figure 4 is a flowchart of another data transmission method provided by the embodiments of the present disclosure;

[0042] Figure 5 is a block diagram of a receiving unit provided by the embodiments of the present disclosure;

[0043] Figure 6 is a block diagram of a chip provided by the embodiments of the present disclosure;

[0044] Figure 7 is a block diagram of a computer readable medium provided by the embodiments of the present disclosure;

[0045] Figure 8 is a schematic diagram of a sampling write pointer signal in different situations in another data transmission method provided by the embodiments of the present disclosure;

[0046] Figure 9 is a timing diagram in situation 2 in another data transmission method provided by the embodiments of the present disclosure;

[0047] Figure 10A timing diagram of another data transmission method provided in an embodiment of this disclosure;

[0048] Figure 11 This is a timing diagram of a data transmission method in related technologies;

[0049] Figure 12 Timing diagram of reading clock fast in another data transmission method provided in this embodiment of the present disclosure;

[0050] Figure 13 Timing diagram for a slow read clock in another data transmission method provided in this embodiment of the present disclosure;

[0051] Figure 14 A system architecture diagram of the data transmission method of Example 1 provided in this disclosure embodiment;

[0052] Figure 15 This is a schematic diagram of the structure of the DES in Example 1 provided in the embodiments of this disclosure;

[0053] Figure 16 A partial detailed structural diagram of the receiving unit in Example 1 provided in this embodiment of the present disclosure;

[0054] Figure 17 for Figure 16 A schematic diagram of the structure of a phase detector;

[0055] Figure 18 A system architecture diagram of the data transmission method provided in Example 2 of this disclosure;

[0056] Figure 19 This is a partial detailed structural diagram of the receiving unit in Example 2 provided in the embodiments of this disclosure. Detailed Implementation

[0057] To enable those skilled in the art to better understand the technical solutions of this disclosure, the data transmission method, receiving unit, sending unit, chip, computer-readable medium, and computer program product provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0058] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0059] The accompanying drawings are provided to further illustrate this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. These and other features and advantages will become more apparent to those skilled in the art from the description of detailed embodiments with reference to the accompanying drawings.

[0060] Unless otherwise specified, each embodiment and feature of this disclosure may be used individually or in combination with other embodiments and features thereof.

[0061] Those skilled in the art will understand that various changes in form and detail may be made to the embodiments of this disclosure without departing from the scope of this disclosure as set forth by the appended claims.

[0062] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0063] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0064] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0065] A chip is an independent computing device that includes packaged integrated circuits, such as a central processing unit (CPU) or a general-purpose graphics processing unit (GP-GPU).

[0066] As the size of circuit structures in chips continues to shrink, approaching the quantum tunneling limit, further miniaturization becomes extremely difficult from both a technological and cost perspective. Therefore, building large systems from interconnected smaller systems becomes more economical. For this purpose, chiplet technology can be employed, i.e., referring to...Figure 1 Partial integrated circuits are formed on multiple unpackaged dies. Each die can perform some computational functions relatively independently, and die-to-die connections are set between the dies to achieve cross-die data transmission. The multiple dies and their inter-die connections are then packaged into a chip.

[0067] In some related technologies, refer to Figure 1 To enable cross-die data transmission, a first-in-first-out (FIFO) buffer can be set in both the transmitting (TX) die and the receiving (RX) die. The data to be transmitted is first written to the TX FIFO by the TX die, then read from the TX FIFO, and written to the RX FIFO via the die-to-die connection. Finally, it is read from the RX FIFO and processed by the RX die.

[0068] In some related technologies, multiple bare dies can use a "same-source clock," that is, referenced to... Figure 1 Multiple bare dies generate their own local clocks (LCLK) based on the same reference clock (ref) to control various local operations. However, due to uneven circuit layout, process technology, temperature, aging, etc., there is still a certain difference between the local clocks of different bare dies, i.e., drift, and this drift may fluctuate within a certain range as the chip is used.

[0069] Based on the above-mentioned technologies, the data writing of the RX FIFO is essentially controlled by the local clock of the TX die, and the data reading is controlled by the local clock of the RX die. Therefore, there is a drift between the local clocks of the TX die and the RX die, which is equivalent to the read clock and write clock of the RX FIFO being out of sync. Hence, the RX FIFO is an "asynchronous FIFO".

[0070] In some related technologies, to ensure that the local clock of each bare die will not cause data errors regardless of left or right drift throughout the entire life cycle of the chip, the drift buffer technology can be used. That is, after the read enable of the RX FIFO is enabled, it will pause for 2-3 clock cycles to synchronize with the read clock domain, and then pause for another 1-2 clock cycles to convert to Gray code before reading begins; the specific number of clock cycles is determined according to the maximum possible drift range of the clock.

[0071] Thus, the RX FIFO has a large read-write distance, which requires a large depth of the RX FIFO to store data during synchronization, such as a depth of at least 4, and the large read-write distance also greatly increases the delay of cross-die data transmission. For example, when the local clock is 2GHz, that is, 1 beat or 1 clock cycle is 500ps, the delay of intra-die data transmission is usually 2 beats 1ns; and the read-write distance of the RX FIFO is usually 2-4 clock cycles, and the delay of transmission and the like is added, so that the delay of cross-die data transmission usually needs to be more than 10ns, which cannot meet the requirement of 2ns delay specified in the Universal Chiplet Interconnect Express (UCIe) protocol.

[0072] In a first aspect, with reference to Figures 2 to 13 The embodiments of the present disclosure provide a data transmission method for a receiving unit, the receiving unit and a sending unit are packaged in the same chip and connected through a die-to-die connection, the receiving unit receives a data signal from the sending unit through a receiving side first-in-first-out buffer RX FIFO, the local clock of the sending unit and the local clock of the receiving unit are generated according to the same reference clock, the read clock of the RX FIFO is the local clock of the receiving unit, the write clock of the RX FIFO is a feedforward clock generated according to the local clock of the sending unit, and the read period of the RX FIFO is greater than the write period.

[0073] With reference to Figure 6 The method of the embodiments of the present disclosure is used for a receiving unit, the receiving unit and a sending unit are packaged in a chip (Chip), and the receiving unit includes an RX FIFO, the RX FIFO is connected with the sending unit through a die-to-die connection, so that the sending unit can send a data signal to the receiving unit through the die-to-die connection and the RX FIFO.

[0074] With reference to Figure 6 The receiving unit and the sending unit are also connected with the same reference clock (ref) and generate their own local clocks according to the reference clock.

[0075] For the receiving unit, the read clock of the RX FIFO is generated according to the local clock, and the write clock of the RX FIFO is a feedforward clock (FWD CLK, Forwarding Clock) from the sending unit, which is essentially generated according to the local clock of the sending unit.

[0076] The local clock of the sending unit and the local clock of the receiving unit are generated according to the same reference clock, and the frequencies of the two clocks can be the same, for example, both are 2GHz; and the frequency of the write clock of the RX FIFO, that is, the frequency of the feedforward clock, can be higher than the frequency of the local clock, for example, can be 8GHz, so that the read period of the RX FIFO is greater than the write period.

[0077] For example, as one of the modes of the embodiments of the present disclosure, with reference to Figure 6 , the receiving unit can also be provided with a receiving-side first-in-first-out buffer TX FIFO, and the data signal is transmitted to the RX FIFO through the TX FIFO, so that the write clock of the RX FIFO and the feedforward clock are generated according to the read clock of the RX FIFO, and the read clock of the RX FIFO is generated according to the local clock of the sending great circle.

[0078] It should be understood that the sending unit can also not have a TX FIFO, and the data signal can be sent to the RX FIFO through a register (reg) or other means, as long as the sending unit can send the data signal and provide the write clock of the RX FIFO.

[0079] The receiving unit can be an RX die or a module in the RX die for cross-die data transmission; and the sending unit can be a TX die or a module in the TX die for cross-die data transmission.

[0080] It should be understood that the above TX die and RX die are determined according to the direction of data transmission; and the same die can both send data to other dies and receive data from other dies, so the die can be both a TX die and an RX die, and the die can include both a sending unit and a receiving unit.

[0081] With reference to Figure 2 , the method for data transmission of the embodiments of the present disclosure includes:

[0082] S101, determining an adjusted write pointer according to at least the read clock and the write clock of the RX FIFO, and determining the read enable of the RX FIFO according to the adjusted write pointer.

[0083] In the embodiments of the present disclosure, the receiving unit can generate an adjusted write pointer according to the locally generated read clock of the RX FIFO and the write clock of the RX FIFO generated by the sending unit, and determine the read enable of the RX FIFO according to the adjusted write pointer, so as to shorten the read-write distance and greatly reduce the delay of cross-die data transmission.

[0084] It should be understood that in the embodiments of the present disclosure, only the read enable of the RX FIFO is required to be generated according to the adjusted write pointer, but the write operation of the RX FIFO is not required to be performed according to the adjusted write pointer, that is, the RX FIFO can still perform the writing of data according to the original write clock and write pointer.

[0085] It should be understood that since the adjusted write pointer is to be sampled according to the read clock of the RX FIFO, the period of the adjusted write pointer should be the same as the period of the read clock of the RX FIFO, and greater than the period of the actual write clock or write pointer of the RX FIFO.

[0086] Further, the number of cycle periods of the adjusted write pointer should also be the same as the number of cycle periods of the read clock, that is, equal to the depth of the RX FIFO.

[0087] It should be understood that in order to distinguish different write pointers in a larger range, the label of the adjusted write pointer can be greater than the number of its cycle periods. For example, when the depth of the RX FIFO is 4, the adjusted write pointer should be between 0 and 3, but its label can be 0-7, wherein 0 and 4 labels correspond to the first row of the RX FIFO, 1 and 5 labels correspond to the second row of the RX FIFO, 2 and 6 labels correspond to the third row of the RX FIFO, and 3 and 7 labels correspond to the fourth row of the RX FIFO.

[0088] In some embodiments, referring to Figure 3 , the adjusted write pointer is determined at least according to the read clock and the write clock of the RX FIFO, and the read enable of the RX FIFO is determined according to the adjusted write pointer (S101), comprising:

[0089] S101A1, detecting the offset between the write clock and the read clock of the RX FIFO.

[0090] S101A2, generating a sampled write pointer signal according to the offset and the write clock of the RX FIFO.

[0091] S101A3, sampling the sampled write pointer signal at the sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO according to the sampling result.

[0092] When the read operation and the write operation of a row of the RX FIFO are too close, or the read operation is performed first and then the write operation is performed, data errors will be caused.

[0093] Therefore, referring to Figure 3As a manner of the embodiment of the present disclosure, the receiving unit can first compare the write clock and the read clock of the RX FIFO through a phase detector (PD) or the like to obtain the actual difference therebetween, that is, to obtain the offset.

[0094] For example, since the write clock of the RX FIFO, that is, the feedforward clock, has a higher frequency than the read clock, the feedforward clock can be first divided to have the same frequency as the read clock of the RX FIFO, and then enter the phase detector together with the read clock of the RX FIFO to obtain the offset.

[0095] Further, the receiving unit can also generate a "sampled write pointer signal" according to the above offset and the original write clock of the RX FIFO. The sampled write pointer signal is equivalent to a "pushed write pointer" obtained by adjusting the original write pointer of the RX FIFO according to the offset.

[0096] Further, while the RX FIFO writes data according to the above original write clock, the receiving unit can sample the sampled write pointer signal at the sampling edge of the read clock of the RX FIFO, such as the rising edge or the falling edge, and determine the read enable of the RX FIFO according to the sampling result, that is, determine the read operation of the RX FIFO according to the sampled write pointer signal.

[0097] It can be seen that, according to the embodiment of the present disclosure, the read operation of the RX FIFO is performed according to the sampled write pointer signal, and the sampled write pointer signal is generated according to the offset. That is, the read operation of the RX FIFO is performed according to the difference between the write clock and the read clock of the RX FIFO, so that the RX FIFO can actually work in the manner of a "synchronous FIFO", without the need for separate clock synchronization to cross the clock domains of the TX die and the RX die, and the delay is greatly reduced. At the same time, the sampled write pointer signal is generated according to the "real-time" offset, so that the read enable generated according to the sampled write pointer signal can ensure that there is a necessary read-write distance between the read operation and the write operation, so that data errors will not occur, and the read-write distance is much smaller than the maximum offset in the entire life cycle of the chip, so as to further reduce the delay.

[0098] In some embodiments, the sampling edge of the read clock of the RX FIFO is located in a preset central interval of the write pointer range of the sampled write pointer signal.

[0099] As a manner of the embodiment of the present disclosure, the above generated sampled write pointer signal can be such that the sampling edge of the read clock of the RX FIFO is located in the central interval of the write pointer range thereof, so as to ensure that no data errors will occur within a sufficient offset range.

[0100] In some embodiments, a sample write pointer signal is generated (S101A2) according to the offset and the write clock of the RX FIFO, including:

[0101] S101A21, generating a sample write pointer signal delayed from the write pointer of the RX FIFO according to the offset.

[0102] wherein the delay of the sample write pointer signal from the write pointer of the RX FIFO is nt / 2, t is the write period of the RX FIFO, n is an integer greater than or equal to 0 and less than 2 times the period ratio of the read period to the write period of the RX FIFO.

[0103] As one way of the embodiments of the present disclosure, the newly generated sample write pointer signal can have a certain delay from the original write pointer of the RX FIFO, and can ensure that the sampling edge of the read clock of the RX FIFO is located in the center region of the pointer range of the sample write pointer signal.

[0104] For example, the original write clock of the RX FIFO can be frequency-divided to obtain a write pointer with the same period as the read clock of the RX FIFO, and then the write pointer is delayed to obtain the sample write pointer signal.

[0105] It should be understood that the embodiments of the present disclosure only require that the generated sample write pointer signal meets the above delay relationship with the original write pointer of the RX FIFO, and do not necessarily require that the original write clock is delayed to generate the sample write pointer signal, for example, the local clock can also be adjusted according to the original write clock to generate the sample write pointer signal.

[0106] It should be understood that even if the original write clock of the RX FIFO is delayed to generate the sample write pointer signal, the write operation of the RX FIFO is still performed according to its original write clock.

[0107] For example, when the write period of the RX FIFO is t, the delay of the original write clock of the RX FIFO can be t / 2 or an integer multiple of a unit interval (UI), that is, the original write clock of the RX FIFO can be frequency-divided and then delayed by n t / 2 to obtain the sample write pointer signal; and n is less than 2 times the ratio of the read period T to the write period t of the RX FIFO, or in other words, less than 2 times the "period ratio", that is, the total delay nt / 2 of the write pointer must be less than the read period T to avoid excessive delay.

[0108] For example, refer to Figure 8, the read clock frequency of the RX FIFO can be 2GHz, corresponding to a read period T = 500ps, and the write clock frequency can be 8GHz, corresponding to a write period t = 125ps, corresponding to UI = 62.5ps; thus, the read period T is 4 times the write period t, that is, the period multiple is 4, so the above n can be an integer between 0 and 7, and the maximum delay is 7t / 2.

[0109] wherein, with reference to Figure 8 , since the period multiple is 4, the write pointer that is the object of the delay here can be obtained by dividing the write clock of the RX FIFO by 4, that is, the write pointer is 2GHz, which is the same as the read clock of the RX FIFO.

[0110] Correspondingly, the center interval of the write pointer range can be set to 1t, that is, if the write pointer range is determined to be [0, 4t], then the interval [3t / 2, 5t / 2] is the "center interval".

[0111] Thus, with reference to Figure 8 , the part of generating the sampling write pointer signal according to the write clock of the RX FIFO can include:

[0112] (1) Case 1 (case1), when the sampling edge of the read clock is determined to be located in the shadow area of case1 according to the offset, that is, the difference between the leading edge of the write pointer range and the sampling edge is [-t / 2, t / 2), the write clock should be delayed by 2t to generate the sampling write pointer signal, that is, n = 4, so that the sampling edge is located in the center interval of the write pointer range of the sampling write pointer signal.

[0113] (2) Case 2 (case2), when the sampling edge of the read clock is determined to be located in the shadow area of case2 according to the offset, that is, the difference between the leading edge of the write pointer range and the sampling edge is [-3t / 2, -t / 2), the write clock should be delayed by 3t to generate the sampling write pointer signal, that is, n = 6, so that the sampling edge is located in the center interval of the write pointer range of the sampling write pointer signal.

[0114] (3) Case 3 (case3), when the sampling edge of the read clock is determined to be located in the shadow area of case3 according to the offset, that is, the difference between the leading edge of the write pointer range and the sampling edge is [-5t / 2, -3t / 2), it is originally directly located in the center interval of the write pointer range, so the write clock does not need to be delayed to directly generate the sampling write pointer signal, or it is considered as the write clock is delayed by 0t to generate the sampling write pointer signal, that is, n = 0.

[0115] (4) Case 4 (case4), when the sampling edge of the read clock is determined to be located in the shadow area of case4 according to the offset, that is, the difference between the leading edge of the write pointer range and the sampling edge is [-7t / 2, -5t / 2), which is equivalent to delaying the write clock by 5t. However, the total delay amount 5t exceeds T, so the write clock should actually be delayed by t to generate the sampling write pointer signal, that is, n = 2, so that the sampling edge is located in the center interval of the write pointer range of the sampling write pointer signal.

[0116] It should be understood that the above operation of generating the sampling write pointer signal according to the offset can be performed in an initial state, such as when the chip is powered on. For example, after the chip is powered on, the sending unit can send test data signals to the receiving unit before actually starting to transmit data signals, so that the receiving unit can first collect the offset and correspondingly generate the sampling write pointer signal.

[0117] Meanwhile, after the chip enters the working state, that is, in the process of actually transmitting data signals, the receiving unit can also continuously detect the offset in real time and correspondingly generate the sampling write pointer signal, that is, the offset can be continuously “tracked”.

[0118] In some embodiments, the method of the embodiments of the present disclosure further comprises:

[0119] S100, in response to the reset of the RX FIFO, setting the write pointer of the RX FIFO to the maximum position, and setting the read pointer of the RX FIFO to the minimum position.

[0120] As another way of the embodiments of the present disclosure, when the RX FIFO is reset, such as power-on reset, only the read pointer can be set to the minimum position, that is, “read pointer = 0”; the write pointer is not zeroed, but is set to the maximum position, that is, “write pointer = max”; thus, the RX FIFO can directly read the data at position 0, without having to wait for the write pointer to be 1 before reading the data at position 0 as in the asynchronous FIFO in the related art, and the delay can be reduced by one clock cycle.

[0121] For example, with reference to Figure 9 For the above case 1, the original write pointer of the RX FIFO is delayed by 2t to generate the sampling write pointer signal, which is used for sampling of the read clock of the RX FIFO and correspondingly generates the read enable.

[0122] wherein, since the write pointer = max at reset, when the RX FIFO is empty, we have:

[0123] Empty = (rdptr == sample_wrptr + 1'b1);

[0124] rd_en=~empty;

[0125] wherein, rdptr represents a read pointer, sample_wrptr represents a sample write pointer, rd_en represents a read enable, and 1 represents enabling the read enable, and 0 represents disabling the read enable.

[0126] wherein, when the read and write pointers are reset values, (7+1)%8=0, rd_en=0; when the sample write pointer=0, 0! =0+1, which represents non-empty, and rd_en=1; and when rd_en=1, the data in the RX FIFO can be read according to the read clock, and the read pointer is incremented by 1 each time.

[0127] Therefore, referring to Figure 9 , for the above Figure 8 Case 1, the delay between the read and write of the RX FIFO, that is, the time length from the end of the write pointer 0 to the start of reading the data D0, is 1T.

[0128] Correspondingly, for the above method, the maximum delay of the write pointer is 3.5t, so the maximum read-write delay of the embodiment of the present disclosure is 1T+1.5t=1.375T.

[0129] Therefore, according to the above method, the maximum delay of the RX FIFO is only 1.375T, which is much smaller than the method in the related art.

[0130] In some embodiments, referring to Figure 4 , the method of the embodiment of the present disclosure further comprises:

[0131] S100, in response to the reset of the RX FIFO, setting the write pointer of the RX FIFO to the maximum position, and setting the read pointer of the RX FIFO to the minimum position.

[0132] In some embodiments, referring to Figure 4 , the adjusted write pointer is determined according to at least the read clock and the write clock of the RX FIFO, and the read enable of the RX FIFO is determined according to the adjusted write pointer (S101), comprising:

[0133] S101B1, generating a local high-frequency clock.

[0134] S101B2, synchronizing the write pointer of the RX FIFO to the read clock domain according to the local high-frequency clock.

[0135] S101B3, sampling the synchronized write pointer of the RX FIFO at the sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO according to the sampling result.

[0136] Wherein, the period of the local high frequency clock is equal to the write period of the RX FIFO, the total period of the tapped high frequency clock is less than 2 times of the read period of the RX FIFO, and the write pointer of the RX FIFO is in the form of Gray code.

[0137] Referring to Figure 4 As another mode of the embodiment of the present disclosure, when the RX FIFO is reset, the read pointer is set to 0, and the write pointer is set to max.

[0138] Referring to Figure 4 In this case, the way of adjusting the write pointer of the RX FIFO according to the read clock of the RX FIFO can be that the receiving unit first generates a local high frequency clock with the same frequency as the write clock of the RX FIFO, such as a local high frequency clock with a frequency of 8 GHz, according to the local clock. Since both of them are derived from the local clock of the RX FIFO, the local high frequency clock is synchronized with the read clock of the RX FIFO.

[0139] Further, the receiving unit taps the write pointer of the RX FIFO according to the above local high frequency clock, and synchronizes it to the read clock domain of the RX FIFO according to the working mode of the asynchronous FIFO, that is, the tapping synchronization is performed with the clock period t of the local high frequency clock as a tap.

[0140] For example, the original write clock of the RX FIFO can be divided to obtain a write pointer with the same period as the read clock of the RX FIFO, and then the write pointer signal is tapped to the read clock domain of the RX FIFO according to the above local high frequency clock to obtain the synchronized write pointer of the RX FIFO.

[0141] Then, the above synchronized write pointer of the RX FIFO is sampled at the sampling edge of the read clock of the RX FIFO, and the read enable is generated according to the sampling result.

[0142] Wherein, the total time of the above tapping is less than 2 times of the read period of the RX FIFO.

[0143] Wherein, in the above tapping synchronization, the write pointer of the RX FIFO is converted into the form of Gray code. Gray code is a coding mode of binary data (0 and 1), which ensures that in the coding range, any two adjacent codes of Gray code have only one different bit, so that compared with the conventional binary coding, Gray code can realize cross-clock domain through single bit change in any case, is easy to implement, and is not easy to produce metastable state, data error, etc., which will not be described in detail here.

[0144] In some embodiments, the cycle multiple is 4, the cycle multiple is a ratio of a read cycle to a write cycle of the RX FIFO; and a total cycle of the tapped high-frequency clock is 4 to 6 cycles.

[0145] As a manner of the embodiments of the present disclosure, when the above cycle multiple is 4, such as the write cycle t=125 ps and the read cycle T=500 ps, the 4~6 taps (4~6t) can be synchronized, and the taps in the range are the smallest taps that can be implemented under the normal performance of the devices in the current chip.

[0146] It can be seen that, referring to Figure 10 , in the tap synchronization manner of the embodiments of the present disclosure, when the tap is 6t, the delay between the read and write of the RX FIFO is 2.5T.

[0147] In contrast, referring to Figure 11 , in the related art, the tap synchronization manner directly according to the read clock of the RX FIFO, if the tap is synchronized to 3 taps (3T), then the delay between the read and write of the RX FIFO is 3.5T.

[0148] Therefore, according to the above manner, the delay of the RX FIFO can be reduced from at least 3.5T to 2.5T, which also plays a role in reducing the delay; and the above manner does not need to set a phase detector (PD) or the like to detect the offset, and can also simplify the structure and working manner of the receiving unit.

[0149] In some embodiments, the method of the embodiments of the present disclosure further includes:

[0150] S103A1, in response to the amount of data stored in the RX FIFO reaching a preset data amount threshold, sending a full signal to the sending unit.

[0151] The data amount threshold is less than the maximum capacity of the RX FIFO, and the full signal is used to control the sending unit to suspend sending the data signal.

[0152] As a manner of the embodiments of the present disclosure, since the receiving unit in the scheme of the embodiments of the present disclosure works according to the write pointer (the pushed write pointer or the synchronized write pointer) generated by itself to determine the read enable of the RX FIFO, the RX FIFO does not have the function of blocking the write, so that the situation that the RX FIFO is full (Full) and continues to have data written may occur.

[0153] For example, referring to Figure 12 , according to the above pushed write pointer manner, if the read clock is fast, the above "case 3-case 2-case 1-case 4" cycle will occur, wherein when the read pointer exceeds the write pointer, the read enable will be naturally closed, and therefore no problem will occur.

[0154] However, referring to Figure 13 , according to the above way of pushing the write pointer, if the read clock is slow, the above "case 4-case 1-case 2-case 3" cycle will occur, where the read enable will still be on when the write pointer is larger than the read pointer, that is, when it is full, causing an error.

[0155] Therefore, when the data stored in the RX FIFO reaches the data threshold, that is, "half full", the sending unit can be notified of the "full signal" through the sideband message of the UCIe protocol, etc., to suspend the sending of the data signal for a period of time, such as 2~4t, to avoid the RX FIFO being full (Full).

[0156] For example, the amount of data stored in the RX FIFO can be determined according to the positions of the read pointer and the write pointer, for example, the above Half_Full condition can be set as:

[0157] Half_Full = (sample_wrptr = rdptr+1).

[0158] In some embodiments, the method of the embodiments of the present disclosure further comprises:

[0159] S103B1, in response to the number of write cycles of the RX FIFO continuously receiving the data signal reaching the predetermined cycle number threshold, sending a full signal to the sending unit.

[0160] As another way of the embodiments of the present disclosure, the receiving unit can also send a "full signal" to the sending unit when the number of write cycles of the RX FIFO continuously receiving the data signal reaches the preset cycle number threshold, to notify the sending unit to suspend the sending of the data signal for a period of time, such as 2~4t, to avoid the RX FIFO being full (Full).

[0161] It should be understood that the sending unit can also actively suspend the sending of the data signal when it finds that the number of its continuous sending of the data signal reaches the above cycle number threshold.

[0162] In some embodiments, the method of the embodiments of the present disclosure further comprises:

[0163] S1021, when there is no data signal to be received, no feedforward clock is received from the sending unit.

[0164] S1022, when the time of continuously not receiving the feedforward clock reaches the preset time threshold, the feedforward clock is received from the sending unit, and the write pointer of the RX FIFO is adjusted according to at least the read clock of the RX FIFO.

[0165] In some related technologies, the RX FIFO adopts a constant read and write mode, that is, the read clock and the write clock of the RX FIFO are always on regardless of whether there is data to be transmitted, resulting in high power consumption and failing to meet the requirement of power saving by dynamic gating of the UCIe protocol.

[0166] As one of the embodiments of the present disclosure, when there is no data signal to be sent to the receiving unit, the sending unit can turn off the read clock of the TX FIFO, that is, turn off the feedforward clock of the receiving unit and the write clock of the RX FIFO; and when there is again a data signal to be sent, the sending unit reopens the read clock of the TX FIFO, that is, turns on the feedforward clock of the receiving unit and the write clock of the RX FIFO.

[0167] Therefore, the embodiment of the present disclosure can turn off the read clock of the TX FIFO at part of the time, reduce the power consumption, and meet the requirement of the UCIe protocol.

[0168] However, during the period when the read clock of the TX FIFO is turned off, the local clocks of the sending unit and the receiving unit can actually drift, and if the actual offset caused by the drift during this period is too large, it can directly cause data errors after the read clock of the TX FIFO is restarted.

[0169] For example, for the above 2GHz read clock, the read period is 500ps, and the maximum absolute value of the drift is 250ps, and the minimum unit of the delay of the write clock is 8GHz clock UI = 62.5ps, so if the absolute value of the drift accumulated during the period when the read clock of the TX FIFO is turned off exceeds 250ps-62.5ps = 187.5ps, the sampling edge of the read clock can directly coincide with the boundary of the write pointer, and once the read clock of the TX FIFO is restarted, data errors can be caused.

[0170] Therefore, a "time threshold" can be preset, and the setting of the time threshold should ensure that the drift of the local clock within its range will not cause a large offset, such as not reaching the above 187.5ps; therefore, the time threshold can be set according to the performance of the chip, such as 1ms, 100μs, 10μs, 1μs, etc.

[0171] Further, when the duration without data signal to be sent reaches the above time threshold, that is, the duration of the read clock of the TX FIFO being turned off reaches the time threshold, the sending unit can start the read clock of the TX FIFO and send an analog data signal for detecting the offset, so that the receiving unit can adjust the write pointer of the RX FIFO according to the restarted write clock of the RX FIFO, to avoid the accumulated drift being too large.

[0172] In some embodiments, the receiving unit receives the multiple data signals from the sending unit through multiple RX FIFOs, one of which is a target RX FIFO.

[0173] The adjusted write pointer is determined according to at least the read clock and the write clock of the RX FIFO, and the read enable of the RX FIFO is determined according to the adjusted write pointer (S101), including:

[0174] S101C, the adjusted write pointer is determined according to at least the read clock and the write clock of the target RX FIFO, and the read enable of all the RX FIFOs is determined according to the adjusted write pointer.

[0175] As a way of the embodiments of the present disclosure, there can be multiple RX FIFOs in the receiving unit for receiving data signals, and the read clock and the write clock of these RX FIFOs should be theoretically synchronized, but in practice, there can still be a certain drift, so that the time for reading out the data signals from them also has a certain deviation. Therefore, before actually processing the data signals of these RX FIFOs, the signals read out from each RX FIFO are usually stored in a buffer, so that the data signals from different RX FIFOs are accurately aligned.

[0176] As a way of the embodiments of the present disclosure, one of the multiple RX FIFOs can be pre-set as a target RX FIFO, so that the read enable can be generated according to the write clock and the read clock of the RX FIFO according to the above method, but the read enable is used to control the read operation of all the RX FIFOs, so as to ensure that the read operations of all the RX FIFOs are performed at the same time, that is, to ensure the accurate alignment of the multiple data signals, so that the buffer does not have to be used, further reducing the delay; at the same time, the above method only needs to set the circuit for generating the read enable for the target RX FIFO, and the read enable generated by the circuit can be directly used for the other RX FIFOs, so the product structure can also be simplified.

[0177] In a second aspect, referring to Figure 5 The embodiments of the present disclosure provide a receiving unit, including an RX FIFO, a memory, and a processor; the memory stores a computer program executable by the processor, and the computer program is executed by the processor to implement any one of the data transmission methods of the embodiments of the present disclosure.

[0178] In a third aspect, referring to Figure 6 The embodiments of the present disclosure provide a chip, including:

[0179] a reference clock;

[0180] a sending unit;

[0181] The receiving unit of any one of the embodiments of the present disclosure is implemented.

[0182] In a fourth aspect, referring to Figure 7 The computer readable medium stores a computer program, and the computer program is executed by a processor to implement the method for data transmission of any one of the embodiments of the present disclosure.

[0183] In a fifth aspect, the present disclosure provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the method for data transmission of any one of the embodiments of the present disclosure.

[0184] The processor is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory is a device with data storage capability, including but not limited to a random access memory (RAM), more specifically, SDRAM, DDR, and the like, a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH); the I / O interface, also known as a read-write interface, is connected between the processor and the memory, and can realize information interaction between the memory and the processor, including but not limited to a data bus (Bus) and the like.

[0185] Example 1

[0186] In a fourth aspect, referring to Figures 14 to 17 This example 1 exemplarily introduces a specific method for data transmission of the embodiments of the present disclosure.

[0187] In a fourth aspect, referring to Figure 14 Example 1 is used for transmitting data signals from a sending unit to a receiving unit, wherein the sending unit can belong to a TX die, the receiving unit can belong to a RX die, and an inter-die connection is provided between the sending unit and the receiving unit.

[0188] In a fourth aspect, referring to Figure 14 The sending unit and the receiving unit use the same 100MHz reference clock (ref).

[0189] In the sending unit, the reference clock generates an 8GHz clock through a phase-locked loop (PLL), the 8GHz clock is used as a read clock of a TX FIFO, and is used for processing sequence data (01010101) and transmitting to the receiving unit, as a feedforward clock (FWD CLK) of the receiving unit and a write clock of an RX FIFO. At the same time, the 8GHz clock of the sending unit also generates a 2GHz local clock (LCLK) through a 4 divider (DIV4), and the LCLK is used as a write clock of the TX FIFO.

[0190] In the receiving unit, the reference clock generates a 8GHz clock through a PLL, and then generates a 2GHz LCLK through a 4 divider (DIV4), which is used as the read clock of the RX FIFO.

[0191] The transmitting unit includes a plurality of 8-to-1 data serializers (SERs), each of which is provided with a TX FIFO and connected to the receiving unit through an inter-die connection.

[0192] For example, referring to Figure 14 , the transmitting unit can include:

[0193] SER1 for transmitting an 8-bit data signal (TX data), which is provided with a TX FIFO1 and corresponds to a data channel;

[0194] SER2 for transmitting a feed-forward clock (FWD CLK), which is provided with a TX FIFO2.

[0195] Correspondingly, the receiving unit includes a 1-to-8 data de-serializer (DES), which is provided with an RX FIFO and connected to the TX FIFO of the SER of the receiving unit through an inter-die connection.

[0196] For example, referring to Figure 14 , the receiving unit can include:

[0197] DES1 for receiving a data signal, which is provided with an RX FIFO1.

[0198] Since the FWD CLK signal is a clock signal, the receiving unit can directly receive the signal from the SER2 without setting a corresponding DES.

[0199] Referring to Figure 15 , in the DES of the receiving unit, the serial data input through the RX drv can be sampled at the rising and falling edges of the 8GHz FWD CLK to perform serial-to-parallel conversion (1 to 2), and the converted 2-bit data can be written into the first row of the RX FIFO at positions 0 and 1 at the next rising edge, and then written into the first row of the RX FIFO at positions 2 and 3 at the next rising edge, and so on, until the first row of the RX FIFO is filled with 4 taps of the 8GHz clock, and the next row is continuously written. For example, the depth of the RX FIFO can be 4, and the data read from the RX FIFO can be first entered into a register (reg).

[0200] Referring to Figure 14In the transmitting unit, a small delay line (Deskew) can also be provided for SER1, which is used to make small delay adjustments, such as a delay of about 0.04 UI, which corresponds to about 5 ps for an 8 GHz clock.

[0201] Reference Figure 14 In the receiving unit, a delay matching unit can also be provided for DES1 to compensate for the delay of the RX path.

[0202] Reference Figure 14 In the transmitting unit, a delay loop (DLL) can also be provided, which is used to delay the elapsed clock, that is, to delay FWD CLK to set the eye diagram of the sampled data. Its step can be 1ps, and the total delay can be greater than 1UI (62.5ps).

[0203] Reference Figure 16 The receiving unit also includes a phase detector (PD), which compares its own LCLK with the FWD CLK from the transmitting unit, that is, compares the read clock and write clock of the RX FIFO to determine the offset between them.

[0204] Since the FWD CLK is 8GHz and the receiver unit's LCLK is 2GHz, therefore, refer to... Figure 16 The FWD CLK can be converted into a 2GHz signal by a 4-divider (DIV4) and then compared with the LCLK of the receiving unit in the PD.

[0205] The specific form of PD can be determined according to the required offset accuracy. For example, for a 2GHz clock, a reference can be used. Figure 17 The 64-level phase detector corresponds to an offset accuracy of T / 64, which is 500ps / 64.

[0206] Alternatively, as another embodiment of this disclosure, PD may not be set, but rather 2GHz LCLK may be sampled at the rising or falling edge of 8GHz FWD CLK, and the offset may be determined based on the sampled level; it should be understood that the offset determined in this way has low accuracy, which is T / 4.

[0207] Furthermore, the 2GHz LCLK can be sampled on both the rising and falling edges of the 8GHz FWD CLK to achieve an offset accuracy of T / 8.

[0208] Reference Figure 16, the receiving unit has two RX FIFOs, which are respectively used for receiving two data signals (datalane1, data lane2), and the upper RX FIFO is a target RX FIFO; and the FWD CLK is used as a write pointer of all RX FIFOs to control the write operation of all RX FIFOs.

[0209] With reference to Figure 16 In the target RX FIFO, the FWD CLK is further sent to a 4 divider (DIV4) to generate a 2GHz signal, and the 2GHz signal is sent to a gen wrptr module to generate a 2GHz write pointer for delay. The gen wrptr module can increase the write pointer by 1 after writing 1 row of 8-bit data, and the initial value of the write pointer is set to 4, that is, max. The delay module delays the write pointer of the gen wrptr module by 0-7 UI (62.5ps) according to the offset detected by the PD to generate a sample write pointer signal and input the wrptr sample module. The wrptr sample module samples the sample write pointer signal at the sampling edge of the read clock according to the 2GHz local clock to generate a read enable (rd_en), that is, the read enable is determined according to the pushed write pointer, and the read enable is used to control the read operation of all RX FIFOs.

[0210] In the target RX FIFO, the FWD CLK is further sent to a 4 divider (DIV4) to generate a 2GHz signal, and the 2GHz signal is sent to a gen wrptr module to generate a 2GHz write pointer for delay. The gen wrptr module can increase the write pointer by 1 after writing 1 row of 8-bit data, and the initial value of the write pointer is set to 4, that is, max. The delay module delays the write pointer of the gen wrptr module by 0-7 UI (62.5ps) according to the offset detected by the PD to generate a sample write pointer signal and input the wrptr sample module. The wrptr sample module samples the sample write pointer signal at the sampling edge of the read clock according to the 2GHz local clock to generate a read enable (rd_en), that is, the read enable is determined according to the pushed write pointer, and the read enable is used to control the read operation of all RX FIFOs.

[0211] Therefore, the receiving module of the example 1 can realize the following processes: detecting the offset between the write clock and the read clock of the RX FIFO; generating a sample write pointer signal according to the offset and the write clock of the RX FIFO; sampling the sample write pointer signal at the sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO according to the sampling result.

[0212] It should be understood that, in the above target RX FIFO, the wrptr sample module can compare the read pointer and the write pointer, so as to send a "full signal" to the sending unit through the sideband message of the UCIe protocol when the RX FIFO is about to be full (Half_Full).

[0213] With reference to Figure 16The target RX FIFO can further include a counting (CNT) module for cyclic counting 0~3 of the 8GHz FWDCLK written, that is, counting corresponding to a 2GHz period. The counting of the CNT module can be used to ensure that the reset, clock-off and other operations are performed at the edge of the corresponding 2GHz local clock, and can be used to control the timing at which the delay module starts to delay.

[0214] Example 2

[0215] With reference to Figure 18 , Figure 19 , this example 2 exemplarily introduces another specific data transmission method of the embodiments of the present disclosure.

[0216] With reference to Figure 18 , the system architecture of this example 2 is similar to that of example 1. Figure 14

[0217] The difference is that, with reference to Figure 18 , in this example 2, the receiving unit directly inputs the 8GHz clock generated by the PLL as the local high-frequency clock into the DES.

[0218] Further, with reference to Figure 19 , the structure of the receiving unit of this example 2 is similar to that of example 1. Figure 16

[0219] The difference is that, with reference to Figure 19 , the target RX FIFO of this example 2 does not have the above PD and delay modules, and can also not have the CNT module, but has a synchronization (sync) module for performing beat synchronization; and the above 8GHz local high-frequency clock directly enters the sync module, for synchronizing the write pointer generated by the FWD CLK successively through the DIV4 and gen wrptr modules to the read clock domain of the RX FIFO, and then sending the synchronized signal into the wrptr sample module to generate the read enable of all RXFIFOs.

[0220] Therefore, the receiving module of this example 2 can implement the following processes: generating a local high-frequency clock; beat-synchronizing the write pointer of the RX FIFO to the read clock domain according to the local high-frequency clock; sampling the synchronized write pointer of the RX FIFO at the sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO according to the sampling result.

[0221] Those of ordinary skill in the art can understand that all or some of the functional modules / units in the above disclosed steps, systems and devices can be implemented as software, firmware, hardware and appropriate combinations thereof.

[0222] ​​In hardware implementations, the division of functionality between the functional modules / units referred to in the above description does not necessarily correspond to a division of physical components; for example, one physical component can have multiple functionalities, or one functionality or step can be performed by several physical components in cooperation.

[0223] Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application- specific integrated circuit. Such software can be distributed on computer readable media, which can comprise any medium or mechanism for storing or transmitting information in a form readable by a computer, including computer storage, medium, and communications media. In embodiments of the present disclosure, computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, which can be accessed by a computer and includes any other media that can be used to store and access desired and / or expected information. In embodiments of the present disclosure, communications media typically embody computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims

1. A method for data transmission, characterized in that, For a receiving unit, the receiving unit and the transmitting unit are packaged in the same chip and connected via a bare die interconnect. The receiving unit receives data signals from the transmitting unit through a receiver-side first-in-first-out (FIFO) buffer (RX FIFO). The local clock of the transmitting unit and the local clock of the receiving unit are generated based on the same reference clock. The read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is a feedforward clock generated based on the local clock of the transmitting unit. The read cycle of the RX FIFO is greater than the write cycle. The method includes: The adjusted write pointer is determined based at least on the read clock and write clock of the RX FIFO, and the read enable of the RX FIFO is determined based on the adjusted write pointer; in, The step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: detecting the offset between the write clock and the read clock of the RX FIFO; generating a sampled write pointer signal based on the offset and the write clock of the RX FIFO; sampling the sampled write pointer signal at the sampling edge of the read clock of the RX FIFO; and determining the read enable of the RX FIFO based on the sampling result. or, The method further includes, in response to the RX FIFO reset, setting the write pointer of the RX FIFO to the maximum position and the read pointer of the RX FIFO to the minimum position; and, the step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: generating a local high-frequency clock; synchronizing the write pointer of the RX FIFO to the read clock domain of the RX FIFO by timing according to the local high-frequency clock; sampling the synchronized write pointer of the RX FIFO on the sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO based on the sampling result; wherein, the period of the local high-frequency clock is equal to the write period of the RX FIFO, the total period of the timing high-frequency clock is less than twice the read period of the RX FIFO, and the write pointer of the RX FIFO is in Gray code form.

2. The method according to claim 1, characterized in that, The sampling edge of the read clock of the RX FIFO is located in a preset central interval of the write pointer range of the sampled write pointer signal.

3. The method according to claim 2, characterized in that, The step of generating a sampling write pointer signal based on the offset and the write clock of the RX FIFO includes: Based on the offset, a sampled write pointer signal is generated that is delayed relative to the write pointer of the RX FIFO; wherein the delay of the sampled write pointer signal relative to the write pointer of the RX FIFO is nt / 2, t is the write cycle of the RX FIFO, and n is an integer greater than or equal to 0 and less than a multiple of 2 cycles, wherein the multiple of cycles is the ratio of the read cycle to the write cycle of the RX FIFO.

4. The method according to claim 1, characterized in that, The cycle multiple is 4, whereby the cycle multiple is the ratio of the read cycle to the write cycle of the RX FIFO; The total cycle of the high-frequency clock that beats the clock is 4 to 6 cycles.

5. The method according to claim 1, characterized in that, Also includes: When there is no data signal to be received, the feedforward clock cannot be received from the transmitting unit; When the time during which the feedforward clock is not received reaches a preset time threshold, the feedforward clock is received from the transmitting unit, and the write pointer of the RX FIFO is adjusted at least according to the read clock of the RX FIFO.

6. The method according to claim 1, characterized in that, Also includes: In response to the data volume stored in the RX FIFO reaching a preset data volume threshold, a near-full signal is sent to the transmitting unit; the data volume threshold is less than the maximum capacity of the RX FIFO, and the near-full signal is used to control the transmitting unit to pause the transmission of the data signal.

7. The method according to claim 1, characterized in that, Also includes: In response to the number of write cycles of the RX FIFO continuously receiving the data signal reaching a predetermined number of cycles threshold, a near-full signal is sent to the transmitting unit; the near-full signal is used to control the transmitting unit to pause the transmission of the data signal.

8. The method according to any one of claims 1 to 7, characterized in that, The receiving unit receives multiple data signals from the transmitting unit through multiple RX FIFOs, one of which is the target RX FIFO; The step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: determining the adjusted write pointer based at least on the read clock and write clock of the target RX FIFO, and determining the read enable of all the RX FIFOs based on the adjusted write pointer.

9. A receiving unit, characterized in that, It includes an RX FIFO, a memory, and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the data transmission method according to any one of claims 1 to 8.

10. A chip, characterized in that, include: Reference clock; Transmitting unit; The receiving unit as described in claim 9.

11. A computer-readable medium, characterized in that, It stores a computer program that, when executed by a processor, implements the data transmission method according to any one of claims 1 to 8.

12. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the data transmission method according to any one of claims 1 to 8.

Images