Data transmission device and data transmission method thereof

Abstract

The invention relates to a data transmission device and a data transmission method thereof.The device comprises a first board card and a second board card, and under the condition that the first board card and the second board card are each provided with a plurality of medium-low-speed bus interfaces, a medium-high-speed differential circuit is arranged between the first board card and the second board card; when a bus interface of a first board card receives a medium-low speed bus signal, the medium-low speed bus signal can be analyzed based on a first transceiver module to obtain to-be-transmitted data, then a piece of to-be-transmitted data is selected as first data, differential coding is performed on the first data to obtain a differential coding signal, and the differential coding signal is transmitted to the first board card. And then the differential coding signal is sent to a second board card at the other end through a medium-high speed differential circuit, and then the second board card sends the data to an external device. According to the device, the middle-high speed differential circuit is adopted between the two board cards to realize quick connection, so that the number of connecting lines between the two board cards is reduced, and the anti-interference capability and the transmission distance of communication between the two board cards are improved.

Description

Technical Field

[0001] This application relates to the field of data transmission technology between circuit boards, and in particular to a data transmission device and a data transmission method thereof. Background Technology

[0002] Servers, computing boards, storage boards, and their management devices (BMCs) often have various low-to-medium speed communication interfaces such as UART, CAN, IIC, SPI, QSPI, and GPIO used for transmitting control and management signals. Due to the large variety and number of these low-to-medium speed interfaces, and their electrical and protocol characteristics, they often have drawbacks such as short transmission distance and poor anti-interference capabilities. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] The main objective of this disclosure is to provide a data transmission device and method that can reduce the number of connection lines between two boards and improve the anti-interference capability and transmission distance of communication between the two boards.

[0005] A first aspect of this application provides a data transmission device, the device including a first board, a second board, and a medium-to-high-speed differential circuit located between the first board and the second board; The first board includes: Multiple first bus interfaces, each of which has a corresponding bus interface protocol, and the first bus interface is used to receive a first medium-low speed bus signal; Multiple first transceiver modules, each of which is connected to a corresponding first bus interface, and the first transceiver module is used to parse the data to be transmitted from the first medium-low speed bus signal; A first differential signal transceiver module is connected to the plurality of first transceiver modules. The first differential signal transceiver module is used to differentially encode the first data to obtain a differentially encoded signal; the first data is one of the data to be transmitted. The first medium-high speed differential interface is connected to the first differential signal transmission module. The first medium-high speed differential interface is used to send the differential encoded signal to the second board based on the medium-high speed differential circuit. The second board includes: The second high-speed differential interface is used to receive the differential coded signal; The second differential signal transceiver module is connected to the second medium-high speed differential interface. The second differential signal transceiver module is used to perform differential decoding on the differential coded signal to obtain the second data. Multiple second transceiver modules are connected to the second differential signal transceiver module, and the second transceiver module is used to convert the second data into a second medium-low speed bus signal; Multiple second bus interfaces are provided, each second bus interface is connected to a corresponding second transceiver module, each second bus interface has the same bus interface protocol as the corresponding first bus interface, and the second bus interface is used to send the second medium-low speed bus signal to an external device.

[0006] This embodiment provides a data transmission device, which has at least the following advantages: This device includes a first board and a second board. Both the first and second boards have multiple low-to-medium speed bus interfaces. A high-speed differential circuit is installed between the two boards. When the first board receives a low-to-medium speed bus signal, it can parse the signal to obtain the data to be transmitted. Then, it selects one data segment as the first data segment, performs differential encoding on it to obtain a differential encoded signal, and sends this signal through the high-speed differential circuit to the second board. The second board then processes the signal in reverse until it is transmitted to an external device. This device enables rapid connection between the various low-to-medium speed communication interfaces of the two boards using a high-speed differential circuit, reducing the number of connection lines between the two boards and improving the anti-interference capability and transmission distance of the communication between them.

[0007] In some implementations, the first board further includes a plurality of buffers, each of which is connected to a corresponding first transceiver module and to the first differential signal transceiver module; The buffer is used to buffer the data to be transmitted corresponding to the first transceiver module, generate the in-place signal of the data to be transmitted, and send the in-place signal to the first differential signal transceiver module.

[0008] In some implementations, the first board further includes an arbitrator connected between the plurality of buffers and the first differential signal transceiver module; The arbitrator is configured to select the data to be transmitted as the first data when there is only one in place signal for the data to be transmitted; and to determine the priority of the first bus interface corresponding to at least two data to be transmitted when there are at least two in place signals for the data to be transmitted, and select the data to be transmitted with the highest priority as the first data; and to determine the arrival timestamp of at least two data to be transmitted when there are at least two in place signals for the data to be transmitted and the first bus interface corresponding to at least two data to be transmitted has the same priority, and select the data to be transmitted with the earliest arrival timestamp as the first data.

[0009] In some embodiments, the first board further includes a status acquisition module and a configuration interface. The status acquisition module is connected to the plurality of first bus interfaces, the plurality of first transceiver modules, the first differential signal transceiver module, the first medium-high speed differential interface, the plurality of buffers, and the arbitrator. The configuration interface is connected to the status acquisition module. The configuration interface is used to receive configuration information; The status acquisition module is used to acquire status information of the plurality of first bus interfaces, the plurality of first transceiver modules, the first differential signal transceiver module, the first medium-high speed differential interface, the plurality of buffers and the arbitrator, and to configure the configuration information into the plurality of first bus interfaces, the plurality of first transceiver modules, the first differential signal transceiver module, the first medium-high speed differential interface, the plurality of buffers and the arbitrator.

[0010] In some implementations, the medium-to-high-speed differential circuit is a low-voltage differential circuit (LVDS).

[0011] A second aspect of this application provides a data transmission method for a first board having multiple first bus interfaces, the method comprising: Select a first data from at least one data to be sent; the data to be sent is a first medium-low speed bus signal received based on the first bus interface; The first data is differentially encoded to obtain a differentially encoded signal; Based on the medium-to-high-speed differential circuit associated with the differential encoding, the differential encoded signal is sent to the second board, so that the second board performs differential decoding on the differential encoded signal corresponding to the differential encoding to obtain the second data, and the second board sends the second data to an external device through the second bus interface corresponding to the first bus interface.

[0012] In some implementations, before selecting the first data from at least one pending data, the method further includes: Based on the first bus interface, a first medium-low speed bus signal sent by an external device is received; Based on the bus interface protocol corresponding to the first bus interface, the data to be transmitted is parsed from the first medium-low speed bus signal; The data to be sent is cached, and an in-place signal for the data to be sent is generated.

[0013] In some implementations, selecting the first data from at least one piece of pending data includes: If only one in-situ signal of the data to be sent exists, the data to be sent is selected as the first data; If there are at least two in place signals for the data to be transmitted, determine the priority of the first bus interface corresponding to the at least two data to be transmitted, and select the data to be transmitted with the highest priority as the first data.

[0014] In some implementations, selecting the first data from at least one piece of pending data further includes: When there are at least two arrival signals for the data to be sent, and the first bus interfaces corresponding to the at least two data to be sent have the same priority, the arrival timestamps of the at least two data to be sent are determined, and the data to be sent with the earliest arrival timestamp is selected as the first data.

[0015] In some implementations, the medium-to-high-speed differential circuit is a low-voltage differential circuit (LVDS).

[0016] This embodiment provides a data transmission method, which has at least the following advantages: This method, when both the first and second boards have multiple low-to-medium speed bus interfaces, sets up a high-speed differential circuit between them. When the first board receives a low-to-medium speed bus signal, it parses the signal to obtain the data to be transmitted. Then, it selects one data segment as the first data segment, differentially encodes it to obtain a differentially encoded signal, and sends this signal through the high-speed differential circuit to the second board. The second board then reverses the process until the data is sent to an external device. This method enables rapid connection between the various low-to-medium speed communication interfaces of the two boards using a high-speed differential circuit, reducing the number of connection lines between the two boards and improving the anti-interference capability and transmission distance of the communication between them.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the data transmission method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the first board provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the second board provided in the embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] In the description of this application, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0022] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or function in a specific orientation, and therefore should not be construed as a limitation of this application.

[0023] like Figure 2 and Figure 3 One embodiment of this application provides a data transmission device, which includes a first board, a second board, and a medium-to-high-speed differential circuit located between the first board and the second board; wherein the first board and the second board can be devices such as computing boards and storage boards, and are not specifically limited here.

[0024] The first board includes: Multiple first bus interfaces, each with a corresponding bus interface protocol, are used to receive first medium-low speed bus signals.

[0025] In this embodiment, the first bus interface is a low-to-medium speed bus interface, including but not limited to UART, CAN, IIC, SPI, QSPI, GPIO, sGPIO, etc. The first bus interface can receive data from external devices, and is referred to here as the first low-to-medium speed bus signal. The external device here can be the first server.

[0026] Multiple first transceiver modules are provided, each of which is connected to a corresponding first bus interface. The first transceiver module is used to parse the data to be transmitted from the first medium-low speed bus signal.

[0027] In this embodiment, each first transceiver module corresponds to a first bus interface. When the first bus interface receives a first medium-low speed bus signal, the first transceiver module decodes the signal. Alternatively, the first transceiver module can encode the data and then pass it to the corresponding first bus interface for transmission.

[0028] The first differential signal transceiver module is connected to multiple first transceiver modules. The first differential signal transceiver module is used to differentially encode the first data to obtain a differentially encoded signal; the first data is one of the data to be transmitted.

[0029] In this embodiment, the first differential signal transceiver module encodes only one data to be transmitted at the same timestamp, and the first medium-high speed differential interface transmits only one data to be transmitted at a time. This one data to be transmitted is referred to as the first data. The selection process of the first data is detailed in subsequent embodiments.

[0030] In this embodiment, the first differential signal transceiver module performs differential encoding on the first data according to the encoding protocol corresponding to the medium- and high-speed differential circuit to obtain a differential encoded signal, and then sends the differential encoded signal to the first medium- and high-speed differential interface.

[0031] The first medium-high speed differential interface is connected to the first differential signal transmission module. The first medium-high speed differential interface is used to send differential encoded signals to the second board based on the medium-high speed differential circuit.

[0032] In this embodiment, the first medium-high speed differential interface sends the differential encoded signal to the second board through the medium-high speed differential circuit.

[0033] It should be noted that the medium-to-high-speed differential circuit can be an LVDS circuit or other medium-to-high-speed differential circuits; no specific limitation is made here.

[0034] It should be noted that the first high-speed differential interface can also receive the corresponding differential encoded signal from the second board, and then the first differential signal transceiver module decodes the differential encoded signal.

[0035] The second board includes: The second high-speed differential interface is used to receive differentially coded signals; The second differential signal transceiver module is connected to the second medium-high speed differential interface. The second differential signal transceiver module is used to perform differential decoding on the differential coded signal to obtain the second data. Multiple second transceiver modules are connected to a second differential signal transceiver module. The second transceiver modules are used to convert second data into a second medium-low speed bus signal. Multiple second bus interfaces are provided, each second bus interface is connected to a corresponding second transceiver module, and each second bus interface has the same bus interface protocol as the corresponding first bus interface. The second bus interface is used to send the second medium-low speed bus signal to an external device.

[0036] It should be noted that the structure of the second board is exactly the same as that of the first board. The second board sends data to an external device, which can be another second server that is different from the first server.

[0037] This device includes a first board and a second board. Both the first and second boards have multiple low-to-medium speed bus interfaces. A medium-to-high speed differential circuit is installed between the two boards. When the first board receives a low-to-medium speed bus signal, it can parse the signal using a first transceiver module to obtain the data to be transmitted. Then, it selects one data segment as the first data segment, performs differential encoding on it to obtain a differential encoded signal, and sends this signal through the medium-to-high speed differential circuit to the second board. The second board then transmits the data to an external device using the same structure as the first board. This device enables rapid connection between the various low-to-medium speed communication interfaces of the two boards using a medium-to-high speed differential circuit, reducing the number of connection lines between the two boards and improving the anti-interference capability and transmission distance of the communication between them.

[0038] In some embodiments, the first board further includes a plurality of buffers, each buffer being connected to a corresponding first transceiver module and a first differential signal transceiver module; The buffer is used to buffer the data to be transmitted corresponding to the first transceiver module, and to generate the data to be transmitted and the data to be transmitted to the first differential signal transceiver module.

[0039] In this embodiment, since the first transceiver module can continuously receive the first low-speed bus signal and parse out the data to be transmitted; there are multiple first transceiver modules, but only one first high-speed differential interface, a buffer is added to buffer the data to be transmitted parsed by one first transceiver module. If the buffer receives the data to be transmitted, it generates a ready signal for the data to be transmitted and sends the ready signal to the first differential signal transceiver module, that is, informing the first differential signal transceiver module that the data to be transmitted is ready and waiting for the encoding program of the first differential signal transceiver module.

[0040] In some embodiments, the first board further includes an arbitrator connected between a plurality of buffers and a first differential signal transceiver module; The arbitrator is used to select the data to be transmitted as the first data when there is only one data to be transmitted in place signal, and to determine the priority of the first bus interface corresponding to at least two data to be transmitted when there are at least two data to be transmitted in place signals, and to select the data to be transmitted with the highest priority as the first data, and to determine the arrival timestamp of at least two data to be transmitted when there are at least two data to be transmitted in place signals and the first bus interface corresponding to at least two data to be transmitted has the same priority, and to select the data to be transmitted with the earliest arrival timestamp as the first data.

[0041] In this embodiment, the arbitrator adopts a two-level arbitration mechanism. The first level is priority arbitration, where the priorities of multiple first bus interfaces can be configured in advance. The second level is first-come-first-served arbitration, where when the data to be sent received by two or more first bus interfaces have the same priority, the data that arrives at the arbitrator first is sent first. If they arrive at the same time, the data that has been waiting the longest is sent first.

[0042] In some embodiments, the first board further includes a status acquisition module and a configuration interface. The status acquisition module is connected to multiple first bus interfaces, multiple first transceiver modules, a first differential signal transceiver module, a first medium-high speed differential interface, multiple buffers and an arbitrator. The configuration interface is connected to the status acquisition module. The configuration interface is used to receive configuration information; The status acquisition module is used to acquire status information of multiple first bus interfaces, multiple first transceiver modules, first differential signal transceiver modules, first medium-high speed differential interfaces, multiple buffers and arbitrators, and to configure configuration information into multiple first bus interfaces, multiple first transceiver modules, first differential signal transceiver modules, first medium-high speed differential interfaces, multiple buffers and arbitrators.

[0043] In this embodiment, the configuration interface and status acquisition module are used to configure the functions of each internal module and collect its status, such as the specific protocol configuration of each of the multiple first transceiver modules (e.g., UART baud rate, SPI rate, etc.), the depth of the buffer, the priority configuration of the arbitrator, and the rate configuration of the first differential signal transceiver module. In some embodiments, the medium-speed differential circuit is a low-voltage differential circuit (LVDS).

[0044] Low-Voltage Differential Signaling (LVDS) is a high-speed digital interface technology with low power consumption and good common-mode noise capability, which can improve the reliability of communication between boards.

[0045] like Figure 1 Based on the above device example, a data transmission method is proposed here for a first board having multiple first bus interfaces. The method includes: In step S120, the first board selects the first data from at least one data to be transmitted; the data to be transmitted is a first medium-low speed bus signal received based on the first bus interface. Step S140: The first board performs differential encoding on the first data to obtain a differential encoded signal; In step S160, the first board sends the differential encoding signal to the second board based on the medium-high speed differential circuit associated with differential encoding, so that the second board performs differential decoding on the differential encoding signal corresponding to differential encoding to obtain the second data, and sends the second data to the external device through the second bus interface corresponding to the first bus interface.

[0046] Furthermore, before selecting the first data from at least one piece of data to be sent in step S120, the method further includes steps S1110 to S1130: Step S1110: Receive a first medium-low speed bus signal sent by an external device based on the first bus interface.

[0047] Step S1120: Based on the bus interface protocol corresponding to the first bus interface, the data to be transmitted is parsed from the first medium-low speed bus signal.

[0048] Step S1130: Buffer the data to be sent and generate the in-place signal of the data to be sent.

[0049] Furthermore, step S120, which involves selecting the first data from at least one piece of data to be sent, includes the following steps S1210 and S1220: Step S1210: If there is only one in-place signal for data to be sent, select the data to be sent as the first data.

[0050] Step S1220: In the case of at least two data to be transmitted in place signals, determine the priority of the first bus interface corresponding to the at least two data to be transmitted, and select the data to be transmitted with the highest priority as the first data.

[0051] Furthermore, step S120, which involves selecting the first data from at least one piece of data to be sent, also includes step S1230: Step S1230: When there are at least two data in place signals and the first bus interfaces corresponding to at least two data to be sent have the same priority, determine the arrival timestamps of at least two data to be sent and select the data to be sent with the earliest arrival timestamp as the first data.

[0052] Furthermore, the medium-to-high speed differential circuit is a low-voltage differential circuit (LVDS).

[0053] For ease of understanding, such as Figure 2 and Figure 3 This application provides an embodiment of a data transmission apparatus, the apparatus comprising: 1. The first circuit board, which includes; (1) n first bus interfaces (interface 1, interface 2, ..., interface n, where n is a positive integer, the same below); (2) n first transceiver modules; (3) n buffers; (4) One arbitrator; (5) One first differential signal transceiver module; (6) One first medium-high speed differential interface (7) One configuration interface; (8) One status collection module; 2. The second board has the same structure as the first board. It includes: (1) n second bus interfaces (interface 1', interface 2', ..., interface n', where n is a positive integer, the same below); (2) n second transceiver modules; (3) n buffers; (4) One arbitrator; (5) One second differential signal transceiver module; (6) One second medium-high speed differential interface; (7) One configuration interface; (8) One status collection module; 3. Medium- and high-speed differential circuit (LVDS).

[0054] Taking the first board as an example: The first bus interface of the first board usually uses a medium- or low-speed bus, including but not limited to UART, CAN, IIC, SPI, QSPI, GPIO, sGPIO, etc.

[0055] The second bus interface of the second board has the same function as the first bus interface of the first board. For example, if interface 1 of the first board is connected to a UART, then interface 1 of the second board should also be connected to a UART.

[0056] The first transceiver module of the first board decodes and encodes the signals received by the corresponding first bus interface. Its bus protocol type should be the same as the bus protocol type connected to the corresponding first bus interface. For example, if interface 1 of the first board is connected to UART, then the protocol type of the first transceiver module 1 is also UART transceiver protocol. The same applies to the second board.

[0057] The buffer on the first board implements the reception and buffering management of the data to be transmitted by the first transceiver module. The buffer can be a FIFO, RAM, Flash, DDR, etc. The buffer can realize the storage circuit, device, or equipment for fast data writing and reading; the second board is the same.

[0058] The arbitrator on the first board manages the arbitration of data transmission from n buffers, ensuring that the data to be transmitted from the n first low-speed bus signals of the first bus interface can be transmitted via time-division multiplexing using LVDS differential lines. The arbitrator employs a two-level arbitration mechanism: the first level is priority arbitration, where the priority of the n buses can be configured through the configuration interface; the second level is first-come, first-served arbitration, meaning that when two or more data transmissions have the same priority, the data arriving at the arbitrator first is transmitted first; if they arrive simultaneously, the one with the longest waiting time is transmitted first. Simultaneously, the arbitrator adds a channel number to the data transmitted from each channel and sends it to the first differential signal transceiver module, then sends data to the designated buffer based on the channel number in the data sent from the first differential signal transceiver module to the arbitrator.

[0059] The first differential signal transceiver module performs differential encoding on the data sent by the arbitrator and decodes the differential signal; the rate of the differential signal can be configured through the configuration interface.

[0060] The first differential signal transceiver module of the first board, the second differential signal transceiver module of the second board, and the medium- and high-speed differential circuit realize the connection between the first board and the second board.

[0061] The configuration interface is used to configure the functions and collect the status of each internal module, including: the specific protocol configuration of each of the n first transceiver modules (such as UART baud rate, SPI rate, etc.), the depth of the n buffers, the arbiter priority configuration, the differential signal transceiver module rate configuration, etc., and reading the configuration of each of the above modules.

[0062] The following provides a data transmission method corresponding to the device in this embodiment: In step S210, after receiving the first low-speed bus signal sent by an external device (such as a server) from some or all of the n groups of first bus interfaces of the first board, they send the signal to their respective first transceiver modules through their respective interfaces.

[0063] In step S220, the first transceiver module of the first board parses the corresponding data to be transmitted according to the protocol corresponding to its first bus interface, and sends the data to be transmitted to its respective buffer.

[0064] In step S230, after receiving the data to be sent, each of the buffers on the first board sends a data arrival signal to the arbitrator.

[0065] In step S240, after the arbitrator of the first board receives the in-place signals of several data to be transmitted, it obtains the transmission order of the data to be transmitted through two levels of arbitration. Then, according to the order, it adds the interface channel number to several data to be transmitted and sends them to the first differential signal transceiver module in sequence. It should be noted that only one data to be transmitted can be sent at the same timestamp.

[0066] In step S250, after the first differential signal transceiver module of the first board receives the data to be transmitted from the arbitrator as the first data, it encodes the first data into a corresponding differential coded signal according to the preset signal encoding setting of the first data, and sends the differential coded signal to the second differential signal transceiver module of the second board through the LVDS line.

[0067] In step S260, after the second differential signal transceiver module of the second board receives the differential coded signal sent by the LVDS line, it decodes the differential coded signal into corresponding second data according to the preset decoding method, and sends the second data to the arbitrator of the second board.

[0068] In step S270, after the arbitrator of the second board receives the second data, it sends the second data to the corresponding buffer according to the interface channel number.

[0069] In step S280, after the second transceiver module of the second board receives the second data from the buffer, it encodes the signal to its respective second bus interface according to the corresponding bus interface protocol and sends it to the outside (such as a server) through its respective second bus interface. The data transmission device provided in this embodiment has at least the following beneficial effects: (1) Bus interfaces can be flexibly added or reserved as needed with minimal additional hardware wiring. Communication connection or disconnection between the first board and the corresponding interface of the second board can be completed simply by configuring the interface. (2) By connecting n medium and low speed interfaces through a medium and high speed LVDS link in a time-division multiplexing manner, the number of connection lines is reduced and the hardware complexity is reduced; (3) Enhanced anti-interference capability and increased transmission distance. By converting the single-ended level of various medium and low speed interfaces and medium and low speed communication protocols into medium and high speed LVDS connections, and utilizing the characteristics of LVDS links, the anti-interference capability and transmission distance of communication are improved.

[0070] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0071] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0072] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A data transmission device, characterized in that, The device includes a first board, a second board, and a medium-to-high-speed differential circuit located between the first board and the second board; The first board includes: Multiple first bus interfaces, each of which has a corresponding bus interface protocol, and the first bus interface is used to receive a first medium-low speed bus signal; Multiple first transceiver modules, each of which is connected to a corresponding first bus interface, and the first transceiver module is used to parse the data to be transmitted from the first medium-low speed bus signal; A first differential signal transceiver module is connected to the plurality of first transceiver modules. The first differential signal transceiver module is used to differentially encode the first data to obtain a differentially encoded signal; the first data is one of the data to be transmitted. The first medium-high speed differential interface is connected to the first differential signal transmission module. The first medium-high speed differential interface is used to send the differential encoded signal to the second board based on the medium-high speed differential circuit. The second board includes: The second high-speed differential interface is used to receive the differential coded signal; The second differential signal transceiver module is connected to the second medium-high speed differential interface. The second differential signal transceiver module is used to perform differential decoding on the differential coded signal to obtain the second data. Multiple second transceiver modules are connected to the second differential signal transceiver module, and the second transceiver module is used to convert the second data into a second medium-low speed bus signal; Multiple second bus interfaces are provided, each second bus interface is connected to a corresponding second transceiver module, each second bus interface has the same bus interface protocol as the corresponding first bus interface, and the second bus interface is used to send the second medium-low speed bus signal to an external device.

2. The data transmission device according to claim 1, characterized in that, The first board also includes multiple buffers, each of which is connected to a corresponding first transceiver module and the first differential signal transceiver module; The buffer is used to buffer the data to be transmitted corresponding to the first transceiver module, generate the in-place signal of the data to be transmitted, and send the in-place signal to the first differential signal transceiver module.

3. The data transmission device according to claim 2, characterized in that, The first board also includes an arbitrator connected between the plurality of buffers and the first differential signal transceiver module; The arbitrator is configured to select the data to be transmitted as the first data when there is only one in place signal for the data to be transmitted; and to determine the priority of the first bus interface corresponding to at least two data to be transmitted when there are at least two in place signals for the data to be transmitted, and select the data to be transmitted with the highest priority as the first data; and to determine the arrival timestamp of at least two data to be transmitted when there are at least two in place signals for the data to be transmitted and the first bus interface corresponding to at least two data to be transmitted has the same priority, and select the data to be transmitted with the earliest arrival timestamp as the first data.

4. The data transmission device according to claim 3, characterized in that, The first board also includes a status acquisition module and a configuration interface. The status acquisition module is connected to the plurality of first bus interfaces, the plurality of first transceiver modules, the first differential signal transceiver module, the first medium-high speed differential interface, the plurality of buffers and the arbitrator. The configuration interface is connected to the status acquisition module. The configuration interface is used to receive configuration information; The status acquisition module is used to acquire status information of the plurality of first bus interfaces, the plurality of first transceiver modules, the first differential signal transceiver module, the first medium-high speed differential interface, the plurality of buffers and the arbitrator, and to configure the configuration information into the plurality of first bus interfaces, the plurality of first transceiver modules, the first differential signal transceiver module, the first medium-high speed differential interface, the plurality of buffers and the arbitrator.

5. The data transmission device according to claim 1, characterized in that, The medium-to-high speed differential circuit is a low-voltage differential circuit (LVDS).

6. A data transmission method, characterized in that, For a first board having multiple first bus interfaces, the method includes: Select a first data from at least one data to be sent; the data to be sent is a first medium-low speed bus signal received based on the first bus interface; The first data is differentially encoded to obtain a differentially encoded signal; Based on the medium-to-high-speed differential circuit associated with the differential encoding, the differential encoded signal is sent to the second board, so that the second board performs differential decoding on the differential encoded signal corresponding to the differential encoding to obtain the second data, and the second board sends the second data to an external device through the second bus interface corresponding to the first bus interface.

7. The data transmission method according to claim 6, characterized in that, Before selecting the first data from at least one pending data, the method further includes: Based on the first bus interface, a first medium-low speed bus signal sent by an external device is received; Based on the bus interface protocol corresponding to the first bus interface, the data to be transmitted is parsed from the first medium-low speed bus signal; The data to be sent is cached, and an in-place signal for the data to be sent is generated.

8. The data transmission method according to claim 7, characterized in that, The step of selecting the first data from at least one pending data includes: If only one in-situ signal of the data to be sent exists, the data to be sent is selected as the first data; If there are at least two in place signals for the data to be transmitted, determine the priority of the first bus interface corresponding to the at least two data to be transmitted, and select the data to be transmitted with the highest priority as the first data.

9. The data transmission method according to claim 8, characterized in that, The step of selecting the first data from at least one pending data also includes: When there are at least two arrival signals for the data to be sent, and the first bus interfaces corresponding to the at least two data to be sent have the same priority, the arrival timestamps of the at least two data to be sent are determined, and the data to be sent with the earliest arrival timestamp is selected as the first data.

10. The data transmission method according to claim 6, characterized in that, The medium-to-high speed differential circuit is a low-voltage differential circuit (LVDS).

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