A dual-channel radio frequency low noise amplifier

Abstract

The application relates to the field of radio frequency integrated circuits, in particular to a double-channel radio frequency low noise amplifier, which comprises a double-channel T / R switch, an LNA signal path, a controllable tuning circuit and an overshoot optimization bias circuit. The double-channel T / R switch comprises a depletion mode pHEMT tube M1, a depletion mode pHEMT tube M2, a depletion mode pHEMT tube M3 and a depletion mode pHEMT tube M4, and forms a first output port TX and a second output port. The second output port is connected with the controllable tuning circuit and the LNA signal path simultaneously. VDD is connected with the overshoot optimization bias circuit and a logic circuit, the overshoot optimization bias circuit is connected with the logic circuit, and the overshoot optimization bias circuit provides a bias voltage for the controllable tuning circuit. The controllable tuning circuit changes the impedance of the signal output from the second output port to the LNA signal path. The application can realize double-channel transmission function, and the channels have the characteristics of consistent impedance, high isolation degree and good power linearity.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency integrated circuits, in particular to a dual-channel radio frequency low noise amplifier. BACKGROUND

[0002] The integration of radio frequency front-end modules is increasingly high, and the complexity of application scenarios is also increasing, and multi-channel transceiver function has become an important requirement for wireless communication transmission. In the radio frequency front-end module, the traditional multi-channel structure will have the following effects: the multi-channel parasitic of the receiving end will cause the LNA (low noise amplifier) noise to deteriorate and the stability to decrease, and the multi-channel parasitic of the transmitting end will cause the coupling factors to increase, thereby causing the power linearity to deteriorate, and the isolation and insertion loss of the multi-channel are also difficult to compromise. On the other hand, the vector error amplitude of the LNA at a small power will also deteriorate to a certain extent under the influence of multi-channel parasitic. SUMMARY

[0003] Embodiments of the present application provide a dual-channel radio frequency low noise amplifier, which solves the problem of signal leakage under the influence of multi-channel parasitic.

[0004] The technical implementation scheme of the present application is as follows: a dual-channel radio frequency low noise amplifier, comprising a dual-channel T / R switch, an LNA signal path, a controllable tuning circuit and an overshoot optimization bias circuit;

[0005] The dual-channel T / R switch comprises a radio frequency path, and the radio frequency path comprises a depletion mode pHEMT tube M1, a depletion mode pHEMT tube M2, a depletion mode pHEMT tube M3 and a depletion mode pHEMT tube M4. The source of the depletion mode pHEMT tube M1 is connected with the source of the depletion mode pHEMT tube M2, and one end of the blocking capacitor C2 is connected. The other end of the blocking capacitor C2 is connected with the second antenna. The source of the depletion mode pHEMT tube M3 is connected with the source of the depletion mode pHEMT tube M4, and one end of the blocking capacitor C1 is connected. The other end of the blocking capacitor C1 is connected with the first antenna. The drain of the depletion mode pHEMT tube M1 is connected with the drain of the depletion mode pHEMT tube M3, and one end of the blocking capacitor C3 is connected. The other end of the blocking capacitor C3 is connected with the first output port TX. The drain of the depletion mode pHEMT tube M2 is connected with the drain of the depletion mode pHEMT tube M4, forming a second output port of the dual-channel T / R switch. The first antenna and the second antenna are respectively connected with one end of the isolation inductor L2 and one end of the isolation inductor L3, and the other ends of the isolation inductor L2 and the isolation inductor L3 are connected with the first output port TX.

[0006] The second output port is connected with the controllable tuning circuit and the LNA signal path; the VDD is connected with the overshoot optimization bias circuit and the logic circuit, the overshoot optimization bias circuit is connected with the logic circuit, and a bias voltage is provided for the controllable tuning circuit, and the controllable tuning circuit changes the impedance of the signal output from the second output port to the LNA signal path.

[0007] Further, the double-channel T / R switch further comprises a ground branch, and the ground branch comprises a depletion-mode pHEMT tube M5, a depletion-mode pHEMT tube M6, a depletion-mode pHEMT tube M7 and a depletion-mode pHEMT tube M8.

[0008] The drains of the depletion-mode pHEMT tubes M5, M6, M7 and M8 are respectively connected with the radio frequency ground through a direct-current blocking capacitor C5, a direct-current blocking capacitor C6, a capacitor C7 and a direct-current blocking capacitor C8; the source of the depletion-mode pHEMT tube M5 is connected with one end of a direct-current blocking capacitor C3, the source of the depletion-mode pHEMT tube M6 is connected with one end of a direct-current blocking capacitor C2, the source of the depletion-mode pHEMT tube M7 is connected with the second output port, and the source of the depletion-mode pHEMT tube M8 is connected with one end of the direct-current blocking capacitor C2.

[0009] Further, the double-channel T / R switch further comprises a logic circuit, and the output end of the logic circuit generates a control signal vb11, a control signal vb22, a control signal vb21 and a control signal vb22, which are used to control the switching of the signal transmission channel by acting on the gates of the pHEMT tubes in the double-channel T / R switch and the adjustable tuning circuit.

[0010] Further, the overshoot optimization bias circuit comprises an enhancement-mode pHEMT tube M13, an enhancement-mode pHEMT tube M14, an enhancement-mode pHEMT tube M15, a filter capacitor C9, a diode group D02 and a voltage regulating resistor Rc, wherein the enhancement-mode pHEMT tubes M13 and M14 are connected in diode mode, the gates are short-circuited with the sources, the drain of the enhancement-mode pHEMT tube M13 is connected with the ground, and the gate is connected with the ground through the filter capacitor C9; the drain of the enhancement-mode pHEMT tube M14 is connected with one end of the voltage regulating resistor Rc, and the other end of the voltage regulating resistor Rc is connected with the ground; the source of the enhancement-mode pHEMT tube M13 is used as an output end; the drain of the enhancement-mode pHEMT tube M15 is connected with the VDD, the other end is connected with the source of the enhancement-mode pHEMT tube M14 and the negative direction of the diode group D02, and the diode group D02 is composed of four diodes connected in series and connected with the ground in positive direction.

[0011] Further, the controllable tuning circuit comprises a depletion-mode pHEMT tube M10, a capacitor C7, a choke inductor L1, and a blocking capacitor C11, wherein the capacitor C7 and the choke inductor L1 are connected in parallel to form a resonance network, the gate of the depletion-mode pHEMT tube M10 is connected to the control port Select, the source of the depletion-mode pHEMT tube M10 is connected to the second output port of the dual-channel T / R switch, the drain of the depletion-mode pHEMT tube M10 is connected to one end of the resonance network, and the other end of the resonance network is connected to the ground through the blocking capacitor C11.

[0012] Further, the LNA signal path comprises a depletion-mode pHEMT tube M9, a biasing resistor R9, a blocking capacitor C4, a diode group D01, an enhancement-mode pHEMT tube M11, an enhancement-mode pHEMT tube M12, a filter capacitor C10, a voltage dividing resistor R12, a voltage dividing resistor R13, a voltage dividing resistor R14, a blocking capacitor C11, and a source inductor ML1, wherein:

[0013] The source of the depletion-mode pHEMT tube M9 is connected to the second output port of the dual-channel T / R switch, the drain of the depletion-mode pHEMT tube M9 is connected to one end of the blocking capacitor C4, the other end of the blocking capacitor C4 is connected to the gate of the enhancement-mode pHEMT tube M11, the gate of the enhancement-mode pHEMT tube M11 is connected to the output of the overshoot optimization biasing circuit and one end of the diode group D01, the other end of the diode group D01 is connected to the ground, the diode group D01 is formed by two pairs of diodes connected in a ring, one pair of diodes is connected in forward direction to the ground, and the other pair of diodes is connected in reverse direction to the ground; the drain of the enhancement-mode pHEMT tube M11 is connected to the source of the enhancement-mode pHEMT tube M12 in a cascode structure, the voltage dividing resistor R14 is connected to the gate of the enhancement-mode pHEMT tube M12, the other end of the voltage dividing resistor R14 is connected to one end of the voltage dividing resistor R12 and one end of the voltage dividing resistor R13; the other end of the voltage dividing resistor R13 is connected to the ground, the other end of the voltage dividing resistor R12 is connected to one end of the choke inductor L1, the other end of the choke inductor L1 is connected to VDD; one end of the blocking capacitor C11 is connected to the drain of the enhancement-mode pHEMT tube M12, and the other end of the blocking capacitor C11 is connected to the radio frequency port RF_OUT.

[0014] Compared with the prior art, the dual-channel low noise amplifier has the following advantages:

[0015] The application can realize dual-channel transmission function, and the channels have the characteristics of consistent impedance, high isolation, and good power linearity. The channel isolation can be maintained below -20 dB during high-power and high-frequency transmission; and the noise of each channel is lower than 2.1 dB in the WIFI 5G frequency band.

[0016] The input end of the dual-channel low noise amplifier is two receiving channels. In view of the signal leakage problem caused by multi-channel parasitic, the multi-channel absorption type switch structure is used for improvement, so as to solve the stability problem and noise deterioration caused by the multi-channel parasitic, and the vector error amplitude of the dual-channel low noise amplifier in small power signal processing is significantly reduced. Meanwhile, the buffer design is added in the overshoot optimization bias circuit of the dual-channel low noise amplifier, so as to weaken the transient effect accompanied by the power supply feeding process in the bias circuit, and then solve the signal overshoot problem caused by the transient effect. The controllable tuning circuit is added in the input end, so as to ensure that the input impedance of the low noise amplifier remains consistent under different transmission paths. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is an external architecture diagram of the dual-channel low noise amplifier provided by the embodiment of the application.

[0018] Figure 2 It is a circuit structure diagram of the dual-channel low noise amplifier provided by the embodiment of the application.

[0019] Figure 3 It is the gain performance of the dual-channel low noise amplifier provided by the embodiment of the application.

[0020] Figure 4 It is the channel isolation performance of the dual-channel low noise amplifier provided by the embodiment of the application. DETAILED DESCRIPTION

[0021] Reference Figure 1 Combined Figure 2 As shown in the figure, a dual-channel radio frequency low noise amplifier, off-chip mainly for input matching and output matching, on-chip refers to the dual-channel radio frequency low noise amplifier, mainly including four circuit modules of dual-channel T / R switch, overshoot optimization bias circuit, logic circuit and LNA signal path.

[0022] The dual-channel radio frequency low noise amplifier includes four radio frequency ports. The off-chip input port RF1 and the input port RF2 are respectively connected to the port of the first antenna and the port of the second antenna on the chip after the input matching structure. The off-chip output port RF3 is connected to the radio frequency port RF_OUT on the chip through the output matching. The port RF4 off-chip is connected to the port TX on the chip, and the port TX is also the output end of the dual-channel T / R. Select as a control signal, after the resistance R01, connect the port SEL on the chip, VDD after the filtering capacitor C01, provide power supply for each module on the chip, control signal SEL, control signal Ctr0 and control signal Ctr1 generate four bias voltages vb11, bias voltage vb22, bias voltage vb21 and bias voltage vb22.

[0023] The double-channel T / R switch provides four radio frequency ports, the first output port is TX, and the second output port is connected with the controllable tuning circuit and the LNA signal path at the same time; VDD is connected with the overshoot optimization bias circuit and the logic circuit, wherein the output end of the bias circuit is connected with the LNA signal path, and the input end of the LNA signal path is provided with a stable bias voltage; the output end of the logic circuit generates multiple control signals such as control signal vb11, control signal vb22, control signal vb21 and control signal vb22, which act on the gates of the pHEMT tubes in the double-channel T / R switch and the adjustable tuning circuit, so as to control the switching of the signal transmission channel; VDD is connected with the choke inductance L1 at the same time, and the other end of the choke inductance L1 is connected with the LNA signal path, thereby providing power supply for the LNA signal path.

[0024] Referring to Figure 2 As shown in the figure, a double-channel radio frequency low noise amplifier comprises a double-channel T / R switch, an LNA signal path, a controllable tuning circuit and an overshoot optimization bias circuit.

[0025] The double-channel T / R switch comprises a radio frequency path and a ground branch, and specifically comprises a depletion mode pHEMT tube M1, a depletion mode pHEMT tube M2, a depletion mode pHEMT tube M3, a depletion mode pHEMT tube M4, resistors R1, R2, R3 and R4 at the gates of the tubes, isolation inductances L2 and L3, isolation capacitors C1, C2, C3 and C4, a depletion mode pHEMT tube M5, a depletion mode pHEMT tube M6, a depletion mode pHEMT tube M7 and a depletion mode pHEMT tube M8, and resistors R5, R6, R7 and R8 at the gates of the tubes.

[0026] The source of the depletion mode pHEMT tube M1 is connected with the source of the depletion mode pHEMT tube M2, and is connected with one end of the isolation capacitor C2 at the same time, and the other end of the isolation capacitor C2 is connected with the second antenna; the source of the depletion mode pHEMT tube M3 is connected with the source of the depletion mode pHEMT tube M4, and is connected with one end of the isolation capacitor C1 at the same time, and the other end of the isolation capacitor C1 is connected with the first antenna; the drain of the depletion mode pHEMT tube M1 is connected with the drain of the depletion mode pHEMT tube M3, and is connected with one end of the isolation capacitor C3 at the same time, and the other end of the isolation capacitor C3 is connected with the first output port TX; the drain of the depletion mode pHEMT tube M2 is connected with the drain of the depletion mode pHEMT tube M4, and forms the second output port of the double-channel T / R switch, and is connected with the drain of the depletion mode pHEMT tube M7 at the same time.

[0027] One end of a resistor R1 connected to a gate of a depletion-mode pHEMT transistor M1, the other end of the resistor R1 connected to a control signal Vb22, one end of a resistor R2 connected to a gate of a depletion-mode pHEMT transistor M2, the other end of the resistor R2 connected to a control signal Vb21, one end of a resistor R3 connected to a gate of a depletion-mode pHEMT transistor M3, the other end of the resistor R3 connected to a control signal Vb12, one end of a resistor R4 connected to a gate of a depletion-mode pHEMT transistor M4, the other end of the resistor R4 connected to a control signal Vb11.

[0028] The second output port is connected to a controllable tuning circuit and an LNA signal path; VDD is connected to an overshoot optimization bias circuit and a logic circuit, the overshoot optimization bias circuit is connected to the logic circuit, and the controllable tuning circuit provides a bias voltage for the controllable tuning circuit, and the controllable tuning circuit changes the impedance of the signal output by the second output port to the LNA signal path.

[0029] In an embodiment, the ground branch includes: depletion-mode pHEMT transistors M5, M6, M7 and M8, a DC blocking capacitor C5, a DC blocking capacitor C6, a capacitor C7 and a DC blocking capacitor C8; the source of the depletion-mode pHEMT transistor M5 is connected to one end of the DC blocking capacitor C3, realizing the first output port TX DC blocking, the gate of the depletion-mode pHEMT transistor M5 is connected to a resistor R5, the drain of the depletion-mode pHEMT transistor M5 is connected to one end of the DC blocking capacitor C5, and the other end of the DC blocking capacitor C5 is grounded; the source of the depletion-mode pHEMT transistor M6 is connected to one end of the DC blocking capacitor C2, the other end of the DC blocking capacitor C2 is connected to the second antenna, the drain of the depletion-mode pHEMT transistor M6 is connected to one end of the DC blocking capacitor C6, the other end of the DC blocking capacitor C6 is grounded, and the gate of the depletion-mode pHEMT transistor M6 is connected to a resistor R6, the other end of the resistor R6 is grounded, realizing the second antenna port DC blocking; the source of the depletion-mode pHEMT transistor M8 is connected to one end of the DC blocking capacitor C1, the other end of the DC blocking capacitor C1 is connected to the first antenna, realizing the first antenna port DC blocking, the gate of the depletion-mode pHEMT transistor M8 is connected to one end of a resistor R8, the other end of the resistor R8 is grounded, and the drain of the depletion-mode pHEMT transistor M8 is connected to one end of the DC blocking capacitor C8, the other end of the DC blocking capacitor C8 is connected to a control signal.

[0030] The source of the depletion-mode pHEMT transistor M7 is connected to the common terminal of the depletion-mode pHEMT transistors M2 and M4. The gate of the depletion-mode pHEMT transistor M7 is connected to one end of a resistor R7, the other end of the resistor R7 is connected to a control signal, and the drain of the depletion-mode pHEMT transistor M7 is connected to one end of a capacitor C7, the other end of the capacitor C7 is grounded.

[0031] In an embodiment, the LNA signal path comprises a depletion-mode pHEMT M9, a bias resistor R9, a DC blocking capacitor C4, a diode group D01, an enhancement-mode pHEMT M11, an enhancement-mode pHEMT M12, a filter capacitor C10, a voltage divider resistor R12, a voltage divider resistor R13, a voltage divider resistor R14, a DC blocking capacitor C11, and a source inductor ML1.

[0032] The source of the depletion-mode pHEMT M9 is connected to the double-channel T / R switch and the controllable tuning circuit, the drain of the depletion-mode pHEMT M9 is connected to the DC blocking capacitor C4, the other end of the DC blocking capacitor C4 is connected to the gate of the depletion-mode pHEMT M11, the gate is also connected to the ground of the diode group D01, the diode group D01 is composed of two pairs of diodes connected in a ring, one pair is forward connected to the ground and the other pair is reverse connected to the ground; the source of the depletion-mode pHEMT M11 is connected to the drain of the depletion-mode pHEMT M12, which adopts a cascode structure, one end of the voltage divider resistor R14 is connected to the gate of the depletion-mode pHEMT M12, the other end is connected to the voltage divider resistor R12 and the voltage divider resistor R13; the other end of the voltage divider resistor R13 is connected to the ground, the other end of the voltage divider resistor R12 is connected to one end of the choke inductor L1; the DC blocking capacitor C11 is connected to the drain of the depletion-mode pHEMT M12, the other end of the depletion-mode pHEMT M12 is connected to the RF_OUT port, the gate of the depletion-mode pHEMT M12 is connected to one end of the filter capacitor C10, and the other end of the filter capacitor C10 is connected to the ground.

[0033] In an embodiment, the controllable tuning circuit comprises a depletion-mode pHEMT M10, a bias resistor R10, a tuning capacitor C7, a tuning choke inductor L1, and a DC blocking capacitor C11. The source of the depletion-mode pHEMT M10 is connected to the double-channel T / R switch and the source of the depletion-mode pHEMT M9, the tuning capacitor C7 and the tuning choke inductor L1 are connected in parallel to form a resonance circuit, one end of the resonance circuit is connected to the drain of the pHEMT M10, and the other end is connected to the RF ground through the DC blocking capacitor C11.

[0034] In an embodiment, the overshoot-optimized bias circuit includes an enhanced pHEMT tube M13, an enhanced pHEMT tube M14, an enhanced pHEMT tube M15, a voltage regulating resistor Rc, a filter capacitor C9, and a diode group D02. The source of the enhanced pHEMT tube M15 is connected to one end of the choke inductor L1, the drain of the enhanced pHEMT tube M15 is connected to the source of the enhanced pHEMT tube M14 and the negative terminal of the diode group D02, the diode group D02 is connected in series with four diodes and is connected to the positive terminal of the ground. The source and the gate of the enhanced pHEMT tube M13 and the enhanced pHEMT tube M14 are shorted, the source of the enhanced pHEMT tube M13 is connected to the source of the enhanced pHEMT tube M14, the drain of the enhanced pHEMT tube M14 is connected to the voltage regulating resistor Rc, the drain of the enhanced pHEMT tube M13 is connected to the ground, and the source of the enhanced pHEMT tube M13 is connected to the ground through the filter capacitor C9.

[0035] In an embodiment, the logic circuit part, powered by VDD, includes but is not limited to: three control signals SEL, control signals Ctr0, control signals Ctr1, to generate four items vb11, control signals vb22, vb21, and vb22. Each bias voltage acts on the depletion-mode pHEMT tubes in the T / R switch, the LNA signal path, and the controllable tuning circuit to realize the switching of the signal transmission path.

[0036] Figure 2 In an embodiment, the depletion-mode pHEMT tube M1, the depletion-mode pHEMT tube M2, the depletion-mode pHEMT tube M3, and the depletion-mode pHEMT tube M4 are used as the first radio frequency path, the second radio frequency path, the third radio frequency path, and the fourth radio frequency path, respectively. The depletion-mode pHEMT tube M5, the depletion-mode pHEMT tube M6, the depletion-mode pHEMT tube M7, and the depletion-mode pHEMT tube M8 are used as the first ground branch, the second ground branch, the third ground branch, and the fourth ground branch, respectively.

[0037] When the dual-channel radio frequency low noise amplifier works in the first channel, the signal enters from the first antenna port, at this time the control signal vb11 is high potential, the control signal vb12, the control signal vb21 and the control signal vb22 are low potential, the fourth radio frequency path is in the conducting state, that is, the depletion mode pHEMT tube M4 is in the conducting state, which is used for transmitting the main path signal; The first radio frequency path, the second radio frequency path and the third radio frequency path are in the cut-off state to prevent signal leakage; The first pair of ground branches and the second pair of ground branches of the depletion mode pHEMT tube M5 and the depletion mode pHEMT tube M6 are in the conducting state, which absorbs a small amount of signal leaked by the parasitic capacitor and improves the port isolation; The third pair of ground branches and the fourth pair of ground branches of the depletion mode pHEMT tube M7 and the depletion mode pHEMT tube M8 are in the cut-off state. The depletion mode pHEMT tube M3 is in the cut-off state, which is equivalent to a parasitic capacitor, and forms an impedance network with the isolation inductor L3 in parallel, thereby improving the high frequency impedance between the first output port TX and the first antenna, and achieving good isolation effect in a wide frequency band.

[0038] In an embodiment, when the dual-channel radio frequency low noise amplifier works in the first channel, the depletion mode pHEMT tube M10 is in the cut-off state, which is equivalent to a capacitor. The capacitor C7 and the choke inductor L1 form a resonant network in parallel and are grounded, but the choke inductor L1 will ground the direct current, causing the drain potential of the depletion mode pHEMT tube M10 to be zero, which cannot be turned off, so the resonant network needs to be connected in series with the direct current blocking capacitor C11, and the radio frequency ground. When the depletion mode pHEMT tube M10 is cut off, the controllable tuning circuit has little effect on the input impedance, and the input impedance of the first channel is subject to the effect of off-chip matching.

[0039] When the dual-channel radio frequency low noise amplifier works in the first channel, the overshoot optimization bias circuit, the enhancement pHEMT tube M15 is in the on state, and VDD is the power supply for the bias circuit; the enhancement pHEMT tube M13 and the enhancement pHEMT tube M14 are both in diode connection, the diode group D02 is in forward conduction state, and the diode group D02 is four positive bias diodes in series, and the forward conduction voltage of a single diode is about 0.6V. When VDD enters the overshoot optimization bias circuit, the diode group D02 clamps the VDD voltage to about 2.4V, avoiding the transient response delay caused by the excessive voltage drop of the enhancement pHEMT tube M13, and the diode group D02 has a first-stage voltage buffer effect; the enhancement pHEMT tube M13 and the enhancement pHEMT tube M14 have the same voltage characteristics after being connected in diode connection, and have more sensitive temperature characteristics than the diode group D02. The enhancement pHEMT tube M14 has a second-stage voltage buffer effect, but the same voltage characteristics will lower the voltage output of the enhancement pHEMT tube M13, so a voltage regulating resistor Rc is added to the drain of the enhancement pHEMT tube M14 to increase the forward conduction voltage of the enhancement pHEMT tube M14, and the resistance value of the voltage regulating resistor Rc is adjusted to make the enhancement pHEMT tube M14 have different voltage characteristics. The enhancement pHEMT tube M13 processes the output voltage of the enhancement pHEMT tube M14 into a stable and delay-free bias voltage, which acts on the gate of the enhancement pHEMT tube M11, so that the gain of the dual-channel radio frequency low noise amplifier shows a good effect of no overshoot in time domain.

[0040] In an embodiment, in the LNA signal path, the enhancement pHEMT tube M11 and the enhancement pHEMT tube M12 form a cascode structure, the diode group D01 has an amplitude limiting effect on the input signal, and the voltage dividing resistors R12, R13 and R14 are connected in a manner to provide a gate voltage for the enhancement pHEMT tube M12. Figure 1 The amplified signal is transmitted to the radio frequency port RF_OUT through the DC blocking capacitor C11.

[0041] Further, the three external input control signals Select, Ctr0 and Ctr1 act on the logic circuit, and VDD generates control signals under the processing of the logic circuit, which act on the gates of the depletion pHEMT tubes in the dual-channel T / R switch and the LNA signal path, thereby controlling the transmission path of the radio frequency signal. The structure of the logic circuit for generating control signals can be realized by using a conventional structure.

[0042] When the dual-channel radio frequency low noise amplifier works in the second channel, the signal enters from the second antenna port, at this time the control signal vb21 is high potential, the control signal vb12, the control signal vb11 and the control signal vb22 are low potential, the second radio frequency path is in the conducting state, used for transmitting the main path signal; the first radio frequency path, the fourth radio frequency path and the third radio frequency path are in the cut-off state, preventing signal leakage; the first ground branch and the fourth ground branch where the depletion mode pHEMT tube M5 and the depletion mode pHEMT tube M8 are located are in the conducting state, absorbing a small amount of signal leaked by the parasitic capacitor, and improving the port isolation; the second ground branch and the third ground branch where the depletion mode pHEMT tube M6 and the depletion mode pHEMT tube M7 are located are in the cut-off state. The depletion mode pHEMT tube M2 is in the cut-off state, and itself is equivalent to a parasitic capacitor, which is connected in parallel with the isolation inductor L2 to form an impedance network, thereby improving the high-frequency impedance between the first output port TX and the second antenna, and achieving good isolation effect in a wide frequency band.

[0043] Further, when the dual-channel radio frequency low noise amplifier works in the second channel, the depletion mode pHEMT tube M10 is in the conducting state, the capacitor C7 and the choke inductor L1 form a resonance network, thereby changing the input impedance of the second channel, adjusting the capacitance value of the capacitor C7 and the inductance value of the choke inductor L1, and finally realizing the effect that the input impedance of the second channel is consistent with that of the first channel.

[0044] In the example of the present application, VDD is powered by 5V, and the control voltages Select, Ctr0 and Ctr1 are 2.5V. Referring to Figure 3 and Figure 4 , the S parameter curve in Figure 3 , S21 is the gain curve, S11 is the return loss curve of the input end, S22 is the return loss curve of the output end, and m16 marks the gain effect of the amplification circuit at 5.5GHz; Figure 4 is the isolation of each port of the dual-channel radio frequency low noise amplifier in the first channel mode, S41 is the isolation between the first antenna and the second antenna, S12 is the isolation between the radio frequency port RF_OUT and the first antenna 1 port, m26 marks the isolation effect between the first antenna 1 and the second antenna 2 at 5.5GHz, and m27 marks the isolation effect between the first antenna 1 and the radio frequency port RF_OUT at 5.5GHz. Through simulation test, in the frequency band of 5.2GHz to 5.8GHz, the gain of the dual-channel radio frequency low noise amplifier can reach 16dB with good flatness; in the dual-channel T / R switch structure, the isolation between the port of the first antenna and the port of the second antenna can reach-25dB, and the reverse isolation between the output port and the input port of the dual-channel radio frequency low noise amplifier can reach-36dB.

Claims

1. A dual-channel radio frequency low-noise amplifier, characterized in that: Includes a dual-channel T / R switch, an LNA signal path, a controllable tuning circuit, and an overshoot-optimized bias circuit; The dual-channel T / R switch includes an RF path, which comprises depletion-mode pHEMT transistors M1, M2, M3, and M4. The source of depletion-mode pHEMT transistor M1 is connected to the source of depletion-mode pHEMT transistor M2, and is also connected to one end of DC blocking capacitor C2. The other end of DC blocking capacitor C2 is connected to a second antenna. The source of depletion-mode pHEMT transistor M3 is connected to the source of depletion-mode pHEMT transistor M4, and is also connected to one end of DC blocking capacitor C1. The other end of DC blocking capacitor C1... The first antenna is connected to the first antenna; the drain of depletion-type pHEMT transistor M1 is connected to the drain of depletion-type pHEMT transistor M3, and one end of DC blocking capacitor C3 is also connected to it. The other end of DC blocking capacitor C3 is connected to the first output port TX; the drain of depletion-type pHEMT transistor M2 is connected to the drain of depletion-type pHEMT transistor M4, forming the second output port of the dual-channel T / R switch; the first antenna and the second antenna are respectively connected to one end of isolation inductor L2 and one end of isolation inductor L3, and the other ends of isolation inductor L2 and isolation inductor L3 are simultaneously connected to the first output port TX; The second output port is connected to both the controllable tuning circuit and the LNA signal path. VDD connects the overshoot optimization bias circuit and the logic circuit. The overshoot optimization bias circuit is connected to the logic circuit and provides a bias voltage for the controllable tuning circuit. The controllable tuning circuit changes the impedance of the signal output from the second output port to the LNA signal path. The dual-channel T / R switch also includes a ground branch, which includes depletion-type pHEMT tubes M5, M6, M7, and M8. The drains of depletion-type pHEMT transistors M5, M6, M7, and M8 are grounded via RF capacitors C5, C6, C7, and C8, respectively. The source of depletion-type pHEMT transistor M5 is connected to one end of DC blocking capacitor C3, the source of depletion-type pHEMT transistor M6 is connected to one end of DC blocking capacitor C2, the source of depletion-type pHEMT transistor M7 is connected to the second output port, and the source of depletion-type pHEMT transistor M8 is connected to one end of DC blocking capacitor C2.

2. The dual-channel RF low-noise amplifier according to claim 1, characterized in that: It also includes a logic circuit, the output of which generates control signals vb11, vb22, vb21 and vb22. The control signals act on the gates of each pHEMT transistor in the dual-channel T / R switch and the adjustable tuning circuit to control the switching of the signal transmission channel.

3. A dual-channel RF low-noise amplifier according to claim 1, characterized in that: The overshoot optimization bias circuit includes enhancement-mode pHEMT transistors M13, M14, and M15, a filter capacitor C9, a diode group D02, and a voltage regulating resistor Rc. Enhancement-mode pHEMT transistors M13 and M14 are both diodes with their gates and sources shorted. The drain of enhancement-mode pHEMT transistor M13 is grounded, and its gate is grounded via the filter capacitor C9. The drain of enhancement-mode pHEMT transistor M14 is connected to one end of the voltage regulating resistor Rc, and the other end of Rc is grounded. The source of enhancement-mode pHEMT transistor M13 serves as the output terminal. The drain of enhancement-mode pHEMT transistor M15 is connected to VDD, and the other end is connected to the source of enhancement-mode pHEMT transistor M14 and the negative terminal of diode group D02. Diode group D02 consists of four diodes connected in series and is grounded via the forward terminal.

4. A dual-channel RF low-noise amplifier according to claim 1, characterized in that: The controllable tuning circuit includes a depletion-type pHEMT transistor M10, a capacitor C7, a choke inductor L1, and a DC blocking capacitor C11. The capacitor C7 and the choke inductor L1 are connected in parallel to form a resonant network. The gate of the depletion-type pHEMT transistor M10 is connected to the control port Select, the source is connected to the second output port of the dual-channel T / R switch, and the drain is connected to one end of the resonant network. The other end of the resonant network is grounded through the DC blocking capacitor C11.

5. A dual-channel RF low-noise amplifier according to claim 1, characterized in that: The LNA signal path includes a depletion-mode pHEMT transistor M9, a bias resistor R9, a DC blocking capacitor C4, a diode group D01, an enhancement-mode pHEMT transistor M11, an enhancement-mode pHEMT transistor M12, a filter capacitor C10, voltage divider resistors R12, R13, and R14, a DC blocking capacitor C11, and a source inductor ML1, wherein: The source of the depletion-mode pHEMT M9 is connected to the second output port of the dual-channel T / R switch, and its drain is connected to one end of the DC blocking capacitor C4. The other end of the DC blocking capacitor C4 is connected to the gate of the enhancement-mode pHEMT M11. The gate of the enhancement-mode pHEMT M11 is connected to the output terminal of the overshoot optimization bias circuit and also to one end of the diode group D01. The other end of the diode group D01 is grounded. The diode group D01 consists of two pairs of diodes connected in a loop, one pair forward-grounded and one pair reverse-grounded. The drain of the enhancement-mode pHEMT M11 is connected to the enhancement-mode pHEMT M11. The source connection of the enhancement-mode pHEMT transistor M12 adopts a cascode structure. The voltage divider resistor R14 is connected to the gate of the enhancement-mode pHEMT transistor M12, and the other end of the voltage divider resistor R14 is connected to one end of the voltage divider resistor R12 and one end of the voltage divider resistor R13. The other end of the voltage divider resistor R13 is grounded, and the other end of the voltage divider resistor R12 is connected to one end of the choke inductor L1. The other end of the choke inductor L1 is connected to VDD. One end of the DC blocking capacitor C11 is connected to the drain of the enhancement-mode pHEMT transistor M12, and the other end is connected to the RF port RF_OUT.

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