Optical fiber array coupling type 24-path receiving and transmitting integrated optical module

Abstract

The invention relates to an optical fiber array coupling type 24-path transceiving integrated optical module, which comprises a PCB (printed circuit board) combined module, the PCB combined module is connected with a socket through a tail sleeve, the PCB combined module adopts high-speed differential wiring via hole anti-pad setting, the PCB combined module comprises a PCB, the PCB is a bearing plate of a high-speed circuit, a VCSEL (vertical cavity surface emitting laser) driving chip, a VCSEL array, a PD (PD) array, a PD receiving and amplifying chip and a micro-control chip are integrally mounted, and the VCSEL driving chip, the VCSEL array, the PD array, the PD receiving and amplifying chip and the micro-control chip are integrated. The PCB gives consideration to the signal integrity, guarantees the signal quality, and guarantees the electromagnetic interference and electrostatic discharge protection requirements.

Description

Technical Field

[0001] This invention relates to optoelectronic communication technology and its equipment, specifically, a fiber array coupled 24-channel transceiver integrated optical module. Background Technology

[0002] Optical communication has advantages such as no need to purchase spectrum resources, high security, high privacy, and strong resistance to electromagnetic interference.

[0003] However, current optical communication devices suffer from numerous components and bulky size in some space-constrained application scenarios. In addition, most current optical communication devices use a single optical channel, which limits information carrying capacity and information transmission rate, and is not conducive to improving modulation bandwidth.

[0004] Therefore, how to make optical communication devices smaller and easier to miniaturize while improving their information carrying capacity and information transmission rate has become a technical problem that urgently needs to be solved in this field.

[0005] Therefore, it is necessary to provide a fiber array coupled 24-channel transceiver optical module to solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to provide a fiber array coupled 24-channel transceiver optical module.

[0007] The technical solution is as follows:

[0008] A fiber array coupled 24-channel transceiver integrated optical module includes a PCB assembly module. The PCB assembly module is connected to a socket via a tail sleeve. The PCB assembly module is designed with high-speed differential trace via anti-soldering pads. The PCB assembly module includes a PCB board, which is the carrier board of high-speed circuits. It integrates and installs a VCSEL driver chip, a VCSEL array, a PD array, a PD receiver amplifier chip, and a microcontroller chip. The PCB board needs to ensure signal integrity and signal quality, as well as meet the requirements of electromagnetic interference and electrostatic discharge protection.

[0009] The differential impedance was verified through TDR simulation analysis.

[0010] TDR simulation analysis includes:

[0011] 1) Selection of board material:

[0012] 1-1) The selected high-frequency board material meets the requirements of speeds above 25G and has strong reliability and stability; the differential line insertion loss is 0.25dB and the return loss is <-20dB under the three anti-pad sizes of 12mil, 13mil and 14mil.

[0013] 1-2) The internal length of the high-speed differential (P / N) pair is strictly controlled within 1 mil to meet the signal timing consistency requirements; return ground vias are added at the high-speed differential layer transition points to improve signal EMC and return path; high-speed differential traces use curved traces to avoid electron emission and reduce electromagnetic radiation; inner high-speed differential traces are grounded as much as possible and surrounded by multiple GND vias to reduce crosstalk; the inner high-speed differential trace layers are located on the third and eighth layers respectively, and the signal integrity requirements are fully considered during the stack-up design, with the two adjacent layers of the high-speed trace layer set as GND layers to ensure signal quality;

[0014] 2) Simulation frequency setting: The simulation frequency setting range is DC-75GHz. Since the actual operating speed is 25Gbps, we only need to focus on the S-parameters within the 12.5GHz range. By simulating the anti-pad size under different conditions of 12mil, 13mil, and 14mil, we can analyze that the insertion loss, return loss, and TDR parameter performance are better under the 12mil anti-pad size.

[0015] 3) According to the requirements of signal integrity, for differential lines, in order to ensure that the signal is transmitted to the receiving end as completely as possible, impedance matching of the transmission line must be performed to keep the impedance of the entire link constant and matched, and the differential lines should be of equal length and as short as possible; the impedance design requirement for differential lines is 100 ohms ± 10%.

[0016] 4) Import the high-speed differential traces drawn using Ansys HFSS simulation software. Since the entire module is a 24-channel transceiver parallel optical module with a total of 48 pairs of differential lines, a cutting process is used to cut out the channels that need to be simulated. The four differential lines of the receiving channel are mainly extracted.

[0017] 5) The differential level swing, drive signal rise time, and simulation rate were set. The simulation analysis was performed with a differential swing of 800mV, a drive signal rise time of 14ps, and a signal rate of 25Gbps. Specifically, the signal rise time and fall time were 11ps, and the signal-to-noise ratio was 24.29.

[0018] 6) Using SIWAVE to simulate near-end crosstalk, with terminations at both ends of the transmission line, noise occurs near the line due to coupling between the two lines. The noise value rises rapidly to a fixed value and remains there for a period of time before decreasing. The design requires the crosstalk coefficient between high-speed differential lines to be less than 0.1.

[0019] Furthermore, the socket is an MT socket.

[0020] Furthermore, the PCB assembly module is equipped with several high-speed chips, with a total of four high-speed chips arranged in pairs, connected by optical fibers to form a fiber-coupled PCB main structure.

[0021] Furthermore, the PCB assembly module is located on the lower shell, and an electrical connector is also located below the PCB assembly module.

[0022] Furthermore, a protective cover and a thermal pad are provided on the top of the PCB assembly module, and the protective cover and the thermal pad are held in place by the top cover.

[0023] Furthermore, the lower shell and the upper cover are fixedly connected by screws and snap-fit ​​structures.

[0024] Compared with existing technologies, the present invention is smaller in size and easier to miniaturize, while effectively improving the information carrying capacity and information transmission rate of optical communication devices. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the present invention.

[0026] Figure 2 This is a schematic diagram of a PCB assembly module.

[0027] Figure 3 It is an insertion loss curve.

[0028] Figure 4 This is a schematic diagram of the return waveform loss.

[0029] Figure 5 This is a schematic diagram of the TDR impedance. Detailed Implementation

[0030] Example:

[0031] Please see Figure 1 This embodiment demonstrates a fiber array coupled 24-channel transceiver integrated optical module, including a PCB assembly module 100. The PCB assembly module 100 is connected to a socket 300 via a tail sleeve 200. The PCB assembly module 100 is a high-speed differential trace via anti-soldering pad type setting. The PCB assembly module includes a PCB board, which is the carrier board of high-speed circuits. It integrates and installs a VCSEL driver chip, a VCSEL array, a PD array, a PD receiver amplifier chip, and a microcontroller chip. The PCB board needs to take into account signal integrity, ensure signal quality, and also meet the requirements of electromagnetic interference and electrostatic discharge protection.

[0032] The differential impedance was verified through TDR simulation analysis.

[0033] TDR simulation analysis includes:

[0034] 1) Selection of board material:

[0035] 1-1) The selected high-frequency board material meets the requirements of speeds above 25G and has strong reliability and stability; the differential line insertion loss is 0.25dB and the return loss is <-20dB under the three anti-pad sizes of 12mil, 13mil and 14mil.

[0036] 1-2) The internal length of the high-speed differential (P / N) pair is strictly controlled within 1 mil to meet the signal timing consistency requirements; return ground vias are added at the high-speed differential layer transition points to improve signal EMC and return path; high-speed differential traces use curved traces to avoid electron emission and reduce electromagnetic radiation; inner high-speed differential traces are grounded as much as possible and surrounded by multiple GND vias to reduce crosstalk; the inner high-speed differential trace layers are located on the third and eighth layers respectively, and the signal integrity requirements are fully considered during the stack-up design, with the two adjacent layers of the high-speed trace layer set as GND layers to ensure signal quality;

[0037] 2) Simulation frequency setting, please refer to... Figure 3-5 The simulation frequency setting range is DC-75GHz. Since the actual operating rate is 25Gbps, we only need to focus on the S-parameters in the 12.5GHz range. By simulating the antipad size under different conditions of 12mil, 13mil, and 14mil, we can analyze that the insertion loss, return loss, and TDR parameters are better under the 12mil antipad size.

[0038] 3) According to the requirements of signal integrity, for differential lines, in order to ensure that the signal is transmitted to the receiving end as completely as possible, impedance matching of the transmission line must be performed to keep the impedance of the entire link constant and matched, and the differential lines should be of equal length and as short as possible; the impedance design requirement for differential lines is 100 ohms ± 10%.

[0039] 4) Import the high-speed differential traces drawn using Ansys HFSS simulation software. Since the entire module is a 24-channel transceiver parallel optical module with a total of 48 pairs of differential lines, a cutting process is used to cut out the channels that need to be simulated. The four differential lines of the receiving channel are mainly extracted.

[0040] 5) The differential level swing, drive signal rise time, and simulation rate were set. The simulation analysis was performed with a differential swing of 800mV, a drive signal rise time of 14ps, and a signal rate of 25Gbps. Specifically, the signal rise time and fall time were 11ps, and the signal-to-noise ratio was 24.29.

[0041] 6) Using SIWAVE to simulate near-end crosstalk, with terminations at both ends of the transmission line, noise occurs near the line due to coupling between the two lines. The noise value rises rapidly to a fixed value and remains there for a period of time before decreasing. The design requires the crosstalk coefficient between high-speed differential lines to be less than 0.1.

[0042] Socket 300 is an MT socket.

[0043] The PCB assembly module 100 is equipped with several high-speed chips 1, with a total of 4 high-speed chips 1 arranged in pairs and connected by optical fibers to form a fiber-coupled PCB main structure.

[0044] The PCB assembly module 100 is mounted on the lower shell 400, and an electrical connector 500 is also mounted below the PCB assembly module 400.

[0045] The PCB assembly module 100 is provided with a protective cover 600 and a thermal pad 700, and the protective cover and thermal pad are held in place by the upper cover 800.

[0046] The tail sleeve 200 and the socket 300 are equipped with a spiral wound tube 900.

[0047] The lower shell 400 and the upper cover 800 are fixedly connected by screws and clips.

[0048] Compared with existing technologies, the present invention is smaller in size and easier to miniaturize, while effectively improving the information carrying capacity and information transmission rate of optical communication devices.

[0049] For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of this invention, and these all fall within the protection scope of this invention.

Claims

1. A fiber array coupled 24-channel transceiver integrated optical module, characterized in that: It includes a PCB assembly module, which is connected to a socket via a tail sleeve. The PCB assembly module is designed with high-speed differential trace via anti-soldering pads. The PCB assembly module includes a PCB board, which is the carrier board of the high-speed circuit. It integrates and installs VCSEL driver chips, VCSEL arrays, PD arrays, PD receiver amplifier chips, and microcontroller chips. The PCB board takes into account signal integrity, ensures signal quality, and meets the requirements for electromagnetic interference and electrostatic discharge protection. The differential impedance was verified through TDR simulation analysis. TDR simulation analysis includes: 1) Selection of board material: 1-1) The selected high-frequency board material meets the requirements of speeds above 25G and has strong reliability and stability; the differential line insertion loss is 0.25dB and the return loss is <-20dB under the three anti-pad sizes of 12mil, 13mil and 14mil. 1-2) The internal length of the high-speed differential (P / N) pair is strictly controlled within 1 mil to meet the signal timing consistency requirements; return ground vias are added at the high-speed differential layer transition points to improve signal EMC and return path; high-speed differential traces use curved traces to avoid electron emission and reduce electromagnetic radiation; inner high-speed differential traces are grounded as much as possible and surrounded by multiple GND vias to reduce crosstalk; the inner high-speed differential trace layers are located on the third and eighth layers respectively, and the signal integrity requirements are fully considered during the stack-up design, with the two adjacent layers of the high-speed trace layer set as GND layers to ensure signal quality; 2) Simulation frequency setting: The simulation frequency setting range is DC-75GHz. Since the actual operating speed is 25Gbps, we only need to focus on the S-parameters within the 12.5GHz range. By simulating the anti-pad size under different conditions of 12mil, 13mil, and 14mil, we can analyze that the insertion loss, return loss, and TDR parameter performance are better under the 12mil anti-pad size. 3) According to the requirements of signal integrity, for differential lines, in order to ensure that the signal is transmitted to the receiving end as completely as possible, impedance matching of the transmission line must be performed to keep the impedance of the entire link constant and matched, and the differential lines should be of equal length and as short as possible; the impedance design requirement for differential lines is 100 ohms ± 10%. 4) Import the high-speed differential traces drawn using Ansys HFSS simulation software. Since the entire module is a 24-channel transceiver parallel optical module with a total of 48 pairs of differential lines, a cutting process is used to cut out the channels that need to be simulated. The four differential lines of the receiving channel are mainly extracted. 5) The differential level swing, drive signal rise time, and simulation rate were set. The simulation analysis was performed with a differential swing of 800mV, a drive signal rise time of 14ps, and a signal rate of 25Gbps. Specifically, the signal rise time and fall time were 11ps, and the signal-to-noise ratio was 24.

29. 6) Using SIWAVE to simulate near-end crosstalk, with terminations at both ends of the transmission line, noise occurs near the line due to coupling between the two lines. The noise value rises rapidly to a fixed value and remains there for a period of time before decreasing. The design requires the crosstalk coefficient between high-speed differential lines to be less than 0.

1.

2. The fiber array coupled 24-channel transceiver integrated optical module according to claim 1, characterized in that: The socket is an MT socket.

3. The fiber array coupled 24-channel transceiver integrated optical module according to claim 1, characterized in that: The PCB assembly module is equipped with several high-speed chips, with a total of four high-speed chips arranged in pairs and connected by optical fibers to form a fiber-coupled PCB main structure.

4. The fiber array coupled 24-channel transceiver integrated optical module according to claim 1, characterized in that: The PCB assembly module is located on the lower shell, and an electrical connector is also located below the PCB assembly module.

5. A fiber array coupled 24-channel transceiver integrated optical module according to claim 4, characterized in that: The PCB assembly module is equipped with a protective cover and a thermal pad, which are held in place by the top cover.

6. A fiber array coupled 24-channel transceiver integrated optical module according to claim 5, characterized in that: The lower shell and the upper cover are fixedly connected by screws and clips.

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