Link training method, chip, device and system

Abstract

The embodiment of the invention provides a link training method, chip, device and system, in the method, a sending end device generates and sends a first link training request to a receiving end PHY chip, the first link training request is used for instructing the receiving end PHY chip to perform link training on a first parameter, the first parameter at least comprises a parameter of a receiving end module, and the first parameter is used for instructing the receiving end PHY chip to perform link training on the first parameter. The parameters of the receiving end module are optical module parameters; and the transmitting end device receives first state information, wherein the first state information indicates a state after link training is performed on the first parameter based on the first link training request. Thus, even if the receiving end module in the communication system does not comprise an oDSP chip, link training of parameters in the receiving end module connected with the receiving end PHY chip by the receiving end PHY chip can be realized through interaction of an end-to-end link training request and state information between the sending end equipment and the receiving end PHY chip, so that the working performance of the communication system is guaranteed.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a link training method, chip, device and system. Background Technology

[0002] In some high-speed interconnection scenarios, communication systems typically require link training (LT) to ensure their performance. Link training needs to be performed on the electrical signal loops formed within the communication system. For example, in a communication system where a first network device is connected to a second network device sequentially through a first traditional optical module and a second traditional optical module, since both the first and second traditional optical modules include an Optical Digital Signal Processing (oDSP) chip, which has both an electrical signal transmitter and a receiving end, link training can be performed between the first network device and the first traditional optical module, and also between the second network device and the second traditional optical module.

[0003] However, to reduce the cost and power consumption of modules connecting network devices, the oDSP chip in the module is removed or partially omitted, resulting in an improved module. For communication systems including the improved module, since an electrical signal loop cannot be formed between the network device and the module, current link training methods that require an electrical signal loop are not applicable.

[0004] Therefore, there is an urgent need to provide a link training scheme suitable for communication systems that include the improved modules, so as to ensure the working performance of the communication system. Summary of the Invention

[0005] Based on this, this application provides a link training method, chip, device, and system that can perform link training on a communication system including the improved module to improve the performance of the improved module, thereby ensuring the working performance of the communication system including the improved module.

[0006] Firstly, this application provides a link training method applied to a transmitting device. The method may include, for example, the following steps: First, the transmitting device generates a first link training request; then, the transmitting device sends the first link training request to a receiving physical layer (PHY) chip, the first link training request instructing the receiving PHY chip to perform link training on a first parameter, which may include at least parameters of a receiving module, specifically optical module parameters; thereby, the transmitting device receives first status information indicating the status after link training on the first parameter based on the first link training request. In this way, even if the receiving module in the communication system does not include an oDSP chip, the receiving PHY chip can still perform link training on the parameters within its connected receiving module through end-to-end interaction of link training requests and status information between the transmitting device and the receiving PHY chip. For communication systems where current link training methods are not applicable (i.e., communication systems including improved modules), effective link training can be achieved, ensuring the performance of the communication system.

[0007] It is understood that the communication system addressed in this application can be understood to include: a transmitting PHY chip, a transmitting module, a receiving module, and a receiving PHY chip, wherein the transmitting PHY chip is connected to the receiving PHY chip sequentially through the transmitting module and the receiving module. At least one of the transmitting module and the receiving module is the improved module mentioned in this application. Depending on the transmitting module and the receiving module, the communication system has different architectures, and in different architecture communication systems, the transmitting device can correspond to either a transmitting PHY chip or a transmitting module. In this application, the transmitting end and the receiving end are described with reference to the direction of the interactive link training request; that is, the transmitting device sends a link training request to the receiving PHY chip, but the link training is performed on the link from the receiving PHY chip to the transmitting device.

[0008] In some possible implementations, in one case, the receiver module may include an optical module with parameters that are part of the optical module itself. For example, if the receiver module is a linear-drive pluggable optical module (LPO, also known as a linear direct-drive optical module or linear optical module), then the optical module parameters can be those of the driver continuous-time linear equalizer (DRV_CTLE) in the LPO. In another case, the receiver module may also include an active copper cable linear (ACC-Linear) module with parameters that are part of the ACC-Linear module itself. It should be noted that the structure of the ACC-Linear module differs from that of the LPO in that the ACC-Linear module does not include the components that convert electrical signals to optical signals (such as a laser) or the components that convert optical signals to electrical signals (such as a photodiode (PD)).

[0009] In some possible implementations, for the case where the receiver module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the transmitter PHY chip is connected to an LPO transmitter module, and the transmitter device can refer to the transmitter PHY chip. As another example, the communication system can be an LPO-traditional optical module (also called a retimed optical module) architecture, that is, the transmitter PHY chip is connected to a retimed optical module, and the transmitter device can refer to either the transmitter PHY chip or the transmitter module. As yet another example, the communication system can be an LPO-LRO architecture, that is, the transmitter PHY chip is connected to an LRO transmitter module, and the transmitter device can refer to either the transmitter PHY chip or the transmitter module. For the latter two examples, whether the transmitter device is specifically a transmitter PHY chip or a transmitter module depends on whether the oDSP chip in the transmitter module has the ability to send, receive, and parse training frames. If it does, the transmitter device can be a transmitter module; if it does not, the transmitter device can be a transmitter PHY chip.

[0010] In other possible implementations, for the case where the receiver module is an LRO, as an example, the communication system can be an LRO-LPO architecture, i.e., the transmitter module connected to the transmitter PHY chip is an LPO, then the transmitter device is the transmitter PHY chip; as another example, the communication system can be an LRO-retimed architecture, i.e., the transmitter module connected to the transmitter PHY chip is a retimed optical module, then the transmitter device is either the transmitter PHY chip or the transmitter module; as yet another example, the communication system can be an LRO-LRO architecture, i.e., the transmitter module connected to the transmitter PHY chip is an LRO, then the transmitter device is either the transmitter PHY chip or the transmitter module. For the latter two examples, whether the transmitter device is specifically a transmitter PHY chip or a transmitter module depends on whether the oDSP chip in the transmitter module has the ability to send, receive, and parse training frames. If it does, the transmitter device can be a transmitter module; if it does not, the transmitter device can be a transmitter PHY chip.

[0011] In this application, the LRO may include an oDSP chip, the transmitter (TX) of the receiver PHY chip is connected to the oDSP chip of the LRO, and the receiver (RX) of the transmitter PHY chip is not connected to the oDSP chip of the LRO.

[0012] In some possible implementations, if the first parameter only includes the parameters of the receiving module and not the parameters of the receiving PHY chip, as an example, if in the link training process, the transmitting device needs the receiving PHY chip to perform link training not only on the parameters of the receiving module but also on its own parameters, then the method may further include: First, the transmitting device generates a second link training request, which instructs the receiving PHY chip to perform link training on a second parameter, the second parameter including the parameters of the receiving PHY chip; then, the transmitting device sends the second link training request to the receiving PHY chip; thus, after the receiving PHY chip performs link training on the second parameter according to the second link training request, the transmitting device receives second status information sent by the receiving PHY chip, which indicates the status after performing link training on the second parameter based on the second link training request. For example, the parameters of the receiving PHY chip may include the tap coefficients in the TX-FFE (Forward Feedback Equalizer, FFE) of the receiving PHY chip. In this way, the transmitting device can instruct the receiving PHY chip to perform link training on its own parameters and those of the receiving module through two link training requests.

[0013] In some possible implementations, the first parameter may include not only the parameters of the receiving module but also the parameters of the receiving PHY chip. Therefore, the first link training request can instruct the receiving PHY chip not only to perform link training on the parameters of the receiving module but also to perform link training on its own parameters. In this way, the transmitting device can instruct the receiving PHY chip to perform link training on its own parameters and those of the receiving module through a single link training request, thus saving network resources to some extent.

[0014] In some possible implementations, the transmitting device can receive not only the first state information but also test information. This allows the transmitting device to test the link quality from the receiving PHY chip to the transmitting device based on the test information and obtain test results. Thus, after training the link from the receiving PHY chip to the transmitting device using the first parameters based on the first link training request, the link quality can be accurately understood, providing a reliable data foundation for further decisions in the link training process.

[0015] As an example, if the transmitting device determines that the test result does not meet the first condition, the method may further include: the transmitting device continuing to instruct the receiving PHY chip to perform link training on the first parameter. For example, firstly, the transmitting device generates a third link training request, which instructs the receiving PHY chip to continue performing link training on the first parameter; then, the transmitting device sends the third link training request to the receiving PHY chip; thereby, the transmitting device receives third status information, which indicates the status after performing link training on the first parameter based on the third link training request. The first parameter may include: parameters of the receiving module, and / or parameters of the receiving PHY chip. In this case, the first parameter may be the same as or different from the first parameter indicated in the first link training request; even if the first link training request and the third link training request indicate the same first parameter, the adjustment method of the first parameter indicated by the third link training request may be different from the adjustment method of the first parameter indicated by the first link training request. The first condition can include any one of the following: the change in the value of a first quality indicator is less than or equal to a first threshold. The first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. A smaller value of the first quality indicator indicates better link quality. For example, the first quality indicator is the bit error rate (BER). The change in the value of a second quality indicator is greater than or equal to a second threshold. The second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. A larger value of the second quality indicator indicates better link quality. For example, the second quality indicator is the signal-to-noise ratio (SNR). Thus, if the transmitting device determines that the test result does not meet the first condition (i.e., the parameters adjusted in this link training are not optimized to a satisfactory state, and the adjusted parameters can be further optimized), it continues to adjust the receiving PHY chip and / or the receiving module to achieve link training of the link from the receiving PHY chip to the transmitting device.

[0016] As another example, if the transmitting device determines that the test result meets the first condition, the method may further include: the transmitting device continuing to determine whether the test result meets a preset second condition. If it does, it can be considered that the current link training has enabled the link from the receiving PHY chip to the transmitting device to meet the expected performance requirements, and there is no need to continue link training for the link from the receiving PHY chip to the transmitting device. In this case, the transmitting device can generate local receiving end preparation information, which is used to indicate that the link training from the receiving PHY chip to the transmitting device is complete. In this way, the completion of link training in a certain direction can be identified through the second condition, providing a reliable basis for judging the link training progress of the communication system. If it does not meet the condition, it can be considered that the current link training has not enabled the link from the receiving PHY chip to the transmitting device to meet the expected performance requirements, and it is necessary to continue link training for the parameters of other parts of the link from the receiving PHY chip to the transmitting device. In this case, the transmitting device can perform link training for a third parameter, which includes the parameters of the transmitting module, and the parameters of the transmitting module are optical module parameters. In this way, by first training the parameters of the receiving PHY chip and / or the receiving module to ensure the test results meet the first condition, link training is then performed on the parameters of the transmitting module to ensure the test results meet the second condition. This enables effective link training of the link from the receiving PHY chip to the transmitting device in the communication system. The second condition can include any one of the following: the value of the first quality indicator is less than or equal to a third threshold, or the value of the second quality indicator is greater than or equal to a fourth threshold. For example, the first quality indicator is BER, and the second quality indicator is SNR.

[0017] In some possible implementations, the first link training request can be a training frame, which may include a control field to indicate link training for the first parameter. As an example, link training for the first parameter can be indicated by multiple reserved bits in the control field; as another example, it can be indicated by one reserved bit in the control field and a Coefficient select (coef_sel) field; as yet another example, it can be indicated by a combination of reserved values ​​in the Coefficient select field of the control field.

[0018] Secondly, this application also provides a link training method applied to a receiving-end PHY chip. This method may include, for example, the following steps: First, the receiving-end PHY chip receives a first link training request sent by a transmitting device. The first link training request instructs the receiving-end PHY chip to perform link training on a first parameter, which includes parameters of the receiving-end module, specifically optical module parameters. The receiving-end PHY chip then performs link training on the first parameter according to the first link training request. Finally, the receiving-end PHY chip sends first status information to the transmitting device, indicating the status after link training on the first parameter based on the first link training request. In this way, even if the receiving-end module in the communication system does not include an oDSP chip, the receiving-end PHY chip can still perform link training on the parameters within its connected receiving-end module through end-to-end link training requests and status information interaction between the transmitting device and the receiving-end PHY chip. This enables effective link training for communication systems where current link training methods are not applicable (i.e., communication systems including improved modules), ensuring the performance of the communication system.

[0019] In some possible implementations, the receiver module includes an optical module with parameters that are the same as those in the optical module; or, the receiver module includes an ACC-Linear module with parameters that are the same as those in the ACC-Linear module.

[0020] In some possible implementations, for the case where the receiver module is an LPO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LPO.

[0021] In some other possible implementations, for the case where the receiver module is an LRO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LRO.

[0022] In this embodiment of the application, the LRO includes an optical digital signal processor (oDSP) chip, the transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

[0023] In some possible implementations, the receiving PHY chip performs link training on the first parameters according to the first link training request, which may include: in response to the first link training request, the receiving PHY chip performs link training on the parameters of the receiving module through the built-in integrated circuit (IIC or I2C) bus.

[0024] In some possible implementations, the method may further include: the receiving PHY chip receiving a second link training request sent by the transmitting device, the second link training request instructing the receiving PHY chip to perform link training on a second parameter, the second parameter including parameters of the receiving PHY chip; the receiving PHY chip performing link training on the second parameter according to the second link training request; and the receiving PHY chip sending second status information to the transmitting device, the second status information indicating the status after performing link training on the second parameter based on the second link training request.

[0025] In some possible implementations, the first parameter may also include parameters of the receiving PHY chip.

[0026] In some possible implementations, the first link training request is a training frame, which includes a control field used to indicate link training for the first parameter. Specifically, link training for the first parameter can be indicated by multiple reserved bits in the control field; alternatively, it can be indicated by one reserved bit in the control field and a parameter selection field; or, it can be indicated by a combination of reserved values ​​from the parameter selection field in the control field.

[0027] It should be noted that for the relevant explanations in the second aspect, please refer to the corresponding description in the first aspect.

[0028] Thirdly, this application also provides a chip, which includes an interface circuit and a processing circuit. The processing circuit is used to generate a first link training request; the interface circuit is used to send the first link training request to a receiving PHY chip, the first link training request instructing the receiving PHY chip to perform link training on a first parameter, the first parameter including at least parameters of the receiving module, which are optical module parameters; the interface circuit is also used to receive first state information, the first state information indicating the state after link training on the first parameter based on the first link training request.

[0029] In some possible implementations, in one case, the receiver module may include an optical module whose parameters are those of the optical module itself. For example, if the receiver module is an LPO, then the optical module parameters can be those of the DRV_CTLE parameter in the LPO. In another case, the receiver module may also include an ACC-Linear module whose parameters are those of the ACC-Linear module itself.

[0030] In some possible implementations, for the case where the receiving module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the chip protected in this application is a transmitting PHY chip, and the transmitting module connected to the transmitting PHY chip is an LPO. In this case, the transmitting device can refer to the transmitting PHY chip. As another example, the communication system can be an LPO-retimed architecture, that is, the chip protected in this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is a retimed optical module. In this case, the transmitting device can refer to the transmitting PHY chip or the transmitting module. As yet another example, the communication system can be an LPO-LRO architecture, that is, the chip protected in this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is an LRO. In this case, the transmitting device can refer to the transmitting PHY chip or the transmitting module.

[0031] In some other possible implementations, for the case where the receiving module is an LRO, as an example, the communication system can be an LRO-LPO architecture, that is, the chip protected in this application is a transmitting PHY chip, and the transmitting module connected to the transmitting PHY chip is an LPO, then the transmitting device is a transmitting PHY chip; as another example, the communication system can be an LRO-retimed architecture, that is, the chip protected in this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is a retimed optical module, then the transmitting device is a transmitting PHY chip or a transmitting module; as yet another example, the communication system can be an LRO-LRO architecture, that is, the chip protected in this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is an LRO, then the transmitting device is a transmitting PHY chip or a transmitting module.

[0032] In this application, the LRO may include an oDSP chip, the TX pin of the receiving PHY chip is connected to the oDSP chip of the LRO, and the RX pin of the transmitting PHY chip is not connected to the oDSP chip of the LRO.

[0033] In some possible implementations, the processing circuit is further configured to generate a second link training request, which instructs the receiving PHY chip to perform link training on the second parameters, the second parameters including the parameters of the receiving PHY chip; the interface circuit is further configured to send the second link training request to the receiving PHY chip; the interface circuit is further configured to receive second status information sent by the receiving PHY chip, the second status information indicating the status after link training on the second parameters based on the second link training request.

[0034] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0035] In some possible implementations, the interface circuit is also used to receive test information; the processing circuit is also used to test the link quality from the receiving PHY chip to the transmitting device based on the test information and obtain test results.

[0036] In some possible implementations, the processing circuit is further configured to generate a third link training request if it is determined that the test result does not meet the first condition. The third link training request is used to instruct the receiving PHY chip to continue link training on the first parameter. The interface circuit is further configured to send the third link training request to the receiving PHY chip. The interface circuit is further configured to receive third state information, which indicates the state after link training on the first parameter based on the third link training request.

[0037] As an example, the first condition may include any one of the following: the change in the value of the first quality indicator is less than or equal to the first threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the change in the value of the second quality indicator is greater than or equal to the second threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0038] In some possible implementations, the processing circuit is also used to perform link training on the third parameter if it is determined that the test result meets the first condition but not the second condition. The third parameter includes the parameters of the transmitting module, which are the parameters of the optical module.

[0039] As an example, the second condition may include any one of the following conditions: the value of the first quality indicator is less than or equal to the third threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the value of the second quality indicator is greater than or equal to the fourth threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0040] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0041] It should be noted that for the relevant explanations of the third aspect, please refer to the corresponding description of the first aspect.

[0042] Fourthly, this application also provides a chip, which should be a receiver PHY chip. The chip includes an interface circuit and a processing circuit. The interface circuit is used to receive a first link training request sent by a transmitting device, the first link training request instructing the receiver PHY chip to perform link training on first parameters, the first parameters including parameters of the receiver module, which are optical module parameters; the processing circuit is used to perform link training on the first parameters according to the first link training request; the interface circuit is also used to send first status information to the transmitting device, the first status information indicating the status after link training on the first parameters based on the first link training request.

[0043] In some possible implementations, the receiver module includes an optical module with parameters that are the same as those in the optical module; or, the receiver module includes an ACC-Linear module with parameters that are the same as those in the ACC-Linear module.

[0044] In some possible implementations, for the case where the receiver module is an LPO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LPO.

[0045] In some other possible implementations, for the case where the receiver module is an LRO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LRO.

[0046] In this embodiment of the application, the LRO includes an optical digital signal processor (oDSP) chip, the transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

[0047] In some possible implementations, the processing circuitry is specifically used to: perform link training on the parameters of the receiving module via the IIC bus in response to a first link training request.

[0048] In some possible implementations, the interface circuit is further configured to receive a second link training request sent by the transmitting device, the second link training request being used to instruct the receiving PHY chip to perform link training on the second parameters, the second parameters including the parameters of the receiving PHY chip; the processing circuit is further configured to perform link training on the second parameters according to the second link training request; the interface circuit is further configured to send second status information to the transmitting device, the second status information indicating the status after performing link training on the second parameters based on the second link training request.

[0049] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0050] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0051] It should be noted that the relevant explanations for the fourth aspect can be found in the corresponding descriptions for the second aspect.

[0052] Fifthly, this application also provides a link training apparatus, which is applied to a transmitting end device. The apparatus may include, for example, a processing unit, a transmitting unit, and a receiving unit. The processing unit is used to generate a first link training request; the transmitting unit is used to send the first link training request to a receiving end PHY chip, the first link training request instructing the receiving end PHY chip to perform link training on a first parameter, the first parameter including at least parameters of the receiving end module, which are optical module parameters; the receiving unit is used to receive first state information, the first state information indicating the state after link training on the first parameter based on the first link training request.

[0053] In some possible implementations, in one case, the receiver module may include an optical module whose parameters are those of the optical module itself. For example, if the receiver module is an LPO, then the optical module parameters can be those of the DRV_CTLE parameter in the LPO. In another case, the receiver module may also include an ACC-Linear module whose parameters are those of the ACC-Linear module itself.

[0054] In some possible implementations, for the case where the receiver module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LPO, then the transmitter device can refer to the transmitter PHY chip; as another example, the communication system can be an LPO-retimed architecture, that is, the transmitter module connected to the transmitter PHY chip is a retimed optical module, then the transmitter device can refer to the transmitter PHY chip or the transmitter module; as yet another example, the communication system can be an LPO-LRO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LRO, then the transmitter device can refer to the transmitter PHY chip or the transmitter module.

[0055] In some other possible implementations, for the case where the receiver module is an LRO, as an example, the communication system can be an LRO-LPO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LPO, then the transmitter device is the transmitter PHY chip; as another example, the communication system can be an LRO-retimed architecture, that is, the transmitter module connected to the transmitter PHY chip is a retimed optical module, then the transmitter device is either the transmitter PHY chip or the transmitter module; as yet another example, the communication system can be an LRO-LRO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LRO, then the transmitter device is either the transmitter PHY chip or the transmitter module.

[0056] In this application, the LRO may include an oDSP chip, the TX pin of the receiving PHY chip is connected to the oDSP chip of the LRO, and the RX pin of the transmitting PHY chip is not connected to the oDSP chip of the LRO.

[0057] In some possible implementations, the processing unit is further configured to generate a second link training request, which instructs the receiving PHY chip to perform link training on the second parameters, the second parameters including the parameters of the receiving PHY chip; the sending unit is further configured to send the second link training request to the receiving PHY chip; and the receiving unit is further configured to receive second status information sent by the receiving PHY chip, the second status information indicating the status after link training on the second parameters based on the second link training request.

[0058] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0059] In some possible implementations, the receiving unit is also used to receive test information; the processing unit is also used to test the link quality from the receiving PHY chip to the transmitting device based on the test information and obtain test results.

[0060] In some possible implementations, the processing unit is further configured to generate a third link training request if it is determined that the test result does not meet the first condition. The third link training request is used to instruct the receiving PHY chip to continue link training on the first parameter. The sending unit is further configured to send the third link training request to the receiving PHY chip. The receiving unit is further configured to receive third status information, which indicates the status after link training on the first parameter based on the third link training request.

[0061] As an example, the first condition may include any one of the following: the change in the value of the first quality indicator is less than or equal to the first threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the change in the value of the second quality indicator is greater than or equal to the second threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0062] In some possible implementations, the processing unit is further configured to perform link training on the third parameter if it is determined that the test result satisfies the first condition but not the second condition. The third parameter includes the parameters of the transmitting module, which are the parameters of the optical module.

[0063] As an example, the second condition may include any one of the following conditions: the value of the first quality indicator is less than or equal to the third threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the value of the second quality indicator is greater than or equal to the fourth threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0064] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0065] It should be noted that for the relevant explanations of the fifth aspect, please refer to the corresponding description of the first aspect.

[0066] Sixthly, this application also provides a link training apparatus, which should be a receiving PHY chip. The apparatus may include at least a receiving unit, a transmitting unit, and a processing unit. The receiving unit is used to receive a first link training request sent by a transmitting device, the first link training request instructing the receiving PHY chip to perform link training on first parameters, the first parameters including parameters of the receiving module, which are optical module parameters; the processing unit is used to perform link training on the first parameters according to the first link training request; and the transmitting unit is used to send first status information to the transmitting device, the first status information indicating the status after link training on the first parameters based on the first link training request.

[0067] In some possible implementations, the receiver module includes an optical module with parameters that are the same as those in the optical module; or, the receiver module includes an ACC-Linear module with parameters that are the same as those in the ACC-Linear module.

[0068] In some possible implementations, for the case where the receiver module is an LPO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LPO.

[0069] In some other possible implementations, for the case where the receiver module is an LRO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LRO.

[0070] In this embodiment of the application, the LRO includes an optical digital signal processor (oDSP) chip, the transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

[0071] In some possible implementations, the processing unit is specifically used to: perform link training on the parameters of the receiving module via the IIC bus in response to the first link training request.

[0072] In some possible implementations, the receiving unit is further configured to receive a second link training request sent by the transmitting device, the second link training request being used to instruct the receiving PHY chip to perform link training on the second parameters, the second parameters including the parameters of the receiving PHY chip; the processing unit is further configured to perform link training on the second parameters according to the second link training request; and the sending unit is configured to send second status information to the transmitting device, the second status information indicating the status after performing link training on the second parameters based on the second link training request.

[0073] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0074] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0075] It should be noted that for the relevant explanations in the sixth aspect, please refer to the corresponding description in the second aspect.

[0076] In a seventh aspect, this application provides a communication device, which includes an interface and a processor. The interface is used to receive instructions and transmit them to the processor; the processor is used to execute the methods corresponding to the first aspect, the second aspect, and their possible implementations described above.

[0077] Eighthly, this application provides a communication system, which includes a transmitting device and a receiving PHY chip. The transmitting device is used to execute the method corresponding to the first aspect and its possible implementations described above; the receiving PHY chip is used to execute the method corresponding to the second aspect and its possible implementations described above.

[0078] Eighthly, this application also provides a storage medium storing instructions that, when executed on a processor, implement the methods corresponding to the first aspect, the second aspect, and their possible implementations.

[0079] Ninthly, this application also provides a program product, the program product including a program that, when the program is run on a processor, implements the methods corresponding to the first aspect, the second aspect, and their possible implementations. Attached Figure Description

[0080] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0081] Figure 1 This is a schematic diagram of the structure of a communication system with a retimed-retimed architecture according to an embodiment of this application;

[0082] Figure 2a This is a schematic diagram of the structure of a communication system with an LPO-LPO architecture according to an embodiment of this application;

[0083] Figure 2b This is a schematic diagram of the structure of a communication system with an LRO-LRO architecture according to an embodiment of this application;

[0084] Figure 3 This is a schematic diagram of a C2C architecture communication system according to an embodiment of this application;

[0085] Figure 4 This is a schematic diagram of a general structure of a communication system to which the embodiments of this application are applicable;

[0086] Figure 5 This is a flowchart illustrating a link training method 100 in an embodiment of this application.

[0087] Figure 6 This is a flowchart illustrating an example of a link training method in the embodiments of this application;

[0088] Figure 7This is a schematic diagram of the structure of a communication system with a retimed-LPO architecture according to an embodiment of this application;

[0089] Figure 8 This is a schematic diagram of the structure of a communication system with a retimed-LRO architecture according to an embodiment of this application;

[0090] Figure 9 This is a schematic diagram of the structure of a communication system with an LRO-LPO architecture according to an embodiment of this application;

[0091] Figure 10 This is a schematic diagram of the structure of a chip 1000 in an embodiment of this application;

[0092] Figure 11 This is a schematic diagram of the structure of a communication device 1100 in an embodiment of this application;

[0093] Figure 12 This is a schematic diagram of the structure of a communication device 1200 according to an embodiment of this application;

[0094] Figure 13 This is a schematic diagram of the structure of a communication system 1300 in an embodiment of this application. Detailed Implementation

[0095] To ensure the performance of communication systems, communication standards (e.g., IEEE 802.3CL72, CL136, and CL162, and the Optical Internetworking Forum (OIF) Common Management Interface Specification (CMIS) protocol) define the relevant content of link training. Link training can be understood as an important stage in preparing the communication system for operation, involving the tuning and configuration of parameters, including equalization parameters, for the electrical signal loops within the system. The standard is called linktraining (LT). Link training can be divided into three steps: first, frame locking, which can be understood as the identification of training frames; second, the training process, used to complete parameter interaction and negotiation; and third, parameter updating. It should be noted that the embodiments in this application do not involve improvements to the above three steps of link training, therefore, these three steps will not be described in detail.

[0096] Currently, in some communication scenarios, the architecture of communication systems is typically as follows: Figure 1As shown. This communication system may include network device 1, a traditional optical module (also called a retimed optical module) 1, a traditional optical module 2, and network device 2. The traditional optical module 1 may include at least: an oDSP chip 11, a laser driver (Laser DRV) 12, a laser 13, a PD 14, and a trans-impedance amplifier (TIA) 15. Similarly, the traditional optical module 2 may include at least: an oDSP chip 21, a laser DRV 22, a laser 23, a PD 24, and a TIA 25. Figure 1 Link training of a communication system (which can be called a retimed-retimed architecture communication system) can include: link training of electrical signal loop 1 between network device 1 and traditional optical module 1, and link training of electrical signal loop 2 between network device 2 and traditional optical module 2. Electrical signal loop 1 can refer to: from TX 1 of PHY chip 1 of network device 1, sequentially through RX 11 near network device 1 in oDSP chip 11 of traditional optical module 1, and TX 14 near network device 1 in oDSP chip 11 of traditional optical module 1, to RX 2 of PHY chip 1 of network device 1. Similarly, electrical signal loop 2 can refer to: from TX 3 of PHY chip 2 of network device 2, sequentially through RX 21 near network device 2 in oDSP chip 21 of traditional optical module 2, and TX 24 near network device 2 in oDSP chip 21 of traditional optical module 2, to RX 4 of PHY chip 2 of network device 2. The oDSP chip 11 may also include TX 12 and RX 13 near the traditional optical module 2, and the oDSP chip 21 may also include TX 22 and RX 23 near the traditional optical module 1. Taking the electrical signal loop 1 as an example, the data interaction between the network device 1 and the oDSP chip 11 of the traditional optical module 1 can be achieved through different buses under different standards. For example, according to the relevant provisions of IEEE 802.3, the data interaction between the network device 1 and the oDSP chip 11 of the traditional optical module 1 can be achieved through a chip-to-module (C2M) bus; as another example, according to the relevant provisions of the OIF CMIS protocol, the data interaction between the network device 1 and the oDSP chip 11 of the traditional optical module 1 can be achieved through an out-of-band method such as a two-wire interface (TWI, also known as an inter-integrated circuit (IIC or I2C)) bus.

[0097] It should be noted that for retimed-retimed architecture communication systems, link training can be performed on electrical signal loop 1 and electrical signal loop 2 separately because both traditional optical modules 1 and 2 include oDSP chips, enabling the network device to form an electrical signal loop with the oDSP chip of the traditional optical module. However, considering the high power consumption of the oDSP chip in the traditional optical module (accounting for more than 50% of the total power consumption) and its high cost, the Linear Optical Engine (LPO) was developed. Since the LPO uses a linear optical engine interface to connect to network devices, and the linear optical engine interface has significant advantages in terms of power consumption, cost, and latency, the LPO is likely to be widely used in future high-speed interconnected communication systems.

[0098] An LPO (Light Optical Point) can include at least a Laser DRV, Laser, PD (Power Distribution Module), and TIA (Transmission Interchange Amplifier). Compared to traditional optical modules, it removes the oDSP (Optical DSP chip) and offloads its equalization capability to the serializer / deserializer (SerDes) on the application-specific integrated circuit (ASIC) side of the network equipment to which the LPO is connected. The LPO can integrate a Continuous Time Linear Equalizer (CTLE) to compensate for channel impairments. Furthermore, the SerDes on the ASIC side of the network equipment connected to the LPO include a Feedforward Equalizer (FFE) to reduce the link's BER (Breakpoint Error) through stronger equalization performance. Since there are many equalization parameters to be configured and they are interconnected, the impact of each equalization parameter on the end-to-end communication link needs to be considered.

[0099] If Figure 1 If the traditional optical module in the communication system shown is replaced with an LPO, then the communication system can be referred to... Figure 2a As shown (which can be called an LPO-LPO architecture communication system), since LPO 1 does not include an oDSP chip, the electrical signal entering LPO 1 from network device 1 is converted into an optical signal through Laser DRV 12 and Laser 13, and cannot be directly converted back to network device 1 in the form of an electrical signal. Therefore, an electrical signal loop cannot be formed between the network device and LPO 1. Therefore, current link training schemes for retimed-retimed architecture communication systems are not applicable to link training of LPO-LPO architecture communication systems.

[0100] Furthermore, some current communication scenarios can also include communication systems from network device 1 to network device 2 (which can be called chip-to-chip (C2C) communication systems), such as... Figure 3 As shown. For C2C communication systems, link training can be directly performed on the electrical signal loop 3 between network device 1 and network device 2. However, since C2C communication systems do not involve optical modules, link training for C2C communication systems does not include the training process for equalization parameters within the optical modules. For LPO-LPO architecture communication systems, this is equivalent to not considering the impact of equalization parameters within the line LPO on the entire communication system. Therefore, link training for C2C communication systems is not applicable to link training for LPO-LPO architecture communication systems.

[0101] Since LPOs do not include oDSP chips, the transmitting end performance (e.g., the performance of Testpoint (TP) 2) of communication systems including LPOs (such as LPO-LPO architecture communication systems) is not ideal. Based on this, embodiments of this application provide a link training method, at least applicable to communication systems including LPOs (such as LPO-LPO architecture communication systems), enabling LPO-integrated communication systems to undergo link training using the method provided in this application. In communication systems that have completed link training, the performance of LPOs is improved, thereby enhancing the operating performance of communication systems including LPOs and making it possible for such communication systems to be widely used in future high-speed interconnected communication systems. Here, TP2 refers to the optical output point of the optical module as defined in IEEE 802.3. Figure 2a For example, in the link from network device 1 through LPO 1 and LPO 2 to network device 2, TP2 can refer to the location of the light output point of Laser 13; in the link from network device 2 through LPO 2 and LPO 1 to network device 1, TP2 can refer to the location of the light output point of Laser 23. IEEE 802.3 not only defines the TP2 point but also sets requirements for TP2 point indicators as a criterion for judging whether the performance of the communication system (such as the performance of the transmitting end of the communication system) is ideal.

[0102] The communication system architecture to which the link training method provided in this application is applicable can be found in [reference needed]. Figure 4 See also Figure 4The communication system may include: network device A (also known as host A, hereinafter referred to as HA), module A (also known as module A, hereinafter referred to as MA), module B (also known as module B, hereinafter referred to as MB), and network device B (also known as host B, hereinafter referred to as HB). HA is connected to HB sequentially through MA and MB. HA can connect to MA via an IIC bus or a bidirectional data interface. The IIC bus is used for HA to configure the parameters of MA, and the data interface is used for sending and receiving service data between HA and MA. Similarly, HB can connect to MB via an IIC bus or a bidirectional data channel. It should be noted that at least one of MA and MB is an improved optical module (such as an LPO) obtained by modifying a traditional optical module. It should also be noted that a network device can be called a host, and from a hardware implementation perspective, it can be implemented using a PHY chip; therefore, a network device can also be a PHY chip.

[0103] The following is combined with Figure 4 The implementation of the link training method provided in the embodiments of this application will be described.

[0104] It should be noted that in the following text, " Figure 4 The link training process from HB to HA is used as an example for illustration. The transmitting device corresponds to the PHY chip or MA of HA, and the receiving PHY chip corresponds to the PHY chip of HB. The link training method provided in this application embodiment may include, for example, the following steps: First, HA generates a link training request 1 and sends the link training request 1 to the PHY chip of HB. The link training request 1 is used to instruct the PHY chip of HB to perform link training on a first parameter. The first parameter may include at least the parameters of the MB, which are optical module parameters. Next, the PHY chip of HB performs link training on the first parameter based on the received link training request 1 to obtain status information 1. The status information 1 indicates the status after performing link training on the first parameter based on the link training request 1. Then, HA receives the status information 1. In this way, even if the receiving module in the communication system does not include an oDSP chip, the receiving PHY chip can still perform link training on the parameters of the receiving module it is connected to through end-to-end link training requests and the exchange of status information. For example, based on the HA indication, the HB PHY chip can perform link training on the parameters of the end-to-end link from HB to HA, including the parameters of MB. In this way, effective link training can be achieved for communication systems where current link training is not applicable, thus ensuring the working performance of the communication system.

[0105] The optical module parameters can refer to parameters used in either the optical module or the ACC-Linear module. It's important to note that the ACC-Linear module differs from the LPO in that it lacks devices that convert electrical signals to optical signals (such as lasers and PDs). An ACC-Linear module may include, for example, a linear equalization chip to improve signal equalization performance. If the MA is an ACC-Linear module, the MB is also an ACC-Linear module. For example, if the receiver module is an LPO, the optical module parameters can be the CTLE parameters in the Laser DRV of the LPO; similarly, if the receiver module is an ACC-Linear module, the optical module parameters can be the equalizer parameters in the linear equalization chip of the ACC-Linear module. The following description uses an optical module as the receiver module; replacing the optical module with an ACC-Linear module will not affect the description of the link training process of the communication system.

[0106] The parameters of the MB can include the parameters on the MB that need to be trained on the link. For example, the MB can be... Figure 2a As shown in the LPO2 example, the parameters of MB can include the equalizer parameters in the Laser DRV 22 of LPO 2. State information 1 can be used to indicate the result after HB performs link training on the first parameter. For example, state information 1 can include the specific parameters and the degree of modification made by HB to MB when HB performs link training on the first parameter. The equalizer parameters, depending on the equalizer type, can specifically include, but are not limited to, finite impulse response (FIR, also known as FFE) parameters or CTLE parameters. It is understood that CTLE belongs to analog circuit equalizers.

[0107] It should be noted that the HA sends a link training request 1 to the HB's PHY chip, instructing the HB's PHY chip to perform link training on the first parameter. In response to this link training request 1, the HB's PHY chip performs link training on the first parameter on the TX side, which includes the parameters of the MB's TX side. Through link training on the first parameter, the link quality from the HB's PHY chip to the HA is improved. Therefore, link training on the first parameter essentially refers to link training on the link from the HB's PHY chip to the HA. Based on this, it can be understood that the link training performed by the receiving PHY chip on the first parameter can be understood as link training on the link from the receiving PHY chip to the transmitting device.

[0108] For a link training request, the following may be included, but are not limited to: parameter adjustment type, specific parameters to be adjusted, and adjustment value. In the case of the training frame corresponding to the link training request, the content included in the link training request can be reflected through the control field in the training frame. For example, the parameter adjustment type can indicate individual coefficient control. When the Initial condition request (ic_req) field in the control field is 00, it indicates that the parameter adjustment type is individual coefficient control. The specific parameters to be adjusted can be indicated through the Coefficient select (coef_sel) field. Different values ​​of the coef_sel field indicate different parameters to be adjusted. The adjustment value can be understood as the adjustment step size (or step value), such as +3, -2, etc. The adjustment value will affect the performance of the equalizer in the receiving module, thereby changing the equalizer's performance curve through the adjustment value of the equalizer parameters.

[0109] The status information may include, but is not limited to: the adjustment results corresponding to the link training, the specific parameters that were adjusted, and the status of the adjusted parameters. When the status information corresponds to a training frame, the content included in the above status information can be reflected through the status field in the training frame. Specifically, the adjustment results corresponding to the link training can indicate whether the parameters that need to be adjusted for a particular link training request have been adjusted; the specific parameters that were adjusted can indicate the parameters that were actually adjusted during the link training process in response to a particular link training request; and the status of the adjusted parameters can indicate whether each adjusted parameter has been adjusted to its limit (i.e., the boundary or range of possible values ​​for that parameter). It should be noted that, in addition to receiving status information, the sending device may also receive test information in the corresponding training frame. This test information can be the training pattern field in the training frame. The training pattern field can be understood as a test sequence, which is used by the sending device to test the link quality of the link transmitting the training frame. Since the link is in a state after responding to the link training request and training the first parameter, testing the link quality is equivalent to obtaining the training effect of this link training, which can provide reliable data for the next decision on the link training.

[0110] It should be noted that the communication system including LPO mentioned above refers to at least one module connected to the PHY chip in the communication system, which is an improved optical module obtained by modifying a traditional optical module. Compared with the traditional optical module, the improved optical module eliminates or omits part of the oDSP chip in the traditional optical module. The optical module that eliminates the oDSP chip can be an LPO, for example... Figure 2a The LPO 1 or LPO 2 shown; the optical module with part of the oDSP chip omitted can be a Transmit Retimed Optics (TRO, also known as a Tx-retimed optical module or LRO, hereinafter referred to as LRO). An LRO can also be understood as: an optical module including an oDSP chip, where the network device connected to the optical module includes TX and RX connections. The TX of the network device is connected to the oDSP chip of the optical module, while the RX of the network device is not connected to the oDSP chip of the optical module, such as... Figure 2b LRO 1 or LRO 2. In other cases, the LRO may also include a complete oDSP chip; see the structure below. Figure 1 The traditional optical module 1 or traditional optical module 2 is used, but in some cases, such as when starting the end-to-end link training process provided in the embodiments of this application, the oDSP chip connected to the RX of the network device is turned off. The actual working structure can be found in [reference]. Figure 2b The LRO 1 or LRO 2 shown.

[0111] Figure 2b The diagram illustrates a communication system based on an LRO-LRO architecture. Within this LRO-LRO architecture communication system, [the system can...]. Figure 2a The LPO in the text is replaced with LRO. LRO 1 includes oDSP chip 11, and... Figure 1 Compared to the oDSP chip 11 shown, it only includes RX 11 near network device 1 and TX 12 near LRO 2; similarly, LRO 2 includes oDSP chip 21, and... Figure 1 Compared to the oDSP chip 21 shown, it only includes RX 21 near network device 2 and TX 22 near LRO 1.

[0112] It should be noted that in the communication system applicable to the embodiments of this application, both ends can be improved optical modules (LPO or LRO). For details, please refer to... Figure 2a , Figure 2b as well as Figure 9 The relevant description; or, one end can be an improved optical module and the other end a traditional optical module, as detailed below. Figure 7 or Figure 8 Related descriptions.

[0113] It should be noted that in the communication system of this application embodiment, the receiving end may include a receiving end PHY chip and a receiving end module, and the transmitting end may include a transmitting end PHY chip and a transmitting end module, so as to Figure 4 For example, if the link training is for a link from HB to HA, then the transmitting PHY chip can correspond to the PHY chip in HA, the receiving PHY chip can correspond to the PHY chip in HB, the transmitting module can correspond to MA, and the receiving module can correspond to MB. If the link training is for a link from HA to HB, then the transmitting PHY chip can correspond to the PHY chip in HB, the receiving PHY chip can correspond to the PHY chip in HA, the transmitting module can correspond to MB, and the receiving module can correspond to MA. For the transmitting device mentioned in the embodiments of this application, in the scenario where the transmitting module is LPO, the transmitting device can be understood as the transmitting PHY chip; in the scenario where the transmitting module is LRO, the transmitting device can be the oDSP chip in LRO (i.e., the oDSP chip connected to the TX of the transmitting PHY chip), or it can be the transmitting PHY chip itself.

[0114] It should be noted that the PHY chip can be implemented using an ASIC chip, and can also be called an electrical chip. The ASIC-side SerDes mentioned above can be integrated with the ASIC chip or set up independently of the ASIC chip.

[0115] It should be noted that, in this application embodiment, "network device" is a general term for any device that may exist in the network. Specifically, it can be a network device in the conventional sense, such as a switch, router, or firewall, or a terminal device such as a user host or vehicle host. The PHY chip in the network device may include firmware or main control board control software. Firmware can be understood as the operating system of SerDes. Firmware is a control software in the PHY chip and can be deployed in the microcontroller unit (MCU) of SerDes. Its functions include controlling the registers in the equalizer of SerDes. Firmware can execute the methods provided in this application embodiment. The network device where the PHY chip is located may include a main control board and multiple line cards. The main control board is used to control each line card. The main control board control software can execute the methods provided in this application embodiment, and send the obtained link training parameter values ​​down through the main control board. It controls the PMD layer (i.e., the registers of SerDes, etc.) through protocols or other channels to realize the downward configuration of the link training parameter values.

[0116] It should be noted that the method provided in this application embodiment can be applied to link training in various data transmission scenarios, including but not limited to: data centers, supercomputing nodes, artificial intelligence data center networks (AIDCN), etc., and can also be applied to the bearer network of 5G wireless networks, such as the fronthaul bearer scenario.

[0117] It should be noted that for communication systems, end-to-end link training can be performed simultaneously in both directions. When link training in both directions is completed, the bidirectional link training of the communication system is complete. If link training in one direction fails, the bidirectional link training for the communication system is considered to have failed, and link training in both directions needs to be restarted.

[0118] It should be noted that, in this embodiment, the link from the receiving PHY chip to the transmitting device is a link in a specified direction, meaning the link runs from the receiving PHY chip to the transmitting device. The phrase "link from the receiving PHY chip to the transmitting device" in the following text can be understood as "the link in the direction from the receiving PHY chip to the transmitting device".

[0119] In this embodiment, a maximum allowed time (e.g., max-timer) or a maximum number of training iterations can be set for the entire link training process. Link training failure can mean that the link training is not completed within the max-timer. Once the link training duration exceeds the max-timer limit, the link training is considered to have failed, and the entire link training process can be restarted by resetting the link training. Alternatively, link training failure can mean that the maximum number of training iterations has been reached, but the link training is still not completed. In this case, the link training is considered to have failed, and the entire link training process can be restarted by resetting the link training. In the entire link training process, one link training iteration can be understood as: HB performing link training on its own parameters and / or MB parameters based on the link training request sent by HA; or, HA performing link training on MA parameters after HB performs link training on its own parameters and / or MB parameters based on the link training request sent by HA. When setting a maximum number of training iterations, the number of link training iterations is incremented by one after each link training iteration. If the number of link training iterations does not reach the maximum number of training iterations and the link training is not completed, then the next link training session will continue. If the number of link training iterations does not reach the maximum number of training iterations, but the link training is completed, then the link training in this direction will end, and the link training for the communication system will be completed after the link training in the opposite direction is completed. If the number of link training iterations reaches the maximum number of training iterations and the link training is not completed, then the link training is considered to have failed. Link training completion can mean that after link training, the link quality has reached the expected effect, and the values ​​of the metrics characterizing the link quality meet preset thresholds, such as BER being less than or equal to a preset BER threshold, or the link SNR being greater than or equal to a preset SNR threshold.

[0120] To provide a clearer description of the embodiments of this application, the methods provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0121] Figure 5 This is a flowchart illustrating a link training method 100 provided in an embodiment of this application. The method 100 describes the interaction between the transmitting end device and the receiving end PHY chip in a communication system during the link training process. The communication system can correspond to the above... Figure 2a , Figure 2b or Figure 4 The communication system shown can also correspond to the following text. Figure 7 , Figure 8 or Figure 9The communication system shown. The steps executed by the transmitting device in method 100 can be understood as being implemented by the transmitting PHY chip, specifically by the firmware in the transmitting PHY chip or the main control board control software, or by the oDSP chip of the LRO (which is the transmitting module) (the oDSP chip of the LRO needs to have the ability to send, receive, and parse training frames); similarly, the steps executed by the receiving PHY chip in method 100 can be understood as being implemented by the firmware in the receiving PHY chip or the main control board control software.

[0122] like Figure 5 As shown, the method 100 may include, for example, the following steps S101 to S106:

[0123] S101, the transmitting device generates a first link training request. The first link training request is used to instruct the receiving PHY chip to perform link training on a first parameter. The first parameter includes the parameters of the receiving module, which are optical module parameters.

[0124] In a communication system, if it is necessary to perform link training on the link from the receiving PHY chip to the transmitting device, the transmitting device can generate a first link training request and send the first link training request to the receiving PHY chip as an indication to trigger the receiving PHY chip to perform link training on the link from the receiving PHY chip to the transmitting device.

[0125] The first link training request can be a training frame in the link training. This training frame may include a frame marker field, a control field, a state field, and a training mode field. The control field is used to indicate that the first parameter is to be trained. The bits in the control field and the state field of this training frame can be encoded, for example, using Differential Manchester Encoding (DME).

[0126] It is understandable that the receiving PHY chip that receives the training frame can determine the first parameter that needs to be trained on the link based on the control field in the training frame, and perform link training on the first parameter.

[0127] The first parameter can include the parameters of the receiver module. The parameters of the receiver module can refer to the parameters within the receiver module connected to the receiver PHY chip that require link training. If the receiver module is an optical module such as an LPO or LRO, then the parameters of the receiver module can refer to the equalizer parameters of the DRV in the LPO or LRO; or, if the receiver module is an ACC-Linear module, then the parameters of the receiver module can be the equalizer parameters of the DRV in the ACC-Linear module.

[0128] The examples in method 100 are all based on Figure 4 In the communication system shown, the link training of the link from HB to HA is used as an example for explanation. That is, the transmitting end corresponds to HA and MA, the receiving end corresponds to HB and MB, the receiving end PHY chip corresponds to the PHY chip of HB, and the receiving end module corresponds to MB.

[0129] In this case, the parameters of the receiving module can refer to the parameters that need to be trained on the link within the MB. For example, it can be the equalization parameters of DRV_CTLE (i.e., CTLE on DRV) within the MB, specifically at least one of dc_gain, boost0, or boost1 of DRV_CTLE within the MB.

[0130] The control field of a training frame can include 16 bits, from bit 0 to bit 15. The following explanation uses the definition of the control field in a training frame in IEEE 802.3CL136 as an example. The four known combinations of values ​​for bits 2, 3, and 4 of the control field in a training frame are used to indicate link training of the PHY chip link training parameters; bits 5, 6, 7, 10, 11, 14, and 15 are reserved bits.

[0131] by Figure 4Taking the communication system shown as an example, the parameters of the receiver PHY chip can refer to the parameters that need to be trained on the HB, such as the equalization parameters of TX-FFE (i.e., FFE on the TX of HB's SerDes), or at least one of pre2, pre1, post1, or post2 of TX-FFE within HB. For the control field of the training frame, when the known value combination of the 2nd, 3rd, and 4th bits is 011, it can be used to instruct HB to perform link training on pre2 of TX-FFE within HB; when the known value combination of the 2nd, 3rd, and 4th bits is 111, it can be used to instruct HB to perform link training on pre1 of TX-FFE within HB; when the known value combination of the 2nd, 3rd, and 4th bits is 000, it can be used to instruct HB to perform link training on post2 of TX-FFE within HB; when the known value combination of the 2nd, 3rd, and 4th bits is 100, it can be used to instruct HB to perform link training on post1 of TX-FFE within HB.

[0132] In this embodiment of the application, the control field in the training frame can not only instruct the receiving PHY chip to perform link training on its own parameters according to the known definition, but also, by expanding and defining the control field in the training frame, enable the control field to instruct the receiving PHY chip to perform link training on the parameters of the receiving module connected to it.

[0133] As an example, the first link training request can instruct the receiving PHY chip to perform link training on the first parameter through multiple reserved bits in the control field. The number of reserved bits used to instruct the receiving PHY chip to perform link training on the first parameter can be determined based on the number of parameters included in the first parameter, as long as the number of parameters included in the first parameter is less than or equal to a power of 2 for the number of reserved bits. For example, when the first parameter includes 3 parameters, at least 2 reserved bits are required, and these 2 reserved bits can be at least two bits selected from the 5th, 6th, 7th, 10th, 11th, 14th, and 15th bits; as another example, when the first parameter includes 9 parameters, at least 4 reserved bits are required, and these 4 reserved bits can be at least four bits selected from the 5th, 6th, 7th, 10th, 11th, 14th, and 15th bits.

[0134] Taking the first parameter as an example, which only includes the parameters of the receiving module, and the parameters of the receiving module include dc_gain, boost0, and boost1 of DRV_CTLE within the MB, then the HB can be instructed to perform link training on dc_gain, boost0, and boost1 within the MB through the three combinations of the 5th and 6th bits in the DME code block. For example, a combination of 00 for the 5th and 6th bits can be used to instruct the HB to perform link training on dc_gain within the MB; a combination of 01 for the 5th and 6th bits can be used to instruct the HB to perform link training on boost0 within the MB; and a combination of 10 for the 5th and 6th bits can be used to instruct the HB to perform link training on boost1 within the MB.

[0135] As another example, the first link training request can also instruct the receiving PHY chip to perform link training on the first parameter through a reserved bit in the control field and a parameter selection field. For example, the first value of the reserved bit is used to instruct the receiving PHY chip to perform link training on the parameters of the receiving module, and the second value of the reserved bit is used to instruct the receiving PHY chip to perform link training on the parameters of the receiving PHY chip. The first value and the second value are different. The combination of values ​​in the parameter selection field is used to indicate the specific parameters that need to be trained in the link under different values ​​of the reserved bit. Here, the parameter selection field can be, for example, the 2nd bit, the 3rd bit, and the 4th bit, and a reserved bit can be any one of the 5th bit, the 6th bit, the 7th bit, the 10th bit, the 11th bit, the 14th bit, and the 15th bit. Taking the 5th bit as an example, when the value of the 5th bit is 0 (i.e., the second value), it is used by the receiving PHY chip to perform link training on its own parameters. In this case, the meaning of the known value combinations of the 2nd, 3rd, and 4th bits follows the definition in the current standard. When the value of the 5th bit is 1 (i.e., the first value), it is used by the receiving PHY chip to perform link training on the parameters of the receiving module. In this case, the meaning of each value combination of the 2nd, 3rd, and 4th bits can be flexibly defined.

[0136] Taking the first parameter as an example, which only includes the parameters of the receiving module, and the parameters of the receiving module include dc_gain, boost0 and boost1 of DRV_CTLE in MB, then the HB can be instructed to perform link training on itself or on the parameters in MB by different values ​​of the 5th bit in the control field. The parameter selection field can include the 2nd bit, 3rd bit and 4th bit in the control field. For example, when the value of the 5th bit is 1, and the combined values ​​of the 2nd, 3rd, and 4th bits are 100, it is used to instruct HB to perform link training on dc_gain within MB; when the value of the 5th bit is 1, and the combined values ​​of the 2nd, 3rd, and 4th bits are 111, it is used to instruct HB to perform link training on boost0 within MB; when the value of the 5th bit is 1, and the combined values ​​of the 2nd, 3rd, and 4th bits are 110, it is used to instruct HB to perform link training on boost1 within MB; when the value of the 5th bit is 0, and the known combinations of the 2nd, 3rd, and 4th bits are defined below, it is used to instruct HB to perform link training on the PHY chip link training parameters within HB.

[0137] As another example, the first link training request can also instruct the receiving PHY chip to perform link training on the first parameter by using reserved value combinations in the parameter selection field of the control field. The known value combinations in the parameter selection field indicate the parameters of the receiving PHY chip that require link training; these known value combinations differ from the reserved value combinations. For example, the parameter selection field can include the 2nd, 3rd, and 4th bits; known value combinations can be 100, 000, 111, and 011; and reserved value combinations can be 001, 010, 101, and 110. Up to four receiving modules can be defined for link training. The meaning of the reserved value combinations for the 2nd, 3rd, and 4th bits can be flexibly defined.

[0138] Taking a scenario where the first parameter only includes parameters from the receiver module, specifically dc_gain, boost0, and boost1 of DRV_CTLE within the MB, the HB can be instructed to perform link training on itself or on the parameters within the MB through different reserved value combinations of the 2nd, 3rd, and 4th bits in the control field. For example, a value combination of 001 for the 2nd, 3rd, and 4th bits instructs the HB to perform link training on dc_gain within the MB; a value combination of 101 instructs the HB to perform link training on boost0 within the MB; a value combination of 110 instructs the HB to perform link training on boost1 within the MB; and known value combinations of the 2nd, 3rd, and 4th bits, as defined in the current standard, are used to instruct the HB to perform link training on the parameters of the PHY chip within the HB.

[0139] If the first parameter only includes the parameters of the receiving module and not the parameters of the receiving PHY chip, then in one case, during the link training process, the transmitting device can only instruct the receiving PHY chip to perform link training on the parameters of the receiving module, without requiring the receiving PHY chip to perform link training on its own parameters. In another scenario, during the link training process, the transmitting device not only needs the receiving PHY chip to perform link training on the parameters of the receiving module, but also needs the receiving PHY chip to perform link training on its own parameters. In this case, the method 100 may further include: S201, the transmitting device generates a second link training request, which instructs the receiving PHY chip to perform link training on second parameters, the second parameters including the parameters of the receiving PHY chip; S202, the transmitting device sends the second link training request to the receiving PHY chip; S203, the receiving PHY chip receives the second link training request sent by the transmitting device; S204, the receiving PHY chip performs link training on the second parameters according to the second link training request, generating second status information, the second status information indicating the status after link training on the second parameters based on the second link training request; S205, the receiving PHY chip sends the second status information to the transmitting device; S206, the transmitting device receives the second status information sent by the receiving PHY chip. It should be noted that the execution of S201-S206 and S101-S106 is not limited; the concepts and specific implementation methods of S201-S206 can be found in the relevant descriptions of S101-S106. Thus, the transmitting device can instruct the receiving PHY chip to perform link training on its own parameters and the parameters of the modules it is connected to, respectively, through two link training requests.

[0140] In some other possible implementations, the first link training request can instruct the receiving PHY chip not only to perform link training on the parameters of the receiving module, but also to perform link training on its own parameters. In this implementation, the first parameter can also include the parameters of the receiving PHY chip. As an example, the first link training request can instruct the receiving PHY chip to perform link training on the parameters of the receiving module in the first parameter through a combination of values ​​for multiple reserved bits in the control field; the first link training request can also instruct the receiving PHY chip to perform link training on its own parameters through a known combination of the 2nd, 3rd, and 4th bits in the control field.

[0141] by Figure 4Taking the communication system shown as an example, the parameters of the receiving PHY chip in the first parameter can include at least one of pre2, pre1, post1, and post2 of TX-FFE within HB. The parameters of the receiving module in the first parameter include at least one of dc_gain, boost0, and boost1 of DRV_CTLE within MB. Assume that the reserved bits are the 5th and 6th bits in the control field. Then, in the first link training request, when the known value combination of the 2nd, 3rd, and 4th bits in the control field is 011, and the value combination of the 5th and 6th bits is 00, it is used to instruct HB to perform link training on pre2 of TX-FFE within HB and dc_gain within MB; when the known value combination of the 2nd, 3rd, and 4th bits is 111, and the value combination of the 5th and 6th bits is 00, it is used to instruct HB to perform link training on pre1 ... 2nd, 3rd, and 4th bits are 111, and the value combination of the 5th and 6th bits is 00, it is used to instruct HB to perform link training on pre1 of TX-FFE within HB and dc_gain within MB; when the 2nd, 3rd, and 4th bits are 111, and the value combination of the 5th and 6th bits is 00, it is used to instruct HB to perform link training on pre1 of TX-FFE within HB and dc_gain within MB; when the 2nd When the known combination of the 2nd, 3rd, and 4th bits is 000, and the combination of the 5th and 6th bits is 00, it is used to instruct HB to perform link training on post2 of TX-FFE within HB and dc_gain within MB; when the known combination of the 2nd, 3rd, and 4th bits is 100, and the combination of the 5th and 6th bits is 00, it is used to instruct HB to perform link training on post1 of TX-FFE within HB and dc_gain within MB; when the known combination of the 2nd, 3rd, and 4th bits is 011, and the 5th bit... When the combination of the 2nd, 3rd, and 4th bits is 01, it instructs HB to perform link training on pre2 of TX-FFE within HB and boost0 within MB; when the known combination of the 2nd, 3rd, and 4th bits is 111, and the combination of the 5th and 6th bits is 01, it instructs HB to perform link training on pre1 of TX-FFE within HB and boost0 within MB; when the known combination of the 2nd, 3rd, and 4th bits is 000, and the combination of the 5th and 6th bits is 01, it instructs HB to perform link training on pre1 of TX-FFE within HB and boost0 within MB. Link training is performed on post2 of FFE and boost0 in MB; when the known combination of the 2nd, 3rd, and 4th bits is 100, and the combination of the 5th and 6th bits is 01, it is used to instruct HB to perform link training on post1 of TX-FFE in HB and boost0 in MB; when the known combination of the 2nd, 3rd, and 4th bits is 011, and the combination of the 5th and 6th bits is 10, it is used to instruct HB to perform link training on pre2 of TX-FFE in HB and boost1 in MB.When the known combination of the 2nd, 3rd, and 4th bits is 111, and the combination of the 5th and 6th bits is 10, it instructs the HB to perform link training on the pre1 of TX-FFE within the HB and the boost1 of the MB. When the known combination of the 2nd, 3rd, and 4th bits is 000, and the combination of the 5th and 6th bits is 10, it instructs the HB to perform link training on the post2 of TX-FFE within the HB and the boost1 of the MB. When the known combination of the 2nd, 3rd, and 4th bits is 100, and the combination of the 5th and 6th bits is 10, it instructs the HB to perform link training on the post1 of TX-FFE within the HB and the boost1 of the MB. In this way, the transmitting device can simultaneously instruct the receiving PHY chip to perform link training on its own parameters and those of the modules it connects to through a single link training request. In many scenarios, this can accelerate the convergence speed of link training and improve its efficiency. For example, based on experience or experiments, the parameters involved in link training can be decoupled and grouped. Grouping could be based on grouping parameters in the receiver PHY chip and receiver module that have a consistent impact on the same performance (such as equalization performance) into the same group. In a single link training request, parameters in the same group can be trained together, effectively improving the efficiency of link training.

[0142] In this embodiment, the receiver module can refer to a module connected to an LPO, LRO, or ACC-Linear module, and the receiver PHY chip can refer to a PHY chip in a network device connected to the receiver module. When the receiver module is an LPO, the transmitter device can refer to a transmitter PHY chip. When the receiver module is a traditional optical module or an LRO, the transmitter device can refer to a transmitter PHY chip or a transmitter module. The transmitter module refers to a traditional optical module, LPO, LRO, or ACC-Linear module connected to the transmitter PHY chip.

[0143] It should be noted that, prior to S101, the method 100 may further include: the receiving PHY chip performing initialization configuration between the receiving PHY chip and the receiving module, and the transmitting PHY chip performing initialization configuration between the transmitting PHY chip and the transmitting module.

[0144] by Figure 4Taking a communication system as an example, the initialization configuration performed by the receiving PHY chip can be understood as the HB initializing the HB and MB, while the initialization configuration of the transmitting device can be understood as the HA initializing the HA and MA. Taking the HB initializing the HB and MB as an example, the initialization configuration parameters can include: the TX-FFE tap coefficient of the HB, the DRV_CTLE equalization parameters of the MB (e.g., boost1, boost0, and dc_gain), and the TIA output amplitude (TIA_OA) of the MB. As an example, the HB can obtain the preset values ​​of the parameters to be trained on the link in advance, so the HB can directly configure the parameters in the HB and MB to the preset values. As another example, after the HB is connected to the MB and before the MB is connected to the MA, the MB can be connected to a loopback cap or other self-loopback device. Through self-loopback, the optical signal emitted by the HB through the MB is looped back to the HB. The HB can configure the parameters in the HB and MB based on the quality of the electrical signal looped back to the HB. In this way, by initializing the configuration, the communication system for link training has more reasonable starting conditions, providing a better data foundation for link training, which can improve the success rate and efficiency of link training to a certain extent.

[0145] As can be seen, by generating a first link training request in S101, the transmitting device prepares for sending the first link training request to the receiving PHY chip and instructing the receiving PHY chip to perform link training on the first parameters based on the first link training request, thus making it possible to implement the method 100 provided in this application embodiment.

[0146] S102, the transmitting device sends the first link training request to the receiving PHY chip.

[0147] S103, the receiving PHY chip receives the first link training request sent by the transmitting device.

[0148] As an example, the channel through which the transmitting device interacts with the receiving PHY chip may include a data channel for service data transmission. In this case, S102 may include: the transmitting device sending a first link training request to the receiving PHY chip through the data channel between the transmitting device and the receiving PHY chip; S103 may include: the receiving PHY chip receiving the first link training request from the transmitting device through the data channel.

[0149] by Figure 4Taking the communication system shown as an example, S102-S103 may include: S11, the RX of HA determines the first parameter that needs to be trained on the link, and transmits the indication information of the first parameter and related information such as the link training method of the first parameter to the TX of HA; S12, the TX of HA generates a first link training request based on the relevant information obtained from the RX of HA; S13, the TX of HA sends the first link training request to the RX of HB through path 1; S14, the RX of HB parses the received first link training request and obtains the above-mentioned relevant information; S15, the RX of HB transmits the parsed relevant information to the TX of HB. In this way, the TX of HB can execute S104 to train the link on the first parameter based on the relevant information obtained from the RX of HB. Here, path 1 can refer to the transmission path of the service data from the TX of HA to the RX of HB in sequence through MA and MB. This path 1 can be understood as the data channel from HA to HB.

[0150] It is understandable that the transmitting device can send a first link training request to the receiving PHY chip through any channel that can interact with the receiving PHY chip. Upon receiving the first link training request, the receiving PHY chip is ready to perform link training on the first parameters.

[0151] S104, the receiving PHY chip performs link training on the first parameters according to the first link training request, and generates the first state information.

[0152] The first state information corresponds to the first link training request. The first state information can be used to indicate the state of the receiving PHY chip after performing link training on the first parameters based on the first link training request. The first state information may include the specific parameters participating in the link training and the specific link training performed on each parameter when the receiving PHY chip performs link training on the first parameters, so that the other end can understand the specific content of this link training.

[0153] The first state information can be carried in the training frame generated by the receiving PHY chip after performing link training on the first parameter. Specifically, the first state information can be carried in the state field of this training frame. The value of the state field indicates which parameter was modified during this link training, and to what extent it was modified (e.g., whether the modification reached the limit value of the corresponding parameter).

[0154] In some possible implementations, the training frame generated by the receiving PHY chip after link training of the first parameters may include test information in addition to the first state information. This test information is used by the transmitting device to test the link quality from the receiving PHY chip to the transmitting device after this link training, so that the transmitting device can make further decisions regarding the next step of link training from the receiving PHY chip to the transmitting device. The test information can be represented by the training mode field in the training frame.

[0155] Thus, when the sending device receives the training frame, it can understand the specific situation of this link training from the status field of the training frame. It can also test the link quality after this link training based on the training mode field of the training frame, and obtain the value of at least one quality indicator that can characterize the quality of the link, so as to guide the subsequent link training.

[0156] As an example, if the first parameter includes the parameters of the receiving module, then S104 can at least include: the receiving PHY chip performing link training on the parameters of the receiving module. The link training performed by the receiving PHY chip on the parameters of the receiving module requires consideration of the interaction channel between the receiving PHY chip and the receiving module.

[0157] It is understandable that there can be multiple possible interaction channels between the receiving PHY chip and the receiving module, such as the IIC bus, a data channel, or other management register channels. Therefore, the link training of the receiving module's parameters by the receiving PHY chip in S104 can include: the receiving PHY chip performing link training on the parameters of the receiving module within the receiving module through any possible interaction channel. For example, S104 can include: in response to a first link training request, the receiving PHY chip performing link training on the parameters of the receiving module within the receiving module through the IIC bus.

[0158] As another example, the first parameter may include the parameters of the receiving module and the parameters of the receiving PHY chip. Therefore, S104, in addition to the receiving PHY chip performing link training on the parameters of the receiving module, may also include the receiving PHY chip performing link training on its own parameters. Here, the parameters of the receiving PHY chip can be understood as the parameters that the receiving PHY chip itself uses in this link training. In this example, S104 may include, for instance, responding to the first link training request, the receiving PHY chip performing link training on the parameters of the receiving module via the IIC bus, and the receiving PHY chip performing link training on its own parameters.

[0159] If the receiver module is an LPO, then the parameters of the receiver module can include the equalization parameters in the DRV_CTLE of the LPO, and the parameters of the receiver PHY chip can include the tap coefficients in the TX-FFE of the receiver PHY chip.

[0160] It should be noted that link training can be understood as the process of adjusting the values ​​of the corresponding parameters. The specific parameters to be adjusted and the adjustment method can be contained in the first link training request.

[0161] As can be seen, after the receiving PHY chip performs link training on the first parameter through S104, it generates first state information that can reflect the state of the link training, which prepares for feeding back the state of the link training to the sending device and guiding subsequent link training.

[0162] S105, the receiving PHY chip sends the first status information to the transmitting device.

[0163] S106, the sending device receives the first status information.

[0164] In order to feed back the status of the link training to the sending device that instructs the link training, method 100 needs to transmit the first status information to the sending device through S105 to S106.

[0165] In some possible implementations, the method 100 may further include: the transmitting device testing the link quality of the link from the receiving PHY chip to the transmitting device based on test information, and obtaining test results. Then, based on the test results, the transmitting device determines whether the link training in the direction from the receiving PHY chip to the transmitting device meets a preset first condition. If it does, it can be considered that the parameters adjusted in this link training have been adjusted to an optimal state, and there is no need to further adjust the parameters to improve the link quality of the trained link; if it does not meet the condition, it can be considered that the parameters adjusted in this link training can continue to be optimized. If the link training from the receiving PHY chip to the transmitting device meets the preset first condition, the transmitting device can further determine whether the link training from the receiving PHY chip to the transmitting device meets the preset second condition. If it does, it can be considered that the link training has enabled the link from the receiving PHY chip to the transmitting device to meet the expected performance requirements, and there is no need to continue link training for the link from the receiving PHY chip to the transmitting device. If it does not meet the second condition, it can be considered that the link training has not enabled the link from the receiving PHY chip to the transmitting device to meet the expected performance requirements, and it is necessary to continue link training for the parameters of other parts of the link from the receiving PHY chip to the transmitting device.

[0166] The first and second conditions can be flexibly set based on the actual situation of link training.

[0167] The first condition indicates whether adjusting the same parameters can further improve the link quality of the trained link. As an example, the first condition may include any one of the following: Condition 1: The change in the value of the first quality indicator is less than or equal to a first threshold. The first quality indicator characterizes the link quality from the receiving PHY chip to the transmitting device; a smaller value of the first quality indicator indicates better link quality. Condition 2: The change in the value of the second quality indicator is greater than or equal to a second threshold. The second quality indicator characterizes the link quality from the receiving PHY chip to the transmitting device; a larger value of the second quality indicator indicates better link quality. The first quality indicator may be, for example, BER (Bit Rate), and the second quality indicator may be, for example, SNR (Short-Range Noise Ratio).

[0168] The second condition is used to determine whether the link training has enabled the link performance to meet the requirements of business data transmission, thereby determining whether the link training is complete. As an example, the second condition may include any one of the following conditions: Condition 3, the value of the first quality indicator is less than or equal to the third threshold; Condition 4, the value of the second quality indicator is greater than or equal to the fourth threshold. Here, the first quality indicator may be, for example, BER, and the second quality indicator may be, for example, SNR.

[0169] Taking condition 1 as the first condition, condition 3 as the second condition, and BER as the first quality index as an example, method 100 may include, for example, the following steps: After S106, the transmitting device performs a link quality test on the link from the receiving PHY chip to the transmitting device based on the test information to obtain the BER value, which characterizes the link quality from the receiving PHY chip to the transmitting device; the transmitting device calculates the difference between the BER value obtained this time and the BER value obtained after the previous link training on the link from the receiving PHY chip to the transmitting device, and determines whether the difference in BER is less than or equal to a first threshold. If it is, the link training from the receiving PHY chip to the transmitting device is considered to meet the first condition; if not, the link training from the receiving PHY chip to the transmitting device is considered not to meet the first condition. If the link training from the receiving PHY chip to the transmitting device satisfies the first condition, the transmitting device can continue to determine whether the obtained BER value is less than or equal to the third threshold. If it is, the link training from the receiving PHY chip to the transmitting device is considered to satisfy the second condition; otherwise, the link training from the receiving PHY chip to the transmitting device is considered not to satisfy the second condition.

[0170] As an example, if the transmitting device determines that the link training from the receiving PHY chip to the transmitting device meets both the first and second conditions, the method 100 may further include: the transmitting device generating local receiver ready information (local_rx_ready) to indicate that the link training from the receiving PHY chip to the transmitting device is complete. In this way, the second condition can be used to identify whether link training in a certain direction has been completed, providing a reliable basis for judging the link training progress of the communication system.

[0171] As another example, if the transmitting device determines that the link training from the receiving PHY chip to the transmitting device does not meet the second condition, the method 100 may further include: the transmitting device continuing to perform link training on the link from the receiving PHY chip to the transmitting device.

[0172] In one scenario, if the transmitting device determines that the link training from the receiving PHY chip to the transmitting device does not meet the first condition, the transmitting device can continue to instruct the receiving PHY chip to perform link training on itself or with the receiving module. For example, the transmitting device generates a third link training request, which instructs the receiving PHY chip to continue link training on the first parameter. The transmitting device sends the third link training request to the receiving PHY chip. Based on the received third link training request, the receiving PHY chip performs link training on the first parameter and generates third state information for link training. The receiving PHY chip sends the third state information corresponding to the third link training request to the transmitting device. In this scenario, the first parameter may include: parameters of the receiving module, and / or parameters of the receiving PHY chip. The first parameter in this scenario may be the same as or different from the first parameter in S101. Even if the first parameter in this scenario is the same as the first parameter in S101, the adjustment method of the first parameter indicated by the third link training request may be different from the adjustment method of the first parameter indicated by the first link training request.

[0173] In another scenario, if the transmitting device determines that the link training from the receiving PHY chip to the transmitting device satisfies the first condition but not the second condition, it can be considered that the receiving PHY chip's link training for itself and for the receiving module can no longer improve the link quality from the receiving PHY chip to the transmitting device. Alternatively, it can be determined that the link training result obtained by instructing the receiving PHY chip to perform link training on the first parameter meets the expected effect of the receiving PHY chip performing link training on the first parameter. In this case, during the continued link training process from the receiving PHY chip to the transmitting device, the method 100 may further include: the transmitting device performing link training on a third parameter, which includes the parameters of the transmitting module. The parameters of the transmitting module can be understood as the parameters of the transmitting module that participate in the link training. After the transmitting device performs link training on the third parameter, if it is determined that the link training from the receiving PHY chip to the transmitting device meets the preset second condition, then the transmitting device is considered to no longer need to perform link training on the third parameter. At this point, the link training from the receiving PHY chip to the transmitting device can be terminated as needed. Alternatively, if it is determined that the link training from the receiving PHY chip to the transmitting device meets the preset first condition again, but still does not meet the second condition, the transmitting device can automatically start link training on its own parameters until the link training from the receiving PHY chip to the transmitting device meets the second condition. If it is determined that the link training from the receiving PHY chip to the transmitting device does not meet the preset first and second conditions, then the transmitting device can continue to perform link training on the third parameter. It should be noted that the third parameter involved in each link training session by the transmitting device can be the same or different.

[0174] by Figure 4 Taking the communication system shown as an example, the transmitting device performs link training on the third parameter, which may include: HA performing link training on the parameters in MA. Taking the transmitting module as an LPO as an example, the parameters of the transmitting module may include the equalization parameters in TIA_OA of the LPO.

[0175] If the transmitting device determines that the link training performed by the receiving PHY chip on itself and on the receiving module can no longer improve the link quality from the receiving PHY chip to the transmitting device, or if it determines that the link training result obtained by instructing the receiving PHY chip to perform link training on the first parameter meets the expected effect of the receiving PHY chip's link training on the first parameter, this can be achieved through a preset first condition. For example, if the transmitting device determines that the link training result meets the first condition after the receiving PHY chip performs link training on the first parameter, then it is considered that the link quality from the receiving PHY chip to the transmitting device can no longer be improved through the link training performed by the receiving PHY chip on itself and on the receiving module, or that the link training result obtained by instructing the receiving PHY chip to perform link training on the first parameter meets the expected effect of the receiving PHY chip's link training on the first parameter. In this case, the transmitting device can continue to perform link training on the link from the receiving PHY chip to the transmitting device by adjusting the transmitting module.

[0176] It should be noted that during the link training process of the third parameter of the transmitting module, the transmitting device can continue to send link training requests to the receiving PHY chip, and the receiving PHY chip can choose not to process the received link training requests by default.

[0177] It should be noted that after the transmitting device performs link training on the third parameter of the transmitting module, the method 100 may further include: the transmitting device continuing to instruct the receiving PHY chip to perform link training on itself or the receiving module. For example, after the transmitting device performs link training on the third parameter of the module connected to it, if the transmitting device determines that the link training from the receiving PHY chip to the transmitting device does not meet the second condition, or if the transmitting device determines that the link training from the receiving PHY chip to the transmitting device does not meet the second condition but meets the first condition, then the transmitting device may continue to instruct the receiving PHY chip to continue performing link training on itself or the receiving module.

[0178] It should be noted that all of the above possible link training processes must be completed within the set maximum allowed time and / or maximum number of training iterations. Once the link training execution time reaches the maximum allowed time or the number of link training iterations reaches the maximum number of training iterations, the entire link training process can be considered a failure.

[0179] Thus, through this method 100, even if the receiving end module and / or transmitting end module in the communication system do not include an oDSP chip, the receiving end PHY chip can still perform link training on the first parameter, including the parameters of the receiving end module, through end-to-end link training requests and the interaction of status information. For communication systems where current link training is not applicable, effective link training can be achieved, thus ensuring the working performance of the communication system.

[0180] To make the link training method provided in the embodiments of this application easier to understand, the following is combined with Figure 6 A possible link training process is described.

[0181] like Figure 6 As shown, assuming a maximum allowed time for link training is preset, a possible example of the link training method provided in this application embodiment may include S601 to S610:

[0182] S601, the local network device and the module connected to the local network device (hereinafter referred to as the local module) are initialized and configured, and the peer network device and the module connected to the peer network device (hereinafter referred to as the peer module) are initialized and configured.

[0183] S602, within the maximum allowable time for link training, the local network device determines whether the link quality 1 of the link from the peer network device to the local network device meets the requirements for service data transmission. If it meets the requirements, proceed to S610; otherwise, proceed to S603.

[0184] The requirements for business data transmission in S602 can be understood as the second condition mentioned above.

[0185] S603, the local network device instructs the peer network device to perform link training on the parameters of the peer network device's PHY chip and / or the parameters of the peer module, thereby the local network device obtains the link quality 2 of the link from the peer network device to the local network device;

[0186] S604, if the link training implementation time is within the maximum allowable time, the local network device determines that the difference between the link quality 2 and the link quality 2' obtained in the previous link training is less than the first preset value. If so, execute S605; otherwise, return to execute S603.

[0187] Among them, the difference between link quality 2 and link quality 2' obtained in the previous link training is less than the first preset value, which can be understood as the first condition mentioned above.

[0188] The specific value of the first preset value can be flexibly set based on actual needs. The difference between link quality 2 and link quality 2' obtained in the previous link training is less than the first preset value. This is used to indicate that after two adjacent link training sessions, the link quality of the linked link remains basically unchanged or changes only slightly. That is, the effect of the link training corresponding to link quality 2 is not significant enough, so there is no need to continue optimizing the same content.

[0189] S605, The local network device performs link training on the parameters of the local module to obtain the link quality 3 of the link from the peer network device to the local network device;

[0190] S606, if the link training implementation time is within the maximum allowable time, the local network device determines whether the link quality 3 meets the requirements of service data transmission. If it does, the link training is considered complete and S610 is executed; otherwise, S607 is executed.

[0191] The requirements for business data transmission in S606 can be understood as the second condition mentioned above.

[0192] S607, the local network device determines whether the implementation time of the link training is within the maximum allowed time. If yes, then execute S608; otherwise, execute S609.

[0193] S608, the local network device determines that the difference between the link quality 3 and the link quality 3' obtained in the previous link training is less than the second preset value. If so, it returns to execute S603; otherwise, it returns to execute S605.

[0194] The specific value of the second preset value can be flexibly set based on actual needs. The second preset value can be the same as or different from the first preset value. The difference between the link quality 3 and the link quality 3' obtained in the previous link training is less than the second preset value. This is used to indicate that after two adjacent link training sessions, the link quality of the trained link remains basically unchanged or changes only slightly. That is, the effect of the link training corresponding to obtaining link quality 3 is not significant enough, so there is no need to continue optimizing the same content.

[0195] S609, The local network device has determined that the overall link training process has failed and restarted the link training process.

[0196] S610, the link between the local network device and the peer network device is used for the transmission of service data.

[0197] Thus, through Figure 6As can be seen from the embodiments shown, the link training method provided in this application no longer relies on the oDSP chip in the module connected to the network device. It does not require the network device to form an electrical signal loop with the module it is connected to. Based on the end-to-end link training indication and timely feedback of link quality, it can realize end-to-end link training of the communication system. For communication systems that are not applicable to the current link training, it can realize effective link training, so that the working performance of the communication system can be guaranteed.

[0198] The communication systems applicable to the embodiments of this application, in addition to those described above... Figure 2a The LPO-LPO architecture communication system shown and Figure 2b The LRO-LRO architecture communication system shown can also be applied to the following: Figure 7 The communication system shown is based on the retimed-LPO architecture. Figure 8 The communication system of the retimed-LRO architecture shown and Figure 9 The LRO-LPO architecture communication system is shown below. The following sections will describe the communication systems of various architectures and the process of link training using the methods provided in the embodiments of this application for each corresponding communication system.

[0199] Scenario 1, for Figure 2a The LPO-LPO architecture communication system shown here, the link training process can be found in [reference needed]. Figure 5 or Figure 6 The relevant descriptions in the illustrated embodiments.

[0200] Scenario 2, for communication systems with a retimed-LPO architecture, such as Figure 7 As shown, with Figure 2a Compared to the communication system shown, it will Figure 2a Replace LPO 1 in the text with Figure 1 The traditional optical module 1 shown.

[0201] against Figure 7 The communication system shown can perform initialization configurations between network device 1 and traditional optical module 1, and between network device 2 and LPO 2, before link training begins. For example, the initialization configuration between network device 1 and traditional optical module 1 can be completed before leaving the factory, and the initialization configuration between network device 2 and LPO 2 can be completed before leaving the factory or through a loopback mechanism.

[0202] Link training for link 1 from network device 1 to network device 2 can include:

[0203] The first step, link training in link 1 from network device 1 to traditional optical module 1, can refer to the current training... Figure 1The link training scheme for electrical signal loop 1 in the network device 1 can refer to the link training mechanisms of CL136 or CL162 in IEEE 802.3, which will not be described in detail here. After the link training of electrical signal loop 1 is completed, the values ​​of the equalization parameters of TX in network device 1 (such as the tap coefficient of TX-FFE) will no longer change. It should be noted that a bit (such as the 15th bit of the control field of the training frame) can be used to indicate whether the link training from network device 1 to traditional optical module 1 is completed. For example, if the value of this bit is 0, it means that the link training from network device 1 to traditional optical module 1 is not completed; if the value of this bit is 1, it means that the link training from network device 1 to traditional optical module 1 is completed.

[0204] The second step is to start the link training from network device 1 to traditional optical module 1 in link 1 after completing the link training in link 1.

[0205] As an example, the equalization parameters (such as the tap coefficient of TX-FFE within the oDSP chip 11) of the traditional optical module 1 are configured before the traditional optical module 1 leaves the factory, and the indicators of the output port TP2 point meet the protocol requirements. Therefore, the traditional optical module 1 can participate in link training. After receiving a link training request from network device 2, network device 1 or the traditional optical module 1 can choose not to perform link training by default. In this example, network device 2 can perform link training on the equalization parameters (such as TIA_OA in LPO 2) through the IIC bus or other management register channels. If, within the maximum allowed time or maximum number of training iterations, it is determined that the link training from network device 1 to network device 2 meets the second condition, then the link training from network device 1 to network device 2 is considered complete.

[0206] As another example, when adjusting only the equalization parameters in LPO 2 (such as TIA_OA in LPO 2) cannot complete the link training, the equalization parameters in the oDSP chip 11 of the traditional optical module 1 (such as the tap coefficient of TX-FFE in oDSP chip 11) can also be used as the object of link training. Next, in scenario one, network device 1 receives a link training request from network device 2. Network device 1 can adjust the equalization parameters in the oDSP chip 11 of the traditional optical module 1 according to the link training request, and send the obtained status information and test information to network device 2. Network device 2 can determine the effect of this link training based on the received test information. In scenario two, when network device 2 determines that the effect of this link training meets the first condition, for example, the change in the BER of the link is less than or equal to the threshold D, network device 2 continues to perform link training on the equalization parameters (such as TIA_OA in LPO 2) in LPO 2 through the IIC bus or other management register channels. At this time, after receiving the link training request from network device 2, network device 1 or traditional optical module 1 can default to not performing link training. In scenario three, after network device 2 performs link training on the equalization parameters in LPO 2, when network device 2 determines that the effect of this link training meets the first condition, for example, the change in the BER of the link is less than or equal to the threshold D, network device 2 can stop training the LPO. 2. Training of equalization parameters: Actively initiate link training for the equalization parameters (such as the tap coefficient of TX-FFE within the oDSP chip 11 of the traditional optical module 1). During the iteration of cases one, two, and three above, if network device 2 determines that the effect of this link training meets the second condition within the maximum allowed time or maximum number of training iterations, for example, if the BER of link 1 is less than or equal to the threshold T, then the link training from network device 1 to network device 2 is considered complete.

[0207] The RX of network device 2 can transmit link training-related information to the TX of network device 2. The TX of network device 2 carries the link training-related information in a training frame and sends the training frame to the RX of network device 1 or the RX of traditional optical module 1. The RX of network device 1 or the RX of traditional optical module 1 parses the received training frame to obtain the link training-related information and transmits it to the TX of network device 1 or the TX of traditional optical module 1. The TX of network device 1 or the TX of traditional optical module 1 adjusts the equalization parameters (such as the tap coefficient of TX-FFE in the oDSP chip 11) in traditional optical module 1 based on the obtained link training-related information. If the TX 12 and RX 12 of the oDSP chip 11 of traditional optical module 1, which are close to LPO 2, have the function of transmitting, receiving, and parsing training frames (such as DME code blocks in the training frame), then the TX of network device 2 sends the training frame carrying the link training-related information to the RX 12 of traditional optical module 1, and network device 1 does not participate in the transmission and parsing of training frames. If the TX 12 and RX 12 of the oDSP chip 11 of the traditional optical module 1, which are close to the LPO 2, do not have the function of transmitting, receiving, and parsing training frames (such as DME code blocks in the training frame), then the TX of network device 2 will send the training frame carrying the relevant information of link training to the RX of network device 1. After parsing the training frame, the RX of network device 1 will obtain the relevant information of link training and pass the relevant information of link training to the TX of network device 1. Based on the relevant information of link training, the TX of network device 1 will perform link training on the equalization parameters in the oDSP chip 11 of the traditional optical module 1 through the IIC bus, other management register channels, or data channels.

[0208] Link training from network device 2 to network device 1 can include: network device 1 sending a link training request to network device 2; network device 2 adjusting its own equalization parameters (such as the tap coefficient of TX-FFE) and / or adjusting the equalization parameters of LPO 2 (such as the equalization parameters of DRV_CTLE) through the IIC bus, other management register channels, or data channels according to the instructions of the received link training request; network device 2 sending the corresponding status information and test information to network device 1; if, within the maximum allowed time or maximum number of training iterations, network device 1 determines based on the test information that the link training from network device 2 to network device 1 meets the second condition, then the link training from network device 2 to network device 1 is considered complete. Here, network device 1 determines that the effect of this link training meets the second condition, for example, the BER of link 2 may be less than or equal to a threshold T.

[0209] The RX of network device 1 or the RX of traditional optical module 1 can transmit link training-related information to the TX of network device 1 or the TX of traditional optical module 1. The TX of network device 1 or the TX of traditional optical module 1 carries the link training-related information in a training frame and sends the training frame to the RX of network device 2. The RX of network device 2 parses the received training frame to obtain the link training-related information and transmits the link training-related information to the TX of network device 2. The TX of network device 2 adjusts the equalization parameters in LPO 2 (such as the equalization parameters of DRV_CTLE in LPO 2) according to the obtained link training-related information. If the TX 12 and RX 12 of the oDSP chip 11 of traditional optical module 1, which are close to the LPO 2 side, have the function of transmitting, receiving, and parsing training frames (such as DME code blocks in the training frame), then the TX 12 of traditional optical module 1 sends the training frame carrying the link training-related information to the RX of network device 2. Network device 1 does not participate in the transmission and parsing of training frames. If the TX 12 and RX 12 of the oDSP chip 11 of the traditional optical module 1, which are close to the LPO 2, do not have the function of transmitting, receiving and parsing training frames (such as DME code blocks in the training frames), then the TX of the network device 1 will send the training frames carrying the relevant information of link training to the RX of the network device 2.

[0210] It should be noted that link training for link 1 and link training for link 2 can be considered as... Figure 7 The two parts of the communication system's link training process shown can run simultaneously, with the same maximum allowed time and maximum number of training iterations. Failure to train link 1 or link 2 will cause the entire link training process to fail, requiring a restart of the link training process to ensure the communication system is ready to transmit service data.

[0211] It should be noted that for link training from network device 1 to network device 2, the transmission path of the link training request can be a data channel used for business data transmission.

[0212] Scenario 3, targeting Figure 2b The LRO-LRO architecture communication system shown can perform initialization configurations between network device 1 and LRO 1, and between network device 2 and LRO 2, before link training begins. For example, the initialization configuration between network device 1 and LRO 1 can be completed before leaving the factory, and the initialization configuration between network device 2 and LRO 2 can be completed before leaving the factory or through a loopback mechanism.

[0213] As an example, the LRO may include a complete oDSP chip. The oDSP RX of this oDSP chip is only enabled during link training, as described in the current link training scheme, between network device 1 and LRO 1, and between network device 2 and LRO 2. Once the corresponding link training is complete, the oDSP chip's RX is disabled. For example, after training of the link between network device 1 and LRO 1 is completed, the RX of oDSP chip 11 in LRO 1 is disabled; similarly, after training of the link between network device 2 and LRO 2 is completed, the RX of oDSP chip 21 in LRO 2 is disabled.

[0214] As another example, such as Figure 2b As shown, only the TX portion is fabricated internally within the LRO. In the first scenario, the equalization parameters of the TX portion of network device 1 can be configured before shipment, eliminating the need for link training between network device 1 and LRO 1. In the second scenario, the equalization parameters of the TX portion of network device 1 require link training. For example, a bidirectional feedback channel for information related to link training can be constructed between network device 1 and LRO 1 using an out-of-band channel (such as an IIC bus). Feedback information from the oDSP chip 11 in LRO 1 can be transmitted to network device 1 to adjust its equalization parameters, thereby achieving link training between network device 1 and LRO 1. It should be noted that in both scenarios, the link from network device 1 to LRO 1 has been supplemented. For the subsequent link training process from LRO 1 to network device 2, please refer to [link details missing]. Figure 7 The second step in the link training of link 1 is described in the following section. In the third case, the equalization parameters of network device 1's TX can participate in the link training of end-to-end equalization parameters. That is, the equalization parameters of network device 1's TX are adjusted based on the instructions of the link training request sent by network device 2, and the link training between network device 1 and LRO 1 is no longer considered separately. The link training process is the same as... Figure 2a The link training process shown is basically the same, with the main differences being the following two points: First, the LRO internally adjusts the equalization parameters of the oDSP chip (such as the tap coefficient of the TX_FFE of the oDSP chip); Second, network devices can configure the equalization parameters within the oDSP chip of the LRO through the IIC bus, other management register channels, or data channels.

[0215] It should be noted that training frames used to carry information related to link training can be transmitted in the communication system through the data channel.

[0216] Scenario 4, for communication systems with a retimed-LRO architecture, such as Figure 8 As shown, with Figure 7 Compared to the communication system shown, it will Figure 7Replace LPO 2 in Figure 2b The LRO 2 is shown. For link training of link 3 from network device 1 to network device 2, please refer to... Figure 7 For a description of the link training for link 1, see [link 1], or [link 2]. Figure 2b The relevant descriptions for link training in any direction are provided. For link training of link 4 from network device 2 to network device 1, please refer to the section on... Figure 1 The text describes how the retimed-retimed architecture communication system uses current link training methods for link training.

[0217] Scenario 5, for communication systems with an LRO-LPO architecture, such as Figure 9 As shown, with Figure 2b Compared to the communication system shown, it will Figure 2b Replace LRO 2 with Figure 2a The LPO 2 is shown. For link training of link 5 from network device 1 to network device 2, please refer to... Figure 7 For a description of the link training for link 1, see [link 1], or [link 2]. Figure 2b For a description of link training in any direction, see [link to documentation], or [see also] Figure 8 The relevant description of link training for link 3 is provided in [the document / section]. For link training of link 6 from network device 2 to network device 1, please refer to [the document / section / section]. Figure 2a A description of link training in any direction for a communication system with an LPO-LPO architecture.

[0218] As can be seen, the method provided in this application embodiment can achieve end-to-end link training of a communication system involving multiple links by providing instructions for end-to-end link training and timely feedback on link quality. It is applicable to various possible scenarios in which at least one network device in the communication system is connected to an improved module. For communication systems where current link training methods are not applicable, it can achieve effective link training, thereby ensuring the working performance of the communication system.

[0219] Accordingly, this application also provides a chip 1000, such as... Figure 10 As shown. The chip 1000 may include an interface circuit 1001 and a processing circuit 1002.

[0220] If chip 1000 corresponds to a chip in the transmitting device, then the functions of each structure in chip 1000 are as follows:

[0221] Processing circuit 1002 is used to generate a first link training request. This first link training request instructs the receiving end PHY chip to perform link training on first parameters. These first parameters may include at least parameters of the receiving end module, specifically optical module parameters. This function of processing circuit 1002 can correspond to... Figure 5 The relevant description of S101.

[0222] Interface circuit 1001 is used to send the first link training request to the receiving PHY chip. This function of interface circuit 1001 can correspond to... Figure 5 S102 in the middle.

[0223] Interface circuit 1001 is also used to receive first state information, which indicates the state after link training of the first parameters based on the first link training request. This function of interface circuit 1001 can correspond to... Figure 5 S106 in the middle.

[0224] In some possible implementations, in one case, the receiver module may include an optical module whose parameters are those of the optical module itself. For example, if the receiver module is an LPO, then the optical module parameters can be those of the DRV_CTLE parameter in the LPO. In another case, the receiver module may also include an ACC-Linear module whose parameters are those of the ACC-Linear module itself.

[0225] In some possible implementations, for the case where the receiving module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the chip 1000 protected in the embodiments of this application is a transmitting PHY chip, and the transmitting module connected to the transmitting PHY chip is an LPO. In this case, the transmitting device can refer to the transmitting PHY chip. As another example, the communication system can be an LPO-retimed architecture, that is, the chip 1000 protected in the embodiments of this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is a retimed optical module. In this case, the transmitting device can refer to the transmitting PHY chip or the transmitting module. As yet another example, the communication system can be an LPO-LRO architecture, that is, the chip 1000 protected in the embodiments of this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is an LRO. In this case, the transmitting device can refer to the transmitting PHY chip or the transmitting module.

[0226] In some other possible implementations, for the case where the receiving module is an LRO, as an example, the communication system can be an LRO-LPO architecture, that is, the chip 1000 protected in the embodiments of this application is a transmitting PHY chip, and the transmitting module connected to the transmitting PHY chip is an LPO, then the transmitting device is the transmitting PHY chip; as another example, the communication system can be an LRO-retimed architecture, that is, the chip 1000 protected in the embodiments of this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is a retimed optical module, then the transmitting device is the transmitting PHY chip or a transmitting module; as yet another example, the communication system can be an LRO-LRO architecture, that is, the chip 1000 protected in the embodiments of this application is a transmitting PHY chip or a chip in a transmitting module, and the transmitting module connected to the transmitting PHY chip is an LRO, then the transmitting device is the transmitting PHY chip or a transmitting module.

[0227] In this application, the LRO may include an oDSP chip, the TX pin of the receiving PHY chip is connected to the oDSP chip of the LRO, and the RX pin of the transmitting PHY chip is not connected to the oDSP chip of the LRO.

[0228] In some possible implementations, the processing circuit 1002 is further configured to generate a second link training request, which instructs the receiving PHY chip to perform link training on the second parameters, the second parameters including the parameters of the receiving PHY chip; the interface circuit 1001 is further configured to send the second link training request to the receiving PHY chip; the interface circuit 1001 is further configured to receive second status information sent by the receiving PHY chip, the second status information indicating the status after link training on the second parameters based on the second link training request.

[0229] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0230] In some possible implementations, the interface circuit 1001 is also used to receive test information; the processing circuit 1002 is also used to test the link quality from the receiving PHY chip to the transmitting device based on the test information and obtain test results.

[0231] In some possible implementations, the processing circuit 1002 is further configured to generate a third link training request if it is determined that the test result does not meet the first condition. The third link training request is used to instruct the receiving PHY chip to continue link training on the first parameter. The interface circuit 1001 is further configured to send the third link training request to the receiving PHY chip. The interface circuit 1001 is further configured to receive third status information, which indicates the status after link training on the first parameter based on the third link training request.

[0232] As an example, the first condition may include any one of the following: the change in the value of the first quality indicator is less than or equal to the first threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the change in the value of the second quality indicator is greater than or equal to the second threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0233] In some possible implementations, the processing circuit 1002 is further configured to perform link training on the third parameter if it is determined that the test result meets the first condition but does not meet the second condition. The third parameter includes the parameters of the transmitting module, which are the parameters of the optical module.

[0234] As an example, the second condition may include any one of the following conditions: the value of the first quality indicator is less than or equal to the third threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the value of the second quality indicator is greater than or equal to the fourth threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0235] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0236] It should be noted that for details regarding the chip 1000, please refer to the description of the relevant operations performed by the transmitting device in method 100.

[0237] If chip 1000 corresponds to the receiver PHY chip, then the functions of each structure in chip 1000 are as follows:

[0238] Interface circuit 1001 is used to receive a first link training request sent by the transmitting device. The first link training request instructs the receiving PHY chip to perform link training on first parameters. These first parameters include parameters of the receiving module, which are optical module parameters. This function of interface circuit 1001 can correspond to... Figure 5 The relevant description of S103.

[0239] Processing circuit 1002 is used to perform link training on the first parameters according to the first link training request. This function of processing circuit 1002 can correspond to... Figure 5 The relevant description of S104.

[0240] Interface circuit 1001 is also used to send first status information to the transmitting device, the first status information indicating the status after link training of the first parameters based on the first link training request. This function of interface circuit 1001 can correspond to... Figure 5 The relevant description of S105.

[0241] In some possible implementations, the receiver module includes an optical module with parameters that are the same as those in the optical module; or, the receiver module includes an ACC-Linear module with parameters that are the same as those in the ACC-Linear module.

[0242] In some possible implementations, for the case where the receiver module is an LPO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LPO.

[0243] In some other possible implementations, for the case where the receiver module is an LRO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LRO.

[0244] In this embodiment of the application, the LRO includes an optical digital signal processor (oDSP) chip, the transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

[0245] In some possible implementations, the processing circuit 1002 is specifically used to: in response to a first link training request, perform link training on the parameters of the receiving module via the IIC bus.

[0246] In some possible implementations, the interface circuit 1001 is further configured to receive a second link training request sent by the transmitting device, the second link training request being used to instruct the receiving PHY chip to perform link training on the second parameters, the second parameters including the parameters of the receiving PHY chip; the processing circuit 1002 is further configured to perform link training on the second parameters according to the second link training request; the interface circuit 1001 is further configured to send second status information to the transmitting device, the second status information indicating the status after performing link training on the second parameters based on the second link training request.

[0247] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0248] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0249] It should be noted that for details regarding the chip 1000, please refer to the description of the relevant operations performed by the receiving PHY chip in method 100.

[0250] Accordingly, embodiments of this application also provide a communication device 1100, such as... Figure 11 As shown, the device 1100 may include, for example, a processing unit 1101, a transmitting unit 1102, and a receiving unit 1103. The receiving unit 1103 and the transmitting unit 1102 may correspond to the interface circuit 1001 in the chip 1000 or the interface 1201 in the communication device 1200 described below; the processing unit 1101 may correspond to the processing circuit 1002 in the chip 1000 or the processor 1202 in the communication device 1200 described below.

[0251] If the communication device 1100 is used in a transmitting device, then the functions of each structure in the communication device 1100 are as follows:

[0252] Processing unit 1101 is used to generate a first link training request; sending unit 1102 is used to send the first link training request to the receiving PHY chip, the first link training request being used to instruct the receiving PHY chip to perform link training on a first parameter, the first parameter including at least the parameters of the receiving module, the parameters of the receiving module being optical module parameters; receiving unit 1103 is used to receive first status information, the first status information indicating the status after performing link training on the first parameter based on the first link training request.

[0253] In some possible implementations, in one case, the receiver module may include an optical module whose parameters are those of the optical module itself. For example, if the receiver module is an LPO, then the optical module parameters can be those of the DRV_CTLE parameter in the LPO. In another case, the receiver module may also include an ACC-Linear module whose parameters are those of the ACC-Linear module itself.

[0254] In some possible implementations, for the case where the receiver module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LPO, then the transmitter device can refer to the transmitter PHY chip; as another example, the communication system can be an LPO-retimed architecture, that is, the transmitter module connected to the transmitter PHY chip is a retimed optical module, then the transmitter device can refer to the transmitter PHY chip or the transmitter module; as yet another example, the communication system can be an LPO-LRO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LRO, then the transmitter device can refer to the transmitter PHY chip or the transmitter module.

[0255] In some other possible implementations, for the case where the receiver module is an LRO, as an example, the communication system can be an LRO-LPO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LPO, then the transmitter device is the transmitter PHY chip; as another example, the communication system can be an LRO-retimed architecture, that is, the transmitter module connected to the transmitter PHY chip is a retimed optical module, then the transmitter device is either the transmitter PHY chip or the transmitter module; as yet another example, the communication system can be an LRO-LRO architecture, that is, the transmitter module connected to the transmitter PHY chip is an LRO, then the transmitter device is either the transmitter PHY chip or the transmitter module.

[0256] In this application, the LRO may include an oDSP chip, the TX pin of the receiving PHY chip is connected to the oDSP chip of the LRO, and the RX pin of the transmitting PHY chip is not connected to the oDSP chip of the LRO.

[0257] In some possible implementations, the processing unit 1101 is further configured to generate a second link training request, which instructs the receiving PHY chip to perform link training on the second parameters, the second parameters including the parameters of the receiving PHY chip; the sending unit 1102 is further configured to send the second link training request to the receiving PHY chip; and the receiving unit 1103 is further configured to receive second status information sent by the receiving PHY chip, the second status information indicating the status after link training on the second parameters based on the second link training request.

[0258] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0259] In some possible implementations, the receiving unit 1103 is also used to receive test information; the processing unit 1101 is also used to test the link quality of the link from the receiving PHY chip to the transmitting device based on the test information, and obtain test results.

[0260] In some possible implementations, the processing unit 1101 is further configured to generate a third link training request if it is determined that the test result does not meet the first condition. The third link training request is used to instruct the receiving PHY chip to continue link training on the first parameter. The sending unit 1102 is further configured to send the third link training request to the receiving PHY chip. The receiving unit 1103 is further configured to receive third status information, which indicates the status after link training on the first parameter based on the third link training request.

[0261] As an example, the first condition may include any one of the following: the change in the value of the first quality indicator is less than or equal to the first threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the change in the value of the second quality indicator is greater than or equal to the second threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0262] In some possible implementations, the processing unit 1101 is further configured to perform link training on the third parameter if it is determined that the test result meets the first condition but does not meet the second condition. The third parameter includes the parameters of the transmitting module, which are the parameters of the optical module.

[0263] As an example, the second condition may include any one of the following conditions: the value of the first quality indicator is less than or equal to the third threshold, the first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the smaller the value of the first quality indicator, the better the corresponding link quality; the value of the second quality indicator is greater than or equal to the fourth threshold, the second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device, and the larger the value of the second quality indicator, the better the corresponding link quality.

[0264] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0265] It should be noted that for related descriptions of the communication device 1100, please refer to the descriptions of the relevant operations performed by the transmitting device in method 100.

[0266] If the communication device 1100 is used in a receiving PHY chip, then the functions of each structure in the communication device 1100 are as follows:

[0267] The receiving unit 1103 is used to receive a first link training request sent by the transmitting device. The first link training request is used to instruct the receiving PHY chip to perform link training on a first parameter. The first parameter includes the parameters of the receiving module, which are optical module parameters. The processing unit 1101 is used to perform link training on the first parameter according to the first link training request. The sending unit 1102 is used to send first status information to the transmitting device. The first status information indicates the status after performing link training on the first parameter based on the first link training request.

[0268] In some possible implementations, the receiver module includes an optical module with parameters that are the same as those in the optical module; or, the receiver module includes an ACC-Linear module with parameters that are the same as those in the ACC-Linear module.

[0269] In some possible implementations, for the case where the receiver module is an LPO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LPO.

[0270] In some other possible implementations, for the case where the receiver module is an LRO, if the transmitter device is a transmitter PHY chip, the transmitter module connected to the transmitter PHY chip is an LPO; if the transmitter device is a transmitter PHY chip or a transmitter module, the transmitter module is a traditional optical module or an LRO.

[0271] In this embodiment of the application, the LRO includes an optical digital signal processor (oDSP) chip, the transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

[0272] In some possible implementations, the processing unit 1101 is specifically used to: in response to a first link training request, perform link training on the parameters of the receiving module via the IIC bus.

[0273] In some possible implementations, the receiving unit 1103 is further configured to receive a second link training request sent by the transmitting device. The second link training request is used to instruct the receiving PHY chip to perform link training on the second parameters, which include the parameters of the receiving PHY chip. The processing unit 1101 is further configured to perform link training on the second parameters according to the second link training request. The sending unit 1102 is configured to send second status information to the transmitting device. The second status information indicates the status after performing link training on the second parameters based on the second link training request.

[0274] In some other possible implementations, the first parameter also includes parameters of the receiver PHY chip.

[0275] In some possible implementations, the first link training request is a training frame, which includes a control field to indicate link training for the first parameter. For example, link training for the first parameter can be indicated by multiple reserved bits in the control field; or, link training for the first parameter can be indicated by one reserved bit in the control field and a parameter selection field; or, link training for the first parameter can be indicated by a combination of reserved values ​​in the parameter selection field of the control field.

[0276] It should be noted that for related descriptions of the communication device 1100, please refer to the descriptions of the relevant operations performed by the receiving PHY chip in method 100.

[0277] Accordingly, embodiments of this application also provide a communication device 1200, such as... Figure 12As shown. The communication device 1200 may include an interface 1201 and a processor 1202. The interface 1201 may correspond to the interface circuit 1001 in the chip 1000 or the receiving unit 1103 and the transmitting unit 1102 in the communication device 1100; the processor 1202 may correspond to the processing circuit 1002 in the chip 1000 or the processing unit 1101 in the communication device 1100.

[0278] Interface 1201 is used to receive instructions and transmit them to processor 1202;

[0279] Processor 1202, for performing the above Figure 5 Method 100 or shown Figure 6 The example shown.

[0280] Furthermore, embodiments of this application also provide a communication system 1300, such as... Figure 13 As shown. The communication system 1300 may include a transmitting device 1301 and a receiving PHY chip 1302.

[0281] The transmitting device 1301 is used to execute the above method 100 or Figure 6 The steps performed by the sending device in the illustrated embodiment;

[0282] The receiving PHY chip 1302 is used to perform the above method 100 or Figure 6 The steps performed by the receiving PHY chip in the illustrated embodiment.

[0283] Furthermore, this application embodiment also provides a storage medium storing program code or instructions, which, when run on a processor, cause the processor to execute the method under any of the above embodiments.

[0284] Furthermore, this application also provides a program product that, when run on a processor, causes the processor to execute the method under any of the aforementioned implementations.

[0285] It should be understood that "determining B based on A" mentioned in the embodiments of this application does not mean determining B solely based on A, but also determining B based on A and / or other information.

[0286] It should be understood that the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0287] In this application, ordinal numbers such as “1”, “2”, “3”, “first”, “second”, and “third” are used to distinguish multiple objects, not to limit the order of multiple objects.

[0288] The reference to "A and / or B" in this application should be understood to include the following situations: including only A, including only B, or including both A and B.

[0289] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0290] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system and device embodiments are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device and system embodiments described above are merely illustrative. Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0291] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A link training method, characterized in that, include: The transmitting device generates a first link training request, which is used to instruct the receiving PHY chip to perform link training on a first parameter. The first parameter includes the parameters of the receiving module, which are optical module parameters. The transmitting device sends the first link training request to the receiving PHY chip; The transmitting device receives first status information, which indicates the status after link training of the first parameters based on the first link training request.

2. The method according to claim 1, characterized in that, The method further includes: The transmitting device generates a second link training request, which is used to instruct the receiving PHY chip to perform link training on a second parameter, the second parameter including the parameters of the receiving PHY chip. The transmitting device sends the second link training request to the receiving PHY chip; The transmitting device receives second status information sent by the receiving PHY chip, the second status information indicating the status after link training of the second parameters based on the second link training request.

3. The method according to claim 1, characterized in that, The first parameter also includes the parameters of the receiving end PHY chip.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: The transmitting device receives test information; The transmitting device tests the link quality from the receiving PHY chip to the transmitting device based on the test information, and obtains the test results.

5. The method according to claim 4, characterized in that, The method further includes: If the transmitting device determines that the test result does not meet the first condition, the transmitting device generates a third link training request, which is used to instruct the receiving PHY chip to continue link training on the first parameter. The transmitting device sends the third link training request to the receiving PHY chip; The transmitting device receives third status information, which indicates the status after link training of the first parameter based on the third link training request.

6. The method according to claim 5, characterized in that, The first condition includes any one of the following conditions: The change in the value of the first quality indicator is less than or equal to the first threshold. The first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The smaller the value of the first quality indicator, the better the corresponding link quality. The change in the value of the second quality indicator is greater than or equal to the second threshold. The second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The larger the value of the second quality indicator, the better the corresponding link quality.

7. The method according to claim 5 or 6, characterized in that, The method further includes: If the transmitting device determines that the test result meets the first condition but not the second condition, then the transmitting device performs link training on the third parameter, which includes the parameters of the transmitting module, and the parameters of the transmitting module are the optical module parameters.

8. The method according to claim 7, characterized in that, The second condition includes any one of the following conditions: The value of the first quality indicator is less than or equal to the third threshold. The first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The smaller the value of the first quality indicator, the better the corresponding link quality. The value of the second quality indicator is greater than or equal to the fourth threshold. The second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The larger the value of the second quality indicator, the better the corresponding link quality.

9. The method according to any one of claims 1-8, characterized in that, The first link training request is a training frame, which includes a control field used to indicate link training for the first parameter.

10. The method according to claim 9, characterized in that, The control field uses multiple reserved bits to indicate that the first parameter should be trained via a link; Alternatively, a reserved bit and a parameter selection field in the control field can be used to indicate that the first parameter is to be trained on a link; Alternatively, the reserved value combination of the parameter selection field in the control field can be used to instruct link training on the first parameter.

11. The method according to any one of claims 1-10, characterized in that, The receiving module includes an optical module, and the parameters of the optical module are the parameters in the optical module; Alternatively, the receiving module may include a linear active copper cable ACC-Linear module, and the optical module parameters may be the parameters of the ACC-Linear module.

12. The method according to any one of claims 1-10, characterized in that, The receiving module is a linearly driven pluggable optical module (LPO), and the transmitting device is a transmitting PHY chip. The transmitting PHY chip is connected to the transmitting module, which is the LPO. Alternatively, the receiving module is an LPO, and the transmitting device is a transmitting PHY chip or a transmitting module. The transmitting module is a traditional optical module or an LRO. The LRO includes an optical digital signal processor (oDSP) chip. The transmitting end (TX) of the receiving PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting PHY chip is not connected to the oDSP chip.

13. The method according to any one of claims 1-10, characterized in that, The receiving module is an LRO, the transmitting device is a transmitting PHY chip, and the transmitting PHY chip is connected to the transmitting module an LPO; Alternatively, the receiving module is an LRO, and the transmitting device is a transmitting PHY chip or a transmitting module, wherein the transmitting module is a traditional optical module or an LRO; The LRO includes an optical digital signal processor (oDSP) chip. The transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, while the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

14. A link training method, characterized in that, include: The receiving PHY chip receives a first link training request sent by the transmitting device. The first link training request is used to instruct the receiving PHY chip to perform link training on a first parameter. The first parameter includes the parameters of the receiving module, and the parameters of the receiving module are optical module parameters. The receiving PHY chip performs link training on the first parameters according to the first link training request. The receiving PHY chip sends first status information to the transmitting device, the first status information indicating the status after link training of the first parameters based on the first link training request.

15. The method according to claim 14, characterized in that, The receiving PHY chip performs link training on the first parameters according to the first link training request, including: In response to the first link training request, the receiving PHY chip performs link training on the parameters of the receiving module through the built-in integrated circuit IIC bus.

16. The method according to claim 14 or 15, characterized in that, The method further includes: The receiving PHY chip receives a second link training request sent by the transmitting device. The second link training request is used to instruct the receiving PHY chip to perform link training on a second parameter, which includes the parameters of the receiving PHY chip. The receiving PHY chip performs link training on the second parameters according to the second link training request. The receiving PHY chip sends second status information to the transmitting device, the second status information indicating the status after link training of the second parameters based on the second link training request.

17. The method according to claim 14 or 15, characterized in that, The first parameter also includes the parameters of the receiving end PHY chip.

18. The method according to any one of claims 14-17, characterized in that, The first link training request is a training frame, which includes a control field used to indicate link training for the first parameter.

19. The method according to claim 18, characterized in that, The control field uses multiple reserved bits to indicate that the first parameter should be trained via a link; Alternatively, a reserved bit and a parameter selection field in the control field can be used to indicate that the first parameter is to be trained on a link; Alternatively, the reserved value combination of the parameter selection field in the control field can be used to instruct link training on the first parameter.

20. The method according to any one of claims 14-19, characterized in that, The receiving module includes an optical module, and the parameters of the optical module are the parameters in the optical module; Alternatively, the receiving module may include a linear active copper cable ACC-Linear module, and the optical module parameters may be the parameters of the ACC-Linear module.

21. The method according to any one of claims 14-19, characterized in that, The receiving module is a linearly driven pluggable optical module (LPO), and the transmitting device is a transmitting PHY chip. The transmitting PHY chip is connected to the transmitting module, which is the LPO. Alternatively, the receiving module is an LPO, and the transmitting device is a transmitting PHY chip or a transmitting module. The transmitting module is a traditional optical module or an LRO. The LRO includes an optical digital signal processor (oDSP) chip. The transmitting end (TX) of the receiving PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting PHY chip is not connected to the oDSP chip.

22. The method according to any one of claims 14-19, characterized in that, The receiving module is an LRO, the transmitting device is a transmitting PHY chip, and the transmitting PHY chip is connected to the transmitting module an LPO; Alternatively, the receiving module is an LRO, and the transmitting device is a transmitting PHY chip or a transmitting module, wherein the transmitting module is a traditional optical module or an LRO; The LRO includes an optical digital signal processor (oDSP) chip. The transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, while the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

23. A communication device, characterized in that, The communication device includes an interface and a processor; The interface is used to receive instructions and transmit them to the processor; The processor is configured to perform the method according to any one of claims 1-22.

24. A chip, characterized in that, The chip includes interface circuitry and processing circuitry; The processing circuit is used to generate a first link training request, which instructs the receiving PHY chip to perform link training on a first parameter. The first parameter includes parameters of the receiving module, which are optical module parameters. The interface circuit is used to send the first link training request to the receiving PHY chip; The interface circuit is also used to receive first status information, which indicates the status after link training of the first parameter based on the first link training request.

25. The chip according to claim 24, characterized in that, The processing circuit is further configured to generate a second link training request, which instructs the receiving PHY chip to perform link training on a second parameter, the second parameter including the parameters of the receiving PHY chip. The interface circuit is also used to send the second link training request to the receiving PHY chip; The interface circuit is also used to receive second status information sent by the receiving end PHY chip, the second status information indicating the status after link training of the second parameter based on the second link training request.

26. The chip according to claim 24, characterized in that, The first parameter also includes the parameters of the receiving end PHY chip.

27. The chip according to any one of claims 24-26, characterized in that, The interface circuit is also used to receive test information; The processing circuit is also used to test the link quality of the link from the receiving PHY chip to the transmitting device based on the test information, and obtain the test results.

28. The chip according to claim 27, characterized in that, The processing circuit is further configured to generate a third link training request if it is determined that the test result does not meet the first condition. The third link training request is used to instruct the receiving end PHY chip to continue link training on the first parameter. The interface circuit is also used to send the third link training request to the receiving PHY chip; The interface circuit is also used to receive third state information, which indicates the state after link training of the first parameter based on the third link training request.

29. The chip according to claim 28, characterized in that, The first condition includes any one of the following conditions: The change in the value of the first quality indicator is less than or equal to the first threshold. The first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The smaller the value of the first quality indicator, the better the corresponding link quality. The change in the value of the second quality indicator is greater than or equal to the second threshold. The second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The larger the value of the second quality indicator, the better the corresponding link quality.

30. The chip according to claim 28 or 29, characterized in that, The processing circuit is further configured to perform link training on the third parameter if it is determined that the test result satisfies the first condition but not the second condition, wherein the third parameter includes the parameters of the transmitting end module, and the parameters of the transmitting end module are optical module parameters.

31. The chip according to claim 30, characterized in that, The second condition includes any one of the following conditions: The value of the first quality indicator is less than or equal to the third threshold. The first quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The smaller the value of the first quality indicator, the better the corresponding link quality. The value of the second quality indicator is greater than or equal to the fourth threshold. The second quality indicator is used to characterize the link quality from the receiving PHY chip to the transmitting device. The larger the value of the second quality indicator, the better the corresponding link quality.

32. The chip according to any one of claims 24-31, characterized in that, The first link training request is a training frame, which includes a control field used to indicate link training for the first parameter.

33. The chip according to claim 32, characterized in that, The control field uses multiple reserved bits to indicate that the first parameter should be trained via a link; Alternatively, a reserved bit and a parameter selection field in the control field can be used to indicate that the first parameter is to be trained on a link; Alternatively, the reserved value combination of the parameter selection field in the control field can be used to instruct link training on the first parameter.

34. The chip according to any one of claims 24-33, characterized in that, The receiving module includes an optical module, and the parameters of the optical module are the parameters in the optical module; Alternatively, the receiving module may include a linear active copper cable ACC-Linear module, and the optical module parameters may be the parameters of the ACC-Linear module.

35. The chip according to any one of claims 24-33, characterized in that, The receiving module is a linearly driven pluggable optical module (LPO), the chip is a transmitting PHY chip, and the transmitting PHY chip is connected to the transmitting module LPO. Alternatively, the receiving module is an LPO, the chip is a transmitting PHY chip or a chip in the transmitting module, the transmitting module is a traditional optical module or an LRO, the LRO includes an optical digital signal processor (oDSP) chip, the transmitting end (TX) of the receiving PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting PHY chip is not connected to the oDSP chip.

36. The chip according to any one of claims 24-33, characterized in that, The receiving module is an LRO, the chip is a transmitting PHY chip, and the transmitting PHY chip is connected to the transmitting module an LPO; Alternatively, the receiving module is an LRO, the chip is a transmitting PHY chip or a chip in the transmitting module, and the transmitting module is a traditional optical module or an LRO; The LRO includes an optical digital signal processor (oDSP) chip. The transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, while the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

37. A chip, characterized in that, The chip is a receiver PHY chip, which includes interface circuitry and processing circuitry. The interface circuit is used to receive a first link training request sent by the transmitting device. The first link training request is used to instruct the receiving PHY chip to perform link training on a first parameter. The first parameter includes the parameters of the receiving module, and the parameters of the receiving module are optical module parameters. The processing circuit is used to perform link training on the first parameter according to the first link training request. The interface circuit is also used to send first status information to the transmitting device, the first status information indicating the status after link training of the first parameter based on the first link training request.

38. The chip according to claim 37, characterized in that, The processing circuit is specifically used for: In response to the first link training request, the parameters of the receiving module are trained via the built-in integrated circuit IIC bus.

39. The chip according to claim 37 or 38, characterized in that, The interface circuit is also used to receive a second link training request sent by the transmitting device. The second link training request is used to instruct the receiving PHY chip to perform link training on a second parameter, the second parameter including the parameters of the receiving PHY chip. The processing circuit is further configured to perform link training on the second parameters according to the second link training request; The interface circuit is also used to send second status information to the transmitting device, the second status information indicating the status after link training of the second parameter based on the second link training request.

40. The chip according to claim 37 or 38, characterized in that, The first parameter also includes the parameters of the receiving end PHY chip.

41. The chip according to any one of claims 37-40, characterized in that, The first link training request is a training frame, which includes a control field used to indicate link training for the first parameter.

42. The chip according to claim 41, characterized in that, The control field uses multiple reserved bits to indicate that the first parameter should be trained via a link; Alternatively, a reserved bit and a parameter selection field in the control field can be used to indicate that the first parameter is to be trained on a link; Alternatively, the reserved value combination of the parameter selection field in the control field can be used to instruct link training on the first parameter.

43. The chip according to any one of claims 37-42, characterized in that, The receiving module includes an optical module, and the parameters of the optical module are the parameters in the optical module; Alternatively, the receiving module may include a linear active copper cable ACC-Linear module, and the optical module parameters may be the parameters of the ACC-Linear module.

44. The chip according to any one of claims 37-42, characterized in that, The receiving module is a linearly driven pluggable optical module (LPO), and the transmitting device is a transmitting PHY chip. The transmitting PHY chip is connected to the transmitting module, which is the LPO. Alternatively, the receiving module is an LPO, and the transmitting device is a transmitting PHY chip or a transmitting module. The transmitting module is a traditional optical module or an LRO. The LRO includes an optical digital signal processor (oDSP) chip. The transmitting end (TX) of the receiving PHY chip is connected to the oDSP chip, and the receiving end (RX) of the transmitting PHY chip is not connected to the oDSP chip.

45. The chip according to any one of claims 37-42, characterized in that, The receiving module is an LRO, the transmitting device is a transmitting PHY chip, and the transmitting PHY chip is connected to the transmitting module an LPO; Alternatively, the receiving module is an LRO, and the transmitting device is a transmitting PHY chip or a transmitting module, wherein the transmitting module is a traditional optical module or an LRO; The LRO includes an optical digital signal processor (oDSP) chip. The transmitting end (TX) of the receiving end PHY chip is connected to the oDSP chip, while the receiving end (RX) of the transmitting end PHY chip is not connected to the oDSP chip.

46. ​​A communication system, characterized in that, The communication system includes a receiver PHY chip and a transmitter device; The transmitting device is configured to perform the method according to any one of claims 1-13; The receiving PHY chip is used to perform the method described in any one of claims 14-22.

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