T-shaped deep trench structure capacitor and manufacturing method thereof

Abstract

This invention discloses a T-shaped deep trench capacitor and its manufacturing method. In this capacitor, four T-shaped structures are rotated and combined to form a square minimum unit, with the overall structure exhibiting central symmetry. This solves the wafer warpage problem caused by stress imbalance in individual T-shaped structures. The side length of the minimum unit is 4a+3b. Depending on the process requirements, a and b can be flexibly varied, but the minimum unit always remains square, achieving close packing during manufacturing and increasing capacitor density. Furthermore, the T-shaped silicon pillar structure exhibits superior structural stability compared to rectangular or other structures. Simultaneously, when filling different material films in a high aspect ratio structure, the interconnectedness of all deep trenches facilitates the full flow and uniform diffusion of reactant gases within the trenches. The capacitor manufactured using this method exhibits better structural stability, thin film deposition effect, and coverage, resulting in superior performance.

Description

Technical Field

[0001] This invention belongs to the field of silicon capacitor technology, and particularly relates to a T-type deep trench structure capacitor and its manufacturing method. Background Technology

[0002] In the field of micro-nano electronics, as electronic products develop towards high performance and high integration, the performance requirements for silicon capacitors are becoming increasingly stringent. Silicon capacitors possess unique advantages in high-frequency characteristics, high reliability, and miniaturization, and are widely used in high-end communications, automotive electronics, high-performance chips, aerospace, and other fields, providing functions such as decoupling, filtering, DC blocking, and power matching. However, the typical deep trench structure array distribution of silicon capacitors is prone to stress during the manufacturing process, leading to wafer warping or internal silicon wall cracking, thus affecting the capacitor's production yield and lifespan. On the other hand, to meet the miniaturization and high-capacity requirements of end products, it is necessary to increase capacitor density. However, most deep trench structure array layouts are difficult to achieve dense packing, resulting in wasted substrate area and limiting the increase in capacitance per unit area and the reduction in unit cost. Therefore, researchers have studied deep trench structures that can solve these problems, such as a deep trench manufacturing method disclosed by the Chinese Patent Office [Application No. 201210378133.3]. Figure 1 As shown, the deep trench structure disclosed in this patent can ensure the symmetrical distribution of stress in all directions on the silicon wafer, ensuring that the stress in one direction is not too large, thereby improving the warpage of the silicon wafer to a certain extent. However, in its solution, the deep trench structure array cannot achieve the connection between deep trenches. Therefore, when depositing thin films in the deep trenches, the flow of gaseous material inside the deep trenches will be obstructed and the airflow distribution will be uneven, resulting in unevenness of the deposited thin films. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a T-shaped deep trench structure capacitor and its manufacturing method. By rationally combining and arranging the trench structure units on the substrate, the surface area of ​​the electrode structure is maximized, while improving structural stability, reducing the impact of stress imbalance, and ensuring uniform dielectric filling to meet the application requirements of high-precision, high-yield, and high-reliability capacitors.

[0004] To achieve the above-mentioned objective, this invention provides a T-shaped deep trench capacitor, comprising a substrate having a plurality of square minimum units. Each minimum unit is composed of four T-shaped structures, with gaps between the T-shaped structures forming trenches. Each T-shaped structure includes a first arm and a second arm, one end of the second arm being perpendicularly connected to the middle of the first arm. The four T-shaped structures rotate around the center of the minimum unit, and the first arms of the four T-shaped structures are respectively located at the upper left, lower left, upper right, and lower right corners of the minimum unit, arranged in a centrally symmetrical manner. The ends of the second arms of the four T-shaped structures that are not connected to the first arm all face the center of the minimum unit. The four T-shaped structures in each minimum unit are spaced apart and not in contact, with the gaps between the four T-shaped structures forming interconnected trenches. A stacked layer is provided on the substrate surface and the trench surface. The stacked layer is formed by stacking a first conductive layer and a dielectric layer from bottom to top. The first conductive layer has one more layer than the dielectric layer. A first insulating isolation layer is provided on the stacked layer. A second conductive layer is provided on the first insulating isolation layer. A second insulating isolation layer is provided on the second conductive layer. A first contact via and a second contact via are provided from the second insulating isolation layer downwards, connecting to the surface of the bottom first conductive layer of the stacked layer. A second conductive layer is provided at the bottom of the first contact via where it contacts the surface of the first conductive layer. A second insulating isolation layer is provided on the wall of the first contact via. The first contact via is filled with conductive material to form a first electrode. The second contact via is filled with conductive material to form a second electrode.

[0005] Preferably, the first arm of the T-shaped structure is formed by connecting three a·a squares and two a·b squares in sequence, with a length of 3a+2b and a width; the second arm of the T-shaped structure is formed by connecting one a·a square and one a·b square, with a length of a+b and a width; the side length of the smallest unit is 4a+3b; the depth of the groove is H; the area of ​​the inner sidewall of the smallest unit is 4(6a+4b)H; the sum of the bottom and top areas is (4a+3b). 2 The total surface area is: 4(6a+4b)H +(4a+3b) 2 The corners of the T-shaped structure are chamfered, preferably rounded.

[0006] Preferably, the substrate is one of a silicon substrate, a quartz substrate, a silicon carbide substrate, or silicon-on-insulator.

[0007] Preferably, the raw material of the first conductive layer is one of heavily doped polycrystalline silicon, metal, or metal silicide.

[0008] Preferably, the raw material of the dielectric layer is one or more combinations of single metal oxide, multilayer metal oxide, silicon oxide, and silicon nitride.

[0009] Preferably, the first insulating layer is a silicon nitride or silicon oxide thin film layer.

[0010] Preferably, the second conductive layer is an aluminum layer.

[0011] Preferably, the second insulating layer is a silicon nitride or silicon oxide layer.

[0012] Preferably, the conductive material is one or a combination of tungsten, nickel, titanium, gold, and palladium.

[0013] A method for manufacturing a T-type deep trench capacitor mainly includes the following steps:

[0014] Step 1: Form a hard mask layer and a photoresist layer on the substrate. Divide the photoresist layer into several square minimum units using photolithography, and form a pattern on each minimum unit. The pattern consists of four T-shaped structures rotating around the center of the minimum unit. Each T-shaped structure includes a first arm and a second arm. One end of the second arm is vertically connected to the middle of the first arm. The first arms of the four T-shaped structures are located at the upper left, lower left, upper right, and lower right corners of the minimum unit, respectively, and are centrally symmetrically distributed. The ends of the second arms of the four T-shaped structures that are not connected to the first arm all face the center of the minimum unit. The four T-shaped structures in each minimum unit are spaced apart and not in contact. The gaps between the four T-shaped structures in each minimum unit form trenches, which are interconnected. Dry etching is performed on the non-photoresist areas outside the pattern to form trenches with a high aspect ratio on the substrate. The pattern projection area is the silicon wall of the T-shaped structure. Wet and dry etching processes are used to remove the photoresist and hard mask layer.

[0015] Step 2: Form a stacked layer on the surface of the substrate and the inner surface of the trench. The stacked layer is formed by stacking a first conductive layer and a dielectric layer from bottom to top. The first conductive layer has one more layer than the dielectric layer.

[0016] Step 3: Using photolithography and etching processes, remove the first conductive layer and dielectric layer sequentially from top to bottom at specific locations of the stacked layers until the surface of the bottom first conductive layer is removed, which serves as a contact hole connecting to the bottom first conductive layer.

[0017] Step 4: SiO2 and silicon nitride are deposited on the surface of the uppermost first conductive layer and the surface of the lowermost first conductive layer using chemical vapor deposition to form a first insulating isolation layer. After photolithography and etching processes, windows are formed to serve as contact holes with the uppermost first conductive layer. At the same time, the first insulating isolation layer deposited on the surface of the lowermost first conductive layer is removed.

[0018] Step 5: An aluminum layer is formed using physical vapor deposition. After patterning, the aluminum layer forms a second conductive layer that is connected to both the uppermost and lowermost first conductive layers.

[0019] Step 6: On the second conductive layer, a second insulating isolation layer is formed by high-density plasma chemical vapor deposition using silicon nitride or silicon oxide. From the second insulating isolation layer downwards, a first contact via and a second contact via are formed by photolithography and etching processes. The first contact via is connected to the surface of the second conductive layer connected to the bottom first conductive layer, and the second contact via is connected to the surface of the second conductive layer connected to the top first conductive layer. Conductive material is filled into the first contact via and the second contact via to form corresponding first electrodes and second electrodes.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1. The smallest unit can maintain its square shape even when a and b are changed. At the same time, by rationally distributing the square units on the substrate, a close-packed structure can be maintained in a limited space, increasing the capacitance of the capacitor so that it can store more charge. Furthermore, it can improve the structural stability while maximizing the surface area of ​​the electrode structure to meet application requirements.

[0022] 2. T-shaped solid structures are more stable and can easily withstand mechanical forces from multiple angles. Due to the lateral support or tensile force, they are less likely to collapse during processing, especially for structures with high aspect ratio and high density.

[0023] 3. Four T-shaped solid structures are used to form a square centrally symmetrical structural unit. The trenches are interconnected and centrally symmetrically distributed, which is conducive to the uniform distribution and smooth flow of gas in the trenches, thereby obtaining a uniform thin film deposition effect and improving the step coverage of the thin film deposition.

[0024] 4. Due to the adoption of a centrally symmetrical T-shaped square unit, the stress generated during the processing can be mutually canceled out, ensuring that the substrate will not warp due to stress in a specific direction. The larger the substrate, the more severe the warping. In addition, during the use of the capacitor, there will be no device failure or reliability loss due to thermal or mechanical stress.

[0025] 5. By controlling the physical dimensions of the "T" shape and the width of the groove, a higher unit surface area can be obtained, thereby achieving a higher capacitance density. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a deep trench structure in the prior art from a top-down perspective.

[0027] Figure 2 This is a schematic diagram of the smallest unit of the T-shaped deep trench capacitor of the present invention from a top view.

[0028] Figure 3 A cross-sectional view of the T-shaped deep trench capacitor of the present invention.

[0029] Figure 4 This is a schematic diagram of the T-shaped deep trench structure capacitor of the present invention after changing the sizes of a and b of the T-shaped structure.

[0030] Figure 5 The diagram shows the gas velocity distribution in (a) the structure of the present invention and (b) a conventional strip groove structure array.

[0031] Figure 6 The diagram shows the gas pressure distribution inside (a) the structure of the present invention and (b) the strip groove structure.

[0032] In the figure, 1 is the substrate; 2 is the T-structure; 3 is the trench; 4 is the first conductive layer; 5 is the dielectric layer; 6 is the first insulating layer; 7 is the second conductive layer; 8 is the second insulating layer; 9 is the first electrode; and 10 is the second electrode. Detailed Implementation

[0033] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0034] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual images. They should not be construed as limiting the scope of this patent. To better illustrate the embodiments of the present invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0035] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0037] Example 1

[0038] like Figures 2-3 As shown, this invention provides a T-shaped deep trench capacitor, including a substrate 1. The substrate 1 has several square minimum units, each minimum unit consisting of four T-shaped structures 2. The gaps between the T-shaped structures 2 form trenches 3. Each T-shaped structure 2 includes a first arm and a second arm. One end of the second arm is vertically connected to the middle of the first arm. The four T-shaped structures 2 rotate around the center of the minimum unit, and the first arms of the four T-shaped structures 2 are located at the upper left, lower left, upper right, and lower right corners of the minimum unit, respectively, in a centrally symmetrical distribution. The ends of the second arms of the four T-shaped structures 2 that are not connected to the first arm all face the center of the minimum unit. The four T-shaped structures 2 in each minimum unit are arranged without contact and with gaps. The gaps between the four T-shaped structures 2 in each minimum unit form trenches 3, and the trenches 3 intersect each other. A stacked layer is provided on the surface of the substrate 1 and the surface of the trench 3 structure. The stacked layer is formed by stacking a first conductive layer 4 and a dielectric layer 5 from bottom to top. The first conductive layer 4 has one more layer than the dielectric layer 5. A first insulating isolation layer 6 is provided on the stacked layer. A second conductive layer 7 is provided on the first insulating isolation layer 6. A second insulating isolation layer 8 is provided on the second conductive layer 7. A first contact via is provided downward from the second insulating isolation layer 8, connecting to the surface of the bottom first conductive layer 4 of the stacked layer and a second contact via is provided, connecting to the surface of the second conductive layer 7. The bottom of the first contact via is connected to the surface of the first conductive layer 4, and the second insulating isolation layer 8 is provided on the wall of the first contact via. The first contact via is filled with conductive material to form a first electrode 9, and the second contact via is filled with conductive material to form a second electrode 10.

[0039] See Figure 2The first and second arms of the T-shaped structure 2, as well as the corners where they intersect (as indicated by A and B in the figure), are all chamfered, preferably rounded. The first arm of the T-shaped structure 2 is composed of three a·a squares and two a·b squares connected alternately, with a length of 3a+2b and a width of a; the second arm of the T-shaped structure 2 is composed of one a·a square and one a·b square connected, with a length of a+b and a width of a; the side length of the smallest unit is 4a+3b; the depth of the groove 3 is H, and the area of ​​the inner wall of the smallest unit is 4(6a+4b)H; the sum of the bottom and top areas is (4a+3b). 2 The total surface area is: 4(6a+4b)H +(4a+3b) 2 .like Figure 4 As shown, this structural design can maintain the square shape of the smallest unit even when a and b are changed. This allows for the reasonable distribution of the square smallest units on the substrate 1, thereby maintaining a close-packed structure within a limited space, increasing the capacitance of the capacitor, enabling it to store more charge, and improving structural stability while maximizing the surface area of ​​the electrode structure to meet application requirements.

[0040] Example 2

[0041] Reference Figure 3 This embodiment provides a method for manufacturing a T-type deep trench capacitor, which mainly includes the following steps:

[0042] Step 1: Select silicon as substrate 1. Form a hard mask layer and a photoresist layer on substrate 1. Divide the photoresist layer into several square units using photolithography, and form a pattern on each unit. (Refer to...) Figure 2 or Figure 4 The pattern consists of four T-shaped structures 2 rotating around the center of the smallest unit. Each T-shaped structure 2 includes a first arm and a second arm, with one end of the second arm vertically connected to the middle of the first arm. The first arms of the four T-shaped structures 2 are located at the upper left, lower left, upper right, and lower right corners of the smallest unit, respectively, and are centrally symmetrically distributed. The ends of the second arms of the four T-shaped structures 2 that are not connected to the first arm all face the center of the smallest unit. The four T-shaped structures 2 in each smallest unit are spaced apart and not in contact. The gaps between the four T-shaped structures 2 in each smallest unit form trenches 3, which are interconnected. Dry etching is performed on the non-photoresistive area outside the pattern to form trenches 3 with a high aspect ratio on the substrate 1. The pattern projection area is the silicon wall of the T-shaped structure 2. Wet and dry etching processes are used to remove the photoresist and hard mask layer. In other embodiments of the invention, the substrate 1 can also be a quartz substrate, a silicon carbide substrate, or silicon-on-insulator. Specifically, such as... Figure 2As shown in Figure 4, the first arm of the T-shaped structure 2 is composed of three a·a squares and two a·b squares connected in sequence with intervals, with a length of 3a+2b and a width; the second arm of the T-shaped structure 2 is composed of one a·a square and one a·b square connected, with a length of a+b and a width; the side length of the smallest unit is 4a+3b; the depth of the trench 3 is H, and the area of ​​the inner wall of the smallest unit is 4(6a+4b)H; the sum of the areas of the bottom and top is (4a+3b). 2 The total surface area is: 4(6a+4b)H +(4a+3b) 2 The corners of T-shaped structure 2 are chamfered.

[0043] Step 2: A stacked layer is formed on the surface of substrate 1 and the inner surface of trench 3. The stacked layer is formed by stacking a first conductive layer 4 and a dielectric layer 5 sequentially from bottom to top, with the first conductive layer 4 having one more layer than the dielectric layer 5. This constitutes a capacitor structure equivalent to a metal / insulator / metal (MIM). In this invention, the combination of the first conductive layer 4 and the dielectric layer 5 is not limited to this and can be adjusted according to the specific requirements of capacitance density, such as MIMIM, MIMIMIM, etc. That is, when the number of dielectric layer 5 layers is m, the number of first conductive layer 4 layers is m+1.

[0044] The first conductive layer 4 is made of heavily doped polycrystalline silicon, a metal layer, or a metal silicide. The materials of the first conductive layers 4 in different layers can be the same or different. In this embodiment, the first conductive layers 4 in different layers are preferably made of the same material. The dielectric layer 5 is a single metal oxide, multilayer metal oxide, silicon oxide, silicon nitride, or a composite material composed of these, such as SiO2, Si3N4, HfO2, Al2O3, ZrO2, La2O3, etc. The first conductive layer 4 can be prepared by low-pressure chemical vapor deposition or atomic layer deposition. The dielectric layer 5 can be prepared by atomic layer deposition or low-pressure chemical vapor deposition.

[0045] Step 3: Using photolithography and etching processes, remove the first conductive layer 4 and dielectric layer 5 sequentially from top to bottom at specific locations in the stacked layers until the surface of the bottom first conductive layer 4 is removed, which serves as a contact hole connecting the bottom first conductive layer 4.

[0046] Step 4: SiO2 and silicon nitride are deposited on the surface of the uppermost first conductive layer 4 and the surface of the lowermost first conductive layer 4 using chemical vapor deposition to form a first insulating isolation layer 6. After photolithography and etching processes, windows are formed, which serve as contact holes with the uppermost first conductive layer 4. At the same time, the first insulating isolation layer 6 deposited on the surface of the lowermost first conductive layer 4 is removed, which serves as a contact hole with the lowermost first conductive layer 4.

[0047] Step 5: An aluminum layer is formed using physical vapor deposition. After patterning, the aluminum layer forms a second conductive layer 7 that is connected to both the uppermost first conductive layer 4 and the lowermost first conductive layer 4.

[0048] Step 6: On the second conductive layer 7, a second insulating isolation layer 8 is formed by high-density plasma chemical vapor deposition using silicon nitride or silicon oxide. From the second insulating isolation layer 8 downwards, a first contact via and a second contact via are formed by photolithography and etching processes. The first contact via is connected to the surface of the second conductive layer 7 connected to the bottom first conductive layer 4, and the second contact via is connected to the surface of the second conductive layer 7 connected to the top first conductive layer 4. Conductive materials are filled into the first contact via and the second contact via to form corresponding first electrodes 9 and second electrodes 10. The conductive materials are tungsten, nickel, titanium, gold, palladium, and various combinations thereof.

[0049] Figure 5 This demonstrates the differences between (a) the structure of the present invention and (b) an array of existing strip-shaped trench structures. Figure 1 The simulation results show the gas flow rate in the array shown. The simulation reveals that the structure of this invention exhibits a high flow rate only at the center (as shown in red), while other areas show good flow rate uniformity. However, in existing strip-groove structure arrays, significant gas flow rate non-uniformity and large variations occur within each groove 3. This leads to non-uniformity during film deposition, resulting in a thicker center that gradually thins outwards. Therefore, the T-shaped deep trench structure capacitor of this invention has a better gas flow rate distribution, resulting in a more uniform deposited film.

[0050] Figure 6 The simulation results of the internal gas pressure distribution of (a) the structure of the present invention and (b) the strip trench structure are presented. It can be seen that the pressure difference in the vertical direction inside the trench 3 of the present invention is 9.3 Pa, while the pressure difference inside the trench 3 of the comparative structure is 12.5 Pa, meaning the latter has a pressure difference approximately 34% greater than the former. This indicates that the gas flow resistance in the latter trench 3 is significantly greater than that in the former, thus affecting the film deposition rate and the filling efficiency of the trench 3. Higher top pressure means a higher concentration of reactive gases, i.e., more concentrated reactants, resulting in a faster film deposition rate. For trenches with a high aspect ratio, overhangs will form at the top of the trench 3, ultimately leading to voids inside the trench 3 and preventing dense filling.

[0051] The above experiments show that, compared with the existing strip trench structure array in the background technology, the T-type deep trench structure capacitor of the present invention has better thin film deposition effect and coverage.

[0052] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A T-shaped deep trench capacitor, characterized in that, The system includes a substrate (1) having several square minimum units. Each minimum unit is composed of four T-shaped structures (2). The gaps between the T-shaped structures (2) form a trench (3). Each T-shaped structure (2) includes a first arm and a second arm. One end of the second arm is vertically connected to the middle of the first arm. The four T-shaped structures (2) rotate around the center of the minimum unit. The first arms of the four T-shaped structures (2) are located at the upper left, lower left, upper right, and lower right corners of the minimum unit, respectively, and are centrally symmetrically distributed. The ends of the second arms of the four T-shaped structures (2) that are not connected to the first arm all face the center of the minimum unit. The four T-shaped structures (2) in each minimum unit are arranged with gaps and do not contact each other. The gaps between the four T-shaped structures (2) form a trench (3), which is interconnected. The substrate (1) of the smallest unit and the surface of the trench (3) are deposited to form the various components of the capacitor. The first arm of the T-shaped structure (2) is formed by three a·a squares and two a·b squares connected in sequence, with a length of 3a+2b and a width of a. The second arm of the T-shaped structure (2) is formed by one a·a square and one a·b square connected, with a length of a+b and a width of a. The side length of the smallest unit is 4a+3b. The depth of the trench (3) is H. The area of ​​the inner sidewall of the smallest unit is 4(6a+4b)H. The sum of the bottom and top areas is (4a+3b). 2 The total surface area is: 4(6a+4b)H +(4a+3b) 2 The corners of the T-shaped structure (2) are chamfered.

2. A T-shaped deep trench capacitor according to claim 1, characterized in that, The substrate (1) is one of silicon substrate, quartz substrate, silicon carbide substrate, and silicon-on-insulator.

3. A T-shaped deep trench capacitor according to claim 1 or 2, characterized in that, The capacitor comprises a stacked layer consisting of a first conductive layer (4) and a dielectric layer (5) stacked from bottom to top. The first conductive layer (4) has one more layer than the dielectric layer (5). The stacked layer has a first insulating isolation layer (6), a second conductive layer (7) on the first insulating isolation layer (6), and a second insulating isolation layer (8) on the second conductive layer (7). A first contact via connecting to the surface of the first conductive layer (4) at the bottom of the stacked layer and a second contact via connecting to the surface of the second conductive layer (7) are provided from the second insulating isolation layer (8) downwards. The second contact via is provided at the bottom of the first contact via where it contacts the surface of the first conductive layer (4). The second insulating isolation layer (8) is provided on the wall of the first contact via. The first contact via is filled with conductive material to form a first electrode (9), and the second contact via is filled with conductive material to form a second electrode (10).

4. A T-shaped deep trench capacitor according to claim 3, characterized in that, The raw material of the first conductive layer (4) is one of heavily doped polycrystalline silicon, metal layer or metal silicide.

5. A T-shaped deep trench capacitor according to claim 3, characterized in that, The dielectric layer (5) is made of one or more combinations of single metal oxide, multilayer metal oxide, silicon oxide, and silicon nitride.

6. A T-shaped deep trench capacitor according to claim 5, characterized in that, Both the first insulating layer (6) and the second insulating layer (8) are silicon nitride or silicon oxide thin film layers.

7. A T-shaped deep trench capacitor according to claim 5, characterized in that, The second conductive layer (7) is an aluminum layer.

8. A T-shaped deep trench capacitor according to claim 5, characterized in that, The conductive material is one or more of tungsten, nickel, titanium, gold, and palladium.

9. A method for manufacturing a T-shaped deep trench capacitor, characterized in that, The main steps include: Step 1: A hard mask layer and a photoresist layer are formed on the substrate (1). The photoresist layer is divided into several square minimum units by photolithography, and a pattern is formed on the minimum unit. The pattern is formed by four T-shaped structures (2) rotating around the center of the minimum unit. Each T-shaped structure (2) includes a first arm and a second arm. One end of the second arm is vertically connected to the middle of the first arm. The first arms of the four T-shaped structures (2) are located at the upper left, lower left, upper right, and lower right corners of the minimum unit, respectively, and are centrally symmetrically distributed. The end of the second arm of the four T-shaped structures (2) that is not connected to the first arm is facing the center of the minimum unit. The four T-shaped structures (2) in each minimum unit are set with gaps and do not contact each other. The gaps between the four T-shaped structures (2) in each minimum unit form a trench (3). The trenches (3) are interconnected; dry etching is performed on the non-photoresist area outside the pattern to form a trench (3) with a high aspect ratio on the substrate (1), and the pattern projection area is the silicon wall of the T-shaped structure (2); wet and dry etching processes are used to remove the photoresist and hard mask layer; the first arm of the T-shaped structure (2) is composed of three a·a squares and two a·b squares connected in sequence, with a length of 3a+2b and a width of a; the second arm of the T-shaped structure (2) is composed of one a·a square and one a·b square connected, with a length of a+b and a width of a; the side length of the smallest unit is 4a+3b; the depth of the trench (3) is H, and the area of ​​the inner sidewall of the smallest unit is 4(6a+4b)H; the sum of the bottom and top areas is (4a+3b). 2 The total surface area is: 4(6a+4b)H +(4a+3b) 2 The corners of the T-shaped structure (2) are chamfered. Step 2: A stacked layer is formed on the surface of the substrate (1) and the inner surface of the trench (3). The stacked layer is formed by stacking a first conductive layer (4) and a dielectric layer (5) from bottom to top. The first conductive layer (4) has one more layer than the dielectric layer (5). Step 3: Using photolithography and etching processes, remove the first conductive layer (4) and dielectric layer (5) sequentially from top to bottom at specific locations of the stacked layers until the surface of the bottom first conductive layer (4) is removed, which serves as a contact hole connecting the bottom first conductive layer (4). Step 4: SiO2 and silicon nitride are deposited on the surface of the uppermost first conductive layer (4) and the surface of the lowermost first conductive layer (4) by chemical vapor deposition to form a first insulating isolation layer (6). After photolithography and etching processes, windows are formed to serve as contact holes with the uppermost first conductive layer (4). At the same time, the first insulating isolation layer (6) deposited on the surface of the lowermost first conductive layer (4) is removed. Step 5: An aluminum layer is formed by physical vapor deposition. The aluminum layer is then patterned to form a second conductive layer (7) that is connected to the uppermost first conductive layer (4) and the lowermost first conductive layer (4). Step 6: On the second conductive layer (7), a second insulating isolation layer (8) is formed by high-density plasma chemical vapor deposition of silicon nitride or silicon oxide. A first contact via and a second contact via are formed from the second insulating isolation layer (8) downwards by photolithography and etching. The first contact via is connected to the surface of the second conductive layer (7) connected to the bottom first conductive layer (4), and the second contact via is connected to the surface of the second conductive layer (7) connected to the top first conductive layer (4). Conductive materials are filled into the first contact via and the second contact via to form the corresponding first electrode (9) and second electrode (10).

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