Semiconductor device structure and forming method thereof

Abstract

The invention particularly relates to a semiconductor device structure and a forming method thereof. According to the method, a gate oxide layer on the surface of a part of a groove structure is removed, and a first material epitaxial layer is exposed to serve as a cathode material of a heterojunction diode structure; a second material layer is formed in the groove structures, the second material layer formed on the exposed first material epitaxial layer serves as an anode material of the heterojunction diode structure, and the second material layer formed on the gate oxide layer serves as a gate electrode medium; and carrying out graphical processing on the second material layer to respectively form an anode electrode and a gate electrode. According to the embodiment of the invention, the heterojunction diode structure can be introduced into a part of cells in the semiconductor device structure under the condition that the cell structure and the size are not changed.

Description

Technical Field

[0001] This application relates to the field of semiconductor device design and manufacturing, and in particular to a semiconductor device structure and a method for forming the same. Background Technology

[0002] The body diode characteristic of metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the important performance parameters, significantly affecting the device's switching dynamics and reliability. In silicon carbide (SiC) MOSFETs, due to the wide bandgap of SiC material, the body diode voltage drop is much larger than that of silicon (Si) MOSFETs.

[0003] During the switching process of SiC MOSFET devices, especially in half-bridge topology applications, a short period of high freewheeling current occurs within the dead time. This means the body diode of the SiC MOSFET device experiences a large current. If the body diode characteristics are poor during this period, it will significantly impact system efficiency. Furthermore, due to the unique properties of SiC material, particularly the high density of stacking faults (SFs), the conduction of the body diode under high current in SiC MOSFET devices may also lead to reliability issues such as bipolar degradation. Therefore, improving the body diode characteristics of SiC MOSFET devices is crucial for the device's switching dynamics and reliability. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this application provides a semiconductor device structure and a method for forming the same.

[0005] In a first aspect, this application provides a method for forming a semiconductor device structure, the method comprising:

[0006] Different injection mask layers are sequentially formed on the first material epitaxial layer, and P-body regions, N+ regions and P+ regions are respectively formed on the first material epitaxial layer based on the different injection mask layers;

[0007] Multiple trench structures are formed on the first material epitaxial layer, and a P+ region is formed at the bottom of the multiple trench structures;

[0008] A gate oxide layer is formed on the surface of the plurality of trench structures;

[0009] Remove the gate oxide layer from part of the surface of the trench structure to expose the first material epitaxial layer as the cathode material of the heterojunction diode structure;

[0010] A second material layer is formed within the plurality of trench structures, wherein the second material layer formed on the exposed first material epitaxial layer serves as the anode material of the heterojunction diode structure, and the second material layer formed on the gate oxide layer serves as the gate electrode dielectric.

[0011] The second material layer is patterned to form the anode electrode and the gate electrode, respectively.

[0012] In one possible implementation of the first aspect described above, the method further includes:

[0013] Forming an insulating dielectric layer;

[0014] A source ohmic contact is formed on the surface of the first material epitaxial layer corresponding to the source region;

[0015] The insulating dielectric layer formed on the anode electrode is etched to expose the anode electrode;

[0016] A surface metal layer is formed, wherein the exposed anode electrode is connected to the source metal, the gate electrode is connected to the gate metal, and the source ohmic contact is connected to the source metal.

[0017] In one possible implementation of the first aspect described above, the first material is silicon carbide and the second material is polycrystalline silicon.

[0018] In one possible implementation of the first aspect described above, a dry etching process or a wet etching process or both are used to remove the gate oxide layer on a portion of the surface of the trench structure.

[0019] In one possible implementation of the first aspect described above, a thin film deposition process is used to form the second material layer, and a back-etching process is used to remove excess of the second material layer from the surface of the plurality of trench structures and achieve surface planarization.

[0020] In one possible implementation of the first aspect above, the method further includes: using an in-situ doping process or an ion diffusion process after the growth of the second material to dope the second material layer, so as to form the doped second material layer.

[0021] In one possible implementation of the first aspect above, the method further includes: annealing the interface between the second material and the first material.

[0022] In one possible implementation of the first aspect described above, a dry etching process or a wet etching process or both are used to etch the insulating dielectric layer corresponding to the source region, and a nickel secondary annealing process is used to form the source ohmic contact.

[0023] In one possible implementation of the first aspect described above, a dry etching process or a wet etching process or both are used to etch the insulating dielectric layer formed on the anode electrode.

[0024] Secondly, this application also provides a semiconductor device structure, which is formed according to the method described in the first aspect above.

[0025] This application introduces heterojunction diode (HJD) structures, such as polysilicon (Poly-Si) / SiC heterojunction diode structures, into some cells within a SiC MOSFET device, instead of integrating a metal / SiC Schottky barrier diode (SBD) in the device source. In this way, the body diode characteristics and reliability of the SiC MOSFET device can be improved without changing the cell structure or introducing additional surface-source Schottky metal processing. Attached Figure Description

[0026] Figure 1a and Figure 1b A flowchart illustrating a method for forming a semiconductor device structure according to some embodiments of this application is shown;

[0027] Figures 2a to 2i A schematic diagram of the process flow of a semiconductor device structure according to some embodiments of this application is shown;

[0028] Figure 3 A band structure diagram of a semiconductor device structure according to some embodiments of this application is shown;

[0029] Figure 4 A general schematic diagram of a semiconductor device structure according to other embodiments of this application is shown. Detailed Implementation

[0030] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0031] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0033] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0034] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0035] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0036] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0037] The "body diode" characteristic of metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the important performance parameters, significantly impacting the device's switching dynamics and reliability. Specifically, a MOSFET device has a diode between its drain and source. Structurally, this diode is generated by the PN junction between the source (P-type body region) and drain (N-type epitaxial layer), hence the name "body diode." When the gate voltage is zero volt biased, if a positive voltage is applied between the source and drain, current will flow between them, exhibiting diode-like voltage-current characteristics. At this time, the device channel is not conductive; this diode characteristic is due to the body diode's turn-on capability. In SiC MOSFETs, due to the wide bandgap of SiC material, the body diode voltage drop is much larger than that of SiMOSFETs.

[0038] During the switching process of SiC MOSFET devices, especially in half-bridge topology applications, a short period of high freewheeling current occurs within the dead time. This means the body diode of the SiC MOSFET device experiences a large current. If the body diode characteristics are poor during this period, it will significantly impact system efficiency. Furthermore, due to the unique properties of SiC material, particularly the high density of stacking defects, the conduction of the body diode under high current in SiC MOSFET devices may also lead to reliability issues such as bipolar degradation. Therefore, improving the characteristics of the body diode in SiC MOSFET devices is crucial for the device's switching dynamics and reliability.

[0039] To improve the body diode characteristics of SiC MOSFETs, one approach is to integrate a Schottky diode within the body region of the SiC MOSFET device. This approach has two drawbacks. First, integrating the Schottky diode within the device body region increases the lateral cell pitch, affecting the device's conduction characteristics. Second, to simultaneously form both ohmic and Schottky contacts in the source region, the device fabrication process requires additional photolithography and processing steps, increasing complexity and impacting yield.

[0040] Based on this, this application introduces heterojunction diode structures, such as Poly-Si / SiC heterojunction diode structures, into some cells inside the SiC MOSFET device, instead of integrating metal / SiC Schottky diodes in the device source. In this way, the body diode characteristics and reliability of the SiC MOSFET device can be improved without changing the cell structure or introducing additional surface source Schottky metal processing.

[0041] Figure 1aA flowchart illustrating a method for forming a semiconductor device structure according to some embodiments of this application is shown.

[0042] like Figure 1a As shown, the forming method includes:

[0043] Step 101: Different injection mask layers are sequentially formed on the first material epitaxial layer, and P-body region, N+ region and P+ region are formed on the first material epitaxial layer based on the different injection mask layers;

[0044] Step 102: A plurality of trench structures are formed on the first material epitaxial layer, and a P+ region is formed at the bottom of the plurality of trench structures;

[0045] Step 103: Form a gate oxide layer on the surface of the multiple trench structures;

[0046] Step 104: Remove the gate oxide layer on the surface of part of the trench structure to expose the first material epitaxial layer as the cathode material of the heterojunction diode structure;

[0047] Step 105: A second material layer is formed within a plurality of trench structures, wherein the second material layer formed on the exposed first material epitaxial layer serves as the anode material of the heterojunction diode structure, and the second material layer formed on the gate oxide layer serves as the gate electrode dielectric.

[0048] Step 106: The second material layer is patterned to form the anode electrode and the gate electrode respectively.

[0049] According to steps 101 to 106 in this embodiment, a heterojunction diode structure can be introduced into a portion of the cells inside the semiconductor device structure without changing the cell structure and size.

[0050] Figures 2a to 2h A schematic diagram of the process flow of a semiconductor device structure according to some embodiments of this application is shown.

[0051] In one example, such as Figure 2a As shown, a substrate 201 for a semiconductor device structure can be prepared first, and then a first material epitaxial layer 202 can be grown on the substrate 201. The first material epitaxial layer 202 can be a SiC epitaxial layer 202. For ease of explanation, the following description uses SiC epitaxial layer, but those skilled in the art will understand that the embodiments of this application can also be applied to epitaxial layers of other materials. Furthermore, the first material epitaxial layer 202 can be an N-type doped SiC epitaxial layer 202.

[0052] In one example, such as Figure 2aAs shown, different implantation mask layers can be sequentially formed on the SiC epitaxial layer 202 according to step 101, and P-body (BodyP) regions, N+ regions, and P+ regions can be formed on the SiC epitaxial layer 202 based on the different implantation mask layers. The specific type of implantation mask layer is not limited in this embodiment; for example, the implantation mask layer can be a photoresist or a hard mask. The specific implementation method for forming each region is not limited in this embodiment; for example, the P-body region can be formed by P-type ion implantation, the N+ region can be formed by high-concentration N-type ion implantation, and the P+ region can be formed by high-concentration P-type ion implantation. Subsequently, high-temperature annealing can be performed to activate the implanted ions.

[0053] In one example, such as Figure 2b As shown, multiple trench structures 2021 can be formed on the SiC epitaxial layer 202 according to step 102. The specific implementation of forming the multiple trench structures 2021 is not limited in this embodiment; for example, dry etching, wet etching, or both can be used to form the multiple trench structures 2021. More specifically, multiple etching mask layers are formed on the SiC epitaxial layer 202, and multiple trench structures 2021 are formed on the SiC epitaxial layer 202 based on the multiple etching mask layers. The specific type of etching mask layer is not limited in this embodiment; for example, the etching mask layer can be photoresist or a hard mask, preferably a hard mask.

[0054] In one example, such as Figure 2b As shown, P+ regions can be formed at the bottom of multiple trench structures 2021 according to step 102. More specifically, multiple etching mask layers previously formed on the SiC epitaxial layer 202 can be used as implantation mask layers for bottom implantation of the trench structure 2021. Alternatively, dielectric deposition can be performed on the sidewalls of the trench structure 2021 before bottom implantation, which can effectively prevent ion implantation into the sidewalls of the trench structure 2021 and affecting device characteristics. The specific implementation method for forming the P+ region is not limited in this application embodiment. For example, the P+ region can be formed by high-concentration P-type ion implantation, followed by high-temperature annealing to activate the implanted ions.

[0055] In one example, such as Figure 2c As shown, a gate oxide layer 203 can be formed on the surface of the plurality of trench structures 2021 according to step 103. The specific implementation of forming the gate oxide layer 203 is not limited in the embodiments of this application. For example, processes including thermal oxidation or dielectric deposition or both can be used to form the gate oxide layer 203.

[0056] In one example, such as Figure 2dAs shown, step 104 can be used to remove part of the gate oxide layer 203 on the surface of the trench structure 2021, exposing the SiC epitaxial layer 202 as the cathode material of the heterojunction diode structure. For example, a dry etching process or a wet etching process or both can be used to remove part of the gate oxide layer 203 on the surface of the trench structure 2021.

[0057] In one example, such as Figure 2e As shown, a second material layer 204 can be formed within multiple trench structures 2021 according to step 105. More specifically, a thin-film deposition process can be used to form the second material layer 204. The second material layer 204 formed on the exposed SiC epitaxial layer 202 serves as the anode material of the heterojunction diode structure, and the second material layer 204 formed on the gate oxide layer 203 serves as the gate electrode dielectric. The second material layer 204 can be a Poly-Si layer 204, and when the first material epitaxial layer 202 is a SiC epitaxial layer 202, the heterojunction diode structure can be a Poly-Si / SiC heterojunction diode structure. For ease of explanation, the following description uses Poly-Si layer and Poly-Si / SiC heterojunction diode structures, but those skilled in the art will understand that embodiments of this application can also introduce heterojunction diodes of other materials into some cells inside the SiC MOSFET device.

[0058] In one example, the Poly-Si layer 204 can be doped using an in-situ doping process or an ion diffusion process after Poly-Si growth to form a doped Poly-Si layer 204. For example, an in-situ doping process can be used to dope the Poly-Si layer 204 to form a doped Poly-Si layer 204 (such as P-type or N-type doped). As another example, an ion diffusion process can be used to dope the Poly-Si layer 204 after Poly-Si growth to form a doped Poly-Si layer 204 (such as P-type or N-type doped). Specifically, using boron ion diffusion to dope the Poly-Si layer 204 can form a P-type doped Poly-Si layer 204, and using phosphorus ion diffusion to dope the Poly-Si layer 204 can form an N-type doped Poly-Si layer 204. For example, the doping process can be saturation doping. Both the P-type doped Poly-Si layer 204 and the N-type doped Poly-Si layer 204 can form a Poly-Si / SiC heterojunction diode structure with the SiC epitaxial layer 202. However, in terms of device leakage current characteristics, the P-type doped Poly-Si layer 204 has better blocking characteristics.

[0059] In one example, the Poly-Si / SiC interface can be annealed. For instance, the doped Poly-Si layer 204 can be annealed or the Poly-Si / SiC interface can be annealed using the thermal process during doping to form a well-contact Poly-Si / SiC heterojunction diode structure.

[0060] In one example, such as Figure 2e As shown, the Poly-Si layer 204 can be patterned according to step 106 to form the anode electrode 205 and the gate electrode 206 respectively. More specifically, multiple etching mask layers can be formed on the Poly-Si layer 204, and plasma etching of the Poly-Si layer 204 can be performed based on the multiple etching mask layers. The specific type of etching mask layer is not limited in this embodiment. For example, the etching mask layer can be photoresist or a hard mask, preferably photoresist. Plasma etching can include etch-back in the active region and polycrystalline line etching in other regions. In the active region, etch-back removes excess Poly-Si layer 204 from the surface of the multiple trench structures 2021 and achieves surface planarization to form the anode electrode 205 and the gate electrode 206, while polycrystalline line etching in other regions connects Poly-Si layers 204 of different cells together. As will be described below, the Poly-Si layer 204 of cell 301 is interconnected and eventually connected to the source of the device, and the Poly-Si layer 204 of cell 302 is interconnected and eventually connected to the gate of the device.

[0061] Figure 1b A flowchart illustrating a method for forming a semiconductor device structure according to some embodiments of this application is shown.

[0062] like Figure 1b As shown, the forming method further includes:

[0063] Step 107: Form an insulating dielectric layer;

[0064] Step 108: Form a source ohmic contact on the surface of the first material epitaxial layer corresponding to the source region;

[0065] Step 109: Etch the insulating dielectric layer formed on the anode electrode to expose the anode electrode;

[0066] Step 110: Form a surface metal layer, wherein the exposed anode electrode is connected to the source metal, the gate electrode is connected to the gate metal, and the source ohmic contact is connected to the source metal.

[0067] In one example, such as Figure 2fAs shown, an insulating dielectric layer 207 is formed according to step 107. The specific implementation of forming the insulating dielectric layer 207 is not limited in this application embodiment. For example, an ILD process including ILD deposition and ILD patterning can be used to form the insulating dielectric layer 207.

[0068] In one example, such as Figure 2g As shown, according to step 108, a source ohmic contact 208 is formed on the surface of the SiC epitaxial layer 202 corresponding to the source region. For example, the insulating dielectric layer 207 corresponding to the source region can be etched using a dry etching process or a wet etching process or both, and the source ohmic contact 208 can be formed using a nickel secondary annealing process.

[0069] In one example, such as Figure 2h As shown, the insulating dielectric layer 207 formed on the anode electrode 205 is etched according to step 109 to expose the anode electrode 205. For example, a dry etching process or a wet etching process or both can be used to etch the insulating dielectric layer 207 formed on the anode electrode 205.

[0070] In one example, such as Figure 2i As shown, a surface metal layer 209 is formed according to step 110, wherein the exposed anode electrode 205 is connected to the source metal, the gate electrode 206 is connected to the gate metal (not shown) through a layout, and the source ohmic contact 208 is connected to the source metal. The specific implementation of forming the surface metal layer 209 is not limited in this application embodiment; for example, surface metal deposition and etching processes can be used to form the surface metal layer 209.

[0071] This application implements, for example Figures 2a to 2i As shown, a heterojunction diode structure can be introduced into a portion of the cells 301 inside the semiconductor device structure without changing the cell structure and size, while the MOS structure of the remaining cells 302 remains unchanged.

[0072] The embodiments of this application also relate to semiconductor device structures formed according to the above-described forming method, such as trench gate semiconductor device structures, and more specifically, trench gate SiC MOSFET device structures.

[0073] Figure 3 A band structure diagram of a semiconductor device structure according to some embodiments of this application is shown.

[0074] A heterojunction is introduced in a portion of the cell 301 within the semiconductor device structure. The anode material is P-type saturated doped Poly-Si, and the cathode material is N-type doped SiC epitaxially to form a P-type heterojunction. + -Poly-Si / N -In the case of a SiC heterojunction, the band structure at the vertical dashed line of the heterojunction when no external voltage is applied is as follows: Figure 3 As shown, distance 0 refers to the boundary between Poly-Si and SiC. Moving from this boundary towards Poly-Si results in a negative distance, while moving from this boundary towards SiC results in a positive distance. Figure 3 As can be seen, the heterojunction exhibits diode characteristics, which means that it can replace the body diode of a semiconductor device under certain conditions. This solves the problems of poor body diode characteristics that significantly affect system efficiency and cause bipolar degradation, and is crucial to the switching dynamic characteristics and reliability of the device.

[0075] Figure 4 A general schematic diagram of a semiconductor device structure according to other embodiments of this application is shown.

[0076] like Figure 4 The method for forming the semiconductor device structure shown is the same as the one mentioned above. Figure 1a and Figure 1b The formation method already described is basically the same, and the process flow is the same as the one mentioned above. Figures 2a to 2i The process flow described above is basically the same, and the structural diagram is the same as above. Figure 3 The band structure diagrams shown are basically the same, so the similar parts will not be described again here.

[0077] As a distinction, compared to Figure 2i ,like Figure 4 The semiconductor device structure shown also includes multiple N-type doped SiC pillars 2022 and multiple P-type doped SiC pillars 2023. More specifically, after growing a SiC epitaxial layer 202 (also referred to as the first epitaxial layer) on the substrate 201, N-type ions are implanted into the SiC epitaxial layer 202 to form a second epitaxial layer. Then, P-type ions are implanted into the second epitaxial layer, penetrating the second epitaxial layer to reach the first epitaxial layer, thereby forming multiple P-type doped SiC pillars 2023, with multiple N-type doped SiC pillars 2022 located between the multiple P-type doped SiC pillars 2023. Then, a P-body region, an N+ region, and a P+ region can be formed on the second epitaxial layer, and multiple trench structures can be formed on the second epitaxial layer, with a P+ region formed at the bottom of the multiple trench structures. The process flow is basically the same as the process flow already described above, so the same parts will not be repeated here.

[0078] It is understood that the various method embodiments mentioned above in this application can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this application will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0079] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming a semiconductor device structure, characterized in that, The method includes: Different injection mask layers are sequentially formed on the first material epitaxial layer, and P-body regions, N+ regions and P+ regions are respectively formed on the first material epitaxial layer based on the different injection mask layers; Multiple trench structures are formed on the first material epitaxial layer, and a P+ region is formed at the bottom of the multiple trench structures; A gate oxide layer is formed on the surface of the plurality of trench structures; Remove the gate oxide layer from part of the surface of the trench structure to expose the first material epitaxial layer as the cathode material of the heterojunction diode structure; A second material layer is formed within the plurality of trench structures, wherein the second material layer formed on the exposed first material epitaxial layer serves as the anode material of the heterojunction diode structure, and the second material layer formed on the gate oxide layer serves as the gate electrode dielectric. The second material layer is patterned to form the anode electrode and the gate electrode, respectively.

2. The method according to claim 1, characterized in that, The method further includes: Forming an insulating dielectric layer; A source ohmic contact is formed on the surface of the first material epitaxial layer corresponding to the source region; The insulating dielectric layer formed on the anode electrode is etched to expose the anode electrode; A surface metal layer is formed, wherein the exposed anode electrode is connected to the source metal, the gate electrode is connected to the gate metal, and the source ohmic contact is connected to the source metal.

3. The method according to claim 1 or 2, characterized in that, The first material is silicon carbide, and the second material is polycrystalline silicon.

4. The method according to claim 1 or 2, characterized in that, The gate oxide layer on the surface of a portion of the trench structure is removed using a dry etching process, a wet etching process, or both.

5. The method according to claim 1 or 2, characterized in that, The second material layer is formed using a thin film deposition process, and the excess second material layer is removed from the surface of the plurality of trench structures using a back-etching process to achieve surface planarization.

6. The method according to claim 1 or 2, characterized in that, The method further includes: using an in-situ doping process or an ion diffusion process after the growth of the second material to dope the second material layer, so as to form the doped second material layer.

7. The method according to claim 1, characterized in that, The method further includes annealing the interface between the second material and the first material.

8. The method according to claim 2, characterized in that, The insulating dielectric layer corresponding to the source region is etched using a dry etching process, a wet etching process, or both, and the source ohmic contact is formed using a nickel secondary annealing process.

9. The method according to claim 2, characterized in that, The insulating dielectric layer formed on the anode electrode is etched using a dry etching process, a wet etching process, or both.

10. A semiconductor device structure, characterized in that, The semiconductor device structure is formed by the method according to any one of claims 1-9.

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