Back contact cells and methods of making the same, stacked cells, and photovoltaic modules

Abstract

Back contact cell, preparation method thereof, laminated cell and photovoltaic module belong to the technical field of photovoltaic technology. The back contact cell comprises a substrate, the substrate comprises a first region, a second region and a spacing region between the first region and the second region, a tunneling oxide layer and a doped polysilicon layer are arranged in the first region and the spacing region, the doped polysilicon layer is arranged on the surface of the tunneling oxide layer away from the substrate in the thickness direction, an amorphous silicon passivation layer and a doped amorphous silicon layer are arranged in the second region and the spacing region, and the doped amorphous silicon layer is arranged on the surface of the amorphous silicon passivation layer away from the substrate in the thickness direction. In the spacing region, the amorphous silicon passivation layer is located on the side of the doped polysilicon layer away from the substrate in the thickness direction. An insulating layer is arranged between the amorphous silicon passivation layer and the doped polysilicon layer, and the insulating layer comprises a first insulating part extending in the thickness direction and arranged at the junction position of the second region and the spacing region. The first insulating part can prevent the back contact cell from leaking in the horizontal direction and improve the overall electrical performance of the back contact cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to back contact cells and their preparation methods, tandem cells and photovoltaic modules. Background Technology

[0002] A back-contact battery is a type of battery in which the emitter, surface field, and metal electrodes are all located on the back (non-light-receiving side) of the battery. The front (light-receiving side) of the battery has no metal electrodes obstructing the light, allowing the battery to receive more incident light, reducing optical losses, and improving photoelectric conversion efficiency. Specifically, the back of a back-contact battery typically has N-regions, P-regions, and a spacer region between the N and P-regions. This spacer region contains an isolation zone. There is a risk of lateral leakage at the boundary between the spacer region and either the P or N region, which can lead to a lower parallel resistance and affect the battery's electrical performance. Summary of the Invention

[0003] This application provides a back-contact battery and its preparation method, a tandem battery, and a photovoltaic module to solve the problem of lateral leakage in back-contact batteries, which affects the electrical performance of the battery.

[0004] A first aspect of this application provides a back contact battery, the back contact battery comprising at least:

[0005] The substrate, the back side of which includes a first region, a second region, and a spacer region located between the first region and the second region;

[0006] A tunneling oxide layer and a doped polysilicon layer are disposed in the first region and the spacer region, and the doped polysilicon layer is disposed on the surface of the tunneling oxide layer away from the substrate along the thickness direction of the back contact cell;

[0007] An amorphous silicon passivation layer and a doped amorphous silicon layer are disposed in the second region. The doped amorphous silicon layer is disposed in a portion of the spacer region. The amorphous silicon passivation layer is disposed in a portion or all of the spacer region. The doped polycrystalline silicon layer has the opposite conductivity type to the doped amorphous silicon layer. The doped amorphous silicon layer is disposed on the surface of the amorphous silicon passivation layer away from the substrate along the thickness direction of the back contact cell.

[0008] In the spacer region, the amorphous silicon passivation layer is located on the side of the doped polycrystalline silicon layer away from the substrate along the thickness direction of the back contact cell. The spacer region is provided with an isolation trench, which penetrates the amorphous silicon passivation layer and the doped amorphous silicon layer, or the isolation trench penetrates the doped amorphous silicon layer.

[0009] An insulating layer is disposed between the amorphous silicon passivation layer and the doped polycrystalline silicon layer. The insulating layer includes at least a first insulating portion extending along the thickness direction of the back contact cell. The first insulating portion is disposed at the boundary between the second region and the spacer region.

[0010] In this design, the insulating layer can be used to isolate the doped polycrystalline silicon layer from the amorphous silicon passivation layer and the doped amorphous silicon layer. The insulating layer includes at least a first insulating portion extending along the thickness direction of the back contact cell. The first insulating portion is used to isolate the doped polycrystalline silicon layer from the amorphous silicon passivation layer and the doped polycrystalline silicon layer in the horizontal direction. The first insulating portion can prevent the risk of the doped amorphous silicon layer passing through the amorphous silicon passivation layer and conducting with the doped polycrystalline silicon layer due to the amorphous silicon passivation layer being too thin at the junction of the second region and the spacer region. That is, the first insulating portion can prevent the back contact cell from leaking current in the horizontal direction, increase the parallel resistance of the back contact cell, and increase the fill factor of the back contact cell. At the same time, the first insulating portion can reduce the risk of carrier recombination at the junction, increase the short-circuit current and open-circuit voltage of the back contact cell, thereby improving the overall electrical performance of the back contact cell.

[0011] In this scheme, the insulating layer is a silicon nitride layer, and the dimension L1 of the first insulating part in the horizontal direction satisfies: 3nm≤L1≤80nm.

[0012] In this solution, the insulating layer further includes a second insulating portion extending in a horizontal direction. The second insulating portion is disposed in the interval region, and the dimension S1 of the second insulating portion along the thickness direction of the back contact battery satisfies: 5nm≤S1≤100nm.

[0013] In this design, the projection of the second insulating portion onto the substrate can block the isolation trench. The horizontal dimension L2 of the spacing region satisfies: 20um≤L2≤200um, and the horizontal dimension L3 of the isolation trench satisfies: 10um≤L3≤180um.

[0014] In this scheme, in the spacer region, the dimension S2 of the amorphous silicon passivation layer along the thickness direction of the back contact cell satisfies: 5nm≤S2≤20nm, and the dimension S3 of the doped amorphous silicon layer along the thickness direction of the back contact cell satisfies: 10nm≤S3≤100nm.

[0015] In this solution, the back contact battery includes a transparent conductive layer, which is disposed on the surface of the doped amorphous silicon layer away from the substrate along the thickness direction of the back contact battery, and a first electrode and a second electrode are respectively disposed on the transparent conductive layer located in the first region and the second region.

[0016] Along the thickness direction of the back contact battery, a passivation layer and an antireflection layer are sequentially disposed on the front side of the substrate.

[0017] A second aspect of this application provides a method for preparing a back contact battery, the method comprising:

[0018] Provide substrate;

[0019] A tunneling oxide layer and a doped polycrystalline silicon layer are sequentially deposited on both the front and back sides of the substrate along the thickness direction;

[0020] Wet etching is used to remove the phosphosilicate glass layer on the front and back sides of the substrate;

[0021] The back side of the substrate includes a first region, a second region, and a spacer region between the first region and the second region. The second region is laser-grooved to remove the tunneling oxide layer and the doped polysilicon layer, thereby exposing the substrate in the second region.

[0022] An insulating layer is deposited on the back side of the substrate.

[0023] In this scheme, during the deposition of the insulating layer, silane, ammonia, nitrogen, and hydrogen are simultaneously introduced for deposition. The amount of silane introduced, R1, satisfies: 500 sccm ≤ R1 ≤ 2000 sccm; the amount of ammonia introduced, R2, satisfies: 500 sccm ≤ R2 ≤ 3000 sccm; the amount of nitrogen introduced, R3, satisfies: 5000 sccm ≤ R3 ≤ 15000 sccm; and the amount of hydrogen introduced, R4, satisfies: 1000 sccm ≤ R4 ≤ 10000 sccm.

[0024] In this scheme, during the step of depositing the insulating layer, the deposition temperature T1 satisfies: 100℃≤T1≤300℃, and the deposition pressure P1 satisfies: 1Torr≤P1≤10Torr.

[0025] In this scheme, during the step of depositing the insulating layer, the power W1 of the radio frequency power supply satisfies: 500W≤W1≤50000W, and the electrode spacing K of the reaction chamber satisfies: 10mm≤K≤50mm.

[0026] In this scheme, after the insulating layer is deposited, the method for preparing the back contact battery further includes:

[0027] The insulating layer is partially removed by laser in the second region to expose the substrate in the second region, and wet etching is performed on the exposed substrate in the second region and the front side of the substrate.

[0028] A passivation layer and an antireflection layer are sequentially deposited on the front side of the substrate.

[0029] In this scheme, after completing the wet etching of the substrate exposed in the second region and the front side of the substrate, the fabrication method of the back contact cell further includes:

[0030] An amorphous silicon passivation layer and a doped amorphous silicon layer are sequentially deposited on the back side of the substrate using plate-type plasma-enhanced chemical vapor deposition.

[0031] In the step of depositing the doped amorphous silicon layer, silane, hydrogen and diborane are simultaneously introduced for deposition. The deposition temperature T2 satisfies: 150℃≤T2≤250℃, and the deposition pressure P2 satisfies: 1Torr≤P2≤10Torr.

[0032] In this scheme, after completing the deposition of the doped amorphous silicon layer, the fabrication method of the back contact cell further includes:

[0033] Laser removal of the amorphous silicon passivation layer, the doped amorphous silicon layer, and the insulating layer located in the first region;

[0034] A transparent conductive layer is deposited on the back side of the substrate;

[0035] Laser grooving is performed at a portion of the spacer region to remove at least the transparent conductive layer and the doped amorphous silicon layer, thereby forming an isolation trench;

[0036] A first electrode is prepared in the first region, and a second electrode is prepared in the second region.

[0037] A third aspect of this application provides a stacked battery, the stacked battery comprising a perovskite battery and the back contact battery described above, or the stacked battery comprising a perovskite battery and the back contact battery prepared by the back contact battery preparation method described above.

[0038] A fourth aspect of this application provides a photovoltaic module, the photovoltaic module comprising the back contact cell described above, or the photovoltaic module comprising the back contact cell prepared by the back contact cell preparation method described above, or the photovoltaic module comprising the stacked cell described above.

[0039] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the back contact battery provided in this application in a specific embodiment;

[0041] Figure 2 This is a schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application, performed in step one.

[0042] Figure 3This is a schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application, which is performed in step four.

[0043] Figure 4 This is a schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application, performed in step five.

[0044] Figure 5 A schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application by performing step six;

[0045] Figure 6 A schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application by performing step seven;

[0046] Figure 7 A schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application by performing step eight;

[0047] Figure 8 A schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application by performing step nine;

[0048] Figure 9 A schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application by performing step ten;

[0049] Figure 10 A schematic diagram of the structure formed in a specific embodiment of the method for preparing the back contact battery provided in this application by performing step eleven;

[0050] Figure 11 A schematic diagram of the structure formed in another specific embodiment of the method for preparing the back contact battery provided in this application by performing step eleven;

[0051] Figure 12 A flowchart illustrating the method for preparing the back contact battery provided in this application;

[0052] Figure 13 This is a schematic diagram of the structure of the stacked battery provided in this application;

[0053] Figure 14 A schematic diagram of a connection method for the back contact battery and perovskite battery provided in this application;

[0054] Figure 15 A schematic diagram illustrating another connection method for the back contact battery and perovskite battery provided in this application;

[0055] Figure 16This is a schematic diagram illustrating another connection method for the back contact battery and perovskite battery provided in this application.

[0056] Figure 17 This is a schematic diagram of the structure of a photovoltaic module provided in one embodiment of this application;

[0057] Figure 18 This is a schematic diagram of the structure of the photovoltaic module provided in one embodiment of this application.

[0058] Explanation of reference numerals in the attached figures:

[0059] 1- Back contact battery;

[0060] 101 - First electrode;

[0061] 102 - Second electrode;

[0062] 11-Substrate;

[0063] 111-First District;

[0064] 112 - Second District;

[0065] 113-Interval Zone;

[0066] 12-Tunneling oxide layer;

[0067] 13-Doped polycrystalline silicon layer;

[0068] 14-Amorphous silicon passivation layer;

[0069] 15-Doped amorphous silicon layer;

[0070] 16 - Insulation layer;

[0071] 161 - Second insulation section;

[0072] 162 - First Insulation Section;

[0073] 17-Transparent conductive layer;

[0074] 18-Antireflection layer;

[0075] 19-Passivation layer;

[0076] 2-Stacked battery;

[0077] 21-Perovskite solar cells;

[0078] 3-Welding strip;

[0079] 4-Front plate;

[0080] 5- Front encapsulation layer;

[0081] 6- Backside encapsulation layer;

[0082] 7-Back panel.

[0083] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0084] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0085] In one specific embodiment, the present application will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0086] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0087] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0088] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0089] It should be noted that the directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should be understood that when it is mentioned that an element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0090] The back contact battery 1 includes a substrate 11, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer have opposite conductivity types. A first insulating portion 162 extending along the thickness direction Y of the back contact battery 1 is provided between the first semiconductor layer and the second semiconductor layer. The first insulating portion 162 is used to isolate the first semiconductor layer and the second semiconductor layer along the horizontal direction X. The first insulating portion 162 can prevent the risk of the first semiconductor layer and the second semiconductor layer from conducting, that is, the first insulating portion 162 can prevent the back contact battery 1 from leaking current along the horizontal direction X, improve the parallel resistance of the back contact battery 1, improve the fill factor of the back contact battery 1, and improve the electrical performance of the back contact battery 1.

[0091] Specifically, this application provides a back contact battery 1, such as Figure 1 As shown, the back contact cell 1 can be a heterojunction back contact (HBC) cell. The back contact cell 1 includes at least a substrate 11, a tunneling oxide layer 12, a doped polycrystalline silicon layer 13, an amorphous silicon passivation layer 14, a doped amorphous silicon layer 15, and an insulating layer 16. The tunneling oxide layer 12 and the doped polycrystalline silicon layer 13 can be the first semiconductor layer described above, and the amorphous silicon passivation layer 14 and the doped amorphous silicon layer 15 can be the second semiconductor layer described above.

[0092] The back side of the substrate 11 includes a first region 111, a second region 112, and a spacer region 113 located between the first region 111 and the second region 112.

[0093] The tunneling oxide layer 12 and the doped polysilicon layer 13 are disposed in the first region 111 and the spacer region 113, and the doped polysilicon layer 13 is disposed on the surface of the tunneling oxide layer 12 away from the substrate 11 along the thickness direction Y of the back contact cell 1.

[0094] An amorphous silicon passivation layer 14 and a doped amorphous silicon layer 15 are disposed in the second region 112. The doped amorphous silicon layer 15 is disposed in a portion of the spacer region 113. The amorphous silicon passivation layer 14 is disposed in a portion of the spacer region 113 or in all of the spacer region 113. The doped polycrystalline silicon layer 13 has the opposite conductivity type to the doped amorphous silicon layer 15. The doped amorphous silicon layer 15 is disposed on the surface of the amorphous silicon passivation layer 14 away from the substrate 11 along the thickness direction Y of the back contact cell 1.

[0095] In the spacer region 113, the amorphous silicon passivation layer 14 is located on the side of the doped polycrystalline silicon layer 13 away from the substrate 11 along the thickness direction Y of the back contact cell 1. The spacer region 113 is provided with an isolation trench that penetrates the amorphous silicon passivation layer 14 and the doped amorphous silicon layer 15, or the isolation trench penetrates the doped amorphous silicon layer 15.

[0096] An insulating layer 16 is disposed between an amorphous silicon passivation layer 14 and a doped polycrystalline silicon layer 13. The insulating layer 16 includes at least a first insulating portion 162 extending along the thickness direction Y of the back contact cell 1. The first insulating portion 162 is disposed at the junction of the second region 112 and the spacer region 113.

[0097] In this embodiment, the insulating layer 16 can be used to isolate the doped polycrystalline silicon layer 13 from the amorphous silicon passivation layer 14 and the doped amorphous silicon layer 15. The insulating layer 16 includes at least a first insulating portion 162 extending along the thickness direction Y of the back contact cell 1. The first insulating portion 162 is used to isolate the doped polycrystalline silicon layer 13 from the amorphous silicon passivation layer 14 and the doped polycrystalline silicon layer 15 along the horizontal direction X. The first insulating portion 162 can prevent the amorphous silicon passivation layer located at the junction of the second region 112 and the spacer region 113 from being affected by the passivation. If the passivation layer 14 is too thin, there is a risk that the doped amorphous silicon layer 15 will pass through the amorphous silicon passivation layer 14 and conduct with the doped polycrystalline silicon layer 13. That is, the first insulating part 162 can prevent leakage of the back contact battery 1 in the horizontal direction X, increase the parallel resistance of the back contact battery 1, increase the fill factor of the back contact battery 1, and at the same time, the first insulating part 162 can reduce the risk of carrier recombination at the above-mentioned interface, increase the short-circuit current and open-circuit voltage of the back contact battery 1, thereby improving the overall electrical performance of the back contact battery 1.

[0098] The insulating layer 16 can be any one of silicon nitride film, silicon oxide film, and film layer.

[0099] Furthermore, in this scheme, the back contact cell 1 is an HBC cell. Compared with the traditional tunnel oxide back contact cell 1 (TBC) with a tunnel oxide layer 12, the HBC cell uses an amorphous silicon passivation layer 14 as the passivation structure, while the TBC uses a tunnel oxide layer 12 and a doped polycrystalline silicon layer 13 as the passivation structure. Since the amorphous silicon passivation layer 14 has a good passivation effect, the passivation effect of the back contact cell 1 of the HBC cell in this scheme is better than that of the TBC cell, which is conducive to improving the open circuit voltage and thus improving the cell efficiency.

[0100] Meanwhile, in one possible implementation, a doped amorphous silicon layer 15 is directly disposed on the surface of the amorphous silicon passivation layer 14 away from the substrate 11 along the thickness direction Y of the back contact cell 1. The doped amorphous silicon layer 15 can be a doped nanocrystalline silicon layer (e.g., p-nc-Si:H) or a doped microcrystalline silicon layer (e.g., p-μc-Si:H). The doped nanocrystalline silicon layer or the doped microcrystalline silicon layer has better conductivity than the doped amorphous hydride layer (e.g., pa-Si:H), avoiding the need for subsequent laser irradiation crystallization of the doped amorphous silicon layer 15, thereby avoiding the need for subsequent laser irradiation of the second region 112, and thus avoiding the risk that the passivation effect of the second region 112 will be affected by laser irradiation, thereby further improving the passivation effect of the back contact cell 1.

[0101] In summary, by directly depositing a doped amorphous silicon layer 15 on the surface of the amorphous silicon passivation layer 14 away from the substrate 11 along the thickness direction Y of the back contact battery 1, and simultaneously placing an insulating layer 16 between the amorphous silicon passivation layer 14 and the doped polycrystalline silicon layer 13, it is beneficial to prevent internal leakage of the back contact battery 1, improve the parallel resistance of the back contact battery 1, and improve the passivation effect of the back contact battery 1, thereby jointly promoting the excellent electrical performance of the back contact battery 1.

[0102] In one possible implementation, the substrate 11 can be selected from any one of the following materials: monocrystalline silicon, polycrystalline silicon, amorphous silicon, cadmium telluride, copper indium gallium selenide, and perovskite.

[0103] In one possible implementation, such as Figure 1 As shown, the substrate 11 can be an N-type silicon substrate (abbreviated as N-type c-Si). The doping element of the N-type silicon substrate can be any one or more of phosphorus, arsenic, antimony, and bismuth. The doped amorphous silicon layer 15 is a P-type doped amorphous silicon layer (abbreviated as p-nc-Si:H or p-μc-Si:H), and the doped polycrystalline silicon layer 13 is an N-type doped polycrystalline silicon layer (abbreviated as n-poly-Si). That is, in this embodiment, the doped region of the first region 111 is the tunneling oxide layer 12 and the phosphorus doped polycrystalline silicon layer, and the doped region of the second region 112 is the amorphous silicon passivation layer 14 and the boron doped amorphous silicon layer.

[0104] In another possible implementation, the substrate 11 can be a P-type silicon substrate (abbreviated as P-type c-Si). The doping element of the P-type silicon substrate can be any one or more of boron, aluminum, gallium or indium. The doped amorphous silicon layer 15 is an N-type doped amorphous silicon layer (abbreviated as n-nc-Si:H or n-μc-Si:H), and the doped polycrystalline silicon layer 13 is a P-type doped polycrystalline silicon layer (abbreviated as p-poly-Si). That is, in this embodiment, the doped region of the first region 111 is the tunneling oxide layer 12 and the boron doped polycrystalline silicon layer, and the doped region of the second region 112 is the amorphous silicon passivation layer 14 and the phosphorus doped amorphous silicon layer.

[0105] Furthermore, in one embodiment, such as Figure 10 As shown, the isolation trench penetrates the amorphous silicon passivation layer 14 and the doped amorphous silicon layer 15, so that the amorphous silicon passivation layer 14 and the doped amorphous silicon layer 15 are disposed in a portion of the spacing region 113, thereby improving the short-circuit protection effect of the back contact battery 1.

[0106] In another embodiment, such as Figure 11 As shown, the isolation trench penetrates the doped amorphous silicon layer 15 so that the amorphous silicon passivation layer 14 is disposed in the entire area of ​​the spacer region 113, and the doped amorphous silicon layer 15 is disposed in a portion of the spacer region 113, thereby reducing the risk of short circuit of the back contact cell 1 through the doped amorphous silicon layer 15.

[0107] It should be noted that in this application, the horizontal direction X can be the length direction of the back contact battery 1 or the width direction of the back contact battery 1.

[0108] The following detailed description uses examples of N-type silicon substrates, P-type doped amorphous silicon layers, and N-type doped polycrystalline silicon layers.

[0109] In one possible implementation, such as Figure 1 and Figure 10 As shown, the insulating layer 16 is a silicon nitride layer, and the dimension L1 of the first insulating part 162 along the horizontal direction X satisfies: 3nm≤L1≤80nm.

[0110] In this embodiment, L1 satisfies: 3nm ≤ L1 ≤ 80nm, ensuring that the size of the first insulating portion 162 along the horizontal direction X is moderate. This prevents the size of the first insulating portion 162 from being too small, improving its insulation effect and enhancing the leakage protection performance of the back contact battery 1, thereby increasing the fill factor of the back contact battery 1. Simultaneously, the size of the first insulating portion 162 along the horizontal direction X is not too large, reducing production load and costs.

[0111] Optionally, the dimension L1 of the first insulating portion 162 along the horizontal direction X can be 3nm, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, or 80nm, or other values ​​within the above range. This embodiment does not limit this.

[0112] In one possible implementation, such as Figure 1 and Figure 10 As shown, the insulating layer 16 also includes a second insulating portion 161 extending in the horizontal direction X. The second insulating portion 161 is disposed in the spacer region 113. The dimension S1 of the second insulating portion 161 in the thickness direction Y of the back contact battery 1 satisfies: 5nm≤S1≤100nm.

[0113] In this embodiment, the second insulating portion 161 can prevent the risk that the doped amorphous silicon layer 15 will pass through the amorphous silicon passivation layer 14 and conduct with the doped polycrystalline silicon layer 13 due to the amorphous silicon passivation layer 14 being too thin in the spacer region 113. That is, the second insulating portion 161 can prevent leakage of the back contact battery 1 along the thickness direction Y, increase the parallel resistance of the back contact battery 1, increase the fill factor of the back contact battery 1, and thus improve the overall electrical performance of the back contact battery 1.

[0114] Furthermore, the dimension S1 of the second insulating portion 161 along the thickness direction Y of the back contact battery 1 satisfies: 5nm ≤ S1 ≤ 100nm, making the dimension of the second insulating portion 161 along the thickness direction Y moderate. This ensures the dimension of the second insulating portion 161 along the thickness direction Y is not too small, improving the insulation effect of the second insulating portion 161, enhancing the leakage protection performance of the back contact battery 1, and thus increasing the fill factor of the back contact battery 1. Simultaneously, the dimension of the second insulating portion 161 along the horizontal direction X is not too large, reducing production costs.

[0115] Optionally, the dimension S1 of the second insulating portion 161 along the thickness direction Y of the back contact battery 1 can be 5nm, 6nm, 10nm, 12nm, 15nm, 16nm, 20nm, 22nm, 25nm, 26nm, 30nm, 32nm, 35nm, 36nm, 40nm, 42nm, 45nm, 46nm, 50nm, 52nm, 55nm, 56nm, 60nm, 62nm, 65nm, 66nm, 70nm, 72nm, 75nm, 76nm, 80nm, 85nm, 90nm, 95nm, or 100nm, or other values ​​within the above range. This embodiment does not limit this value.

[0116] In one possible implementation, such as Figure 1 and Figure 10 As shown, the projection of the second insulating portion 161 onto the substrate 11 can block the isolation trench. The dimension L2 of the spacer region 113 along the horizontal direction X satisfies: 20um≤L2≤200um, and the dimension L3 of the isolation trench along the horizontal direction X satisfies: 10um≤L3≤180um.

[0117] In this embodiment, the projection of the second insulating portion 161 onto the substrate 11 can block the isolation trench, meaning the isolation trench does not penetrate the second insulating portion 161 along the thickness direction Y of the back contact cell 1. The second insulating portion 161 can form a high-resistance barrier between the first region 111 and the second region 112, greatly improving the parallel resistance and increasing the effective output efficiency of the back contact cell 1. Furthermore, the second insulating portion 161 located at the isolation trench can protect the substrate 11, preventing damage to the substrate 11 from subsequent laser processes. In addition, when the insulating film is silicon nitride, the second insulating film can act as an anti-reflection film, which helps reduce light loss and thus improves the light absorption efficiency of the back contact cell 1.

[0118] The dimension L2 of the spacer region 113 along the horizontal direction X satisfies: 20um≤L2≤200um, so that the dimension of the spacer region 113 along the horizontal direction X is moderate. The dimension L2 of the spacer region 113 along the horizontal direction X is not too large, so that the area of ​​the first region 111 and the second region 112 is moderate, increasing the light absorption area and improving the efficiency of the back contact battery 1. At the same time, the dimension L2 of the spacer region 113 along the horizontal direction X is not too small, reducing the risk of short circuit and improving the parallel resistance. It also reduces the difficulty of subsequent production processes, improves production efficiency and production qualification rate.

[0119] Optionally, the dimension L2 of the interval region 113 along the horizontal direction X can be 20um, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm, 190nm, 195nm, or 200um, or other values ​​within the above range. This embodiment does not limit this.

[0120] The dimension L3 of the isolation trench along the horizontal direction X satisfies: 10um≤L3≤180um, making the dimension of the isolation trench along the horizontal direction X moderate. The dimension L3 of the isolation trench along the horizontal direction X will not be too large, so that the ineffective area of ​​the battery will not be too large, reducing the carrier diffusion path, reducing the loss of short-circuit current, and improving battery efficiency. At the same time, the dimension L3 of the isolation trench along the horizontal direction X will not be too small, effectively preventing leakage and short circuit, and improving parallel resistance.

[0121] Optionally, the dimension L3 of the isolation trench along the horizontal direction X can be 10um, 15um, 16um, 20um, 22um, 25nm, 28um, 30nm, 32um, 35nm, 38um, 40nm, 42um, 45nm, 48um, 50nm, 52um, 55nm, 58um, 60nm, 62um, 65nm, 68um, 70nm, 72um, 75nm, 78um, 80nm, 82um, 85nm, 88um, 90nm, 92um, 95nm, 98um, 100nm, 102nm, 1 The wavelengths are 0.5nm, 108nm, 110nm, 112nm, 115nm, 118nm, 120nm, 122nm, 125nm, 128nm, 130nm, 132nm, 135nm, 138nm, 140nm, 142nm, 145nm, 148nm, 150nm, 152nm, 155nm, 158nm, 160nm, 162nm, 165nm, 168nm, 170nm, 172nm, 175nm, 178nm, or 180um, or other values ​​within the above range. This embodiment does not limit these values.

[0122] In summary, the dimension L2 of the spacer region 113 along the horizontal direction X satisfies: 20um≤L2≤200um, and the dimension L3 of the isolation groove along the horizontal direction X satisfies: 10um≤L3≤180um. This is beneficial for preventing leakage and short circuit of the back contact battery 1, improving the parallel resistance, and jointly improving the photoelectric conversion efficiency of the back contact battery 1.

[0123] In one possible implementation, such as Figure 1 and Figure 10 As shown, in the spacer region 113, the dimension S2 of the amorphous silicon passivation layer 14 along the thickness direction Y of the back contact cell 1 satisfies: 5nm≤S2≤20nm, and the dimension S3 of the doped amorphous silicon layer 15 along the thickness direction Y of the back contact cell 1 satisfies: 10nm≤S3≤100nm.

[0124] In addition, such as Figure 1 and Figure 10 As shown, at the texturing position in the second region 112, the thickness S4 of the amorphous silicon passivation layer 14 satisfies: 3nm≤S4≤15nm, and the thickness S5 of the doped amorphous silicon layer 15 satisfies: 5nm≤S5≤80nm.

[0125] In this embodiment, the dimension S2 of the amorphous silicon passivation layer 14 along the thickness direction Y of the back contact battery 1 satisfies: 5nm≤S2≤20nm, and S4 satisfies: 3nm≤S4≤15nm, so that the thickness of the amorphous silicon passivation layer 14 is moderate: the thickness of the amorphous silicon passivation layer 14 is not too small, which improves the passivation capability of the back contact battery 1, and the amorphous silicon passivation layer 14 and the insulating layer 16 can jointly isolate and insulate the doped amorphous silicon layer 15 and the doped polycrystalline silicon layer 13, further improving the leakage and short-circuit protection performance of the back contact battery. At the same time, the thickness of the amorphous silicon passivation layer 14 is not too large, which is beneficial to reduce parasitic absorption, reduce the carrier recombination probability, reduce the series resistance of the battery, improve the fill factor, and improve the efficiency of the back contact battery 1.

[0126] Optionally, the dimension S2 of the amorphous silicon passivation layer 14 along the thickness direction Y of the back contact cell 1 can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm, or other values ​​within the above range. This embodiment does not limit this.

[0127] Optionally, the thickness S4 of the amorphous silicon passivation layer 14 can be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm or 15nm, or other values ​​within the above range. This embodiment does not limit this.

[0128] In this embodiment, the dimension S3 of the doped amorphous silicon layer 15 along the thickness direction Y of the back contact cell 1 satisfies: 10nm≤S3≤100nm, and S5 satisfies: 5nm≤S5≤80nm, so that the thickness of the doped amorphous silicon layer 15 is moderate: the thickness of the doped amorphous silicon layer 15 is not too small, which improves carrier recombination and ohmic contact, and reduces the difficulty of the fabrication process. At the same time, the thickness of the doped amorphous silicon layer 15 is not too large, which is beneficial to reducing the series resistance of the cell and reducing parasitic absorption, thereby improving the efficiency of the back contact cell 1.

[0129] Optionally, the dimension S3 of the doped amorphous silicon layer 15 along the thickness direction Y of the back contact cell 1 can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm or 100nm, or other values ​​within the above range. This embodiment does not limit this.

[0130] Optionally, the thickness S5 of the doped amorphous silicon layer 15 can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm or 80nm, or other values ​​within the above range. This embodiment does not limit this.

[0131] In summary, the dimensions S2 of the amorphous silicon passivation layer 14 along the thickness direction Y of the back contact cell 1 satisfy: 5nm≤S2≤20nm, and S4 satisfies: 3nm≤S4≤15nm. Meanwhile, the dimensions S3 of the doped amorphous silicon layer 15 along the thickness direction Y of the back contact cell 1 satisfy: 10nm≤S3≤100nm, and S5 satisfies: 5nm≤S5≤80nm. Together, these dimensions can reduce the series resistance of the cell, improve the fill factor, and enhance the photoelectric conversion efficiency of the back contact cell 1.

[0132] In addition, such as Figure 1 and Figure 10 As shown, at the texturing position in the second region 112, the thickness S4 of the amorphous silicon layer satisfies: 3nm≤S4≤15nm, and the thickness S5 of the doped amorphous silicon layer 15 satisfies: 5nm≤S5≤80nm.

[0133] In one possible implementation, such as Figure 1 and Figure 10 As shown, the back contact battery 1 includes a transparent conductive layer 17. The transparent conductive layer 17 is disposed on the surface of the doped amorphous silicon layer 15 away from the substrate 11 along the thickness direction Y of the back contact battery 1. A first electrode 101 and a second electrode 102 are respectively disposed on the transparent conductive layer 17 located in the first region 111 and the second region 112. The transparent conductive layer 17 is used to transmit current to the first electrode 101 and the second electrode 102. The first electrode 101 and the second electrode 102 are used to output or input current to the outside.

[0134] Along the thickness direction Y of the back contact cell 1, a passivation layer 19 and an antireflection layer 18 are sequentially disposed on the front side of the substrate 11. The passivation layer 19 is used to reduce the nonradiative recombination of charge carriers on the surface, thereby improving the open-circuit voltage and overall efficiency of the back contact cell 1. The antireflection layer 18 can reduce light reflection, improve the light absorption of the substrate 11, and increase the short-circuit current.

[0135] The passivation layer 19 can be an aluminum oxide thin film, and the antireflection layer 18 can be a silicon nitride thin film.

[0136] The back contact battery 1 in any of the above embodiments can be prepared by the following method for preparing back contact battery 1.

[0137] This application also provides a method for preparing a back contact battery 1, such as... Figures 2-9 and Figure 12 As shown, the method for preparing the back contact battery 1 includes:

[0138] Step 1: As Figure 2 As shown, a substrate 11 is provided: the substrate 11 is cleaned and polished;

[0139] Step 2: A tunneling oxide layer 12 and a doped polysilicon layer 13 are sequentially deposited on both the front and back sides of the substrate 11 along the thickness direction Y.

[0140] Step 3: Wet etching is used to remove the phosphosilicate glass (PSG) layer on the front and back sides of the substrate 11 to improve ohmic contact and enhance electrical performance, laying a good foundation for subsequent processes.

[0141] Step Four: As Figure 1 and Figure 3 As shown, the back side of the substrate 11 includes a first region 111, a second region 112 and a spacer region 113 located between the first region 111 and the second region 112. The second region 112 is laser-grooved to remove the tunneling oxide layer 12 and the doped polysilicon layer 13, so that the substrate 11 in the second region 112 is exposed to form a P region.

[0142] Step 5: As Figure 4 As shown, an insulating layer 16 is deposited on the back side of the substrate 11.

[0143] In this embodiment, step five enables the thin film layer subsequently deposited on the surface of the insulating layer 16 on the side opposite to the substrate 11 along the thickness direction Y of the back contact cell 1 to be insulated from the doped polysilicon layer 13, reducing the risk of the thin film layer and the doped polysilicon layer 13 being interconnected.

[0144] Furthermore, since the above method performs step four before step five, that is, after laser grooving to form the P region, the insulating layer 16 is deposited, the insulating layer 16 can uniformly cover the sidewall of the grooved area to form the first insulating part 162. This allows the insulating layer 16 to insulate and isolate the thin film layer and the doped polysilicon layer 13 along the horizontal X direction, preventing leakage of the back contact battery 1 along the horizontal X direction, increasing the parallel resistance of the back contact battery 1, increasing the fill factor of the back contact battery 1, and thus improving the overall electrical performance of the back contact battery 1.

[0145] In addition, since the above method performs step four before step five, step five can deposit the first insulating part 162 and the second insulating part 161 in one step, which simplifies the preparation steps, reduces the production load, and improves production efficiency.

[0146] In one possible implementation, such as Figure 4As shown, in the step of depositing the insulating layer 16, silane, ammonia, nitrogen and hydrogen are simultaneously introduced for deposition. The amount of silane introduced, R1, satisfies: 500 sccm ≤ R1 ≤ 2000 sccm; the amount of ammonia introduced, R2, satisfies: 500 sccm ≤ R2 ≤ 3000 sccm; the amount of nitrogen introduced, R3, satisfies: 5000 sccm ≤ R3 ≤ 15000 sccm; and the amount of hydrogen introduced, R4, satisfies: 1000 sccm ≤ R4 ≤ 10000 sccm.

[0147] In this embodiment, the prepared insulating layer 16 is a silicon nitride thin film. The silicon source is silane, the nitrogen source is nitrogen and ammonia, and hydrogen is used as an auxiliary gas to regulate the hydrogen content in the deposited insulating layer 16 and assist in ignition. That is, hydrogen can assist in the excitation of the reactive gas by external energy, causing it to ionize and promoting the uniform deposition of the insulating layer 16.

[0148] The silane injection rate, R1, primarily affects the deposition rate of the prepared insulating layer 16. The deposition rate refers to the thickness of the film deposited on the substrate surface per unit time during the thin film deposition process. The silane injection rate R1 should satisfy the following condition: 500 sccm ≤ R1 ≤ 2000 sccm. This ensures that the silane injection rate R1 is moderate, preventing it from being too high and reducing the risk of excessive deposition rate. This improves the density and acid / alkali resistance of the prepared insulating layer 16 and reduces the risk of crystal defects such as vacancies and dislocations within the insulating layer 16. Simultaneously, a silane injection rate R1 should not be too low, as this will not increase the preparation time of the insulating layer 16 and improve production efficiency.

[0149] Optionally, the silane injection rate R1 can be 500 sccm, 550 sccm, 600 sccm, 650 sccm, 700 sccm, 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm, 1000 sccm, 1050 sccm, 1100 sccm, or 2000 sccm, or other values ​​within the above range. This embodiment does not limit this.

[0150] The amount of ammonia gas introduced, R2, and the amount of nitrogen gas introduced, R3, mainly affect the optical properties of the insulating film. The amount of ammonia gas introduced, R2, satisfies the following condition: 500 sccm ≤ R2 ≤ 3000 sccm, and the amount of nitrogen gas introduced, R3, satisfies the following condition: 5000 sccm ≤ R3 ≤ 15000 sccm, so that the amount of nitrogen source introduced is moderate. The amount of ammonia gas introduced, R2, and the amount of nitrogen gas introduced, R3, will not be too large, thus improving the extinction coefficient, increasing the refractive index, improving the passivation effect, and reducing the difficulty of matching the insulating layer 16 with subsequent processes. At the same time, the amount of ammonia gas introduced, R2, and the amount of nitrogen gas introduced, R3, will not be too small, thus not increasing the preparation time of the insulating layer 16, improving production efficiency, and reducing the difficulty of matching the insulating layer 16 with subsequent processes.

[0151] Among them, the extinction coefficient is a key optical parameter describing a material's ability to absorb light.

[0152] Optionally, the ammonia flow rate R2 can be 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, 1000 sccm, 1100 sccm, 1200 sccm, 1300 sccm, 1400 sccm, 1500 sccm, 1600 sccm, 1700 sccm, 1800 sccm, 1900 sccm, 2000 sccm, 2100 sccm, 2200 sccm, 2300 sccm, 2400 sccm, 2500 sccm, 2600 sccm, 2700 sccm, 2800 sccm, 2900 sccm, or 3000 sccm, or other values ​​within the above range. This embodiment does not limit this.

[0153] Optionally, the nitrogen flow rate R3 can be 500 sccm, 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 10500 sccm, 11000 sccm, 11500 sccm, 12000 sccm, 12500 sccm, 13000 sccm, 13500 sccm, 14000 sccm, 14500 sccm, or 15000 sccm, or other values ​​within the above range. This embodiment does not limit this.

[0154] Hydrogen is used as an auxiliary gas to regulate the hydrogen content of the thin film and assist in ignition. The hydrogen flow rate R4 satisfies: 1000sccm≤R4≤10000sccm. The hydrogen flow rate is matched with the silane flow rate R1, the ammonia flow rate R2 and the nitrogen flow rate R3 to promote the uniform deposition of the insulating layer 16.

[0155] Optionally, the hydrogen flow rate R4 can be 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, 3000 sccm, 3500 sccm, 4000 sccm, 4500 sccm, or 10000 sccm, or other values ​​within the above range. This embodiment does not limit this.

[0156] In summary, the silane inlet flow rate R1 satisfies: 500 sccm ≤ R1 ≤ 2000 sccm; the ammonia inlet flow rate R2 satisfies: 500 sccm ≤ R2 ≤ 3000 sccm; the nitrogen inlet flow rate R3 satisfies: 5000 sccm ≤ R3 ≤ 15000 sccm; and the hydrogen inlet flow rate R4 satisfies: 1000 sccm ≤ R4 ≤ 10000 sccm. This ensures a suitable ratio of silane, ammonia, nitrogen, and hydrogen, which is beneficial for increasing the deposition rate of the insulating layer 16, improving the refractive index, reducing internal defects in the prepared insulating layer 16, thereby improving the quality of the insulating layer 16, enhancing the passivation effect, and improving the insulation effect of the insulating layer 16.

[0157] In one possible implementation, such as Figure 4 As shown, in the step of depositing insulating layer 16, the deposition temperature T1 satisfies: 100℃≤T1≤300℃, and the deposition pressure P1 satisfies: 1Torr≤P1≤10Torr, so that the temperature and pressure of depositing insulating layer 16 in step five are moderate.

[0158] The deposition temperature T1 satisfies the condition that 100℃≤T1≤300℃, which is conducive to the formation of a dense, uniform insulating layer 16 without internal defects, thus improving the passivation effect. At the same time, it reduces the risk of damage to the tunneling oxide layer 12 and the doped polycrystalline silicon layer 13 formed in step two.

[0159] Optionally, the deposition temperature T1 of the insulating layer 16 can be 100℃, 120℃, 140℃, 150℃, 160℃, 180℃, 200℃, 220℃, 240℃, 250℃, 260℃, 280℃ or 300℃, or other values ​​within the above range. This embodiment does not limit this.

[0160] The deposition pressure P1 satisfies: 1 Torr ≤ P1 ≤ 10 Torr, which is beneficial to improving the deposition rate of the insulating layer 16, improving the uniformity of the plasma distribution inside the insulating layer 16, forming a dense and smooth silicon nitride film, and reducing the difficulty of depositing the amorphous silicon passivation layer 14 on the insulating layer 16.

[0161] Optionally, the deposition pressure P1 of the insulating layer 16 can be 1 Torr, 2 Torr, 3 Torr, 4 Torr, 5 Torr, 6 Torr, 7 Torr, 8 Torr, 9 Torr or 10 Torr, or other values ​​within the above range. This embodiment does not limit this.

[0162] Therefore, the deposition temperature T1 satisfies: 100℃≤T1≤300℃, and the deposition pressure P1 satisfies: 1Torr≤P1≤10Torr, which is beneficial to improving the deposition rate and deposition quality of the insulating layer 16.

[0163] In one possible implementation, such as Figure 4 As shown, in the step of depositing insulating layer 16, the power W1 of the radio frequency power supply satisfies: 500W≤W1≤50000W, and the electrode spacing K of the reaction chamber satisfies: 10mm≤K≤50mm.

[0164] The radio frequency (RF) power supply is used to ionize the reactive gas. The power W1 of the RF power supply meets the following condition: 500W≤W1≤50000W, so that the power W1 of the RF power supply is moderate. The power W1 of the RF power supply is not too small, which improves the deposition rate and increases production efficiency. At the same time, the power W1 of the RF power supply is not too large, which reduces the stress generated in the insulating layer 16, reduces the risk of film warping or cracking, ensures the quality of the insulating layer 16, and can also accurately control the thickness of the deposited insulating layer 16.

[0165] Optionally, the power W1 of the RF power supply can be 500W, 1000W, 5000W, 10000W, 15000W, 20000W, 25000W, 30000W, 35000W, 40000W, 45000W or 50000W, or other values ​​within the above range. This embodiment does not limit this.

[0166] The electrode spacing K of the reaction chamber satisfies: 10mm≤K≤50mm, which makes the electrode spacing K of the reaction chamber moderate, promotes uniform plasma distribution, improves the uniformity of the deposited insulating layer 16, and allows the plasma to react fully, improves the deposition rate, and improves the density of the insulating layer 16, thereby improving the insulation effect of the insulating layer 16.

[0167] Optionally, the electrode spacing K of the reaction chamber can be 10mm, 15mm, 20mm, 25mm, 30mm, 35mm, 40mm, 45mm or 50mm, or other values ​​within the above range. This embodiment does not limit this.

[0168] In one possible implementation, such as Figure 5 As shown, after completing the deposition of the insulating layer 16, the fabrication method of the back contact battery 1 further includes:

[0169] Step 6: In the second region 112, a portion of the horizontally arranged insulating layer 16 is removed by laser to expose the substrate 11 in the second region 112. The exposed substrate 11 and the front side of the substrate 11 are then wet-etched to remove the damage to the lattice of the substrate 11 caused by the laser and other preceding processes. This removes harmful defects on the surface of the substrate 11, improves the uniformity and quality of subsequent deposition of other film layers, and enhances the insulating effect of the insulating layer 16.

[0170] Step Seven: As Figure 6As shown, a passivation layer 19 and an antireflection layer 18 are sequentially deposited on the front side of the substrate 11. The passivation layer 19 can suppress carrier recombination and improve the open-circuit voltage, while the antireflection layer 18 can reduce reflection loss and improve the efficiency of the back contact cell 1.

[0171] In one possible implementation, such as Figure 7 As shown, after completing the wet etching of the exposed substrate 11 in the second region 112 and the front side of the substrate 11, the fabrication method of the back contact cell 1 further includes:

[0172] Step 8: On the back side of substrate 11, an amorphous silicon passivation layer 14 and a doped amorphous silicon layer 15 are deposited sequentially using plate-type plasma-enhanced chemical vapor deposition (PECVD). Depositing the doped amorphous silicon layer 15 can reduce the contact resistance of the P region, increase the parallel resistance of the battery, and improve the overall electrical performance of the battery.

[0173] Specifically, in step eight, an amorphous silicon passivation layer 14, which is an intrinsic amorphous silicon layer (abbreviated as: ia-Si:H), is directly deposited on the back side of the substrate 11. That is, at this time, the amorphous silicon passivation layer 14 is an undoped amorphous silicon passivation layer 14, and a doped nanocrystalline silicon layer (e.g., p-nc-Si:H) or a doped microcrystalline silicon layer (e.g., p-μc-Si:H) doped amorphous silicon layer 15 is directly deposited on the amorphous silicon passivation layer 14. Since the present application has a first insulating portion 162, the risk of conduction between the doped amorphous silicon layer 15 and the doped polycrystalline silicon layer 13 is prevented. Compared with the traditional method of first depositing a doped amorphous hydride layer (e.g., pa-Si:H) and then... Laser irradiation induces the doped amorphous hydride layer to crystallize into a doped nanocrystalline silicon layer or a doped microcrystalline silicon layer with better conductivity. In this application, a doped amorphous silicon layer 15 can be directly deposited as a doped nanocrystalline silicon layer (e.g., p-nc-Si:H) or a doped microcrystalline silicon layer (e.g., p-μc-Si:H) using plate plasma-enhanced chemical vapor deposition. This eliminates the need for additional laser equipment, simplifies the preparation steps, and reduces production costs. At the same time, direct deposition of the doped amorphous silicon layer 15, without the need for laser crystallization, can prevent the passivation effect of the P region (second region 112) from being reduced due to laser irradiation, improve the passivation effect of the P region, and enhance the battery performance of the back contact battery 1.

[0174] It should be noted that in subsequent processes, some doping elements in the doped amorphous silicon layer 15 are incorporated into the intrinsic amorphous silicon layer, forming a lightly doped or gradient-doped amorphous silicon passivation layer 14.

[0175] In the step of depositing the doped amorphous silicon layer 15, silane, hydrogen and diborane are simultaneously introduced for deposition. The deposition temperature T2 satisfies: 150℃≤T2≤250℃, and the deposition pressure P2 satisfies: 1Torr≤P2≤10Torr.

[0176] The deposition temperature T2 satisfies the condition that 150℃≤T2≤250℃, which is conducive to the formation of a dense, uniform, and stable doped amorphous silicon layer 15 with crystal nuclei, thereby increasing the hole concentration and thin film conductivity, and improving the passivation effect.

[0177] Optionally, the deposition temperature T2 of the doped amorphous silicon layer 15 can be 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 230°C, 240°C or 250°C, or other values ​​within the above range. This embodiment does not limit this.

[0178] The deposition pressure P2 satisfies: 1 Torr ≤ P2 ≤ 10 Torr, which is beneficial to improving the deposition rate of the doped amorphous silicon layer 15, and also beneficial to improving the uniformity of the plasma distribution inside the doped amorphous silicon layer 15, which is beneficial to forming a dense and smooth doped amorphous silicon layer 15, and reducing the difficulty of subsequently depositing a transparent conductive layer 17 on the doped amorphous silicon layer 15.

[0179] Optionally, the deposition pressure P2 of the doped amorphous silicon layer 15 can be 1 Torr, 2 Torr, 3 Torr, 4 Torr, 5 Torr, 6 Torr, 7 Torr, 8 Torr, 9 Torr or 10 Torr, or other values ​​within the above range. This embodiment does not limit this.

[0180] In one possible implementation, such as Figure 1 , Figure 8 and Figure 9 As shown, after completing the deposition of the doped amorphous silicon layer 15, the fabrication method of the back contact cell 1 further includes:

[0181] Step Nine: Figure 8 As shown, the laser removes the amorphous silicon passivation layer 14, the doped amorphous silicon layer 15, and the insulating layer 16 located in the first region 111 to form the N region.

[0182] Step 10: As Figure 9 As shown, a transparent conductive layer 17 is deposited on the back side of the substrate 11. The transparent conductive layer 17 is used to collect current and transmit current to the electrode. The transparent conductive layer 17 also reduces the series resistance and improves the fill factor.

[0183] Step 11: As Figure 10 and Figure 11As shown, laser grooving is performed at a portion of the spacer region 113 to remove at least the transparent conductive layer 17 and the doped amorphous silicon layer 15 to form an isolation trench. The isolation trench isolates the N-region and the P-region, preventing the N-region and the P-region from conducting through the transparent conductive layer 17 and the doped amorphous silicon layer 15, thus preventing short circuits.

[0184] In one possible embodiment, such as Figure 10 As shown, during laser grooving, the transparent conductive layer 17, the amorphous silicon passivation layer 14, and the doped amorphous silicon layer 15 are removed to improve the short-circuit protection performance of the back contact battery 1.

[0185] In another possible embodiment, such as Figure 11 As shown, during laser grooving, the transparent conductive layer 17 and the doped amorphous silicon layer 15 are removed. Since the amorphous silicon passivation layer 14 is basically non-conductive, it is also possible not to remove the amorphous silicon passivation layer 14.

[0186] Step 12: Prepare the first electrode 101 in the first region 111 and prepare the second electrode 102 in the second region 112.

[0187] This application also provides a stacked battery 2, such as Figure 13 As shown, the stacked battery 2 includes a perovskite battery 21 and a back contact battery 1 in any of the above embodiments, or the stacked battery 2 includes a perovskite battery 21 and a back contact battery 1 prepared by the above preparation method of the back contact battery 1.

[0188] Along the thickness direction of the tandem cell 2, the perovskite cell 21 forms an electrical connection with the light-facing surface of the back contact cell 1. The perovskite cell 21 is a thin-film solar cell with perovskite material as the photoactive layer. The structure of the perovskite cell 21 mainly consists of the following key parts: a transparent conductive substrate, an electron transport layer, a perovskite light-absorbing layer, a hole transport layer, and a metal electrode. These components work together to enable the perovskite cell 21 to effectively absorb sunlight and convert it into electrical energy. The perovskite material in the perovskite light-absorbing layer has excellent light absorption performance, can absorb a wider spectral range, and effectively convert short-wavelength spectra, giving the perovskite cell 21 high photoelectric conversion efficiency.

[0189] In some embodiments, the back contact battery 1 further includes a first gate line electrically connected to the doped polycrystalline silicon layer 13 and a second gate line electrically connected to the doped amorphous silicon layer 15.

[0190] In some embodiments, such as Figure 14As shown, the stacked cell 2 can be a three-terminal stacked solar cell of perovskite cell 21 and back contact cell 1. That is, the perovskite cell 21 and the back contact cell 1 form a three-terminal stacked structure. A terminal is led out from the end of the perovskite cell 21 away from the back contact cell 1. The first grid line and the second grid line in the back contact cell 1 are led out as two independent terminals. The mismatch current can be output through the extra terminal to ensure that the stacked cell 2 operates at a higher power.

[0191] In other embodiments, such as Figure 15 As shown, the stacked cell 2 can be a solar cell stacked at both ends of a perovskite cell 21 and a back contact cell 1. That is, the perovskite cell 21 and the back contact cell 1 form a stacked structure at both ends. The positive electrode of the perovskite cell 21 is electrically connected to one of the first grid line and the second grid line in the back contact cell 1 to form a terminal, and the negative electrode of the perovskite cell 21 is electrically connected to the other of the first grid line and the second grid line in the back contact cell 1 to form another terminal.

[0192] In some other embodiments, such as Figure 16 As shown, the stacked solar cell 2 can be a four-terminal stacked solar cell consisting of a perovskite cell 21 and a back contact cell 1. That is, the perovskite cell 21 and the back contact cell 1 form a four-terminal stacked structure. The positive and negative electrodes of the perovskite cell 21 are respectively led out as independent terminals, and the first and second grid lines of the back contact cell 1 are also respectively led out as independent terminals. Therefore, in this embodiment, the circuits of the perovskite cell 21 and the back contact cell 1 are independent of each other, and each has its own independent output.

[0193] This application also provides a photovoltaic module, such as Figure 17 As shown, the photovoltaic module includes the back contact cell 1 in any of the above embodiments, or the photovoltaic module includes the back contact cell 1 prepared by the above-described method for preparing the back contact cell 1, or, as... Figure 18 As shown, the photovoltaic module includes the tandem cell 2 in any of the above embodiments.

[0194] Specifically, a photovoltaic module includes a battery module, which in turn includes several battery strings. Each battery string includes a back-contact battery 1 or a stacked battery 2, as described in any of the above embodiments. The back-contact batteries 1 or stacked batteries 2 in the battery module can be connected in series via solder strips 3 to form a battery string. The individual battery strings in the battery module can achieve current collection and output by connecting them in series, parallel, or a combination of series and parallel connections using busbars.

[0195] like Figure 17 and Figure 18As shown, the photovoltaic module also includes a front panel 4, a front encapsulation layer 5, a back encapsulation layer 6, and a back panel 7. The front panel 4 and the back panel 7 together sandwich the front encapsulation layer 5, the photovoltaic cells, the solder ribbons 3, and the back encapsulation layer 6, and form the photovoltaic module through lamination. The front encapsulation layer 5 protects the light-facing side of the photovoltaic cells, and the back encapsulation layer 6 protects the back-facing side of the photovoltaic cells. During the lamination process, the front encapsulation layer 5 and the back encapsulation layer 6 encapsulate and protect the photovoltaic cells and solder ribbons 3, preventing external environmental factors from affecting their performance. They also bond the front panel 4, the back panel 7, the photovoltaic cells, and the solder ribbons 3 into a single unit. The photovoltaic cells are either back-contact cells 1 or stacked cells 2 as described in any of the above embodiments.

[0196] The front panel 4 and back panel 7 can be made of rigid materials such as tempered glass, polyethylene terephthalate (PET), and polycarbonate (PC), or flexible materials such as polyvinyl fluoride (PVF), ethylene-tetrafluoroethylene copolymer (ETFE), and polyvinylidene fluoride (PVDF). The front and back encapsulation layers 6 are adhesive films, which can be made of materials such as ethylene-vinyl acetate copolymer (EVA), polyolefin elastomer (POE), and polyvinyl butyral (PVB). The front encapsulation layer 5 and back encapsulation layer 6 can also be EPE film (EVA-POE-EVA co-extrusion structure) or EP film (EVA-EP co-extrusion structure).

[0197] The above descriptions are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A back-contact battery, characterized in that, The back contact battery (1) includes at least: The substrate (11) has a back surface comprising a first region (111), a second region (112) and a spacer region (113) located between the first region (111) and the second region (112). A tunneling oxide layer (12) and a doped polysilicon layer (13) are disposed in the first region (111) and the spacer region (113), and the doped polysilicon layer (13) is disposed on the surface of the tunneling oxide layer (12) away from the substrate (11) along the thickness direction of the back contact cell (1); An amorphous silicon passivation layer (14) and a doped amorphous silicon layer (15) are disposed in the second region (112). The doped amorphous silicon layer (15) is disposed in a portion of the spacer region (113). The amorphous silicon passivation layer (14) is disposed in a portion of the spacer region (113) or all of the spacer region (113). The doped polycrystalline silicon layer (13) has the opposite conductivity type to the doped amorphous silicon layer (15). The doped amorphous silicon layer (15) is disposed on the surface of the amorphous silicon passivation layer (14) away from the substrate (11) along the thickness direction of the back contact cell (1). In the spacer region (113), the amorphous silicon passivation layer (14) is located on the side of the doped polycrystalline silicon layer (13) away from the substrate (11) along the thickness direction of the back contact cell (1). The spacer region (113) is provided with an isolation trench, which penetrates the amorphous silicon passivation layer (14) and the doped amorphous silicon layer (15), or the isolation trench penetrates the doped amorphous silicon layer (15). An insulating layer (16) is disposed between the amorphous silicon passivation layer (14) and the doped polycrystalline silicon layer (13). The insulating layer (16) includes at least a first insulating portion (162) extending along the thickness direction of the back contact cell (1). The first insulating portion (162) is disposed at the junction of the second region (112) and the spacer region (113).

2. The back contact battery according to claim 1, characterized in that, The insulating layer (16) is a silicon nitride layer, and the dimension L1 of the first insulating part (162) in the horizontal direction satisfies: 3nm≤L1≤80nm.

3. The back contact battery according to claim 1, characterized in that, The insulating layer further includes a second insulating portion (161) extending in a horizontal direction, the second insulating portion (161) being disposed in the spacer region (113), and the dimension S1 of the second insulating portion (161) along the thickness direction of the back contact battery (1) satisfies: 5nm≤S1≤100nm.

4. The back contact battery according to claim 3, characterized in that, The projection of the second insulating part (161) onto the substrate (11) can block the isolation groove. The dimension L2 of the spacer area (113) in the horizontal direction satisfies: 20um≤L2≤200um, and the dimension L3 of the isolation groove in the horizontal direction satisfies: 10um≤L3≤180um.

5. The back contact battery according to claim 1, characterized in that, In the spacer region (113), the dimension S2 of the amorphous silicon passivation layer (14) along the thickness direction of the back contact cell (1) satisfies: 5nm≤S2≤20nm, and the dimension S3 of the doped amorphous silicon layer (15) along the thickness direction of the back contact cell (1) satisfies: 10nm≤S3≤100nm.

6. The back contact battery according to claim 1, characterized in that, The back contact cell (1) includes a transparent conductive layer (17), which is disposed on the surface of the doped amorphous silicon layer (15) away from the substrate (11) along the thickness direction of the back contact cell (1), and a first electrode (101) and a second electrode (102) are respectively disposed on the transparent conductive layer (17) located in the first region (111) and the second region (112). Along the thickness direction of the back contact battery (1), a passivation layer (19) and an antireflection layer (18) are sequentially disposed on the front side of the substrate (11).

7. A method for preparing a back-contact battery, characterized in that, The method for preparing the back contact battery (1) includes: Provide substrate (11); A tunneling oxide layer (12) and a doped polysilicon layer (13) are sequentially deposited on the front and back sides of the substrate (11) along the thickness direction. Wet etching is used to remove the phosphosilicate glass layers on the front and back sides of the substrate (11); The back side of the substrate (11) includes a first region (111), a second region (112), and a spacer region (113) located between the first region (111) and the second region (112). The second region (112) is laser-grooved to remove the tunneling oxide layer (12) and the doped polysilicon layer (13) so that the substrate (11) in the second region (112) is exposed. An insulating layer (16) is deposited on the back side of the substrate (11). In the second region (112), a portion of the horizontally arranged insulating layer (16) is removed by laser to expose the substrate (11) in the second region (112), and wet etching is performed on the exposed substrate (11) in the second region (112) and the front side of the substrate (11). An amorphous silicon passivation layer (14) and a doped amorphous silicon layer (15) are sequentially deposited on the back side of the substrate (11).

8. The method for preparing a back contact battery according to claim 7, characterized in that, In the step of depositing the insulating layer (16), silane, ammonia, nitrogen and hydrogen are simultaneously introduced for deposition. The amount of silane introduced, R1, satisfies: 500 sccm ≤ R1 ≤ 2000 sccm; the amount of ammonia introduced, R2, satisfies: 500 sccm ≤ R2 ≤ 3000 sccm; the amount of nitrogen introduced, R3, satisfies: 5000 sccm ≤ R3 ≤ 15000 sccm; and the amount of hydrogen introduced, R4, satisfies: 1000 sccm ≤ R4 ≤ 10000 sccm.

9. The method for preparing a back contact battery according to claim 7, characterized in that, In the step of depositing the insulating layer (16), the deposition temperature T1 satisfies: 100℃≤T1≤300℃, and the deposition pressure P1 satisfies: 1Torr≤P1≤10Torr.

10. The method for preparing a back contact battery according to claim 7, characterized in that, In the step of depositing the insulating layer (16), the power W1 of the radio frequency power supply satisfies: 500W≤W1≤50000W, and the electrode spacing K of the reaction chamber satisfies: 10mm≤K≤50mm.

11. The method for preparing a back contact battery according to claim 7, characterized in that, After completing the deposition of the insulating layer (16), the method for preparing the back contact battery (1) further includes: A passivation layer (19) and an antireflection layer (18) are sequentially deposited on the front side of the substrate (11).

12. The method for preparing a back contact battery according to claim 11, characterized in that, After completing the wet etching of the substrate (11) exposed in the second region (112) and the front side of the substrate (11), the method for fabricating the back contact cell (1) further includes: When depositing the amorphous silicon passivation layer (14) and the doped amorphous silicon layer (15), the amorphous silicon passivation layer (14) and the doped amorphous silicon layer (15) are deposited by plate plasma enhanced chemical vapor deposition. In the step of depositing the doped amorphous silicon layer (15), silane, hydrogen and diborane are simultaneously introduced for deposition, and the deposition temperature T2 satisfies: 150℃≤T2≤250℃, and the deposition pressure P2 satisfies: 1Torr≤P2≤10Torr.

13. The method for preparing a back contact battery according to claim 12, characterized in that, After completing the deposition of the doped amorphous silicon layer (15), the method for fabricating the back contact cell (1) further includes: Laser removal of the amorphous silicon passivation layer (14), the doped amorphous silicon layer (15), and the insulating layer (16) located in the first region (111). A transparent conductive layer (17) is deposited on the back side of the substrate (11). Laser grooving is performed at a portion of the spacer region (113) to remove at least the transparent conductive layer (17) and the doped amorphous silicon layer (15) to form an isolation groove; A first electrode (101) is prepared in the first region (111), and a second electrode (102) is prepared in the second region (112).

14. A stacked battery, characterized in that, The stacked battery (2) includes a perovskite battery (21) and a back contact battery (1) according to any one of claims 1-6, or the stacked battery (2) includes a perovskite battery (21) and the back contact battery (1) prepared by the preparation method of the back contact battery (1) according to any one of claims 7-13.

15. A photovoltaic module, characterized in that, The photovoltaic module includes a back contact cell (1) according to any one of claims 1-6, or the photovoltaic module includes the back contact cell (1) prepared by the method of the back contact cell (1) according to any one of claims 7-13, or the photovoltaic module includes the tandem cell (2) according to claim 14.

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