Display panel and preparation method thereof

Abstract

The invention discloses a display panel and a preparation method thereof. The distance between a first surface of a first pixel definition part located in a display area and a substrate is larger than the distance between a second surface of a second pixel definition part located in a bonding area and the substrate. The thickness of the first supporting columns located on the first pixel defining parts is smaller than that of the second supporting columns located on the second pixel defining parts, and the surfaces, away from the substrate, of the first supporting columns are flush with the surfaces, away from the substrate, of the sides of the second supporting columns. Therefore, when the fine metal mask plate is placed on the first supporting column and the second supporting column, a flat supporting surface can be provided for the fine metal mask plate through the first supporting column and the second supporting column, so that the probability of inclination of the fine metal mask plate is reduced, and the situation that the supporting columns are damaged due to inclination of the fine metal mask plate is improved; and black spots or black spots are displayed.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] In display panel fabrication, a fine metal mask inverted vapor deposition method can be used to deposit luminescent material at the pixel locations to form the luminescent layer. During this deposition, the fine metal mask rests on support pillars, maintaining a certain distance between the mask and the pixel, thus reducing damage to the pixel area. However, multiple support pillars cannot provide a flat support surface for the fine metal mask, making it prone to tilting during luminescent layer fabrication. This can cause the mask to scratch the pillars, resulting in luminescent material being deposited onto them as foreign matter. The presence of this foreign matter can damage the encapsulation layer on the luminescent layer, causing encapsulation failure and subsequently leading to black spots or dark patches on the display. Summary of the Invention

[0003] This application provides a display panel and its manufacturing method to improve the problem of display black spots or black dots.

[0004] To achieve the above objectives, this application provides a display panel having a display area and a bonding area located on one side of the display area. The display panel includes a substrate, a pixel definition layer, a first support pillar, and a second support pillar. The substrate is located in the display area and the bonding area. The pixel definition layer is located on the substrate and includes a first pixel definition portion located in the display area and a second pixel definition portion located in the bonding area. The first support pillar is located on the first pixel definition portion, and the second support pillar is located on the second pixel definition portion. The first pixel definition portion has a first surface on the side away from the substrate, and the second pixel definition portion has a second surface on the side away from the substrate. Along the thickness direction of the display panel, the distance between the first surface and the substrate is greater than the distance between the second surface and the substrate. The thickness of the first support pillar is less than the thickness of the second support pillar, and the surfaces of the first and second support pillars on the side away from the substrate are flush.

[0005] This application also provides a method for manufacturing a display panel, comprising: providing a substrate; and fabricating a pixel definition layer, a first support pillar, and a second support pillar on the substrate. The pixel definition layer includes a first pixel definition portion located in the display area of ​​the display panel and a second pixel definition portion located in the bonding area of ​​the display panel. The first pixel definition portion has a first surface on the side away from the substrate, and the second pixel definition portion has a second surface on the side away from the substrate. Along the thickness direction of the display panel, the distance between the first surface and the substrate is greater than the distance between the second surface and the substrate. The first support pillar is located on the first pixel definition portion, and the second support pillar is located on the second pixel definition portion. The thickness of the first support pillar is less than the thickness of the second support pillar, and the surfaces of the first and second support pillars on the side away from the substrate are flush.

[0006] In the display panel and its manufacturing method according to the embodiments of this application, the distance between the first surface of the first pixel definition portion in the display area away from the substrate and the substrate is greater than the distance between the second surface of the second pixel definition portion in the bonding area away from the substrate and the substrate. Furthermore, the thickness of the first support pillar on the first pixel definition portion is less than the thickness of the second support pillar on the second pixel definition portion. The surfaces of the first and second support pillars away from the substrate are flush. Thus, when the fine metal mask is placed on the first and second support pillars, a flat support surface can be provided for the fine metal mask, reducing the probability of the fine metal mask tilting and mitigating the problem of display black spots or dots caused by damage to the support pillars due to tilting of the fine metal mask.

[0007] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0010] Figure 1 This is a mechanism diagram of forming black spots or dots provided in an exemplary embodiment of this application;

[0011] Figure 2 This is a schematic diagram of a support column with foreign objects provided in an exemplary embodiment of this application;

[0012] Figure 3 This is a schematic diagram of the encapsulation layer provided in an exemplary embodiment of this application;

[0013] Figure 4 This is a schematic diagram showing a display panel with black spots or dots in an exemplary embodiment of this application;

[0014] Figure 5 This is a schematic diagram of the structure of the display panel provided in an exemplary embodiment of this application;

[0015] Figures 6A-6B This is a schematic diagram of the film layer structure of the display panel provided in an exemplary embodiment of this application;

[0016] Figures 7A to 7C This is a flowchart illustrating the fabrication process of the display panel provided in an exemplary embodiment of this application;

[0017] Figures 8A-8B This is a schematic diagram of the structure of the mask area and the support column relative to each other in an exemplary embodiment of this application;

[0018] Figure 9 This is a comparative structural diagram of the display panel provided in an exemplary embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0020] It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the invention. In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its actual use or operation, specifically the directions shown in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0021] Self-emissive display panels that use light-emitting devices as sub-pixels are widely used due to their advantages such as thinness, high brightness, and low power consumption. The light-emitting layer of the light-emitting device requires a fine metal mask during fabrication. By placing the fine metal mask on a support pillar, the light-emitting material is fabricated at the location of the pixel hole using the openings in the mask corresponding to the display area.

[0022] Figure 1This is a mechanism diagram illustrating the formation of black spots or dots provided in an exemplary embodiment of this application. Figure 2 This is a schematic diagram of a support column with foreign objects provided in an exemplary embodiment of this application. Figure 3 This is a schematic diagram of the encapsulation layer provided in an exemplary embodiment of this application. Figure 4 This is a schematic diagram illustrating the presence of black spots or dots on a display panel provided in an exemplary embodiment of this application. Because the top surfaces of the multiple support pillars (PS) in the display panel are located in different planes, the fine metal mask (FMM) will tilt when placed on the surfaces of the multiple support pillars (PS). For example... Figure 1 As shown, when the support pillar PS in the display area AA is higher than the support pillar PS in the bonding area DA, the fine metal mask FMM placed on the support pillar PS will tilt. Furthermore, the mask frame MF in the fine metal mask FMM corresponding to the bonding area DA will compress the mask MS in the fine metal mask FMM corresponding to the display area AA. This causes the stress of the fine metal mask FMM on the support pillar PS to concentrate on the higher support pillar PS. The fine metal mask FMM is prone to scratching the support pillar PS, and the relative positions of the opening area and the pixel hole in the fine metal mask FMM are prone to misalignment. This results in the luminescent material being easily fabricated on the support pillar PS during the pixel hole fabrication process, forming foreign matter Fb, such as... Figure 2 As shown. In some embodiments, the higher support post PS on the top surface is located near the edge of the display area AA, close to the bonding area DA.

[0023] The presence of foreign matter can damage the encapsulation layer fabricated on the light-emitting layer, causing encapsulation failure. For example... Figure 3 As shown, the encapsulation layer includes a first encapsulation layer CVD1, a second encapsulation layer IJP, and a third encapsulation layer CVD2. The second encapsulation layer IJP is located between the first encapsulation layer CVD1 and the third encapsulation layer CVD2, and the first encapsulation layer CVD1 is located on the side of the second encapsulation layer IJP closer to the light-emitting layer. The presence of foreign matter can penetrate the third encapsulation layer CVD2, causing encapsulation failure. Encapsulation failure can cause black spots or dark patches on the display, such as… Figure 4 As shown.

[0024] Therefore, this application provides a display panel and a method for manufacturing the same, in order to improve the problem of display black spots or black dots.

[0025] like Figure 5 This is a schematic diagram of the structure of a display panel provided in an exemplary embodiment of this application. This application provides a display panel having a display area AA and a bonding area DA1 located on one side of the display area AA.

[0026] The display panel includes a self-emissive display panel, which in turn includes a display panel that uses light-emitting devices as sub-pixels (SPX). The light-emitting devices include at least one of organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (PMLEDs), and micro LEDs.

[0027] The display area AA of the display panel is configured to implement the display function of the display panel. The display area AA of the display panel may include multiple sub-pixels SPX, which are configured to realize the display of the display panel according to the received data signals.

[0028] The bonding area DA1 is configured to electrically connect multiple sub-pixels SPX of the display area AA and the driving unit. In some embodiments, the bonding area DA1 may be provided with multiple connection electrodes and multiple connection traces, and the multiple connection electrodes and corresponding connection traces are electrically connected. The driving unit is electrically connected to the multiple sub-pixels SPX through the multiple connection electrodes and multiple connection traces.

[0029] Optionally, the driving unit may include at least one of a source driver chip, a display driver chip, or a chip integrating touch and driving. Optionally, the driving unit may be configured to generate multiple data signals to be transmitted to multiple sub-pixels SPX via multiple connection electrodes and multiple connection traces, so that the multiple sub-pixels SPX can display according to the received data signals.

[0030] Optionally, the drive unit can be electrically connected to the connection electrode in the form of a flip-chip thin film.

[0031] Optionally, at least a portion of the bonding area DA1 may be bent to the back of the substrate 100 of the display panel to reduce the bezel size of the display panel.

[0032] like Figures 6A-6B This is a schematic diagram of the film layer structure of a display panel provided in an exemplary embodiment of this application. The display panel includes a substrate 100, a pixel definition layer 200, a first support pillar 301, and a second support pillar 302.

[0033] The substrate 100 is located in the display area AA and the bonding area DA1. The portion of the substrate 100 located in the display area AA and the portion of the substrate 100 located in the bonding area DA1 can be continuously arranged.

[0034] Optionally, substrate 100 may include at least one of a flexible substrate and a rigid substrate. The flexible substrate may include a single layer or multiple layers formed of polyimide. The rigid substrate may include at least one of glass, ceramic, etc.

[0035] Please continue reading. Figures 6A-6BThe pixel definition layer 200 is located on the substrate 100. The pixel definition layer 200 includes a first pixel definition portion 201 located in the display area AA and a second pixel definition portion 202 located in the bonding area DA1. The first pixel definition portion 201 has a first surface on the side away from the substrate 100, and the second pixel definition portion 202 has a second surface on the side away from the substrate 100. Along the thickness direction Dr1 of the display panel, the distance L1 between the first surface and the substrate 100 is greater than the distance L2 between the second surface and the substrate 100.

[0036] Optionally, the first pixel definition section 201 and the second pixel definition section 202 can be set continuously or at intervals.

[0037] Optionally, the pixel definition layer 200 may include organic or inorganic materials. In some embodiments, the pixel definition layer 200 may be an organic photoresist. For example, the pixel definition layer 200 may be a polyimide positive photoresist, an olefin positive photoresist, or an acrylic negative photoresist. The pixel definition layer 200 may be a transparent photoresist or a colored photoresist. Colored photoresist may include black photoresist, or a photoresist containing one of inorganic pigments, organic pigments, organic dyes, and pigment / dye mixtures.

[0038] Please continue reading. Figures 6A-6B The first support post 301 is located on the first pixel definition portion 201, and the second support post 302 is located on the second pixel definition portion 202. The thickness H1 of the first support post 301 is less than the thickness H2 of the second support post 302, and the surface of the first support post 301 away from the substrate 100 and the surface of the second support post 302 away from the substrate 100 are flush.

[0039] By making the first pixel defining portion 201 higher than the second pixel defining portion 202, and the thickness H1 of the first support pillar 301 less than the thickness H2 of the second support pillar 302, the difference between the sum of the thicknesses of the first support pillar 301 and the first pixel defining portion 201 and the sum of the thicknesses of the second support pillar 302 and the second pixel defining portion 202 is reduced. This reduces the distance between the surface of the first support pillar 301 away from the substrate 100 and the surface of the second support pillar 302 away from the substrate 100, resulting in a smaller step difference between the display area AA and the bonding area DA1 above the substrate 100. Therefore, when the fine metal mask is placed on the first support pillar 301 and the second support pillar 302, the first support pillar 301 and the second support pillar 302 can provide a flat support surface for the fine metal mask, reducing the probability of the fine metal mask tilting and improving the problem of display black spots or black dots caused by damage to the support pillars due to tilting of the fine metal mask.

[0040] Optionally, at least two of the first support pillar 301, the second support pillar 302, and the pixel definition layer 200 are made of the same material, so that at least two of the first support pillar 301, the second support pillar 302, and the pixel definition layer 200 can be prepared simultaneously, thereby saving process steps and improving manufacturing efficiency.

[0041] Optionally, the materials of the first support pillar 301 and the second support pillar 302 may include organic or inorganic materials. In some embodiments, the materials of the first support pillar 301 and the second support pillar 302 may be organic photoresists. For example, the materials of the first support pillar 301 and the second support pillar 302 may be polyimide positive photoresist, olefin positive photoresist, or acrylic negative photoresist, respectively. The materials of the first support pillar 301 and the second support pillar 302 may be transparent photoresists or colored photoresists. Colored photoresists may include black photoresists, or photoresists containing one of inorganic pigments, organic pigments, organic dyes, and pigment / dye mixtures.

[0042] In some embodiments, the difference between the thickness H2 of the second support post 302 and the thickness H1 of the first support post 301 is equal to the distance between the first surface and the second surface, so that the surface of the first support post 301 on the side away from the substrate 100 and the surface of the second support post 302 on the side away from the substrate 100 are flush.

[0043] Optionally, the difference between the thickness H2 of the second support column 302 and the thickness H1 of the first support column 301 is greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer. In some embodiments, the difference between the thickness H2 of the second support column 302 and the thickness H1 of the first support column 301 is greater than or equal to 0.4 micrometers and less than or equal to 0.8 micrometers. For example, the difference between the thickness H2 of the second support column 302 and the thickness H1 of the first support column 301 can be equal to 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, or 0.8 micrometers.

[0044] The display panel may also include a pixel driving circuit, which is electrically connected to the light-emitting device and configured to drive the light-emitting device to emit light. The driving circuit can be implemented in the form of 2T1C, 5T1C, 7T1C, 7T2C, or 8T1C, etc. Here, T represents a transistor, and C represents a capacitor. 2T1C means that the pixel driving circuit includes two transistors and one capacitor.

[0045] Please continue reading. Figures 6A-6B The display panel may also include a first active layer 1011, a first insulating layer 1021, a first metal layer 1031, a first interlayer insulating layer 1041, a first source / drain layer 1051, a first planarization layer 1061, an anode layer 1071, a light-emitting layer 1072, a cathode layer 1073, and an encapsulation layer 108.

[0046] The first active layer 1011 is located on the substrate 100, and the first active layer 1011 includes an active pattern located in the display area AA. The active pattern may include an active region, a first doped region and a second doped region located on opposite sides of the active region.

[0047] Optionally, the first active layer 1011 may be a silicon semiconductor layer. The silicon semiconductor layer may include polycrystalline silicon, amorphous silicon, or monocrystalline silicon materials.

[0048] The first insulating layer 1021 is located on the active layer and is located in the display area AA.

[0049] Optionally, the first insulating layer 1021 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0050] A first metal layer 1031 is located on a first insulating layer 1021, and the first metal layer 1031 includes a first electrode pattern located in the display area AA. The first electrode pattern includes a gate corresponding to the active area of ​​the active pattern. In some embodiments, the first metal layer 1031 may further include a routing pattern for forming scan lines or other signal lines.

[0051] Optionally, the first metal layer 1031 comprises at least one metal selected from molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten, and copper. The first metal layer 1031 may be a single layer or multiple layers.

[0052] The first interlayer insulating layer 1041 is located on the first metal layer 1031 and is located in the display area AA. Optionally, the first interlayer insulating layer 1041 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene.

[0053] The first source / drain layer 1051 is located on the first interlayer insulating layer 1041. The first source / drain layer 1051 includes a first connection portion located in the display area AA and electrically connected to the active pattern, and a second connection portion located in the bonding area DA1.

[0054] Understandably, the first source / drain layer 1051 may include multiple first connection portions, which may include first sub-connection portions and second sub-connection portions. The first sub-connection portions are connected to a first doped region of the active pattern, and the second sub-connection portions are connected to a second doped region of the active pattern. The first sub-connection portions and the second sub-connection portions may be formed as source and drain, respectively.

[0055] Optionally, the first source / drain layer 1051 may include at least one of molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten, and copper. The first source / drain layer 1051 may be configured as a single layer or multiple layers.

[0056] For the same active pattern, the first electrode pattern corresponding to the active pattern, the first sub-connection portion electrically connected to the active pattern, and the second sub-connection portion can respectively form the gate, source, and drain of a transistor.

[0057] The first planarization layer 1061 is located on the first source / drain layer 1051 and is located in the display area AA and the bonding area DA1.

[0058] Optionally, the first planarization layer 1061 may comprise multiple layers or a single layer formed of silicon nitride or silicon oxide, and may be formed of an organic material (such as polyimide) having a low dielectric constant.

[0059] The anode layer 1071 is located on the first planarization layer 1061 and on the side of the pixel definition layer 200 near the substrate 100. The anode layer 1071 is located in the display area AA and may include multiple anode patterns.

[0060] Optionally, the anode pattern can be connected to the corresponding first connection portion through a via penetrating the first planarization layer 1061, and the anode pattern can be formed as the anode of the light-emitting device.

[0061] The pixel definition layer 200 may have an opening at the location corresponding to the anode pattern, the opening exposing at least a portion of the surface of the corresponding anode pattern so that the luminescent material can come into contact with the anode pattern.

[0062] The light-emitting layer 1072 is located in the opening of the pixel definition layer 200, and the light-emitting layer 1072 may include an emission layer. Optionally, the light-emitting layer 1072 may also include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The hole injection layer may be located on the anode pattern, and the hole transport layer, emission layer, electron transport layer, and electron injection layer are sequentially stacked on the hole injection layer.

[0063] The cathode layer 1073 is located on the light-emitting layer 1072 and the pixel definition layer 200, and is situated in the display area AA. Optionally, the cathode layer 1073 can be arranged as a whole surface or patterned. The cathode layer 1073 can be formed as the cathode of a light-emitting device. The cathode, anode, and the light-emitting layer 1072 located between the cathode and anode form a light-emitting device.

[0064] Optionally, the cathode layer 1073 may include one or more of magnesium, silver, gold, calcium, lithium, chromium, and aluminum, or alloys thereof. Optionally, the cathode layer 1073 may also include indium tin oxide, indium zinc oxide, zinc oxide, or indium oxide.

[0065] Encapsulation layer 108 is located on cathode layer 1073, and encapsulation layer 108 can extend from display area AA to the area between bonding area DA1 and display area AA. For example, encapsulation layer 108 can extend from display area AA to connection area DA2 located between display area AA and bonding area DA1.

[0066] Optionally, the encapsulation layer 108 includes an alternating inorganic encapsulation layer 108 and an organic encapsulation layer 108.

[0067] In some embodiments, the organic encapsulation layer 108 may comprise a multilayer or single-layer structure formed from any one of polyethylene terephthalate, polyimide, polycarbonate, epoxy resin, polyethylene, and polyacrylate.

[0068] In some embodiments, the inorganic encapsulation layer 108 may be a multilayer or a single layer comprising metal oxides or metal nitrides. For example, the inorganic encapsulation layer 108 may include at least one of silicon nitride, aluminum oxide, silicon oxide, and titanium oxide.

[0069] Optionally, the layer 108 furthest from the substrate 100 can be an inorganic encapsulation layer 108, so as to reduce the probability of moisture being transported to the interior of the light-emitting device and reduce the impact of moisture on the light-emitting device.

[0070] In some embodiments, the encapsulation layer 108 includes a first inorganic encapsulation layer 1081 located on the cathode layer 1073, a first organic encapsulation layer 1082 located on the first inorganic encapsulation layer 1081, and a second inorganic encapsulation layer 1083 located on the first organic encapsulation layer 1082.

[0071] Optionally, the display panel may further include a second insulating layer 1022 and a second metal layer 1032, such as Figures 6A-6B As shown.

[0072] The second insulating layer 1022 is located on the first metal layer 1031 and in the display area AA. Optionally, the second insulating layer 1022 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0073] The second metal layer 1032 is located on the second insulating layer 1022, and the second metal layer 1032 includes a second electrode pattern located in the display area AA. The first electrode pattern and the second electrode pattern can be used to form the two plates of a capacitor in a pixel driving circuit.

[0074] Optionally, the second metal layer 1032 includes at least one of molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten, and copper.

[0075] Optionally, when a pixel driving circuit drives only one light-emitting device, the circuit topology of the pixel driving circuit is complex, and the resolution requirement of the display panel is high, arranging the pixel driving circuits corresponding to multiple light-emitting devices in the display area AA will result in insufficient layout space in the display area AA for the pixel driving circuits and signal lines. Therefore, to increase the space in the display area AA for accommodating the pixel driving circuits and signal line layout, the display panel may further include a second source / drain layer 1052, a second planarization layer 1062, a third source / drain layer 1053, and a third planarization layer 1063, such as... Figures 6A-6B As shown.

[0076] The second source / drain layer 1052 is located on the first planarization layer 1061. The second source / drain layer 1052 may include a third connection portion located in the display area AA and electrically connected to the first connection portion, and a fourth connection portion located in the bonding area DA1. Optionally, the second source / drain layer 1052 may include at least one of molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten, and copper. The second source / drain layer 1052 may be configured as a single layer or multiple layers. In some embodiments, the fourth connection portion may be electrically connected to the second connection portion.

[0077] The second planarization layer 1062 is located on the second source / drain layer 1052 and is situated between the display area AA and the bonding area DA1. Optionally, the second planarization layer 1062 may comprise multiple layers or a single layer formed of silicon nitride or silicon oxide.

[0078] The third source / drain layer 1053 is located on the second planarization layer 1062, and includes a fifth connection portion located in the display area AA and electrically connected to the third connection portion. Optionally, the third source / drain layer 1053 may include at least one of molybdenum, aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, calcium, titanium, tantalum, tungsten, and copper. The third source / drain layer 1053 may be configured as a single layer or multiple layers.

[0079] The third planarization layer 1063 is located on the third source / drain layer 1053 and is situated between the display area AA and the bonding area DA1. Optionally, the third planarization layer 1063 may comprise multiple layers or a single layer formed of silicon nitride or silicon oxide.

[0080] By setting a second source / drain layer 1052 and a third source / drain layer 1053, at least one of the signal lines, electrode patterns, etc. in the display panel can be distributed in different layers, so that the display area AA can accommodate more pixel driving circuits and signal lines.

[0081] Optionally, the transistors and capacitors included in the pixel driving circuit can be formed by a first active layer 1011, a first source-drain layer 1051, a first metal layer 1031, and a second metal layer 1032. The signal lines or wires connecting the transistors and capacitors used in the display panel can be formed by a first source-drain layer 1051, a second source-drain layer 1052, and a third source-drain layer 1053. This reduces interference between the signal lines and the transistors and capacitors. The signal lines can include at least one of scan lines, data lines, and power lines. The signal lines are electrically connected to at least one of the pixel driving circuit and the light-emitting device to transmit corresponding signals to at least one of the pixel driving circuit and the light-emitting device, thereby controlling the light emission of the light-emitting device.

[0082] Because the display area AA has an additional first active layer 1011, a first insulating layer 1021, a first metal layer 1031, a first interlayer insulating layer 1041, and an anode layer 1071 compared to the bonding area DA1, and in some embodiments, the display area AA also has an additional second insulating layer 1022, a second metal layer 1032, and a third source / drain layer 1053 compared to the bonding area DA1, the surfaces of the pixel definition layer 200 corresponding to the display area AA and the bonding area DA1 on the side away from the substrate 100 have a height difference. That is, there is a height difference between the first surface and the second surface.

[0083] It should be noted that the display panel may also include a second active layer 1012, a third insulating layer 1023, a third metal layer 1033, and a second interlayer insulating layer 1042, such as Figure 6A As shown. A second active layer 1012 is located on the first interlayer insulating layer 1041, and the second active layer 1012 includes a semiconductor pattern located in the display area AA. A second metal layer 1032 may include a first gate corresponding to the semiconductor pattern. A third insulating layer 1023 is located on the second active layer 1012, and a third metal layer 1033 is located on the third insulating layer 1023, and the third metal layer 1033 includes a second gate corresponding to the semiconductor pattern. A second interlayer insulating layer 1042 is located on the third metal layer 1033, and a first source / drain layer 1051 is located on the second interlayer insulating layer 1042, and the first source / drain layer 1051 may include electrodes connected to the semiconductor pattern.

[0084] The second active layer 1012 may include an oxide semiconductor material. Oxide semiconductor materials include indium gallium zinc oxide, indium zinc oxide, and other materials.

[0085] Optionally, the pixel driving circuit may further include an oxide transistor, which may include a semiconductor pattern, a first gate and a second gate corresponding to the semiconductor pattern, and an electrode in the first source / drain layer 1051 connected to the semiconductor pattern.

[0086] Please continue reading. Figures 6A-6B The display panel may also have a connection area DA2 located between the display area AA and the bonding area DA1. The display panel also includes at least one barrier 400 and a third support post 303. The barrier 400 is located on the substrate 100 and in the connection area DA2. The third support post 303 is located on the side of the at least one barrier 400 away from the substrate 100.

[0087] Wherein, along the thickness direction Dr1 of the display panel, the distance between the surface of the third support column 303 away from the substrate 100 and the substrate 100 is less than or equal to the distance L1 between the surface of the first support column 301 away from the substrate 100 and the substrate 100.

[0088] By setting up a connection area DA2 and providing a baffle 400 and a third support column 303 in the connection area DA2, the baffle 400 can be used to block the flow of the organic encapsulation layer in the encapsulation layer 108, thereby reducing the probability of overflow problems in the organic encapsulation layer in the encapsulation layer 108.

[0089] Optionally, along the thickness direction of the display panel, the thickness H3 of the third support post 303 is greater than or equal to the thickness H1 of the first support post 301, and less than or equal to the thickness H2 of the second support post 302. In some embodiments, the thickness H3 of the third support post 303 is greater than the thickness H1 of the first support post 301 and less than the thickness H2 of the second support post 302 along the thickness direction of the display panel, so as to reduce the problem of overflow in the organic encapsulation layer in the encapsulation layer 108, while saving the material usage of the third support post 303 and reducing costs.

[0090] Optionally, the surface of the third support pillar 303 away from the substrate 100 is flush with the surface of the first support pillar 301 away from the substrate 100. This reduces the problem of overflow in the organic encapsulation layer in the encapsulation layer 108, while the third support pillar 303, the first support pillar 301 and the second support pillar 302 together form a support for the fine metal mask, reducing the probability of the fine metal mask tilting.

[0091] In some embodiments, the first support post 301 is used to support the mask of the fine metal mask, and the second support post 302 and the third support post 303 are used to support the mask frame of the fine metal mask, so as to provide a more stable support force for the mask frame through the second support post 302 and the third support post 303, reduce the probability of the mask frame squeezing the mask, and the third support post 303 can also be used to reduce the probability of overflow problems in the organic encapsulation layer in the encapsulation layer 108.

[0092] Optionally, the connection area DA2 may be provided with multiple baffles 400, with adjacent baffles 400 spaced apart, so as to use the gap between the two baffles 400 to provide a space for the overflowing organic encapsulation layer, further reducing the risk of the organic encapsulation layer overflowing into the bonding area DA1.

[0093] Optionally, along the direction Dr2 perpendicular to the thickness direction of the display panel, the distance between the barrier wall of the third support column 303 and the display area AA can be less than the distance between the barrier wall without the third support column 303 and the bonding area DA1. This is to reduce the area affected by the overflow of the organic encapsulation layer by utilizing the barrier wall 400 and the third support column 303, so that the distance between the edge of the organic encapsulation layer and the edge of the display area AA is smaller, thereby reducing the probability of moisture and other factors entering the display panel from the organic encapsulation layer and affecting the display effect of the display panel.

[0094] Optionally, the connection area DA2 may also include a trace made of at least one of the first source-drain layer 1051, the second source-drain layer 1052 and the third source-drain layer 1053 to connect the pixel driving circuit or light-emitting device of the display area AA to the connection electrode or connection trace of the bonding area DA1, so as to realize signal transmission between the display area AA and the bonding area DA1.

[0095] It should be understood that, Figures 6A-6B This is merely an illustrative description of an embodiment of this application and is not intended to limit the scope of this application. The display panel may also include scan lines, data lines, and other portions not shown.

[0096] like Figures 7A to 7C This is a flowchart illustrating the fabrication process of a display panel according to an exemplary embodiment of this application. This application also provides a method for fabricating a display panel, comprising:

[0097] Provide substrate 100;

[0098] A pixel definition layer 200, a first support pillar 301, and a second support pillar 302 are fabricated on a substrate 100.

[0099] The pixel definition layer 200 includes a first pixel definition portion 201 located in the display area AA of the display panel and a second pixel definition portion 202 located in the bonding area DA1 of the display panel. The first pixel definition portion 201 has a first surface on the side away from the substrate 100, and the second pixel definition portion 202 has a second surface on the side away from the substrate 100. Along the thickness direction of the display panel, the distance L1 between the first surface and the substrate 100 is greater than the distance L2 between the second surface and the substrate 100. A first support post 301 is located on the first pixel definition portion 201, and a second support post 302 is located on the second pixel definition portion 202. The thickness H1 of the first support post 301 is less than the thickness H2 of the second support post 302, and the surface of the first support post 301 on the side away from the substrate 100 and the surface of the second support post 302 on the side away from the substrate 100 are flush. This reduces the likelihood of the fine metal mask tilting when it is placed on the first support post 301 and the second support post 302, thus mitigating the problem of black spots or dots appearing on the display due to damage to the support post caused by the fine metal mask tilting.

[0100] Optionally, along the thickness direction of the display panel, the thickness H1 of the first support post 301 can be greater than or equal to 0.5 micrometers and less than or equal to 2.5 micrometers. For example, the thickness H1 of the first support post 301 can be equal to 0.5 micrometers, 0.8 micrometers, 1 micrometer, 1.2 micrometers, 1.5 micrometers, 1.8 micrometers, 2 micrometers, 2.2 micrometers, or 2.5 micrometers.

[0101] Optionally, along the thickness direction of the display panel, the difference between the thickness H1 of the first support pillar 301 and the thickness H2 of the second support pillar 302 can be greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer. For example, the difference between the thickness H2 of the first support pillar 301 and the second support pillar 302 can be equal to 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, or 1 micrometer.

[0102] Optionally, the first support column 301 and the second support column 302 are made of the same material, which can allow the first support column 301 and the second support column 302 to be manufactured simultaneously, thereby saving process steps and improving manufacturing efficiency.

[0103] In some embodiments, prior to the step of fabricating the pixel definition layer 200, the first support pillar 301, and the second support pillar 302 on the substrate 100, the method for fabricating the display panel may further include:

[0104] A first active layer 1011 is prepared on the substrate 100, and the first active layer 1011 is patterned to obtain an active pattern located in the display area AA.

[0105] A first insulating layer 1021 is prepared on the first active layer 1011;

[0106] A first metal layer 1031 is prepared on the first insulating layer 1021 and the first metal layer 1031 is patterned to obtain a first electrode pattern located in the display area AA; wherein, the first electrode pattern includes a gate corresponding to the active area of ​​the active pattern.

[0107] A first interlayer insulating layer 1041 is formed on the first metal layer 1031, and vias are formed in the first interlayer insulating layer 1041 and the first insulating layer 1021 to expose the doped regions of the active pattern.

[0108] A first source / drain layer 1051 is prepared on the first interlayer insulating layer 1041, and the first source / drain layer 1051 is patterned to obtain a first connection portion located in the display area AA and electrically connected to the active pattern, and a second connection portion located in the bonding area DA1.

[0109] A first planarization layer 1061 is prepared on the first source / drain layer 1051, and a via is prepared in the first planarization layer 1061 to expose at least one of the first sub-connection portion and the second sub-connection portion included in the first connection portion;

[0110] An anode layer 1071 is prepared on a first planarization layer 1061 and patterned to obtain a plurality of anode patterns located in the display area AA; wherein at least one anode pattern is connected to a corresponding first sub-connection portion or second sub-connection portion; a pixel definition layer 200 is located on the anode layer 1071 and the pixel definition layer 200 has an opening that exposes at least a portion of the anode pattern.

[0111] In some embodiments, the method for manufacturing the display panel may further include:

[0112] A second insulating layer 1022 is prepared on the first metal layer 1031;

[0113] A second metal layer 1032 is prepared on the second insulating layer 1022 and the second metal layer 1032 is patterned to obtain a second electrode pattern located in the display area AA; wherein the first electrode pattern and the second electrode pattern can be used to form two plates of a capacitor in a pixel driving circuit, and the first interlayer insulating layer 1041 is located on the second metal layer 1032.

[0114] In some embodiments, the method for manufacturing the display panel may further include:

[0115] A second source / drain layer 1052 is prepared on the first planarization layer 1061, and the second source / drain layer 1052 is patterned to obtain a third connection portion located in the display area AA and electrically connected to the first connection portion, and a fourth connection portion located in the bonding area DA1.

[0116] A second planarization layer 1062 is prepared on the second source / drain layer 1052, and vias are prepared in the second planarization layer 1062 to expose the third connection portion;

[0117] A third source / drain layer 1053 is prepared on the second planarization layer 1062, and the third source / drain layer 1053 is patterned to obtain a fifth connection portion located in the display area AA and electrically connected to the third connection portion.

[0118] A third planarization layer 1063 is prepared on the third source / drain layer 1053, and vias are prepared in the first planarization layer 1061 to the third planarization layer 1063 to expose the fifth connection portion; wherein, the anode layer 1071 is located on the third planarization layer 1063, and the anode pattern can be connected to the fifth connection portion.

[0119] In some embodiments, the method for manufacturing the display panel may further include:

[0120] The second metal layer 1032 is patterned to obtain the first gate located in the display area AA;

[0121] A second active layer 1012 is prepared on the first interlayer insulating layer 1041, and the second active layer 1012 is patterned to obtain a semiconductor pattern located in the display area AA.

[0122] A third insulating layer 1023 is prepared on the second active layer 1012;

[0123] A third metal layer 1033 is prepared on the third insulating layer 1023, and the third metal layer 1033 is patterned to obtain a second gate corresponding to the semiconductor pattern.

[0124] A second interlayer insulating layer 1042 is prepared on the third metal layer 1033, and vias exposing semiconductor patterns are prepared in the second interlayer insulating layer 1042 and the third insulating layer 1023.

[0125] A first source / drain layer 1051 is formed on the second interlayer insulating layer 1042, wherein the first source / drain layer 1051 includes electrodes connected to a semiconductor pattern.

[0126] In some embodiments, the pixel definition layer 200 and the first support pillar 301 and the second support pillar 302 can be fabricated separately. Figures 8A-8B This is a schematic diagram showing the structure of the mask area and support pillar relative to each other in an exemplary embodiment of this application. Please continue reading. Figure 7B and Figure 8A The steps of fabricating a pixel definition layer 200, a first support pillar 301, and a second support pillar 302 on the substrate 100 include:

[0127] A pixel definition layer 200 is prepared on the substrate 100, and a first pixel definition portion 201 and a second pixel definition portion 202 are obtained.

[0128] A photoresist layer is fabricated on the pixel definition layer 200;

[0129] The first portion of the photoresist layer forming the first support pillar 301 is exposed using the first mask area F1 of the semi-transparent mask; the second portion of the photoresist layer forming the second support pillar 302 is exposed using the second mask area F2 of the semi-transparent mask; and the third portion of the photoresist layer adjacent to the first and second portions is exposed using the third mask area F3 of the semi-transparent mask. The transmittance of the first mask area F1 is greater than that of the second mask area F2 and less than that of the third mask area F3.

[0130] The third part of the photoresist layer is removed, and the first part of the photoresist layer is partially removed, so that the first support post 301 is obtained corresponding to the first part, and the second support post 302 is obtained corresponding to the second part.

[0131] The step of preparing a pixel definition layer 200 on the substrate 100 and obtaining a first pixel definition portion 201 and a second pixel definition portion 202 may further include: preparing a pixel definition layer 200 on the substrate 100 and forming an opening in the pixel definition layer 200 to expose an anode pattern; wherein the first pixel definition portion 201 may be disposed around the opening.

[0132] Optionally, the transmittance of the first mask region F1 can be greater than 0% and less than 100%, the transmittance of the second mask region F2 is 0%, and the transmittance of the third mask region F3 is 100%, so that the first support pillar 301 and the second support pillar 302 can have different thicknesses. Wherein, a transmittance of 0% is considered opaque, and a transmittance of 100% is considered transparent.

[0133] Optionally, when the display panel has a connection area DA2 located between the display area AA and the bonding area DA1, the barrier 400 located in the connection area DA2 can be prepared simultaneously with each film layer located in the display area AA to save process steps and improve production efficiency.

[0134] In some embodiments, the method for fabricating a display panel includes: fabricating a pixel definition layer 200 on a substrate 100, and forming grooves in the portion of the pixel definition layer 200 and the third planarization layer 1063 corresponding to the connection area DA2, to obtain a plurality of spaced-apart barriers 400.

[0135] Optionally, the third support column 303 located in the connection area DA2 can be manufactured simultaneously with the first support column 301 and the second support column 302 to save process steps and simplify process steps.

[0136] In some embodiments, the method for manufacturing the display panel further includes:

[0137] The fourth mask region F4 of the semi-transparent mask is used to expose the fourth portion of the photoresist layer corresponding to the barrier 400 located in the connection region DA2, as follows: Figure 8A As shown; wherein, the transmittance of the fourth mask region F4 is greater than or equal to the transmittance of the second mask region F2, and less than or equal to the transmittance of the first mask region F1;

[0138] The fourth part of the photoresist layer is partially removed to obtain the third support pillar 303 corresponding to the fourth part; wherein, along the thickness direction Dr1 of the display panel, the thickness H3 of the third support pillar 303 is greater than or equal to the thickness H1 of the first support pillar 301 and less than or equal to the thickness H2 of the second support pillar 302.

[0139] By making the transmittance of the fourth mask region F4 less than or equal to the transmittance of the first mask region F1, the thickness H3 of the third support pillar 303 can be made greater than or equal to the thickness H1 of the first support pillar 301. By making the transmittance of the fourth mask region F4 greater than or equal to the transmittance of the second mask region F2, the thickness H3 of the third support pillar 303 can be made less than or equal to the thickness H2 of the second support pillar 302.

[0140] Optionally, the pixel definition layer 200 and the first support pillar 301 and the second support pillar 302 can be made of the same material. The pixel definition layer 200 can also be fabricated simultaneously with the first support pillar 301 and the second support pillar 302 to save fabrication steps in the display panel and simplify the manufacturing process.

[0141] Please continue reading. Figure 7C and Figure 8B The first support pillar 301, the second support pillar 302, and the pixel definition layer 200 are made of the same material. The steps for fabricating the pixel definition layer 200, the first support pillar 301, and the second support pillar 302 on the substrate 100 include:

[0142] A photoresist layer is prepared on substrate 100;

[0143] The first portion of the photoresist layer forming the first support pillar 301 is exposed using the first mask area M1 of the semi-transparent mask; the second portion of the photoresist layer forming the second support pillar 302 is exposed using the second mask area M2 of the semi-transparent mask; the third portion of the photoresist layer adjacent to the first portion is exposed using the third mask area M3 of the semi-transparent mask; the fourth portion of the photoresist layer adjacent to the second portion is exposed using the fourth mask area M4 of the semi-transparent mask; and the fifth portion of the photoresist layer adjacent to the third portion is exposed using the fifth mask area M5 of the semi-transparent mask. The transmittance of the first mask area M1 is greater than that of the second mask area M2 and less than that of the third mask area M3; the transmittance of the fourth mask area M4 is equal to that of the third mask area M3; and the transmittance of the fifth mask area M5 is greater than that of the fourth mask area M4.

[0144] The fifth portion of the photoresist layer is removed, and the first, third, and fourth portions of the photoresist layer are partially removed to obtain a first support pillar 301 corresponding to the portion of the first portion from the surface of the first portion away from the substrate 100 to the portion of the third portion away from the substrate 100. A second support pillar 302 is obtained corresponding to the portion of the second portion from the surface of the second portion away from the substrate 100 to the portion of the fourth portion away from the substrate 100. A first pixel definition portion 201 is obtained corresponding to the portion of the first portion located below the first support pillar 301 and the third portion. A second pixel definition portion 202 is obtained corresponding to the portion of the second portion located at the second support pillar 302 and the fourth portion.

[0145] Optionally, the transmittance of the second mask region M2 is 0%, the transmittance of the third mask region M3 and the fourth mask region can be greater than 15% and less than 35%, respectively, and the transmittance of the fifth mask region can be 100%.

[0146] Optionally, when the pixel definition layer 200 is fabricated simultaneously with the first support pillar 301 and the second support pillar 302, the thickness of the resulting pixel definition layer 200 can be greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers. For example, the thickness of the pixel definition layer 200 can be 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 1 micrometer, 1.2 micrometers, 1.4 micrometers, 1.5 micrometers, 1.8 micrometers, or 2 micrometers.

[0147] In some embodiments, the third support post 303 of the connection area DA2 can also be prepared simultaneously with the first support post 301 and the second support post 302 to save process steps.

[0148] The manufacturing methods for display panels also include:

[0149] The sixth portion of the photoresist layer on at least one barrier 400 located in the connection area DA2 is exposed using the sixth mask area M6 of the semi-transparent mask; wherein the transmittance of the sixth mask area M6 is greater than or equal to the transmittance of the second mask area M2, and less than or equal to the transmittance of the first mask area M1.

[0150] The sixth part of the photoresist layer is partially removed to obtain the third support pillar 303 corresponding to the sixth part; wherein, along the thickness direction of the display panel, the thickness H3 of the third support pillar 303 is greater than the thickness H1 of the first support pillar 301 and less than the thickness H2 of the second support pillar 302.

[0151] In some embodiments, the method for manufacturing the display panel further includes:

[0152] The seventh portion of the photoresist layer forming the barrier 400 is exposed using the seventh mask region M7 of the semi-transparent mask, and the eighth portion of the photoresist layer adjacent to the seventh portion is exposed using the eighth mask region M8 of the semi-transparent mask; wherein, the transmittance of the seventh mask region M7 is less than or equal to the transmittance of the fourth mask region M4, and greater than the transmittance of the sixth mask region M6; the transmittance of the eighth mask region M8 is less than or equal to the transmittance of the fifth mask region M5, and greater than the transmittance of the seventh mask region M7;

[0153] Remove the eighth part of the photoresist layer and partially remove the seventh part of the photoresist layer to obtain the barrier 400 corresponding to the seventh part.

[0154] To enable the display panel to support display functions, the manufacturing method of the display panel also includes:

[0155] A fine metal mask is placed on a plurality of support pillars, wherein the plurality of support pillars include a first support pillar 301 and a second support pillar 302. In some embodiments, the support pillars may further include a third support pillar 303.

[0156] The luminescent material is prepared through the opening of the pixel definition layer 200 through the opening of the fine metal mask to obtain the luminescent layer 1072.

[0157] After the light-emitting layer 1072 is fabricated, the fine metal mask is removed, and the cathode layer 1073 is fabricated on the light-emitting layer 1072.

[0158] An encapsulation layer 108 is prepared on the cathode layer 1073.

[0159] In some embodiments, the step of fabricating an encapsulation layer 108 on the cathode layer 1073 includes: fabricating a first inorganic encapsulation layer 1081 on the cathode layer 1073; fabricating a first organic encapsulation layer 1082 on the first inorganic encapsulation layer 1081; and fabricating a second inorganic encapsulation layer 1083 on the first organic encapsulation layer 1082. The overflow of the first organic encapsulation layer 1082 can be improved using the baffle 400 and the third support post 303.

[0160] like Figure 9 This is a comparative structural diagram of a display panel provided in an exemplary embodiment of this application. In some embodiments, when fabricating the first support pillar 301 and the second support pillar 302 of the display panel, the mask areas corresponding to the portions of the photoresist layer that form the first support pillar 301 and the second support pillar 302 have the same transmittance, resulting in the first support pillar 301 and the second support pillar 302 having the same thickness. However, because the first surface is higher than the second surface, the surface of the first support pillar 301 away from the substrate and the surface of the second support pillar 302 away from the substrate are located in different planes. During the process of evaporating the luminescent material to obtain the luminescent layer, when the fine metal mask is attached to the surface of the support pillar, the support pillar with higher height will become a stress concentration point, which is easily scratched by the fine metal mask. The scratched location is prone to leaving particulate foreign matter, which will cause the encapsulation layer to be punctured in the subsequent fabrication, resulting in encapsulation failure and the formation of display black spots or black dots, causing yield damage.

[0161] In this application, when fabricating the first support pillar 301 and the second support pillar 302 of the display panel, the mask areas of the photoresist layer corresponding to the formation of the first support pillar 301 and the second support pillar 302 have different light transmittances, resulting in the first support pillar 301 and the second support pillar 302 having different thicknesses. The top surfaces of the first support pillar 301 and the second support pillar 302 are flush, which can compensate for the deficiency that the first surface and the second surface are not located on the same plane. During the process of evaporating the luminescent material to obtain the luminescent layer 1072, using the first support pillar 301 and the second support pillar 302 to support the fine metal mask allows the fine metal mask to be located on a relatively flat surface, which can effectively reduce the risk of the support pillars being scratched by the metal mask, reduce the incidence of display black spots or black dots on the display panel, and reduce yield loss.

[0162] It should be understood that, Figures 6A-6B and Figures 8A-8BOnly two first support pillars 301 and one second support pillar 302 are shown for ease of understanding of this application. In practical applications, the display panel may include multiple first support pillars 301 and multiple second support pillars 302. The thickness H1 of the multiple first support pillars 301 may be the same or different, and the thickness H2 of the multiple second support pillars 302 may be the same or different. Similarly, the display panel may also include multiple third support pillars 303, and the thickness H3 of the multiple third support pillars 303 may be different.

[0163] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0164] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a particular embodiment can be referred to in the relevant descriptions of other embodiments. The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0165] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a bonding area located on one side of the display area, the display panel comprising: A substrate is located in the display area and the bonding area; A pixel definition layer, located on the substrate, includes a first pixel definition portion located in the display area and a second pixel definition portion located in the bonding area; A first support post is located on the first pixel definition portion; and The second support column is located on the second pixel definition part; The first pixel defining portion has a first surface on the side away from the substrate, and the second pixel defining portion has a second surface on the side away from the substrate; along the thickness direction of the display panel, the distance between the first surface and the substrate is greater than the distance between the second surface and the substrate; the thickness of the first support post is less than the thickness of the second support post, and the surface of the first support post on the side away from the substrate and the surface of the second support post on the side away from the substrate are flush.

2. The display panel according to claim 1, characterized in that, Along the thickness direction of the display panel, the difference between the thickness of the second support column and the thickness of the first support column is equal to the distance between the first surface and the second surface.

3. The display panel according to claim 2, characterized in that, Along the thickness direction of the display panel, the difference between the thickness of the second support column and the thickness of the first support column is greater than or equal to 0.2 micrometers and less than or equal to 1 micrometer.

4. The display panel according to claim 1, characterized in that, The display panel further includes a connection area located between the display area and the bonding area, and the display panel also includes: At least one retaining wall is located on the substrate and in the connection area; The third support column is located on the side of at least one of the retaining walls away from the substrate; Wherein, along the thickness direction of the display panel, the distance between the surface of the third support post on the side away from the substrate and the substrate is less than the distance between the surface of the first support post on the side away from the substrate and the substrate.

5. The display panel according to claim 4, characterized in that, Along the thickness direction of the display panel, the thickness of the third support column is greater than or equal to the thickness of the first support column, and less than or equal to the thickness of the second support column.

6. The display panel according to claim 4, characterized in that, The connection area of ​​the display panel is provided with multiple baffles, and adjacent baffles are spaced apart.

7. The display panel according to claim 1, characterized in that, At least two of the first support pillar, the second support pillar, and the pixel definition layer are made of the same material.

8. A method for manufacturing a display panel, characterized in that, include: Provide substrate; A pixel definition layer, a first support pillar, and a second support pillar are fabricated on the substrate. The pixel definition layer includes a first pixel definition portion located in the display area of ​​the display panel and a second pixel definition portion located in the bonding area of ​​the display panel; the first pixel definition portion has a first surface on the side away from the substrate, and the second pixel definition portion has a second surface on the side away from the substrate; along the thickness direction of the display panel, the distance between the first surface and the substrate is greater than the distance between the second surface and the substrate. The first support post is located on the first pixel definition portion, and the second support post is located on the second pixel definition portion. The thickness of the first support post is less than the thickness of the second support post, and the surface of the first support post away from the substrate is flush with the surface of the second support post away from the substrate.

9. The method for manufacturing a display panel according to claim 8, characterized in that, The first support pillar is made of the same material as the second support pillar; the step of fabricating the pixel definition layer, the first support pillar, and the second support pillar on the substrate includes: The pixel definition layer is fabricated on the substrate to obtain the first pixel definition portion and the second pixel definition portion; A photoresist layer is fabricated on the pixel definition layer; The first portion of the photoresist layer corresponding to the first support pillar is exposed using a first mask area of ​​a semi-transparent mask; the second portion of the photoresist layer corresponding to the second support pillar is exposed using a second mask area of ​​the semi-transparent mask; and the third portion of the photoresist layer adjacent to the first and second portions is exposed using a third mask area of ​​the semi-transparent mask. The transmittance of the first mask area is greater than that of the second mask area and less than that of the third mask area. Remove the third portion of the photoresist layer and partially remove the first portion of the photoresist layer to obtain the first support pillar corresponding to the first portion and the second support pillar corresponding to the second portion.

10. The method for manufacturing a display panel according to claim 9, characterized in that, The display panel further includes a connection area located between the display area and the bonding area; the manufacturing method further includes: The fourth portion of the photoresist layer located on the barrier wall of the connection area is exposed using the fourth mask area of ​​the semi-transparent mask; wherein the transmittance of the fourth mask area is greater than or equal to the transmittance of the second mask area, and less than or equal to the transmittance of the first mask area. The fourth portion of the photoresist layer is partially removed to obtain a third support pillar corresponding to the fourth portion; wherein, along the thickness direction of the display panel, the thickness of the third support pillar is greater than or equal to the thickness of the first support pillar and less than or equal to the thickness of the second support pillar.

11. The method for manufacturing a display panel according to claim 8, characterized in that, The first support pillar, the second support pillar, and the pixel definition layer are made of the same material; The step of fabricating a pixel definition layer, a first support pillar, and a second support pillar on the substrate includes: A photoresist layer is fabricated on the substrate; The first portion of the photoresist layer corresponding to the first support pillar is exposed using a first mask area of ​​a semi-transparent mask; the second portion of the photoresist layer corresponding to the second support pillar is exposed using a second mask area of ​​the semi-transparent mask; the third portion of the photoresist layer adjacent to the first portion is exposed using a third mask area of ​​the semi-transparent mask; the fourth portion of the photoresist layer adjacent to the second portion is exposed using a fourth mask area of ​​the semi-transparent mask; and the fifth portion of the photoresist layer adjacent to the third portion is exposed using a fifth mask area of ​​the semi-transparent mask. The transmittance of the first mask area is greater than that of the second mask area and less than that of the third mask area; the transmittance of the fourth mask area is equal to that of the third mask area; and the transmittance of the fifth mask area is greater than that of the fourth mask area. The fifth portion of the photoresist layer is removed, and the first, third, and fourth portions of the photoresist layer are partially removed to obtain the first support pillar corresponding to the portion of the first portion away from the substrate to the portion of the third portion away from the substrate. The second support pillar is obtained corresponding to the portion of the second portion away from the substrate to the portion of the fourth portion away from the substrate. The first pixel definition portion is obtained corresponding to the portion of the first portion located below the first support pillar and the third portion. The second pixel definition portion is obtained corresponding to the portion of the second portion located at the second support pillar and the fourth portion.

12. The method for manufacturing a display panel according to claim 11, characterized in that, The display panel further includes a connection area located between the display area and the bonding area; the manufacturing method further includes: The sixth portion of the photoresist layer located on at least one barrier in the connection area is exposed using the sixth mask area of ​​a semi-transparent mask; wherein the transmittance of the sixth mask area is greater than or equal to the transmittance of the second mask area, and less than or equal to the transmittance of the first mask area. The sixth portion of the photoresist layer is partially removed to obtain a third support pillar corresponding to the sixth portion; wherein, along the thickness direction of the display panel, the thickness of the third support pillar is greater than or equal to the thickness of the first support pillar, or the thickness of the third support pillar is less than or equal to the thickness of the second support pillar.

Images