Display device and driving method thereof

Abstract

The display device includes a pixel part including a plurality of pixels, in which one pixel among the plurality of pixels is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, and a fifth scan line, and at least one frame period includes a first period during which the pixel is connected to the first scan line, the second scan line, the third scan line, the fourth scan line, and the fifth scan line. When a scan signal of an on level is applied to the third scan line, a scan signal of an off level is applied to the first scan line, the second scan line, the fourth scan line, and the fifth scan line.

Description

Technical Field

[0001] This invention relates to a display device and its driving method. Background Technology

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become increasingly apparent. Due to the importance of display devices, the use of various display devices (such as liquid crystal displays and organic light-emitting diode displays) has increased.

[0003] Display devices can use pixel components comprising multiple pixels to display images. The pixel circuitry of each pixel can, depending on its structure, cause unnecessary power consumption. Summary of the Invention

[0004] Technical issues

[0005] The technical problem to be solved is to provide a display device and its driving method that can minimize power consumption.

[0006] Technical solution

[0007] Embodiments of this disclosure may provide a display device including a pixel component comprising a plurality of pixels. Each pixel may include: a first transistor including a first gate electrode connected to a first node and a second gate electrode connected to a second node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the first node; a third transistor including a gate electrode connected to a second scan line, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node; a fourth transistor including a gate electrode connected to a third scan line, a first electrode configured to receive an initialization voltage, and a second electrode connected to the third node; a fifth transistor including a gate electrode connected to a fourth scan line, a first electrode connected to a first power line, and a second electrode connected to the first electrode of the first transistor; a sixth transistor including a gate electrode connected to a fifth scan line, a first electrode connected to the second node, and a second electrode connected to the third node; and a first capacitor connecting the first node to the second node. At least one frame period may include a first period during which, when a scan signal at an on level is applied to the third scan line, a scan signal at an off level is applied to the first scan line, the second scan line, the fourth scan line, and the fifth scan line.

[0008] After the first cycle, a scan signal with a conduction level can be applied to the fourth scan line, and a scan signal with a conduction level can be applied to the fifth scan line in sequence.

[0009] The pixel component can display an image at a first frequency in a first mode and at a second frequency lower than the first frequency in a second mode. In the first mode, each frame cycle may include a first scan cycle in which data voltage is written to the pixel and a second scan cycle in which data voltage is not written to the pixel. In the second mode, each frame cycle may include a first scan cycle and a plurality of second scan cycles.

[0010] The first scan cycle may include a first cycle. The first scan cycle may also include a second cycle, during which a cutoff level scan signal is applied to the first scan line and the fourth scan line, and a turn-on level scan signal is applied to the second scan line, the third scan line, and the fifth scan line.

[0011] The first scan cycle may also include a third cycle, during which a cutoff level scan signal is applied to the first scan line, the third scan line, and the fifth scan line, and a turn-on level scan signal is applied to the second scan line and the fourth scan line.

[0012] The first scan cycle may also include a fourth cycle, during which a scan signal at an on level is applied to the first scan line, and a scan signal at an off level is applied to the second, third, fourth, and fifth scan lines.

[0013] The second, third, fourth, and first cycles can be positioned sequentially within the first scan cycle.

[0014] The second scan cycle may include a fifth cycle, during which, when a scan signal at an on level is applied to the third scan line, a scan signal at an off level is applied to the first scan line, the second scan line, the fourth scan line, and the fifth scan line.

[0015] After the fifth cycle, a scan signal with a conduction level can be applied to the fourth scan line, and a scan signal with a conduction level can be applied to the fifth scan line in sequence.

[0016] The second scan cycle may also include a sixth cycle, during which, when a scan signal at an on level is applied to the third scan line, a scan signal at an off level is applied to the first scan line, the second scan line, the fourth scan line, and the fifth scan line.

[0017] The sixth and fifth cycles can be positioned sequentially in the second scan cycle.

[0018] Before the sixth cycle, a cutoff level scan signal can be applied to the fourth and fifth scan lines.

[0019] Embodiments of this disclosure may provide a method for driving a display device, comprising: displaying an image at a first frequency in a first mode; and displaying the image at a second frequency less than the first frequency in a second mode. In the first mode, each frame cycle may include a first scan cycle in which data voltage is written to a pixel and a second scan cycle in which data voltage is not written to a pixel. In the second mode, each frame cycle may include a first scan cycle and a plurality of second scan cycles. In the first scan cycle, the method for driving the display device may sequentially include: connecting a first terminal of a first capacitor included in a pixel to the same initialization voltage source as the anode of a light-emitting element; increasing the voltage at the first terminal of the first capacitor to correspond to a threshold voltage of a driving transistor included in the pixel; applying a data voltage to a second terminal of the first capacitor; and connecting only the anode of the light-emitting element to the initialization voltage source while keeping the first terminal of the first capacitor disconnected from the initialization voltage source.

[0020] In the first scan cycle, the method of driving the display device may further include: connecting the driving transistor to a first power line; and connecting the driving transistor to the anode of the light-emitting element.

[0021] The duration for which the first terminal of the first capacitor and the anode of the light-emitting element are connected to the same initialization voltage source can be longer than the duration for which only the anode of the light-emitting element is connected to the initialization voltage source.

[0022] The duration for which the voltage at the first terminal of the first capacitor is increased can be longer than the duration for which the first terminal of the first capacitor and the anode of the light-emitting element are connected to the same initial voltage source.

[0023] The duration for which the data voltage is applied to the second terminal of the first capacitor can be shorter than the duration for which only the anode of the light-emitting element is connected to the initialization voltage source.

[0024] During the second scan cycle, the method of driving the display device may include: a first operation of connecting only the anode of the light-emitting element to the initialization voltage source while keeping the first terminal of the first capacitor disconnected from the initialization voltage source; and a second operation of connecting only the anode of the light-emitting element to the initialization voltage source while keeping the first terminal of the first capacitor disconnected from the initialization voltage source. The duration of the first operation may be longer than the duration of the second operation.

[0025] In the second scanning cycle, the method of driving the display device may further include: after the second operation, connecting the driving transistor to the first power line; and connecting the driving transistor to the anode of the light-emitting element.

[0026] In the second scan cycle, the method of driving the display device may sequentially include: simultaneously disconnecting the connection between the first power line and the driving transistor and the connection between the driving transistor and the anode of the light-emitting element; connecting only the anode of the light-emitting element to the initialization voltage source while keeping the first terminal of the first capacitor disconnected from the initialization voltage source; connecting the driving transistor to the first power line; and connecting the driving transistor to the anode of the light-emitting element.

[0027] Technical effect

[0028] The display device and driving method of the present invention can minimize power consumption. Attached Figure Description

[0029] Figure 1 This is a diagram used to describe a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is a diagram used to describe pixels according to embodiments of the present disclosure.

[0031] Figure 3 This is a diagram used to describe a first mode of an embodiment according to the present disclosure.

[0032] Figure 4 This is a diagram used to describe a second mode of an embodiment according to the present disclosure.

[0033] Figure 5 This is a diagram used to describe the first scan cycle according to an embodiment of the present disclosure.

[0034] Figure 6 This is a diagram used to describe the second scan cycle according to an embodiment of the present disclosure.

[0035] Figure 7 This is a diagram used to describe a second scan cycle according to another embodiment of the present disclosure.

[0036] Figures 8 to 15 This is a cross-sectional view showing the structure of a light-emitting element according to an embodiment of the present disclosure. Detailed Implementation

[0037] In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the invention. This disclosure can be implemented in various forms and is not limited to the embodiments described herein.

[0038] In the accompanying drawings, parts unrelated to this disclosure will be omitted for clarity. Reference should be made to the drawings, in which similar reference numerals are used in different drawings to denote similar parts. Therefore, the aforementioned reference numerals can be used in other drawings.

[0039] For reference, and for illustrative purposes, the dimensions of each component and the thickness of the lines illustrating the components are presented arbitrarily, and this disclosure is not limited to what is shown in the drawings. In the drawings, the thickness of components may be exaggerated to clearly depict multiple layers and regions.

[0040] Furthermore, the expression "identical" can mean "substantially identical." In other words, the expression "identical" can include a range tolerable to those skilled in the art. Other expressions may also omit the word "substantially."

[0041] Figure 1 This is a diagram used to describe a display device 10 according to an embodiment of the present disclosure.

[0042] refer to Figure 1 The display device 10 according to embodiments of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, and a pixel component 14.

[0043] The timing controller 11 can receive grayscale signals of an image (or frame). The grayscale signals may include a first color grayscale signal, a second color grayscale signal, and a third color grayscale signal. The first color grayscale signal may be a grayscale signal used to represent a first color. The second color grayscale signal may be a grayscale signal used to represent a second color. The third color grayscale signal may be a grayscale signal used to represent a third color.

[0044] In addition, the timing controller 11 can receive control signals for the image. The control signals may include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal. The vertical synchronization signal may include multiple pulses, and each pulse indicates the end of a previous frame period and the start of a current frame period based on the timing of its occurrence. The distance between adjacent pulses of the vertical synchronization signal may correspond to one frame period. The horizontal synchronization signal may include multiple pulses, and each pulse indicates the end of a previous horizontal period and the start of a new horizontal period based on the timing of its occurrence. The distance between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period. The data enable signal may have an enable level in a specific horizontal period and a disable level in other periods. When the data enable signal has an enable level, this indicates that a color grayscale signal is provided in the corresponding horizontal period.

[0045] The timing controller 11 can provide the data driver 12 with grayscale signals that are rendered or corrected to meet the specifications of the display device 10. In addition, the timing controller 11 can provide the scan driver 13 with clock signals, scan start signals, etc.

[0046] Data driver 12 can use grayscale signals and control signals received from timing controller 11 to generate data voltages to be supplied to data lines DL1, DL2, DL3…DLj… and DLn. For example, data driver 12 can sample the grayscale signals using a clock signal and apply data voltages corresponding to the grayscale signals to data lines DL1 to DLn based on pixel rows. Here, n is an integer greater than 0. The term "pixel row" refers to pixels connected to the same scan line.

[0047] The scan driver 13 can receive clock signals, scan start signals, etc. from the timing controller 11, and generate scan signals to be provided to scan lines GWL1, GRL1, GIL1, EML1, EMBL1…GWLi, GRLi, GILi, EMLi, EMBLi…GWLm, GRLm, GILm, EMLm, and EMBLm. Here, m is an integer greater than 0. For example, the scan driver 13 may include a first sub-scan driver connected to the first scan lines GWL1…GWLi… and GWLm, a second sub-scan driver connected to the second scan lines GRL1…GRLi… and GRLm, a third sub-scan driver connected to the third scan lines GIL1…GILi… and GILm, a fourth sub-scan driver connected to the fourth scan lines EML1…EMLi… and EMLm, and a fifth sub-scan driver connected to the fifth scan lines EMBL1…EMBLi… and EMBLm.

[0048] For example, the first sub-scan driver can sequentially provide scan signals with conduction-level pulses to the first scan lines GWL1 to GWLm. For example, the first sub-scan driver can be configured as a shift register and can generate scan signals according to the control of a clock signal, such that conduction-level pulse-type scan start signals are sequentially transmitted to subsequent stage circuits. The second to fifth sub-scan drivers can also be implemented in the same way, thus omitting redundant explanations.

[0049] Pixel component 14 includes pixels. Each pixel PXij can be connected to a corresponding data line, a corresponding scan line, and a transmission line. Here, i and j can each be an integer greater than 0. Pixel PXij can represent a pixel connected to the i-th scan line and the j-th data line.

[0050] Pixel component 14 may include a first pixel configured to emit light of a first color, a second pixel configured to emit light of a second color, and a third pixel configured to emit light of a third color. The first color, second color, and third color may be different colors. For example, the first color may be one of red, green, and blue. The second color may be one of red, green, and blue other than the first color. The third color may be any of the remaining colors of red, green, and blue other than the first and second colors. Furthermore, magenta, cyan, and yellow may be used instead of red, green, and blue as the first to third colors.

[0051] Pixel component 14 can have various pixel arrangement structures, such as diamond pentiles. TM Structure, RGB stripe structure, S-stripe structure, real RGB structure, and normal Pentium TM Structure. For example, the pixels of pixel component 14 can be arranged in an RGBG matrix structure.

[0052] Figure 2 This is a diagram used to describe the pixel PXij according to an embodiment of the present disclosure.

[0053] refer to Figure 2 According to embodiments of the present disclosure, the pixel PXij includes transistors T1, T2, T3, T4, T5 and T6, a first capacitor C1, a second capacitor C2 and a light-emitting diode LD.

[0054] The circuits constructed from N-type transistors will be described below by way of example. However, those skilled in the art can design circuits constructed from P-type transistors by changing the polarity of the voltage applied to the gate terminal of each transistor. Similarly, those skilled in the art can design circuits constructed from combinations of P-type and N-type transistors. The term "P-type transistor" is a general name for a transistor in which the amount of current increases as the voltage difference between the gate and source electrodes increases in the negative direction. The term "N-type transistor" is a general name for a transistor in which the amount of current increases as the voltage difference between the gate and source electrodes increases in the positive direction. Each transistor can be configured in various forms, such as thin-film transistors (TFTs), field-effect transistors (FETs), and bipolar junction transistors (BJTs).

[0055] The following description assumes that transistors T1, T2, T3, T4, T5, and T6 are composed of N-type oxide thin-film transistors. In an embodiment, transistors T1, T2, T3, T4, T5, and T6 may be formed of P-type transistors. In an embodiment, some of transistors T1, T2, T3, T4, T5, and T6 may be formed of N-type oxide thin-film transistors, and others may be formed of P-type silicon thin-film transistors.

[0056] An oxide thin-film transistor can correspond to a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the active pattern (semiconductor layer) comprises oxide. However, this is for illustrative purposes only, and N-type transistors are not limited thereto. For example, the active pattern (or semiconductor layer) included in an N-type transistor can comprise inorganic semiconductors (e.g., amorphous silicon, polycrystalline silicon) or organic semiconductors. A silicon thin-film transistor can correspond to a low-temperature polycrystalline silicon (LTPS) thin-film transistor in which the active pattern (or semiconductor layer) comprises amorphous silicon, polycrystalline silicon, etc.

[0057] The first transistor T1 may include a first gate electrode connected to a first node N1 and a second gate electrode connected to a second node N2. The second gate electrode of the first transistor T1 may be configured to regulate the output current characteristic relative to the input voltage of the first transistor T1. For example, the first transistor T1 mainly operates in saturation. Here, if the second gate of the first transistor T1 is absent, the magnitude of the output current can vary according to the drain-source voltage even if the gate-source voltage remains the same. According to this embodiment, since the characteristics of the first transistor T1 are adjusted to be insensitive to changes in the drain-source voltage, the first transistor T1 can output substantially the same current for the same gate-source voltage. The first transistor T1 can control the drive current flowing from the first power line ELVDDL to the second power line ELVSSL. Therefore, the first transistor T1 can be referred to as a "drive transistor". The first transistor T1 may include a first electrode connected to the second electrode of the fifth transistor T5 and a second electrode connected to the second node N2.

[0058] The second transistor T2 may include a gate electrode connected to the first scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can receive the data voltage applied to the data line DLj. Therefore, the second transistor T2 can be referred to as a "data write transistor".

[0059] The third transistor T3 may include a gate electrode connected to the second scan line GRLi, a first electrode configured to receive a reference voltage VREF, and a second electrode connected to the first node N1. The reference voltage VREF can be provided from a reference voltage source. The third transistor T3 can apply the reference voltage VREF to the first node N1 to initialize the voltage of the first node N1 to the reference voltage VREF. Therefore, the third transistor T3 can be referred to as the "first initialization transistor".

[0060] The fourth transistor T4 may include a gate electrode connected to the third scan line GILi, a first electrode configured to receive an initialization voltage VINT, and a second electrode connected to the third node N3. The initialization voltage VINT can be provided from an initialization voltage source. The fourth transistor T4 can apply the initialization voltage VINT to the third node N3 to initialize the voltage of the third node N3 to the initialization voltage VINT. Therefore, the fourth transistor T4 can be referred to as the "second initialization transistor".

[0061] The fifth transistor T5 may include a gate electrode connected to the fourth scan line EMLi, a first electrode connected to the first power line ELVDDL, and a second electrode connected to the first electrode of the first transistor T1. The fifth transistor T5 can control the opening and closing of the drive current path connecting the first power line ELVDDL to the second power line ELVSSL. Therefore, the fifth transistor T5 can be referred to as the "first emitter control transistor".

[0062] The sixth transistor T6 may include a gate electrode connected to the fifth scan line EMBLi, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The sixth transistor T6 can control the opening and closing of the drive current path connecting the first power line ELVDDL to the second power line ELVSSL. Therefore, the sixth transistor T6 can be referred to as the "second emitter control transistor".

[0063] The first capacitor C1 can connect the first node N1 to or capacitively couple to the second node N2. The second capacitor C2 can connect the first power line ELVDDL to or capacitively couple to the second node N2.

[0064] The light-emitting diode (LD) may include an anode connected to the third node N3 and a cathode connected to the second power line ELVSSL. The light-emitting element (LD) may be a light-emitting diode. The light-emitting element (LD) may be formed from organic light-emitting diodes, inorganic light-emitting diodes, quantum dot / well light-emitting diodes, etc. Although only one light-emitting element (LD) is provided in each pixel in this embodiment, multiple light-emitting elements may be provided in each pixel in another embodiment. Here, multiple light-emitting elements may be connected in series, in parallel, or in a series-parallel connection. The light-emitting element (LD) of each pixel may emit light having one of a first color, a second color, and a third color.

[0065] A first electrical voltage can be applied to a first electrical line ELVDDL. A second electrical voltage can be applied to a second electrical line ELVSSL. For example, the first electrical voltage can be greater than the second electrical voltage.

[0066] Figure 3 This is a diagram used to describe a first mode of an embodiment according to the present disclosure. Figure 4 This is a diagram used to describe a second mode of an embodiment according to the present disclosure.

[0067] Display device 10 may support variable refresh rate (VRR). The term "refresh rate" refers to the frequency at which data voltage is written to pixel PXij, and may also be referred to as screen scan rate or screen refresh rate, and may represent the number of image frames played per second.

[0068] For example, pixel component 14 can display an image at a first frequency AHz in the first mode (see reference). Figure 3 And in the second mode, the image can be displayed at a second frequency BHz, which is less than the first frequency AHz (see reference). Figure 4 ).

[0069] For example, in a first mode, each frame period 1F may include a first scan period AS and a second scan period SS. For example, in a second mode, each frame period 1F may include a first scan period AS and multiple second scan periods SS. When the second frequency BHz decreases, the number of second scan periods SS included in the frame period 1F can be increased. In another example, in a third mode, each frame period 1F may include only one first scan period AS and may not include any second scan periods SS.

[0070] The first scan cycle AS can be the period during which data voltage is written to pixel PXij, and can be referred to as the address scan cycle. The first scan cycle AS can also be referred to as the data programming cycle that receives data voltage from data line DLj.

[0071] The second scan period SS can be a period during which no data voltage is written to pixel PXij, and can be referred to as the self-scan period. During the emission period of the second scan period SS, pixel PXij can emit light using the data voltage written during the first scan period AS. The length of the second scan period SS can be the same as the length of the first scan period AS.

[0072] Figure 5 This is a diagram used to describe the first scan cycle AS1 according to an embodiment of the present disclosure.

[0073] Figure 5 The first scan cycle AS1 is Figure 3 and Figure 4 An example of the first scan cycle AS. The first scan cycle AS1 can sequentially include the second cycle P2, the third cycle P3, the fourth cycle P4, and the first cycle P1. The following description is based on the pixel rows connected to the i-th scan line GWLi, GRLi, GILi, EMLI, and EMBLi.

[0074] First, at time point t1a, a cutoff level (e.g., low level) scan signal EMLs can be applied to the fourth scan line EML1. Therefore, the fifth transistor T5 is turned off, and the transmit cycle based on the data voltage written during the previous frame period is terminated.

[0075] Next, at time point t2a, a scan signal GILs with a conduction level (e.g., high level) is applied to the third scan line GILi, thereby enabling the fourth transistor T4 to conduct. Therefore, the initialization voltage VINT can be applied to the third node N3. Thus, the voltage at the opposite end of the light-emitting element LD can be initialized. Here, because the sixth transistor T6 is in the on state, the initialization voltage VINT can also be applied to the second node N2. Therefore, the voltage at the opposite end of the first transistor T1 can be initialized.

[0076] Next, at time point t3a, a scan signal GRLs with a conduction level can be applied to the second scan line GRLi, thereby allowing the third transistor T3 to conduct. Therefore, the reference voltage VREF can be applied to the first node N1. Thus, the voltage at the opposite terminals of the first capacitor C1 can be initialized.

[0077] The second cycle (P2: t3a to t4a) can be a cycle in which cutoff level scan signals GWLs and EMLs are applied to the first scan line GWLi and the fourth scan line EML, while on-level scan signals GRLs, GILs, and EMLs are applied to the second scan line GRLi, the third scan line GILi, and the fifth scan line EMBLi. During the second cycle P2, the step of connecting one end of the first capacitor C1 included in pixel PXij and the anode of the light-emitting element LD to the same initialization voltage source can be performed. For example, the step of connecting one end of the first capacitor C1 and the anode of the light-emitting element LD to the same initialization voltage source (second cycle P2) can be performed during a longer time period than the step of connecting only the anode of the light-emitting element LD to the initialization voltage source (e.g., connecting the anode of the light-emitting element LD to the initialization voltage source while the sixth transistor T6 is off) (first cycle P1).

[0078] Next, at time point t5a, the on-level scan signal EMLs can be applied to the fourth scan line EMLi, thereby allowing the fifth transistor T5 to turn on. The third cycle (P3: t5a to t6a) can be a cycle in which the off-level scan signals GWLs, GILs, and EMBLs are applied to the first scan line GWLi, the third scan line GILi, and the fifth scan line EMBLi, while the on-level scan signals GRLs and EMLs are applied to the second scan line GRLi and the fourth scan line EMLi.

[0079] During the third cycle P3, the voltage at one end of the first capacitor C1 can be increased to correspond to the threshold voltage of the first transistor T1. As described above, the voltage at the opposite end of the first capacitor C1 has been initialized, and at time point t5a, the first capacitor C1 can be maintained in a state where the voltage difference between the gate electrode (first node N1) and the source electrode (second node N2) of the first transistor T1 is higher than the threshold voltage of the first transistor T1. Therefore, at time point t5a, the first transistor T1 can remain on. Here, the voltage of the second node N2 can gradually increase as current is supplied from the first power line ELVDDL through the on-state fifth transistor T5 and the first transistor T1. If the voltage difference between the gate electrode (first node N1) and the source electrode (second node N2) of the first transistor T1 reaches the threshold voltage of the first transistor T1, then the first transistor T1 can be turned off, and the voltage of the second node N2 can be maintained. Therefore, after the third cycle P3, the first capacitor C1 can store a voltage corresponding to the threshold voltage of the first transistor T1. For example, the step of increasing the voltage at one end of the first capacitor C1 (third cycle P3) can be performed during a longer time period than the step of connecting one end of the first capacitor C1 and the anode of the light-emitting element LD to the same initialization voltage source (second cycle P2).

[0080] Next, at time point t7a, a scan signal GWLs with a conduction level can be applied to the first scan line GWLi, thereby enabling the second transistor T2 to conduct. In this case, a data voltage can be applied to the data line DLj, thereby allowing the data voltage to be written to the first node N1. The voltage of the second node N2 can vary according to the capacitance ratio of capacitors C1 and C2 and the threshold voltage of the first transistor T1.

[0081] The fourth cycle (P4: t7a to t8a) can be a cycle in which, during this cycle, a scan signal GWLs at the on level is applied to the first scan line GWLi, while scan signals GRLs, GILs, EMLs, and EMBLs at the off level are applied to the second scan line GRLi, the third scan line GILi, the fourth scan line EMLi, and the fifth scan line EMBLi. During the fourth cycle P4, the step of applying a data voltage to the opposite terminal of the first capacitor C1 (e.g., to the first node N1) can be performed. For example, the step of applying a data voltage to the opposite terminal of the first capacitor C1 (fourth cycle P4) can be performed during a shorter time period than the step of simply connecting the anode of the light-emitting element LD to the initialization voltage source (first cycle P1).

[0082] Next, at time point t9a, a scan signal GILs with a conduction level can be applied to the third scan line GILi, thereby allowing the fourth transistor T4 to conduct. Therefore, by initializing the anode voltage of the light-emitting element LD, low grayscale images such as black grayscale images can be effectively represented.

[0083] The first cycle (P1: t9a to t10a) can be a cycle in which, during this cycle, when the on-level scan signals GILs are applied to the third scan line GILi, the off-level scan signals GWLs, GRLs, EMLs, and EMBLs are applied to the first scan line GWLi, the second scan line GRLi, the fourth scan line EMLi, and the fifth scan line EMBLi. During the first cycle P1, the step of connecting only the anode of the light-emitting element LD to the initialization voltage source can be performed. For example, during the first cycle P1, the fourth transistor T4 can be in the on state while the sixth transistor T6 is in the off state, so that the electrode (e.g., the anode) of the light-emitting element LD can be electrically coupled (e.g., electrically connected) to the initialization voltage source, while the first capacitor C1 and / or the second node N2 are electrically disconnected (e.g., electrically decoupled) from the initialization voltage source. Here, one end of the first capacitor C1 can be in a state disconnected from the initialization voltage source. In one or more embodiments, the voltage at one end of the first capacitor C1 and / or the voltage at the second node N2 may be independent of the initialization voltage VINT during the first period P1 (e.g., may be substantially unaffected by the initialization voltage VINT). For example, the voltage at one end of the first capacitor C1 and / or the voltage at the second node N2 may be substantially constant during the first period P1, and / or may be different from the initialization voltage VINT during the first period P1.

[0084] During the first cycle P1, the anode of the light-emitting element LD (third node N3) is initialized, but the second node N2 is not initialized because the sixth transistor T6 is in the off state. If the sixth transistor T6 were in the on state and the second node N2 were connected to the initialization voltage source, unnecessary power would be consumed due to the charging of the first capacitor C1 and the second capacitor C2. Therefore, according to this embodiment, power consumption can be reduced. Undesirable stripes due to the decrease in the initialization voltage VINT can be prevented. At the subsequent time point t12a, when the sixth transistor T6 is turned on, the relatively high voltage of the second node N2 can be applied to the third node N3, thereby preventing the emission of the light-emitting element LD from being delayed.

[0085] Subsequently, at time point t11a, a scan signal EMLs with a conduction level can be applied to the fourth scan line EML1, thereby allowing the fifth transistor T5 to conduct. Therefore, the first electrode of the first transistor T1 can be connected to the first power line ELVDDL.

[0086] Subsequently, at time point t12a, a scan signal EMLs with a conduction level can be applied to the fifth scan line EMBLi, thereby allowing the sixth transistor T6 to conduct. Therefore, the first transistor T1 can be connected to the anode of the light-emitting element LD.

[0087] Because the sixth transistor T6 turns on at time t12a and the voltage of the second node N2 increases at time t11a, a higher voltage can be applied to the anode of the light-emitting element LD. Therefore, emission delay can be prevented or reduced. Furthermore, the relatively high voltage of the second node N2 can be applied to the third node N3, thereby preventing or reducing the emission delay of the light-emitting element LD.

[0088] Figure 6 This is a diagram used to describe the second scan cycle SS1 according to an embodiment of the present disclosure.

[0089] Figure 6 The second scan cycle SS1 is Figure 3 and Figure 4 An example of the second scan cycle SS. The second scan cycle SS1 can sequentially include the sixth cycle P6 and the fifth cycle P5. For example, the length of the sixth cycle P6 can be greater than the length of the fifth cycle P5.

[0090] At time point t1b before the sixth cycle (P6: t2b to t3b), the cutoff level scan signals EMLs and EMBLs can be applied to the fourth scan line EMLi and the fifth scan line EMBLi, thereby allowing the fifth transistor T5 and the sixth transistor T6 to be cut off.

[0091] The sixth cycle P6 can be a cycle in which, during the period when on-level scan signals GILs are applied to the third scan line GILi, off-level scan signals GWLs, GRLs, EMLs, and EMBLs are applied to the first scan line GWLi, the second scan line GRLi, the fourth scan line EMLi, and the fifth scan line EMBLi. Therefore, during the sixth cycle P6, a first step can be performed where one end of the first capacitor C1 remains disconnected from the initialization voltage source, as a step of connecting only the anode of the light-emitting element LD to the initialization voltage source. For example, during the sixth cycle P6, the fourth transistor T4 can be in the on state while the sixth transistor T6 is in the off state, such that the electrode (e.g., anode) of the light-emitting element LD can be electrically coupled (e.g., electrically connected) to the initialization voltage source, while the first capacitor C1 and / or the second node N2 are electrically disconnected (e.g., electrically decoupled) from the initialization voltage source. In one or more embodiments, the voltage at one end of the first capacitor C1 and / or the voltage at the second node N2 can be independent of the initialization voltage VINT during the sixth cycle P6 (e.g., can be substantially unaffected by the initialization voltage VINT). For example, the voltage at one end of the first capacitor C1 and / or at the second node N2 may remain substantially constant during the sixth cycle, and / or may differ from the initial voltage VINT during the sixth cycle P6.

[0092] Similarly, the fifth cycle (P5: t4b to t6b) can be a cycle in which, during this cycle, when the on-level scan signals GILs are applied to the third scan line GILi, the off-level scan signals GWLs, GRLs, EMLs, and EMBLs are applied to the first scan line GWLi, the second scan line GRLi, the fourth scan line EMLi, and the fifth scan line EMBLi. Therefore, during the fifth cycle P5, a second step can be performed where one end of the first capacitor C1 remains disconnected from the initialization voltage source, as a step of connecting only the anode of the light-emitting element LD to the initialization voltage source. For example, during the fifth cycle P5, the fourth transistor T4 can be in the on state while the sixth transistor T6 is in the off state, allowing the electrode (e.g., anode) of the light-emitting element LD to be electrically coupled (e.g., electrically connected) to the initialization voltage source, while the first capacitor C1 and / or the second node N2 are electrically disconnected (e.g., electrically decoupled) from the initialization voltage source. In one or more embodiments, the voltage at one end of the first capacitor C1 and / or the voltage at the second node N2 can be independent of the initialization voltage VINT during the fifth cycle P5 (e.g., can be substantially unaffected by the initialization voltage VINT). For example, the voltage at one end of the first capacitor C1 and / or the voltage at the second node N2 can be substantially constant during the fifth cycle P5, and / or can be different from the initialization voltage VINT during the fifth cycle P5.

[0093] At time point t7b after the second step, a scan signal EMLs with a conduction level can be applied to the fourth scan line EMLi, thereby allowing the fifth transistor T5 to conduct. Therefore, at time point t6b, the step of connecting the first transistor T1 to the first power line ELVDDL can be performed.

[0094] Subsequently, at time point t8b, a scan signal EMBLs with a conduction level can be applied to the fifth scan line EMBLi, thereby allowing the sixth transistor T6 to conduct. Therefore, at time point t8b, the step of connecting the first transistor T1 to the anode of the light-emitting element LD can be performed.

[0095] The effects obtained in each of the sixth cycle P6 and the fifth cycle P5 can be compared with those in Figure 5 The effects obtained in the first period P1 are essentially the same. Furthermore, the effects obtained at time points t7b and t8b are essentially the same as those obtained at time points t11a and t12a. Therefore, redundant explanations relating to the previous statements will be omitted.

[0096] Figure 7 This is a diagram used to describe the second scan cycle SS2 according to another embodiment of the present disclosure. Figure 7 The second scan cycle SS2 is Figure 3 and Figure 4 An example of the second scan cycle SS.

[0097] exist Figure 7 During the second scan cycle SS2, subsequent steps can be executed sequentially. First, at time point t1c, the connection between the first power line ELVDDL and the first transistor T1, as well as the connection between the first transistor T1 and the light-emitting element LD, can be simultaneously disconnected. Then, at time point t2c, one end of the first capacitor C1 can be kept disconnected from the initialization voltage source, effectively connecting only the anode of the light-emitting element LD to the initialization voltage source. Next, at time point t4c, the first transistor T1 can be connected to the first power line ELVDDL. Afterward, at time point t5c, the first transistor T1 can be connected to the anode of the light-emitting element LD.

[0098] exist Figure 7 The effect obtained in the sixth cycle (P6': t2c to t3c) is the same as in Figure 6 The effects obtained in the sixth period P6 and the fifth period P5 are essentially the same. Furthermore, the effects obtained at time points t4c and t5c are essentially the same as those obtained at time points t7b and t8b. Therefore, redundant explanations relating to the previous statements will be omitted.

[0099] Figures 8 to 15 This is a cross-sectional view showing the structure of a light-emitting element LD according to an embodiment of the present disclosure. Hereinafter, it is assumed that the light-emitting element LD is formed of an organic light-emitting diode (OLED).

[0100] refer to Figure 8 An organic light-emitting diode (OLED) may include a pixel electrode 211, a counter electrode 215, and an intermediate layer 213 between the pixel electrode 211 (or the first electrode, or the anode) and the counter electrode 215 (or the second electrode, or the cathode).

[0101] Pixel electrode 211 may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Pixel electrode 211 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. For example, pixel electrode 211 may have a three-layer structure comprising ITO / Ag / ITO.

[0102] The opposing electrode 215 may be disposed on the intermediate layer 213. The opposing electrode 215 may comprise a low work function metal, alloy, conductive compound, or any combination thereof. For example, the opposing electrode 215 may comprise lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), lithium aluminum (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), ytterbium (Yb), silver ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The opposing electrode 215 may be a transparent electrode, a semi-transparent electrode, or a reflective electrode.

[0103] The intermediate layer 213 may include polymeric or low-molecular-weight organic materials that emit light of a specific color. The intermediate layer 213 may also include metal-containing compounds such as organometallic compounds, and in addition to various organic materials, may include inorganic materials such as quantum dots.

[0104] In an embodiment, the intermediate layer 213 may include an emitter layer, and a first functional layer and a second functional layer disposed below and above the emitter layer, respectively. The first functional layer may include, for example, a hole transport layer (HTL) or a hole injection layer (HIL). The second functional layer may include, for example, an electron transport layer (ETL) or an electron injection layer (EIL). The first or second functional layer may be omitted. The first and second functional layers may be integrally formed to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the pixel component 14.

[0105] In one embodiment, the intermediate layer 213 may include a charge generation layer CGL disposed between two or more emission units, which are successively stacked between the pixel electrode 211 and the opposing electrode 215. When the intermediate layer 213 includes emission units and the charge generation layer CGL, the organic light-emitting diode (OLED) can be a tandem light-emitting element. The OLED has a stacked structure comprising multiple emission units, thereby improving color purity and luminous efficiency.

[0106] An emitting unit may include an emitting layer, and a first functional layer and a second functional layer disposed below and above the emitting layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The negative and positive charge generation layers can further improve the luminous efficiency of a light-emitting diode (OLED) comprising multiple cascaded emitting elements.

[0107] The negative charge generation layer can be an n-type charge generation layer. The negative charge generation layer can provide electrons. The negative charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant can include a metallic material. The positive charge generation layer can be a p-type charge generation layer. The positive charge generation layer can provide holes. The positive charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant can include a metallic material.

[0108] In the implementation method, such as Figure 9 As shown, an organic light-emitting diode (OLED) may include a first emitting unit EU1 containing a first emitting layer EML1 and a second emitting unit EU2 containing a second emitting layer EML2, wherein the first emitting unit EU1 and the second emitting unit EU2 are stacked sequentially. A charge generation layer CGL may be disposed between the first emitting unit EU1 and the second emitting unit EU2. For example, an OLED may include a pixel electrode 211, a first emitting layer EML1, a charge generation layer CGL, a second emitting layer EML2, and a counter electrode 215 stacked sequentially. A first functional layer and / or a second functional layer may be disposed below and above the first emitting layer EML1, respectively. The first functional layer and / or the second functional layer may be disposed below and above the second emitting layer EML2, respectively. The first emitting layer EML1 may be a blue emitting layer. The second emitting layer EML2 may be a yellow emitting layer.

[0109] In the implementation method, such as Figure 10As shown, an organic light-emitting diode (OLED) may include a first emitting unit EU1 and a third emitting unit EU3, each including a first emitting layer EML1, and a second emitting unit EU2 including a second emitting layer EML2. A first charge-generating layer CGL1 may be disposed between the first emitting unit EU1 and the second emitting unit EU2. A second charge-generating layer CGL2 may be disposed between the second emitting unit EU2 and the third emitting unit EU3. For example, an OLED may include a pixel electrode 211, a first emitting layer EML1, a first charge-generating layer CGL1, a second emitting layer EML2, a second charge-generating layer CGL2, a first emitting layer EML1, and a counter electrode 215 stacked sequentially. A first functional layer and / or a second functional layer may be disposed below and above the first emitting layer EML1 (e.g., the first emitting layer EML1 of the first emitting unit EU1, the first emitting layer EML1 of the third emitting unit EU3, or each of the first emitting layer EML1 of the first emitting unit EU1 and the first emitting layer EML1 of the third emitting unit EU3). The first functional layer and / or the second functional layer may be disposed below and above the second emitting layer EML2. The first emitter layer, EML1, can be a blue emitter layer. The second emitter layer, EML2, can be a yellow emitter layer.

[0110] In an embodiment, in an organic light-emitting diode (OLED), in addition to the second emitting layer EML2, the second emitting unit EU2 may further include a third emitting layer EML3 and / or a fourth emitting layer EML4 that are in direct contact with the second emitting layer EML2, located below and / or above it. Here, the term "direct contact" may imply that no other layers are disposed between the second emitting layer EML2 and the third emitting layer EML3 and / or the second emitting layer EML2 and the fourth emitting layer EML4. The third emitting layer EML3 may be a red emitting layer. The fourth emitting layer EML4 may be a green emitting layer.

[0111] For example, such as Figure 11 As shown, an organic light-emitting diode (OLED) may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, the first emission layer EML1, and a counter electrode 215, which are stacked sequentially. Optionally, as... Figure 12 As shown, an organic light-emitting diode (OLED) may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1, and an opposing electrode 215, which are stacked sequentially.

[0112] Figure 13 It is shown Figure 11A cross-sectional view of an example of an organic light-emitting diode (OLED). Figure 14 It is shown Figure 12 A cross-sectional view of an example of an organic light-emitting diode (OLED).

[0113] refer to Figure 13 An organic light-emitting diode (OLED) may include a first emitting unit EU1, a second emitting unit EU2, and a third emitting unit EU3 stacked sequentially. A first charge generation layer CGL1 may be disposed between the first emitting unit EU1 and the second emitting unit EU2. A second charge generation layer CGL2 may be disposed between the second emitting unit EU2 and the third emitting unit EU3. The first charge generation layer CGL1 and the second charge generation layer CGL2 may each include a negative charge generation layer nCGL and a positive charge generation layer pCGL. In one or more embodiments, the first charge generation layer CGL1 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL, and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0114] The first emitting unit EU1 may include a blue emitting layer BEML. The first emitting unit EU1 may also include a hole injection layer HIL and a hole transport layer HTL disposed between the pixel electrode 211 and the blue emitting layer BEML. In an embodiment, a p-type doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-type doped layer can be formed by doping the hole injection layer HIL with a p-type doping material. In an embodiment, at least one of a blue light emitting auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue emitting layer BEML and the hole transport layer HTL. The blue light emitting auxiliary layer can improve the luminous efficiency of the blue emitting layer BEML. The blue light emitting auxiliary layer can regulate the hole charge balance, thereby enhancing the luminous efficiency of the blue emitting layer BEML. The electron blocking layer can prevent electrons from being injected into the hole transport layer HTL. The buffer layer can compensate for the resonant distance according to the wavelength of the light emitted from the emitting layer.

[0115] The second emitting unit EU2 may include a yellow emitting layer YEML and a red emitting layer REML directly contacting the yellow emitting layer YEML below it. The second emitting unit EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emitting layer REML, and may further include an electron transport layer ETL between the yellow emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0116] The third emitting unit EU3 may include a blue emitting layer BEML. The third emitting unit EU3 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emitting layer BEML. The third emitting unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL disposed between the blue emitting layer BEML and the opposing electrode 215. The electron transport layer ETL may have a single-layer structure or a multi-layer structure. In an embodiment, at least one of a blue light emitting auxiliary layer, an electron blocking layer, and a buffer layer may also be included between the blue emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue emitting layer BEML and the electron transport layer ETL. The hole blocking layer can prevent holes from being injected into the electron transport layer ETL.

[0117] Figure 14 The stacked structure of the second emitting unit EU2 in the organic light-emitting diode OLED depicted in the figure is similar to Figure 13 The organic light-emitting diode (OLED) depicted in the image differs from the OLED, while other configurations remain the same. (Reference) Figure 14 The second emitting unit EU2 may include a yellow emitting layer YEML, a red emitting layer REML directly contacting the yellow emitting layer YEML below it, and a green emitting layer GEML directly contacting the yellow emitting layer YEML above it. The second emitting unit EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emitting layer REML, and may further include an electron transport layer ETL between the green emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0118] refer to Figure 15 The pixel component 14 may include multiple pixels. Each pixel may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, second pixel PX2, and third pixel PX3 may include a pixel electrode 211, a counter electrode 215, and an intermediate layer 213. In an embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Here, the pixels may include organic light-emitting diodes (OLEDs) as display elements. The OLED of each pixel may be electrically connected to the pixel circuitry. The pixel electrode 211 may be independently disposed in each of the first pixel PX1, second pixel PX2, and third pixel PX3.

[0119] The intermediate layer 213 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 in an organic light-emitting diode (OLED) may include a first emitting unit EU1 and a second emitting unit EU2 stacked sequentially, and a charge generation layer CGL disposed between the first emitting unit EU1 and the second emitting unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed throughout the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0120] The first emitter unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emitter layer REML, and an electron transport layer ETL stacked sequentially on the pixel electrode 211. The first emitter unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL stacked sequentially on the pixel electrode 211. The first emitter unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL stacked sequentially on the pixel electrode 211. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emitter unit EU1 may be a common layer continuously formed throughout the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0121] The second emitter unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emitter layer REML, and an electron transport layer ETL stacked sequentially on the charge generation layer CGL. The second emitter unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL stacked sequentially on the charge generation layer CGL. The second emitter unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL stacked sequentially on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emitter unit EU2 may be a common layer continuously formed across the first pixel PX1, the second pixel PX2, and the third pixel PX3. In an embodiment, the second emitter unit EU2 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may further include at least one of a hole blocking layer and a buffer layer between the emitter layer and the electron transport layer ETL.

[0122] The thicknesses H1 of the red emitter layer REML, H2 of the green emitter layer GEML, and H3 of the blue emitter layer BEML can be determined based on the resonant distance. The auxiliary layer AXL can be a layer added to match the resonant distance and can include a resonant auxiliary material. For example, the auxiliary layer AXL can include the same material as the hole transport layer HTL.

[0123] although Figure 15 An example is shown where only the first pixel PX1 includes the auxiliary layer AXL, but embodiments of this disclosure are not limited thereto. For example, the auxiliary layer AXL may be provided in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to match the resonant distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0124] The pixel component 14 may also include a capping layer 217 disposed outside the opposing electrode 215. Based on the principle of constructive interference, the capping layer 217 can improve the emission efficiency. As a result, the light extraction efficiency of the organic light-emitting diode OLED can be improved, thereby improving the emission efficiency of the organic light-emitting diode OLED.

[0125] While preferred embodiments of this disclosure have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure as disclosed in the appended claims. Therefore, the limits and scope of this disclosure should be determined by the technical spirit of the appended claims.

Claims

1. A display device, comprising a pixel component, the pixel component including a plurality of pixels, in, Each of the pixels includes: The first transistor includes a first gate electrode connected to a first node and a second gate electrode connected to a second node; The second transistor includes a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the first node; The third transistor includes a gate electrode connected to the second scan line, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node; The fourth transistor includes a gate electrode connected to the third scan line, a first electrode configured to receive an initialization voltage, and a second electrode connected to the third node; The fifth transistor includes a gate electrode connected to the fourth scan line, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the first transistor. The sixth transistor includes a gate electrode connected to the fifth scan line, a first electrode connected to the second node, and a second electrode connected to the third node; and A first capacitor connects the first node to the second node. Wherein, at least one frame period includes a first period, during which, when a scan signal at an on level is applied to the third scan line, a scan signal at an off level is applied to the first scan line, the second scan line, the fourth scan line, and the fifth scan line.

2. The display device according to claim 1, wherein, After the first cycle, a scan signal with a conduction level is applied to the fourth scan line, and a scan signal with a conduction level is sequentially applied to the fifth scan line.

3. The display device according to claim 1, in, The pixel component displays an image at a first frequency in a first mode, and displays an image at a second frequency lower than the first frequency in a second mode. In the first mode, each frame period includes a first scan period in which data voltage is written to the pixel and a second scan period in which data voltage is not written to the pixel. In the second mode, each frame period includes the first scan period and a plurality of second scan periods.

4. The display device according to claim 3, in, The first scan cycle includes the first cycle, and The first scan cycle further includes a second cycle, during which a cutoff level scan signal is applied to the first scan line and the fourth scan line, and a turn-on level scan signal is applied to the second scan line, the third scan line, and the fifth scan line.

5. The display device according to claim 4, wherein, The first scan cycle further includes a third cycle during which a cutoff level scan signal is applied to the first scan line, the third scan line, and the fifth scan line, and a turn-on level scan signal is applied to the second scan line and the fourth scan line.

6. The display device according to claim 5, wherein, The first scan cycle further includes a fourth cycle during which a scan signal at an on level is applied to the first scan line, and a scan signal at an off level is applied to the second scan line, the third scan line, the fourth scan line, and the fifth scan line.

7. The display device according to claim 6, wherein, The second cycle, the third cycle, the fourth cycle, and the first cycle are positioned sequentially within the first scanning cycle.

8. The display device according to claim 7, wherein, The second scan cycle includes a fifth cycle during which, when a scan signal at an on level is applied to the third scan line, a scan signal at an off level is applied to the first scan line, the second scan line, the fourth scan line, and the fifth scan line.

9. The display device according to claim 8, wherein, After the fifth cycle, a scan signal with a conduction level is applied to the fourth scan line, and a scan signal with a conduction level is sequentially applied to the fifth scan line.

10. The display device according to claim 8, wherein, The second scan cycle also includes a sixth cycle, during which, when a scan signal at an on level is applied to the third scan line, a scan signal at an off level is applied to the first scan line, the second scan line, the fourth scan line, and the fifth scan line.

11. The display device according to claim 10, wherein, The sixth cycle and the fifth cycle are positioned sequentially in the second scanning cycle.

12. The display device according to claim 9, wherein, Prior to the sixth cycle, a cutoff level scan signal is applied to the fourth and fifth scan lines.

13. A method for driving a display device, comprising: The image is displayed at a first frequency in the first mode; And in the second mode, the image is displayed at a second frequency lower than the first frequency. In the first mode, each frame period includes a first scan period in which data voltage is written to the pixel and a second scan period in which data voltage is not written to the pixel. In the second mode, each frame period includes the first scan period and a plurality of second scan periods. In the first scanning cycle, the method of driving the display device includes, in sequence: The first terminal of the first capacitor included in the pixel is connected to the same initialization voltage source as the anode of the light-emitting element; Increase the voltage at the first terminal of the first capacitor to correspond to the threshold voltage of the driving transistor included in the pixel; Apply the data voltage to the second terminal of the first capacitor; and Only the anode of the light-emitting element is connected to the initialization voltage source, while the first terminal of the first capacitor remains disconnected from the initialization voltage source.

14. The method according to claim 13, wherein, In the first scanning cycle, the method of driving the display device further includes, in sequence: Connect the driving transistor to the first power line; and The driving transistor is connected to the anode of the light-emitting element.

15. The method according to claim 13, wherein, The duration for which the first terminal of the first capacitor and the anode of the light-emitting element are connected to the same initialization voltage source is longer than the duration for which only the anode of the light-emitting element is connected to the initialization voltage source.

16. The method according to claim 13, wherein, The duration for which the voltage at the first terminal of the first capacitor is increased is longer than the duration for which the first terminal of the first capacitor and the anode of the light-emitting element are connected to the same initialization voltage source.

17. The method according to claim 13, wherein, The duration for which the data voltage is applied to the second terminal of the first capacitor is shorter than the duration for which only the anode of the light-emitting element is connected to the initialization voltage source.

18. The method according to claim 13, wherein, In the second scan cycle, the method of driving the display device includes: A first operation is performed whereby only the anode of the light-emitting element is connected to the initialization voltage source, while the first terminal of the first capacitor remains disconnected from the initialization voltage source; and A second operation involves connecting only the anode of the light-emitting element to the initialization voltage source while keeping the first terminal of the first capacitor disconnected from the initialization voltage source. The duration of the first operation is longer than the duration of the second operation.

19. The method according to claim 18, wherein, In the second scanning cycle, the method of driving the display device further includes, in sequence: After the second operation, the driving transistor is connected to the first power line; and The driving transistor is connected to the anode of the light-emitting element.

20. The method according to claim 13, wherein, In the second scanning cycle, the method of driving the display device includes, in sequence: Simultaneously disconnect the connection between the first power line and the driving transistor, as well as the connection between the driving transistor and the anode of the light-emitting element; Only the anode of the light-emitting element is connected to the initialization voltage source, while the first terminal of the first capacitor remains disconnected from the initialization voltage source; Connect the driving transistor to the first power line; and The driving transistor is connected to the anode of the light-emitting element.

Images