TEM sample manufacturing method

Abstract

The invention provides a TEM sample manufacturing method, which comprises the following steps of: performing a splitting process on a wafer to obtain a sample to be tested; forming a first protection layer on the to-be-tested sample to preliminarily protect the integrity of the to-be-tested sample; performing an electrochemical electroplating process to form a conductive layer which covers the first protective layer to protect the morphology of the to-be-tested sample; and thinning the sample to be detected to form the TEM sample. The conductive layer is formed on the first protective layer through the electrochemical electroplating process, bubbles are less generated in the electrochemical electroplating process, observation of the sample to be detected is facilitated, the thickness and uniformity of the conductive layer can be effectively controlled through the electrochemical electroplating process, and the conductive layer is good in mechanical performance, small in stress change and high in reliability. The phenomenon that the edge of the to-be-detected sample is cracked can be avoided; the conductive layer is good in electric conduction and heat conduction performance, deformation of the to-be-tested sample caused by charge accumulation can be effectively prevented, the morphology of the to-be-tested sample is further effectively protected, meanwhile, image drifting in the manufacturing process of the TEM sample is reduced, and the image quality is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a TEM sample manufacturing method. BACKGROUND

[0002] TEM (Transmission Electron Microscope) testing is a powerful characterization technology that uses a high-energy electron beam to penetrate an ultrathin sample and analyze the microstructure inside the sample through electromagnetic lens imaging. In the semiconductor field, TEM testing has become an indispensable core characterization technology due to its atomic-level resolution and multi-modal analysis capabilities, and is used throughout the chip design, process development, mass production monitoring, and failure analysis processes.

[0003] The existing TEM sample manufacturing method includes the following steps: selecting a target area of a wafer for dicing and cleaning, forming a protective film on the sample to be tested to provide preliminary integrity protection; covering the target area of the sample to be tested with a glue-based material and performing a curing process to further protect the topography of the sample to be tested; performing laser marking positioning on the target area, and performing sample thinning in a focused ion beam to form a TEM sample.

[0004] However, the glue-based material is prone to cracking when exposed to high voltage for a long time, which cannot effectively protect the sample to be tested; most glues have strong volatility and fluidity, which can easily produce bubbles, resulting in unclear interfaces and affecting measurement; the soft glue can also deform, which cannot effectively protect the original topography of the sample to be tested. SUMMARY

[0005] The present application aims to provide a TEM sample manufacturing method to solve the problem of covering the target area of the sample to be tested with a glue-based material, which cannot effectively protect the original topography of the sample to be tested.

[0006] To solve the above technical problems, the present application provides a TEM sample manufacturing method, comprising:

[0007] providing a wafer;

[0008] performing a dicing process on the target area of the wafer to obtain a sample to be tested;

[0009] forming a first protective layer on the sample to be tested to preliminarily protect the integrity of the sample to be tested;

[0010] performing an electrochemical plating process to form a second protective layer, the second protective layer covering the first protective layer to protect the topography of the sample to be tested, and the material of the second protective layer being a conductive layer;

[0011] thinning the sample to be tested to form a TEM sample.

[0012] Optionally, before performing the electrochemical plating process, the sample to be measured is placed in the plating solution, and air in the plating solution is discharged.

[0013] Optionally, the air in the plating solution is discharged by a vacuum degassing method or an ultrasonic degassing method.

[0014] Optionally, the wafer comprises a substrate and a polysilicon layer and a dielectric layer on the substrate, and the dielectric layer is on the polysilicon layer.

[0015] Optionally, in the step of performing the dicing process on the wafer, the dielectric layer and the polysilicon layer are etched in sequence to form a hole type structure penetrating through the dielectric layer and the polysilicon layer, and the hole type structure exposes the surface of the substrate.

[0016] Optionally, in the step of performing the electrochemical plating process, the second protective layer fills the hole type structure and covers the first protective layer, and the second protective layer filled in the hole type structure constitutes a plastic protective layer.

[0017] Optionally, the thickness of the second protective layer is 1-10 μm.

[0018] Optionally, before performing the electrochemical plating process, a seed layer is formed, and the seed layer covers the first protective layer.

[0019] Optionally, the sample to be measured is thinned by a focused ion beam to form the TEM sample.

[0020] Optionally, before the step of thinning the sample to be measured, the target region is positioned by laser marking.

[0021] In the method for manufacturing a TEM sample provided by the present application, a dicing process is performed on a target region of a wafer to obtain a sample to be measured; a first protective layer is formed on the sample to be measured to preliminarily protect the integrity of the sample to be measured; an electrochemical plating process is performed to form a second protective layer, the second protective layer covers the first protective layer to protect the topography of the sample to be measured, and the material of the second protective layer is a conductive layer; and the sample to be measured is thinned to form a TEM sample. In the present application, a conductive layer is formed on the first protective layer by the electrochemical plating process, and fewer bubbles are generated in the process of the electrochemical plating process, which facilitates the observation of the sample to be measured. The electrochemical plating process can effectively control the thickness and uniformity of the conductive layer, and the mechanical performance of the conductive layer is good and changes little under stress, which can avoid the phenomenon of cracking of the edge of the sample to be measured. The conductive and heat conductive performance of the conductive layer is good, which can effectively prevent the deformation of the sample to be measured caused by the accumulation of electric charge, thereby effectively protecting the topography of the sample to be measured, reducing the image drift in the process of manufacturing the TEM sample, and improving the image quality. BRIEF DESCRIPTION OF DRAWINGS

[0022] Those skilled in the art will appreciate that the appended drawings are provided by way of example only and are not to be construed as limiting the scope of the present application. In the drawings:

[0023] Figure 1 is a flow chart of a method for making a TEM sample of an embodiment of the present application.

[0024] Figure 2 is a schematic diagram of a sample under test after performing a cleaving process of an embodiment of the present application.

[0025] Figure 3 is a schematic diagram of a sample under test after forming a first protective layer of an embodiment of the present application.

[0026] Figure 4 is a schematic diagram of a sample under test after forming a seed layer of an embodiment of the present application.

[0027] Figure 5 is a schematic diagram of a sample under test after forming a second protective layer of an embodiment of the present application.

[0028] Figure 6 is a top view schematic diagram of a TEM sample of an embodiment of the present application.

[0029] In the drawings:

[0030] 10 - substrate; 10a - target region; 11 - polysilicon layer; 12 - dielectric layer; 13 - hole-type structure; 14 - first protective layer; 15 - seed layer; 16 - second protective layer; 17a - first laser mark; 17b - second laser mark. DETAILED DESCRIPTION

[0031] In order to make the objects, advantages and features of the present application clearer, the following further describes the present application in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all very simplified and not drawn to scale, and are only used to facilitate and clearly assist in explaining the purposes of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis shown in each drawing is different, and sometimes different scales are used.

[0032] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The term "or" is generally employed in its sense of "and / or" unless the context clearly dictates otherwise. The term "plurality" is generally employed in its sense of "two or more" unless the context clearly dictates otherwise. The terms "first," "second," "third," etc. are used only to describe different instances and do not imply or suggest relative importance or imply a number of the indicated technical features. Thus, features defined with "first," "second," "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present application, an element disposed on another element generally only indicates that there is a connection, coupling, engagement, or transmission relationship between the two elements, and the two elements can be directly or indirectly connected, coupled, engaged, or transmitted, and cannot be understood as indicating or suggesting the spatial positional relationship between the two elements, i.e. one element can be in any orientation inside, outside, above, below, or one side of the other element, unless the context clearly indicates otherwise. The specific meaning of the above terms in the present application can be understood by those skilled in the art according to the specific circumstances.

[0033] Figure 1 is a flow chart of a method for manufacturing a TEM sample according to an embodiment of the present application. As shown in Figure 1 , the embodiment provides a method for manufacturing a TEM sample, comprising:

[0034] Step S10, providing a wafer;

[0035] Step S20, performing a dicing process on a target region of the wafer to obtain a sample to be tested;

[0036] Step S30, forming a first protective layer on the sample to be tested to preliminarily protect the integrity of the sample to be tested;

[0037] Step S40, performing an electrochemical plating process to form a second protective layer, the second protective layer covering the first protective layer to protect the topography of the sample to be tested, the material of the second protective layer being a conductive layer;

[0038] Step S50, thinning the sample to be tested to form a TEM sample.

[0039] Figure 2 is a schematic diagram of a sample to be tested after performing a dicing process according to an embodiment of the present application. Figure 3 is a schematic diagram of a sample to be tested after forming a first protective layer according to an embodiment of the present application. Figure 4 is a schematic diagram of a sample to be tested after forming a seed layer according to an embodiment of the present application. Figure 5 is a schematic diagram of a sample to be tested after forming a second protective layer according to an embodiment of the present application.Figure 6 is a top view schematic diagram of a TEM sample of an embodiment of the present application. In order to make the above objectives, features and advantages of the present application more obvious and comprehensible, the following will be described in conjunction with the drawings attached to the specification Figures 2 to 6 The specific embodiments of the present application are described in detail.

[0040] As shown in Figure 2 , a wafer is provided; the wafer comprises a substrate 10 and a polysilicon layer 11 and a dielectric layer 12 on the substrate 10, and the dielectric layer 12 is on the polysilicon layer 11. The substrate 10 can be a single crystal silicon or a polysilicon substrate, or can be made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., or can be a composite structure such as a silicon-on-insulator substrate. Those skilled in the art can select the appropriate type of semiconductor substrate according to the requirements of the semiconductor device, and the type of semiconductor substrate should not limit the scope of protection of the present application. The dielectric layer 12 is silicon oxide and / or silicon nitride. The polysilicon layer 11 and the dielectric layer 12 can be formed by chemical vapor deposition.

[0041] Please refer to Figure 2 and Figure 6 , a wafer is provided; the wafer comprises a substrate 10 and a polysilicon layer 11 and a dielectric layer 12 on the substrate 10, and the dielectric layer 12 is on the polysilicon layer 11. The substrate 10 can be a single crystal silicon or a polysilicon substrate, or can be made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., or can be a composite structure such as a silicon-on-insulator substrate. Those skilled in the art can select the appropriate type of semiconductor substrate according to the requirements of the semiconductor device, and the type of semiconductor substrate should not limit the scope of protection of the present application. The dielectric layer 12 is silicon oxide and / or silicon nitride. The polysilicon layer 11 and the dielectric layer 12 can be formed by chemical vapor deposition.

[0042] As shown in Figure 3 , a first protective layer 14 is formed on the sample to be tested to preliminarily protect the integrity of the sample to be tested. The first protective layer 14 covers the sidewalls of the polysilicon layer 11, the sidewalls and top of the dielectric layer 12, and the surface of the substrate. The first protective layer 14 is a metal oxide film. The metal oxide film is, for example, hafnium oxide. The thickness of the first protective layer 14 is, for example, 1-10 nm. The first protective layer 14 is formed by an atomic layer deposition (ALD) process, the temperature of the atomic layer deposition process is, for example, 50-150°C, the pressure of the atomic layer deposition process is, for example, about 10-30 hPa, and the process time of the atomic layer deposition process is, for example, 30-60 minutes. The gas used to generate hafnium oxide is, for example, nitrogen, oxygen and hafnium.

[0043] like Figure 4 As shown, after forming the first protective layer 14 and before performing the electrochemical plating process, a seed layer 15 is formed, which covers the first protective layer 14. The seed layer 15 is a dense conductive layer used to provide a conductive path, allowing the subsequent electroplated metal to uniformly fill the high aspect ratio structure. The material of the seed layer 15 includes metals such as gold and platinum, but is not limited to these metals. In this embodiment, the seed layer 15 is prepared using a gold plating machine.

[0044] like Figure 5 As shown, an electrochemical electroplating process is performed to form a second protective layer 16. This second protective layer 16 fills the pore structure 13 and covers the seed layer 15. The second protective layer 16 filling the pore structure 13 constitutes a shaping protective layer to protect the morphology of the sample under test. The current density of the electrochemical electroplating process is 0.5 A / dm³. 2 ~1.5A / dm 2 For example, 1.0A / dm 2 The voltage of the electrochemical electroplating process is -0.2V to -0.6V, for example -0.3V, -0.4V, or -0.5V. The thickness of the second protective layer 16 is 1μm to 10μm, for example 3μm, 5μm, or 7μm. The thickness of the second protective layer 16 is determined according to the requirements of the sample to be tested. For example, if the depth of the pore structure 13 is tens of nanometers, the second protective layer 16 fills the pore structure 13 and covers the surface of the seed layer 15, in which case the second protective layer 16 can reach 1μm; for example, if the depth of the pore structure 13 is 3μm, the second protective layer 16 fills the pore structure 13 and covers the surface of the seed layer 15, in which case the second protective layer 16 can reach 4μm. The material of the second protective layer 15 is a conductive layer. Preferably, the material of the second protective layer 15 is a metallic material. More preferably, the material of the second protective layer 15 includes copper and / or aluminum. In this embodiment, a conductive layer is used as the second protective layer 16, which can fill the porous structure 13 and further protect the surface of the sample to be tested. Moreover, the good electrical and thermal conductivity of the metal material can effectively prevent the deformation of the sample to be tested caused by charge accumulation, while reducing image drift during the fabrication of TEM samples and improving image quality; in addition, the good mechanical properties of the metal material and the small change under stress can avoid the phenomenon of cracking at the edge of the sample to be tested.

[0045] In the electrochemical plating process, the sample is put into the plating solution before the second protective layer 16 is formed, and the air in the plating solution is discharged, which can significantly reduce defects such as pinholes and pitting in the electrochemical plating process. For example, the air in the plating solution is discharged by vacuum degassing or ultrasonic degassing. The vacuum degassing method reduces the solubility of gas in a negative pressure environment, so that the dissolved air (O2, N2, etc.) is precipitated and discharged. The ultrasonic degassing method (Ultrasonic Degassing) uses the ultrasonic cavitation effect: high-frequency sound waves (>20 kHz) generate microbubbles in the liquid, which can discharge dissolved gas by oscillation, merging, and floating. Since the air in the plating solution is discharged in advance, fewer bubbles are generated during the electrochemical plating process, which facilitates observation of the sample under test, so that the deposition thickness and morphology of the second protective layer 16 can be controlled.

[0046] In other embodiments, the second protective layer 16 can also be formed by electroless plating.

[0047] The electrochemical plating process for forming the second protective layer 16 in this embodiment is performed in a laboratory environment. The controllable electrochemical plating process in the laboratory environment fills the TEM sample structure, and the thickness, rate and morphology of the second protective layer 16 are controllable. The TEM sample structure is not limited to a hole structure, but can also be other structures, which are not limited in this embodiment. The control method of the second protective layer 16 in the laboratory environment is easier to achieve and requires less.

[0048] As shown in Figure 6 Before the step of thinning the sample under test, the target area 10a is laser marked and positioned. Specifically, the target area 10a is marked longitudinally and transversely by a laser marking device to obtain first and second laser marks 17a and 17b. The laser marking device is a laser marker with an optical microscope. After the target area 10a is confirmed by the optical microscope, laser marking is performed near the target area 10a, so that the target area 10a can be confirmed after the sample under test enters the focused ion beam.

[0049] Thinning the sample to be measured to form a TEM sample. In this embodiment, the sample to be measured is thinned by a focused ion beam (FIB) to form a TEM sample. Specifically, in the focused ion beam device, the target area 10a is positioned by the first laser mark 17a and the second laser mark 17b, and after the target area 10a is positioned, the ion beam of the focused ion beam device thins the sample to be measured at the target area 10a to form a TEM sample. The thickness of the sample to be measured depends on the requirements of the TEM sample, and the general thickness is between 30nm-50nm. The ion beam of the focused ion beam is used for thinning, and it is necessary to thin to a certain thickness before subsequent TEM observation. The thinner the thickness of the TEM sample, the more details can be observed by TEM. After the preparation of the TEM sample is completed, the TEM sample is placed in the TEM for observation.

[0050] As can be seen from the above, in the TEM sample preparation method provided in the embodiment of the present application, a wafer target area is subjected to a cleaving process to obtain a sample to be measured; a first protective layer is formed on the sample to be measured to preliminarily protect the integrity of the sample to be measured; an electrochemical plating process is performed to form a second protective layer, the second protective layer covers the first protective layer to protect the morphology of the sample to be measured, and the material of the second protective layer is a conductive layer; and the sample to be measured is thinned to form a TEM sample. The conductive layer formed on the first protective layer by the electrochemical plating process in the present application produces fewer bubbles during the electrochemical plating process, facilitates observation of the sample to be measured, and can effectively control the thickness and uniformity of the conductive layer, and the mechanical performance of the conductive layer is good and changes little under stress, thereby avoiding the phenomenon of edge cracking of the sample to be measured. The conductive and thermal conductivity of the conductive layer are good, which can effectively prevent the deformation of the sample to be measured caused by charge accumulation, thereby effectively protecting the morphology of the sample to be measured, and reducing image drift in the process of preparing a TEM sample and improving image quality.

[0051] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. In addition, the different parts of each embodiment can also be used together, and the present application is not limited in this regard.

[0052] Furthermore, it should be appreciated that the above-described embodiments are merely exemplary as to the present application and need not be practiced as described. It should also be understood that where the above-described embodiments are, for clarity, described in terms of steps or means, these steps or means need not be performed in the order given or even one at a time. Rather, certain steps or means can be performed in an order different than other steps or means or even carried out in parallel. Measured costs, measured values, and other quantities can be determined at different times, or even at the same time. Also, certain steps or means can be carried out intermittently or continuously. Further, steps or means need not be performed by different entities or even by the same entity. For example, steps or means can be performed by one or more entities.

Claims

1. A method for preparing a TEM sample, characterized in that, include: Provide one wafer; A dicing process is performed on the target area of ​​the wafer to obtain a sample to be tested. A first protective layer is formed on the sample to be tested to initially protect the integrity of the sample; An electrochemical electroplating process is performed to form a second protective layer, which covers the first protective layer to protect the morphology of the sample to be tested. The material of the second protective layer is a conductive layer. The sample to be tested is thinned to form a TEM sample.

2. The method for preparing a TEM sample according to claim 1, characterized in that, Before performing the electrochemical plating process, the sample to be tested is placed in the plating solution to remove the air from the plating solution.

3. The method for preparing a TEM sample according to claim 2, characterized in that, The air in the electroplating solution is removed by vacuum degassing or ultrasonic degassing.

4. The method for preparing a TEM sample according to claim 1, characterized in that, The wafer includes a substrate and a polysilicon layer and a dielectric layer located on the substrate, the dielectric layer being located on the polysilicon layer.

5. The method for preparing a TEM sample according to claim 4, characterized in that, In the dicing process performed on the wafer, the dielectric layer and the polysilicon layer are etched sequentially to form a hole structure that penetrates the dielectric layer and the polysilicon layer, the hole structure exposing the surface of the substrate.

6. The method for preparing a TEM sample according to claim 5, characterized in that, In the electrochemical electroplating process, the second protective layer fills the pore structure and covers the first protective layer, and the second protective layer filled in the pore structure constitutes a molding protective layer.

7. The method for preparing a TEM sample according to claim 1, characterized in that, The thickness of the second protective layer is 1 μm to 10 μm.

8. The method for preparing a TEM sample according to claim 1, characterized in that, Before performing the electrochemical plating process, a seed layer is formed, which covers the first protective layer.

9. The method for preparing a TEM sample according to claim 1, characterized in that, The sample to be tested is thinned using a focused ion beam to form the TEM sample.

10. The method for preparing a TEM sample according to claim 1, characterized in that, Before the step of thinning the sample to be tested, the target area is laser-marked and positioned.

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