Packaging method of ultrasonic identification fingerprint chip with vacuum cavity

Abstract

The invention relates to the technical field of semiconductor packaging, in particular to a packaging method of an ultrasonic identification fingerprint chip with a vacuum cavity, and the method comprises the following steps: S1, carrying out the metal wiring of a first layer; s2, laying a PI layer and a PVDF layer; s3, performing metal wiring of a second layer; s4, SnAg metal bumps are planted on the dummy silicon wafers, the dummy silicon wafer on the left side is fixed, and the ASIC chip is inversely installed; s5, vacuum film covering; s6, carrying out plastic packaging; s7, grinding is conducted; s8, stripping the glass substrate; s9, cutting is conducted; scattering and absorption of air to ultrasonic waves are thoroughly eliminated through the vacuum layer formed by vacuum coating, signal transmission loss is greatly reduced, acoustic impedance matching between the PVDF piezoelectric layer and a vacuum medium is better, signal receiving sensitivity is improved, the overall packaging thickness is reduced to 0.3 mm or below through ultrathin stacking of the PI layer and the PVDF layer, and the packaging effect is good. The three breakthroughs of high signal quality, ultra-thin thickness and high reliability are realized, and an ideal packaging method is provided for the ultrasonic fingerprint identification module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a packaging method of an ultrasonic fingerprint recognition chip with a vacuum cavity. BACKGROUND

[0002] The ultrasonic fingerprint recognition technology has become an important development direction in the field of biometric recognition due to its high security, strong penetration and excellent anti-environmental interference capability. In intelligent terminals (such as smart phones, tablet computers, smart door locks, etc.), the ultrasonic fingerprint recognition chip transmits and receives ultrasonic signals to penetrate the screen or protective layer to obtain the ridge valley features of the fingerprint, thereby achieving high-precision identity authentication. However, the performance of the ultrasonic fingerprint recognition chip is highly dependent on the packaging technology.

[0003] The existing ultrasonic fingerprint recognition packaging technology mainly adopts traditional hermetic packaging or plastic packaging process. These methods have obvious shortcomings in signal transmission, structure thickness and reliability. Traditional packaging usually adopts metal or ceramic shells for hermetic sealing, which can provide good moisture-proof and mechanical protection, but has the following disadvantages: (1) severe ultrasonic signal attenuation: the acoustic impedance of metal or ceramic materials does not match the material of the fingerprint sensor (such as PVDF), resulting in large energy loss of ultrasonic signals during transmission, reduced signal-to-noise ratio, and affected recognition accuracy; (2) large packaging thickness: traditional shell packaging requires additional sealing structures and support layers, resulting in increased overall thickness (usually >1mm), which is difficult to meet the demand for thinness of intelligent terminal devices; (3) insufficient vacuum degree: in existing technologies, the cavity of the ultrasonic sensor is filled with inert gas at normal pressure or low pressure, which cannot completely eliminate the scattering and absorption of air to ultrasonic signals, reducing signal reception sensitivity; (4) high process complexity: when integrating multiple layers of metal wiring with the sensor, the mismatch of the coefficient of thermal expansion (CTE) may cause interface delamination or warping, affecting yield. In addition, some improved schemes attempt to use flexible film packaging, but it is difficult to balance vacuum maintenance and mechanical strength, and long-term use may cause film layer peeling or air tightness failure.

[0004] Therefore, in view of the above-mentioned problems that the existing packaging method is difficult to balance vacuum maintenance and mechanical strength, and long-term use may cause film layer peeling or air tightness failure, a packaging method of an ultrasonic fingerprint recognition chip with a vacuum cavity can be designed. A high vacuum layer is formed on the surface of the sensor through a unique vacuum film coating process, which significantly improves the signal transmission efficiency. The vacuum environment completely eliminates the scattering and absorption of air to ultrasonic waves, which is more conducive to receiving ultrasonic signals, and the chip is lighter and thinner. SUMMARY

[0005] In order to overcome the problem that the existing packaging method is difficult to balance vacuum maintenance and mechanical strength, and long-term use may cause film layer peeling or air tightness failure.

[0006] The technical solution of the present invention is: a packaging method for an ultrasonic fingerprint chip with a vacuum cavity, comprising the following steps: S1: Perform the first layer of metal wiring. A metal layer is deposited on the glass substrate by sputtering or evaporation. Interconnect lines are then formed using photolithography and etching processes. ; S2: Lay out the PI layer and PVDF layer; S3: Perform the second layer of metal wiring to obtain... ; S4: Plant SnAg metal bumps on the dummy silicon wafer, use ACF anisotropic conductive adhesive or ultrasonic welding process to fix the left dummy silicon wafer at the designated position of RDL2, flip-chip the ASIC chip, and the bump height is 3~50μm. S5: Vacuum lamination; S6: Plastic sealing; S7: Grinding exposes the ASIC chip and dummy silicon wafer; S8: Peel off the glass substrate; S9: Cutting.

[0007] Preferably, the thickness of the glass substrate is 10–180 μm, and the thickness of the glass substrate for support is 200–1200 μm.

[0008] As a preferred option and The thickness of the metal layer is 50 μm.

[0009] Preferably, the order of laying the PI layer and PVDF layer is PI first, then PVDF. The PI layer is laid by spin coating, and the PVDF layer is laid by corona polarization.

[0010] Preferably, the surface of the dummy silicon wafer is provided with metal bumps, which are evenly distributed in the outer peripheral area of ​​the dummy silicon wafer.

[0011] As a preferred method, specific methods for vacuum coating include: a) Place the flip-chip bonded assembly in a vacuum chamber and evacuate to ≤1× Pa; b) Form a thin film on the component surface by chemical vapor deposition, or press-fit a pre-cured PDMS film layer; c) Laser sealing is performed on the edges of the membrane layer to isolate the cavity from the outside world.

[0012] As a preferred option, the specific steps for plastic sealing are as follows: a) Place the component in a vacuum injection mold and evacuate to ≤1 kPa; b) Inject epoxy resin molding compound and mold at 175℃ / 5MPa; c) After segmented curing, remove the protective film in the acoustic window area to form an ultrasonic transmission channel.

[0013] Preferably, the step of grinding to expose the ASIC chip and dummy silicon wafer includes: a) A chemical mechanical polishing process is used to thin the surface of the molded body with alumina polishing slurry until the metal pads of the ASIC chip and the metal bumps of the dummy silicon wafer are exposed. b) The grinding endpoint is controlled by an optical thickness gauge, the residual molding layer thickness is ≤5μm, and the surface roughness Ra of the ASIC chip pads is <0.05μm.

[0014] Preferably, the stripping step includes: a) Place the glass substrate in an ultraviolet irradiation device with a wavelength of 365 nm and an energy density of 300 mJ / cm². 2 Irradiation causes temporary bonded adhesives to photodegrade and fail. b) The glass substrate is separated by a mechanical pick-up device with a vertical force of ≤10N, and the residual adhesive layer is completely removed by oxygen plasma cleaning.

[0015] The beneficial effects of this invention are as follows: The vacuum layer formed by vacuum coating completely eliminates the scattering and absorption of ultrasonic waves by air, greatly reducing signal transmission loss. The acoustic impedance matching between the PVDF piezoelectric layer and the vacuum medium is better, ensuring improved signal reception sensitivity. Through the ultra-thin stacking of PI and PVDF layers, combined with vacuum coating to replace the traditional metal shell, the overall packaging thickness is reduced to less than 0.3mm. The vacuum environment inhibits water and oxygen penetration, extending the sensor life. The collaborative design of the dummy silicon wafer and ASIC chip disperses thermal stress, resulting in less warpage. This invention achieves a triple breakthrough in high signal quality, ultra-thin thickness, and high reliability, providing an ideal packaging method for ultrasonic fingerprint recognition modules. Attached Figure Description

[0016] Fig. 1 The diagram shown is a cross-sectional view of the chip during the packaging process of this invention. Fig. 2 The diagram shown is a top view of the Dummy silicon wafer of this invention. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Example Please see Figs. 1-2 This invention provides a packaging method for an ultrasonic fingerprint chip with a vacuum cavity, comprising the following steps: S1: A Ti / Cu metal layer (Ti 50nm / Cu 1μm) is sputtered and deposited on a glass substrate with a thickness of 10-180μm, and a first layer of interconnects with a linewidth of 15μm is formed by photolithography and ion beam etching. S2: An 8μm thick PI layer (HD-4104) is laid by spin coating and cured at 250℃ for 1 hour; subsequently, a 25μm thick PVDF layer is laid using corona polarization (100kV / mm, 80℃) to adjust its piezoelectric coefficient. Reaching 25 pC / N; S3: Through holes are formed by laser drilling (355nm, 20μm diameter), and a second layer of metal wiring is fabricated after being filled with Cu by electroplating. The alignment error between the second and first layers of wiring is ≤2μm. S4: Plant SnAg metal bumps on the dummy silicon wafer, use ACF anisotropic conductive adhesive or ultrasonic welding process to fix the left dummy silicon wafer at the designated position of RDL2, flip-chip the ASIC chip, and the bump height is 3~50μm. S5: In 1× A 1μm thick layer was deposited by PECVD under a vacuum of Pa. The encapsulation film and laser-sealed edges form a vacuum cavity; S6: Vacuum injection molding of EP-2300 epoxy resin (175℃ / 5MPa), which forms a 1mm thick encapsulated body after curing; S7: Chemical mechanical polishing (alumina polishing slurry) thins the chip pads to expose the chip pads, leaving a 3μm residual molding layer and a pad roughness Ra of 0.03μm; S8: 365nm ultraviolet irradiation (300mJ / The glass substrate is peeled off, and residual adhesive is removed by oxygen plasma cleaning. S9: The final package is obtained by using 1064nm laser cutting with a heat-affected zone of 15μm.

[0019] Comparative Example Traditional non-vacuum sealing methods: S1: Fabricate identical first and second layer metal wiring on a 10-180μm glass substrate; S2: After laying the PI layer, directly spin-coat ordinary epoxy resin encapsulant (non-vacuum environment). S3: Uses the same flip-chip and dummy silicon process; S4: Injection molding under normal pressure, without vacuum coating step; S5: Same grinding, peeling, and cutting processes.

[0020] S9: After diamond blade cutting (30,000 rpm) Laser trimming.

[0021] The performance comparison table of chips prepared using the example and comparative packaging methods is shown below:

[0022] This embodiment, through vacuum coating and optimized structural design, significantly outperforms traditional packaging methods in terms of signal quality (signal-to-noise ratio improved by 52%), thinness (thickness reduced by 46%), and reliability (lifespan increased by 3 times). Although the cost is slightly increased, the overall performance is significantly improved, making it particularly suitable for high-end smart terminal devices.

[0023] Through the above steps, the vacuum layer formed by vacuum coating completely eliminates the scattering and absorption of ultrasonic waves by air, greatly reducing signal transmission loss. The acoustic impedance matching between the PVDF piezoelectric layer and the vacuum medium is better, ensuring improved signal reception sensitivity. By ultra-thin stacking of PI and PVDF layers, combined with vacuum coating to replace the traditional metal shell, the overall packaging thickness is reduced to less than 0.3mm. The vacuum environment inhibits water and oxygen penetration, extending the sensor's lifespan. The collaborative design of the dummy silicon wafer and ASIC chip disperses thermal stress, resulting in less warpage. This achieves a triple breakthrough in high signal quality, ultra-thin thickness, and high reliability, providing an ideal packaging method for ultrasonic fingerprint recognition modules. This solves the problem that existing packaging methods cannot balance vacuum maintenance and mechanical strength, and may lead to film peeling or airtightness failure after long-term use.

[0024] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for packaging an ultrasonic fingerprint chip with a vacuum cavity, characterized in that: Includes the following steps: S1: Perform the first layer of metal wiring. A metal layer is deposited on the glass substrate by sputtering or evaporation. Interconnect lines are then formed using photolithography and etching processes. ; S2: Lay out the PI layer and PVDF layer; S3: Perform the second layer of metal wiring to obtain... ; S4: Plant SnAg metal bumps on the dummy silicon wafer, use ACF anisotropic conductive adhesive or ultrasonic welding process to fix the left dummy silicon wafer at the designated position of RDL2, flip-chip the ASIC chip, and the bump height is 3~50μm. S5: Vacuum lamination; S6: Plastic sealing; S7: Grinding exposes the ASIC chip and dummy silicon wafer; S8: Peel off the glass substrate; S9: Cutting.

2. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that: The thickness of the glass substrate is 10–180 μm, and the thickness of the glass substrate for support is 200–1200 μm.

3. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that... and The thickness of the metal layer is 50 μm.

4. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that: The order of laying the PI layer and PVDF layer is PI first, then PVDF. The PI layer is laid by spin coating, and the PVDF layer is laid by corona polarization.

5. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that: The surface of the dummy silicon wafer is provided with metal bumps, which are evenly distributed in the outer peripheral area of ​​the dummy silicon wafer.

6. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that: The specific methods of vacuum coating include: a) Place the flip-chip bonded assembly in a vacuum chamber and evacuate to ≤1× Pa; b) Form a thin film on the component surface by chemical vapor deposition, or press-fit a pre-cured PDMS film layer; c) Laser sealing is performed on the edges of the membrane layer to isolate the cavity from the outside world.

7. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that: The specific steps for lamination are as follows: a) Place the component in a vacuum injection mold and evacuate to ≤1 kPa; b) Inject epoxy resin molding compound and mold at 175℃ / 5MPa; c) After segmented curing, remove the protective film in the acoustic window area to form an ultrasonic transmission channel.

8. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that: The steps of grinding to expose the ASIC chip and dummy silicon wafer include: a) A chemical mechanical polishing process is used to thin the surface of the molded body with alumina polishing slurry until the metal pads of the ASIC chip and the metal bumps of the dummy silicon wafer are exposed. b) The grinding endpoint is controlled by an optical thickness gauge, the residual molding layer thickness is ≤5μm, and the surface roughness Ra of the ASIC chip pads is <0.05μm.

9. The packaging method for an ultrasonic fingerprint chip with a vacuum cavity according to claim 1, characterized in that: The stripping steps include: a) Place the glass substrate in an ultraviolet irradiation device with a wavelength of 365 nm and an energy density of 300 mJ / cm². 2 Irradiation causes temporary bonded adhesives to photodegrade and fail. b) The glass substrate is separated by a mechanical pick-up device with a vertical force of ≤10N, and the residual adhesive layer is completely removed by oxygen plasma cleaning.

Images