Gate driving circuit, display substrate, display device and driving method

Abstract

The invention provides a gate driving circuit, a display substrate, a display device and a driving method, and relates to the technical field of display. The gate driving circuit comprises a first driving unit electrically connected to a clock end, and the first driving unit is configured to output a first scanning signal in a blanking period under the control of a clock signal from the clock end and an initial signal from an initial end; and the second driving unit is electrically connected to the clock end, and the second driving unit is configured to output a second scanning signal in the display period under the control of the first scanning signal and the clock signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a gate driving circuit, a display substrate, a display device and a driving method. BACKGROUND

[0002] The display panel can include a display area and a non-display area, for example, the display area is scanned in a display period of a frame of display picture, and the non-display area is scanned in a blanking period of a frame of display picture.

[0003] There is a large difference between the load of the display period and the blanking period of the display panel, which causes the power voltage received by the driving circuit to be unstable, so that the capacitor connected with the power line in the circuit board will vibrate, the capacitor howling phenomenon occurs, and the user experience is affected. SUMMARY

[0004] The present disclosure provides a gate driving circuit, a display substrate, a display device and a driving method.

[0005] According to a first aspect, the present disclosure provides a gate driving circuit, comprising: a first driving unit electrically connected to a clock end; the first driving unit is configured to output a first scanning signal in a blanking period under the control of a clock signal from the clock end and a start signal from a start end; and a second driving unit electrically connected to the clock end, the second driving unit is configured to output a second scanning signal in a display period under the control of the first scanning signal and the clock signal.

[0006] For example, the clock end includes 2N clock ends, and the first driving unit is electrically connected to the 2N clock ends; the first driving unit includes M first shift registers in cascade, a first input end of an mth first shift register in the first driving unit is electrically connected to the start end, N≥m≥1, M is an integer multiple of 2N, and m, N and M are positive integers.

[0007] For example, the first input end of the mth first shift register is electrically connected to the output end of the mth-Nth first shift register, the first reset end of the mth first shift register is electrically connected to the output end of the mth+Nth first shift register, the second reset end of the mth first shift register is electrically connected to the output end of the mth+N+1th first shift register, and M-N>m>N.

[0008] For example, the first reset end of the mth first shift register is electrically connected to the output end of the mth-M+Nth first shift register, the second reset end of the mth first shift register is electrically connected to the output end of the mth-M+N+1th first shift register, and M≥m≥M-N+1 and M≥4N.

[0009] For example, the second input terminal of the mth first shift register is electrically connected to the output terminal of the m+M-Nth first shift register, N≥m≥1 and M≥4N.

[0010] For example, the second driving unit is electrically connected to 2N clock terminals; wherein the second driving unit comprises Q second shift registers in cascade, the output terminal of the mth first shift register is electrically connected to the first reset terminal of the m+Q-Nth second shift register, the output terminal of the mth first shift register is electrically connected to the second reset terminal of the m+Q-N-1th second shift register, N≥m≥1, Q>N, and Q is a positive integer.

[0011] For example, the second driving unit comprises Q second shift registers in cascade, the first input terminal of the mth first shift register is electrically connected to the output terminal of the m+Q-Nth second shift register, N≥m≥1.

[0012] For example, the third input terminal of the mth first shift register is electrically connected to a start terminal, N≥m≥1.

[0013] For example, the qth second shift register of the Q second shift registers in cascade comprises a shift register unit, Q≥q≥1 and q is a positive integer; and the mth first shift register comprises a shift register unit, a first transistor and a second transistor, N≥m≥1; wherein the shift register unit of the mth first shift register is electrically connected to a first power supply, a second power supply, a third power supply, a first input terminal, a first reset terminal, a second reset terminal and an output terminal; the control electrode of the first transistor is electrically connected to a third input terminal, the first electrode of the first transistor is electrically connected to the shift register unit, and the second electrode of the first transistor is electrically connected to the third power supply; the control electrode and the first electrode of the second transistor are electrically connected to a second input terminal, and the first electrode of the second transistor is electrically connected to the first electrode of the first transistor.

[0014] For example, the mth first shift register comprises a shift register unit, M≥m>N.

[0015] According to a second aspect, the present disclosure provides a display substrate, comprising: a timing control circuit configured to output a data enable signal under the control of a power supply voltage; a compensation circuit configured to compensate a first initial voltage under the control of the data enable signal and output a first driving voltage; and a gate driving circuit provided by the embodiments of the present disclosure and configured to output a first scan signal and a second scan signal under the control of the first driving voltage.

[0016] For example, the display substrate further comprises: a source driving circuit configured to output a data signal under the control of a second driving voltage, wherein the second driving voltage is determined by the compensation circuit based on a second initial voltage.

[0017] For example, the compensation circuit includes a first resistor, a second resistor, a first switch tube and a second switch tube; wherein the first end of the first resistor is electrically connected to the first end of the second resistor, the second end of the first resistor is electrically connected to the gate drive circuit; the second end of the second resistor is electrically connected to the control electrode of the first switch tube; the first electrode of the first switch tube is electrically connected to the first end of the first resistor, the second electrode of the first switch tube is electrically connected to the second end of the first resistor; and the control electrode of the second switch tube is electrically connected to the timing control circuit, the first electrode of the second switch tube is electrically connected to the first end of the first resistor, and the second electrode of the second switch tube is electrically connected to the fourth power supply.

[0018] According to a third aspect, the present disclosure provides a display device, comprising a display panel; and a display substrate as provided by the embodiments of the present disclosure, configured to output a first scan signal, a second scan signal and a data signal to the display panel.

[0019] For example, the display panel includes a first pixel circuit located in a non-display area and a second pixel circuit located in a display area; wherein the first pixel circuit is electrically connected to a first drive unit in a gate drive circuit included in the display substrate, and the second pixel circuit is electrically connected to a second drive unit in the gate drive circuit included in the display substrate.

[0020] According to a fourth aspect, the present disclosure provides a driving method applied to the gate drive circuit provided by the embodiments of the present disclosure, comprising: under the control of a clock signal and a start signal, outputting a first scan signal by a first drive unit in a blanking period; and under the control of the first scan signal and the clock signal, outputting a second scan signal by a second drive unit in a display period.

[0021] For example, the clock signal includes 2N clock signals; under the control of the clock signal and the start signal, the first drive unit outputs the first scan signal in the blanking period, including: under the control of the start signal and the first N clock signals of the 2N clock signals, outputting N first scan signals by the first N-stage first shift register in the cascade of the M first shift registers included in the first drive circuit; wherein the first level of the 2N clock signals is sequentially shifted and output, the n-th clock signal and the n+N-th clock signal in the 2N clock signals are not the first level at the same time, n is a positive integer, and N≥n≥1.

[0022] For example, the first timing change of the start signal is consistent with the second timing change of the start signal, wherein the first timing change is the timing change of the start signal in the period that the level of the 1st clock signal in the 2N clock signals in the blanking period is kept as the first level for the first time, and the second timing change is the timing change of the start signal in the period that the level of the 1st clock signal is kept as the first level for the (M / (2N))+1th time.

[0023] For example, during the blanking period, when the first clock signal changes from the first level to the second level for the M / (2N)th time, the start signal changes from the second level to the first level.

[0024] For example, during the display period, when the first clock signal of the 2N clock signals changes from the second level to the first level for the first time, the start signal changes from the second level to the first level, and the duration of the first level of the start signal is (M-N) / N times the duration of the first level of the first clock signal in one scan period.

[0025] According to a fifth aspect, the present disclosure provides a driving method applied to the display substrate provided by the embodiments of the present disclosure, including: compensating a first initial voltage under the control of a data enable signal, and outputting a first driving voltage; and outputting a first scan signal and a second scan signal under the control of the first driving voltage; wherein, during a display period, the data enable signal has a first level; during a blanking period, the data enable signal has a second level; the voltage value of the first driving voltage output based on the data enable signal having the second level is less than the voltage value of the first driving voltage output based on the data enable signal having the first level. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a structural schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0027] Figure 2 is a structural schematic diagram of a first driving unit according to an embodiment of the present disclosure;

[0028] Figure 3A is a structural schematic diagram of a first driving unit according to another embodiment of the present disclosure;

[0029] Figure 3B is a structural schematic diagram of a gate driving circuit according to another embodiment of the present disclosure;

[0030] Figure 4 is a signal timing diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0031] Figure 5 is a structural schematic diagram of a first driving unit according to another embodiment of the present disclosure;

[0032] Figure 6 is a signal timing diagram of a gate driving circuit according to another embodiment of the present disclosure;

[0033] Figure 7 is a structural schematic diagram of a first driving unit according to another embodiment of the present disclosure;

[0034] Figure 8is a structural schematic diagram of a first shift register according to an embodiment of the present disclosure;

[0035] Figure 9 is a signal timing diagram of a gate driving circuit according to another embodiment of the present disclosure;

[0036] Figure 10 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0037] Figure 11 is a structural schematic diagram of a display substrate according to another embodiment of the present disclosure;

[0038] Figure 12 is a schematic diagram of a power supply voltage according to an embodiment of the present disclosure;

[0039] Figure 13A is a structural schematic diagram of a display device according to an embodiment of the present disclosure;

[0040] Figure 13B is a structural schematic diagram of a display device according to another embodiment of the present disclosure;

[0041] Figure 14 is a flowchart of a driving method according to an embodiment of the present disclosure; and

[0042] Figure 15 is a flowchart of a driving method according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any creative effort fall within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals.

[0044] In the following description, some specific embodiments are only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it may cause confusion to the understanding of the present disclosure, the conventional structure or configuration will be omitted. It should be noted that the shapes and sizes of the components in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0045] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be interpreted as is customary in the art by a person skilled in the art. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components.

[0046] In addition, in the description of the present disclosure, the term "connected" or "connected to" can mean that two components are directly connected, or that two components are connected via one or more other components. In addition, the two components can be connected or coupled by wired or wireless means.

[0047] The source and drain of the switching transistor used in the present disclosure are symmetrical, so the source and drain can be interchangeable. In the present disclosure, the gate can be referred to as the control electrode, one of the source and drain can be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode according to its function.

[0048] In addition, in the description of the present disclosure, the terms "first power supply voltage", "second power supply voltage", "third power supply voltage", and "fourth power supply voltage" are only used to distinguish the amplitudes of two power supply voltages. For example, in the following description, "first power supply voltage" and "second power supply voltage" are described as relatively high voltages, and "third power supply voltage" and "fourth power supply voltage" are described as relatively low voltages. Those skilled in the art can understand that the present disclosure is not limited thereto.

[0049] It should be noted that in the description of the present disclosure, the symbol DOUT can represent both the output signal and the level of the output signal. Similarly, the symbol INPUT can represent both the input signal and the level of the input signal, the symbol CLK can represent both the clock terminal and the voltage of the clock signal, and VDD and VSS can represent both the power supply terminal and the power supply voltage provided by the power supply terminal. The following embodiments are the same as this, and similar parts will not be described again.

[0050] During the scanning time of a frame of picture, the load of the display panel in the display period and the blanking period changes greatly, so that the power supply voltage received by the driving circuit is unstable. The voltage value of the power supply voltage should be stable and unchanged, but simulation of the actual power supply voltage can find that there is a large ripple on the voltage value change curve of the power supply voltage.

[0051] On a printed circuit board (PCB), bypass or decoupling capacitors, such as ceramic capacitors, are connected to the power lines used to provide the power supply voltage. These ceramic capacitors are soldered onto the PCB. Ceramic capacitors exhibit the inverse piezoelectric effect; when the power supply voltage is unstable, the ceramic capacitor is subjected to an AC signal of a certain frequency and amplitude, causing elastic strain. Strong elastic strain generates vibration, which is transmitted to the PCB, causing PCB resonance. When the vibration reaches a certain frequency and the resulting sound falls within the audible range, capacitor howling occurs, affecting the user experience.

[0052] In one example, anti-squeak capacitors can be used, but these are expensive. For instance, tantalum capacitors cost more than 10 times more than ordinary ceramic capacitors, and bracket capacitors cost more than 50 times more. This significantly increases the cost of the display substrate, reducing the product's cost competitiveness.

[0053] To address the aforementioned issues, this disclosure provides a driving circuit that designs a gate on array (GOA) driving circuit for the non-display area of ​​the display panel and the timing of the signals driving the GOA. This allows the transistors of the pixel rows in the non-display area to be turned on row by row during the blanking period, and the data signals to charge the pixels in the non-display area. This reduces the difference in load between the display panel during the display period and the blanking period, thereby improving the stability of the power supply voltage, reducing the ripple caused by power supply voltage changes due to load variations, and improving the capacitor howling problem.

[0054] Figure 1 This is a schematic diagram of the gate drive circuit according to an embodiment of the present disclosure.

[0055] like Figure 1 As shown, the gate drive circuit 100 includes a first drive unit 110 and a second drive unit 120.

[0056] In this embodiment of the disclosure, both the first driving unit 110 and the second driving unit 120 are electrically connected to the clock terminal CLK.

[0057] Under the control of the clock signal CLK from the clock terminal CLK and the start signal SVT1 from the start terminal SVT1, the first drive unit 110 outputs the first scan signal DOUT during the blanking period. Under the control of the first scan signal DOUT and the clock signal CLK, the second drive unit 120 outputs the second scan signal OUT during the display period.

[0058] In the embodiments of the present disclosure, the first scan signal DOUT is provided to dummy pixels. The dummy pixels are located in a non-display area of the display panel. The dummy pixels are invisible to a user. For example, the dummy pixels are shielded by a frame of the display device, so that the dummy pixels are invisible, and the area where the dummy pixels are located forms the non-display area of the display panel. For another example, the dummy pixels are shielded by a light shielding layer such as a black matrix (BM), so that the dummy pixels are invisible. For another example, the dummy pixels are shielded by a structure such as a backplane, so that the dummy pixels are invisible.

[0059] In the embodiments of the present disclosure, the second scan signal OUT is provided to light-emitting pixels. The light-emitting pixels are located in a display area of the display panel. The light-emitting pixels are visible to a user.

[0060] In the embodiments of the present disclosure, the display process of a frame of picture includes a display period and a blanking period. Under the control of the clock signal CLK, the second driving unit 120 provides the second scan signal OUT to the light-emitting pixels in the display period, to realize line-by-line scanning of the pixel rows composed of the light-emitting pixels. The pixel rows composed of the light-emitting pixels display the frame of picture in the display period, and enter the blanking period after the display period ends. Under the control of the clock signal CLK and the start signal STV1, the first driving unit 110 provides the first scan signal DOUT to the dummy pixels in the blanking period, to realize line-by-line scanning of the pixel rows composed of the dummy pixels.

[0061] The first scan signal DOUT can be provided to the second driving unit 120. Under the control of the first scan signal DOUT, the second driving unit 120 can be reset in the blanking period, to output the second scan signal OUT for the next frame of picture to the light-emitting pixels in the display period for the next frame of picture. For example, in the blanking period, the level of the first scan signal DOUT provided to the second driving unit 120 is switched between a high level and a low level, and the second driving unit 120 is reset under the control of the high level of the first scan signal DOUT. In the display period, when the second driving unit 120 outputs the second scan signal OUT with a high level, the level of the first scan signal DOUT provided to the second driving unit 120 can remain at a low level.

[0062] In the embodiments of the present disclosure, in the display period, the second scan signal OUT scans the light-emitting pixels, so that the data signal charges the light-emitting pixels. In the blanking period, the first scan signal DOUT scans the dummy pixels, so that the data signal can charge the dummy pixels. This can reduce the difference between the load of the display panel in the display period and the load of the display panel in the blanking period.

[0063] In this embodiment of the present disclosure, under the control of the start signal STV1, the first driving unit 110 can scan the virtual pixels multiple times. For example, after the first scan signal DOUT completes the scanning of the last row of pixels in the row of virtual pixels, if the reset of all light-emitting pixels has not been completed, the first driving unit 110 can be triggered again by the start signal STV1, so that the first driving unit 110 outputs the first scan signal OUT again to scan the virtual pixels, thereby providing sufficient time for the reset of the light-emitting pixels.

[0064] For example, by controlling the duration of the blanking period, all luminous pixels can be reset within the blanking period. During the blanking period, the first driving unit 110 is repeatedly triggered by the start signal STV1 to output the first scan signal DOUT, thereby cyclically scanning the pixel rows composed of virtual pixels. This ensures that the data signal can continuously charge the virtual pixels during the blanking period, thereby reducing the difference in load between the display panel during the display period and the blanking period, improving the stability of the power supply voltage, reducing the ripple of power supply voltage changes caused by load variations, and improving the capacitor howling problem.

[0065] Figure 2 This is a schematic diagram of the structure of the first driving unit according to an embodiment of the present disclosure.

[0066] like Figure 2 As shown, the first driving unit 210 includes M cascaded first shift registers D1 to DM. The first driving unit 210 outputs first scan signals DOUT(1) to DOUT(M) to the M rows of virtual pixels in the display panel to drive the M rows of virtual pixels. The clock terminals include 2N clock terminals CLK1 to CLK2N. The M first shift registers D1 to DM are electrically connected to the 2N clock terminals CLK1 to CLK2N, where N and M are positive integers.

[0067] In this embodiment, the first input terminal INPUT1 of the m-th stage first shift register is electrically connected to the start terminal STV1, where N ≥ m ≥ 1, M is an integer multiple of 2N, and N and M are positive integers. For example, the first input terminal INPUT1 of the first stage first shift register D1 is electrically connected to the start terminal STV1. Under the control of the start signal STV1, the first N stages of first shift registers D1 to DN output first scan signals DOUT(1) to DOUT(N). The first scan signals output by each of the first N stages of first shift registers D1 to DN are provided to their respective cascaded next-stage first shift registers, thereby driving their respective cascaded next-stage first shift registers to output first scan signals.

[0068] In the embodiment of the present disclosure, by controlling the timing of the start signal STV1, the first N-stage first shift register outputs the corresponding first scan signal DOUT, so that the M first shift registers D1-DM included in the first driving unit 210 can output the corresponding first scan signal. For example, after the M first shift registers D1-DM complete the scanning of the M rows of virtual pixels, the first N-stage first shift register is triggered again to output the corresponding first scan signal DOUT based on the start signal STV1, so that the M first shift registers D1-DM realize the cyclic scanning of the M rows of virtual pixels.

[0069] In the embodiment of the present disclosure, the number of first shift registers included in the first driving unit 210 can be an integer multiple of the number of clock terminals, that is, M is an integer multiple of 2N. The M first shift registers D1-DM in cascade are respectively electrically connected with the 2N clock terminals CLK1-CLK2N. For example, every 2N first shift registers in the M first shift registers D1-DM in cascade are respectively electrically connected with the 2N clock terminals CLK1-CLK2N. For example, the first first shift register D1, the first+2N first shift register are electrically connected with the clock terminal CLK1, the second first shift register, the second+2N first shift register are electrically connected with the clock terminal CLK2, …, the 2N first shift register, the 4N first shift register are electrically connected with the clock terminal CLK2N.

[0070] In the embodiment of the present disclosure, the first input end INPUT1 of the mth first shift register Dm of the first driving unit 210 is electrically connected with the output end DOUT of the m-Nth first shift register Dm-N, the first reset end RST1 of the mth first shift register Dm is electrically connected with the output end DOUT of the m+ Nth first shift register Dm+N, the second reset end RST2 of the mth first shift register Dm is electrically connected with the output end DOUT of the m+ N+1th first shift register Dm+N+1, M-N>m>N, and M and m are positive integers.

[0071] In the embodiment of the present disclosure, the first N-stage first shift register in the first driving unit 210 receives the start signal STV1. When the display period enters the blanking period, under the control of the start signal STV1, the first N-stage first shift register respectively outputs the respective first scan signal and drives the respective next-stage first shift register in cascade.

[0072] For example, during the blanking period, the first scan signal DOUT(mN) output by the mNth stage first shift register Dm-N serves as the input signal to the mth stage first shift register Dm, driving the mth stage first shift register Dm to output the first scan signal DOUT(m). The first scan signal DOUT(m+N) output by the m+Nth stage first shift register Dm+N+1 and the first scan signal DOUT(mm+N+1) output by the m+N+1th stage first shift register Dm resets the mth stage first shift register Dm, enabling the mth stage first shift register Dm to scan the next frame.

[0073] In this embodiment of the disclosure, the m-th stage first shift register Dm is also electrically connected to a first power supply VDD1, a second power supply VDD2, and a third power supply VSS. The first power supply VDD1, the second power supply VDD2, and the third power supply VSS provide the first power supply voltage VDD1, the second power supply voltage VDD2, and the third power supply voltage VSS to the M cascaded first shift registers D1 to DM in the first drive unit 210.

[0074] In this embodiment, when transitioning from a display period to a blanking period, a start signal STV1 is used to drive the first driving unit 210, enabling the first driving unit 210 to output a first scan signal DOUT to the virtual pixels in the non-display area during the blanking period. During the blanking period, the transistors of the virtual pixel rows in the non-display area can be turned on row by row, allowing data signals to charge the virtual pixels in the non-display area. This reduces the difference in load between the display panel during the display period and the blanking period, thereby improving power supply voltage stability, reducing the ripple caused by load changes in the power supply voltage, and mitigating capacitor howling issues.

[0075] Taking N=3 and M=6 as an example, combined with Figure 3A The first drive unit is described by way of example.

[0076] Figure 3A This is a schematic diagram of the structure of a first driving unit according to another embodiment of the present disclosure.

[0077] like Figure 3A As shown, the first driving unit 310 is electrically connected to six clock terminals CLK1 to CLK6. The first driving unit 310 includes six cascaded first shift registers D1 to D6.

[0078] In the embodiment of the present disclosure, the first input end INPUT1 of the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 is electrically connected to the start end STV1. The start signal STV1 from the start end STV1 is taken as the input signal of the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3, so that the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 generate the first scanning signal DOUT to drive the next-stage first shift register in the respective cascade.

[0079] By controlling the timing of the start signal STV1, after the sixth-stage first shift register D6 outputs the first scanning signal DOUT(6), the start signal STV1 re-drives the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3. This makes it possible to re-drive the first-stage first shift register D1, the second-stage first shift register D2 and the third-stage first shift register D3 when the sixth-stage first shift register D6 outputs the first scanning signal DOUT(6) but the blanking period has not ended, so as to realize the cyclic scanning of the first driving unit 210 including the cascade of the six first shift registers D1-D6 until the display period is switched from the blanking period.

[0080] For example, the first scanning signal DOUT(1) output by the first-stage first shift register D1 is taken as the input signal of the fourth-stage first shift register D4, so as to drive the fourth-stage first shift register D4 to output the first scanning signal DOUT(4). The first scanning signal DOUT(4) output by the fourth-stage first shift register D4 and the first scanning signal DOUT(5) output by the fifth-stage first shift register D5 reset the first-stage first shift register D1, so as to make the first-stage first shift register D1 scan in the next frame.

[0081] For example, the first scanning signal DOUT(2) output by the second-stage first shift register D2 is taken as the input signal of the fifth-stage first shift register D5, so as to drive the fifth-stage first shift register D5 to output the first scanning signal DOUT(5). The first scanning signal DOUT(5) output by the fifth-stage first shift register D5 and the first scanning signal DOUT(6) output by the sixth-stage first shift register D6 reset the second-stage first shift register D2, so as to make the second-stage first shift register D2 scan in the next frame.

[0082] For example, the first scanning signal DOUT(3) output by the third stage first shift register D3 is taken as the input signal of the sixth stage first shift register D6, and the sixth stage first shift register D6 is driven to output the first scanning signal DOUT(6). The first scanning signal DOUT(5) output by the fifth stage first shift register D5 resets the third stage first shift register D3, so that the third stage first shift register D3 performs scanning in the next frame.

[0083] Hereinafter, N=3 and M=6 are taken as an example, Figure 3B The structure of the gate drive circuit shown in the figure is taken as an example, and the working process of the gate drive circuit provided by the embodiment of the present application is described in combination with Figure 4 The signal timing diagram shown in the figure describes the working process of the gate drive circuit provided by the embodiment of the present application.

[0084] Figure 3B The structure of the gate drive circuit according to another embodiment of the present disclosure is shown in the figure.

[0085] As Figure 3B The gate drive circuit 300 includes a first driving power supply 310 and a second driving unit 320, as shown in the figure.

[0086] In the embodiment of the present disclosure, Figure 3B The first driving unit 310 shown in the figure can refer to the first driving unit 310 described in the foregoing Figure 3A , and will not be described again for the sake of simplicity.

[0087] In the embodiment of the present disclosure, the second driving unit 320 is electrically connected to 6 clock terminals CLK1-CLK6. The second driving unit 320 includes Q second shift registers G1-GQ connected in cascade, Q>N, Q being a positive integer. The second driving unit 320 outputs second scanning signals OUT(1)-OUT(Q) to the light-emitting pixels in the display area of the display panel, and the display picture displayed by the light-emitting pixels in the display area is visible to the user.

[0088] For example, the number of the second shift registers included in the second driving unit 320 can be an integer multiple of the number of the clock terminals. The Q second shift registers G1-GQ connected in cascade are respectively electrically connected to the 6 clock terminals CLK1-CLK6. For example, every 6 second shift registers among the Q second shift registers G1-GQ connected in cascade are respectively electrically connected to the 6 clock terminals CLK1-CLK6. For example, the first stage second shift register Q1, the seventh stage second shift register Q7 are electrically connected to the clock terminal CLK1, the second stage second shift register Q2, the eighth stage second shift register Q8 are electrically connected to the clock terminal CLK2, and so on, the Q-6 stage second shift register Q(Q-6), the Q stage second shift register Q(Q) are electrically connected to the clock terminal CLK6.

[0089] In the embodiment of the present disclosure, the Q second shift registers G1-GQ in cascade are also electrically connected with the first power supply VDD1, the second power supply VDD2 and the third power supply VSS. The first power supply VDD1, the second power supply VDD2 and the third power supply VSS provide the first power supply voltage VDD1, the second power supply voltage VDD2 and the third power supply voltage VSS for the Q second shift registers G1-GQ in cascade. The first stage second shift register G1 is also electrically connected with the start terminal STV0, and the start terminal STV0 provides a start signal STV0 for the first stage second shift register G1.

[0090] In the embodiment of the present disclosure, the cascade relationship between the Q second shift registers G1-GQ included in the second driving unit 320 is similar to the cascade relationship between the M first shift registers D1-DM included in the first driving unit 310, and the details are not described herein for simplicity.

[0091] In the embodiment of the present disclosure, the first N stage first shift registers of the first driving unit 310 are electrically connected with the second shift registers in the second driving unit 320. The output terminal of the mth stage first shift register is electrically connected with the first reset terminal of the m+Q-Nth stage second shift register, and the output terminal of the mth stage first shift register is electrically connected with the second reset terminal of the m+Q-N-1th stage second shift register, where N≥m≥1.

[0092] For example, the first reset terminal RST1 of the Qth stage second shift register GQ is electrically connected with the output terminal DOUT of the 3rd stage first shift register D3, and the second reset terminal RST2 of the Qth stage second shift register GQ is electrically connected with the output terminal DOUT of the 4th stage first shift register D4. The output terminal DOUT of the 1st stage first shift register D1 is electrically connected with the first reset terminal RST1 of the Q-2th stage second shift register, and the output terminal of the 1st stage first shift register D1 is electrically connected with the second reset terminal RST2 of the Q-3th stage second shift register.

[0093] In the embodiment of the present disclosure, the first 4 stages of the first driving unit 310 are used to reset the Q-3th stage second shift register, the Q-2th stage second shift register, the Q-1th stage second shift register and the Qth stage second shift register GQ in the second driving unit 320.

[0094] In the embodiment of the present disclosure, after the Qth stage second shift register GQ outputs the second scan signal OUT(Q), the start signal STV1 triggers the 1st stage first shift register D1, the 2nd stage first shift register D2 and the 3rd stage first shift register D3 to output the respective first scan signals.

[0095] Figure 4 is a signal timing diagram of the gate driving circuit according to the embodiment of the present disclosure. Figure 4The timing waveforms of each signal are shown.

[0096] Figure 4 The diagram shows the display period P1, blanking period P2, and display period P3. For example, the scan time for the first frame may include the display period P1 and the blanking period P2, and the scan time for the second frame may include the display period P2. The end of the blanking period P2 indicates the end of the scan for the first frame. Entering the display period P3 indicates the start of the scan for the second frame.

[0097] like Figure 4 As shown, the data enable signal DE indicates the type of scan period. For example, when the data enable signal DE is high, the current scan period is the display period, using... Figure 3B The second driving unit 320 shown scans the light-emitting pixels of the display area. When the data enable signal DE is low, the current scanning period is the blanking period, using... Figure 3B The first driving unit 310 shown scans the virtual pixels in the non-display area.

[0098] In this embodiment of the present disclosure, under the control of the six clock signals CLK1 to CLK6 from the six clock terminals CLK1 to CLK6, six first scan signals DOUT(1) to DOUT(6) are output through the six cascaded first shift registers D1 to D6, and Q second scan signals OUT(1) to OUT(Q) are output through the Q cascaded second shift registers G1 to GQ.

[0099] like Figure 4 As shown, the first levels of the six clock signals CLK1 to CLK6 are sequentially shifted and output. For example, if the first level is high, the six clock signals CLK1 to CLK6 will sequentially jump to high levels. There are periods when clock signals CLK1, CLK2, and CLK3 are all at high levels, and there are periods when clock signals CLK4, CLK5, and CLK6 are all at high levels. Clock signals CLK1 and CLK4 are not simultaneously high, clock signals CLK2 and CLK5 are not simultaneously high, and clock signals CLK3 and CLK6 are not simultaneously high. For example, when clock signal CLK1 is high, clock signal CLK3 is low, and when clock signal CLK1 is low, clock signal CLK3 is high.

[0100] In this embodiment, the level changes of the six clock signals CLK1 to CLK6 during the display period P1, blanking period P2, and display period P3 follow the same pattern. During the blanking period P2, the six clock signals CLK1 to CLK6 are continuously output.

[0101] In the first stage 1 of the display period P1, the data enable signal DE is at high level, the start signal STV0 is at high level, and the clock signal CLK1 is at low level. In the second stage 2 of the display period P1, the data enable signal DE is at high level, the start signal STV0 is at high level, and the clock signal CLK1 is at high level. In the third stage 3 of the display period P1, the data enable signal DE is at high level, the start signal STV0 is at low level, and the clock signal CLK1 is at high level. In the fourth stage 4 of the display period P1, the data enable signal DE is at high level, the start signal STV0 is at low level, the start signal STV1 is at high level, and the clock signal CLK1 is at low level.

[0102] In the fifth stage 5 of the blanking period P2, the data enable signal DE is at low level, the start signal STV1 is at high level, and the clock signal CLK1 is at high level. In the sixth stage 6 of the blanking period P2, the data enable signal DE is at low level, the start signal STV1 is at low level, and the clock signal CLK1 is at high level. In the seventh stage 7 of the blanking period P2, the data enable signal DE is at low level, the start signal STV1 is at high level, and the clock signal CLK1 is at low level. In the eighth stage 8 of the blanking period P2, the data enable signal DE is at low level, the start signal STV1 is at high level, and the clock signal CLK1 is at high level.

[0103] In the embodiments of the present disclosure, the change rules of the start signal STV0 and the clock signal CLK1 in the first stage 1, the second stage 2 and the third stage 3 are the same as the change rules of the start signal STV1 and the clock signal CLK1 in the fourth stage 4, the fifth stage 5 and the sixth stage 6.

[0104] For example, the duration of high level in one period of the clock signal CLK1 is 3H, and the duration of low level is 3H. The duration of high level of the start signal STV0 is 5H, and the duration of high level in one period of the start signal STV1 is 5H. The start signal STV0 is high by 3H in advance relative to the clock signal CLK1. When the start signal STV0 is high, the start signal STV0 triggers the first-stage second shift register G1 to output the second scan signal OUT(1).

[0105] The start signal STV1 is high for 3H earlier than the first high level of the clock signal CLK1 in the blanking period P2. In the fifth stage 5 of the blanking period P2, the high level of the start signal STV1 lasts for 2H. When the start signal STV1 is high in the fifth stage 5 of the blanking period P2, the start signal STV1 triggers the first stage first shift register D1 to output the first scanning signal DOUT(1). Since the first three stages of the first shift registers all receive the start signal STV1 as the output signal, the first three stages of the first shift registers each output to the next stage of the first shift register in the cascade under the control of the start signal STV1 from the start end STV1.

[0106] For example, when M=6 and N=3, the first stage first shift register D1 outputs to the fourth stage first shift register D4. After the fourth stage first shift register D4, the fifth stage first shift register D5, and the sixth stage first shift register D6 output the first scanning signal in turn, the first driving unit 310 realizes one driving of all the virtual pixels in the non-display area of the display panel.

[0107] If the data enable signal DE still remains low after one driving of all the virtual pixels is completed, the start signal STV1 needs to be high again, so that the start signal STV1 triggers the first stage first shift register D1, the second stage first shift register D2, and the third stage first shift register D3 to output the first scanning signal again.

[0108] The first stage first shift register D1 is electrically connected to the clock end CLK1, and the fourth stage first shift register D4 is electrically connected to the clock end CLK4.

[0109] In the fifth stage 5 and the sixth stage 6 of the blanking period P2, the clock signal CLK1 is high, and under the control of the clock signal CLK1 and the start signal STV1, the first stage first shift register D1 outputs the first scanning signal DOUT(1) (the first first scanning signal DOUT(1) output under the control of the first high level of the clock signal CLK1 in the blanking period P2). In the seventh stage 7, under the control of the clock signal CLK4 and the first scanning signal DOUT(1), the fourth stage first shift register D4 outputs the first scanning signal DOUT(4) (the first first scanning signal DOUT(4) output under the control of the first high level of the clock signal CLK4 in the blanking period P2).

[0110] In the embodiments of the present disclosure, when it is needed to scan and drive the virtual pixels again, the timing of the start signal STV1 in the fifth stage 5 can be repeated in the eighth stage 8, so that the first stage first shift register D1 outputs the first scanning signal DOUT(1) with a high level again in the eighth stage 8.

[0111] Based on this, in order to determine that the signal timing of the second time that the start signal STV1 is set high is consistent with the signal timing of the first time that the start signal STV1 is set high, the start signal STV1 is changed from low to high when the clock signal CLK1 is changed from high to low for the first time in the blanking period P2, thereby achieving re-setting high of the start signal STV1.

[0112] For example, N=3, M=6, and the first driving unit 310 includes a number of first shift registers that is one time the number of clock terminals. The first clock signal CLK1 is in high level for the first time in the blanking period P2, thereby controlling the first shift register D1 of the first stage to output the first scanning signal DOUT(1) with high level. The fourth clock signal CLK4 is in high level for the first time in the blanking period P2, thereby controlling the first shift register D4 of the fourth stage to output the first scanning signal DOUT(4) with high level.

[0113] When it is required to cyclically scan the virtual pixel, the second clock signal CLK1 is in high level in the blanking period P2, thereby controlling the first shift register D1 of the first stage to output the first scanning signal DOUT(1) with high level. In order to determine that the signal change rule between the high level of the start signal STV1 and the clock signal CLK1 is consistent, it is required to control the start signal STV1 to change from low to high when the clock signal CLK1 is changed from high to low for the first time in the blanking period P2. At this time, the period of the start signal STV1 is one time the period of the clock signal CLK1.

[0114] In the embodiment of the present disclosure, the number of first shift registers is M / (2N) times the number of clock terminals. The clock terminal CLK1 is electrically connected with M / (2N) first shift registers in the M first shift registers, and thus when it is required to cyclically scan the virtual pixel, the first shift register D1 of the first stage can be driven to output the first scanning signal DOUT(1) with high level under the control of the clock signal CLK1 being in high level for the (M / (2N))+1 time. At this time, the first timing change of the start signal is consistent with the second timing change of the start signal STV1, wherein the first timing change is the timing change of the start signal in the period that the level of the first clock signal is kept as the first level for the first time in the blanking period, and the second timing change is the timing change of the start signal in the period that the level of the first clock signal is kept as the first level for the (M / (2N))+1 time in the blanking period.

[0115] Since the 3H start signal STV1 is first set to high level before the clock signal CLK1 is first set to high level in the blanking period P2, and the duration of high level and low level of the clock signal CLK1 is 3H, in the blanking period, when the 1st clock signal changes from high level to low level for the M / (2N)th time, the start signal STV1 changes from low level to high level. At this time, the period of the start signal STV1 is M / (2N) times of the period of the clock signal CLK1.

[0116] For example, the duration of high level in one period of the clock signal CLK1 is 3H, and the duration of low level in one period of the clock signal CLK1 is 3H. The duration of high level in one period of the start signal STV1 is 5H, and the duration of low level in one period of the start signal STV1 is 1H.

[0117] In the embodiment of the present disclosure, after one period (6H) of the start signal STV1 is passed, the level of the data enable signal DE can be detected. If it is detected that the data enable signal DE is still low level, the start signal STV1 is set high again, so that the first driving unit 310 drives the virtual pixel circuit again. If the data enable signal DE is always low level, the start signal STV1 can be set high repeatedly, so as to realize the repeated scanning and driving of the virtual pixel circuit by the first driving unit 310. If it is detected that the data enable signal DE jumps from low level to high level, the start signal STV1 can be set high-low, and the start signal STV1 is kept low level.

[0118] In the embodiment of the present disclosure, under the driving of the clock signal CLK1 to the clock signal CLK6, the Q second shift registers G1 to GQ included in the second driving unit 320 output the second scanning signals OUT(1) to OUT(Q) in turn. The second scanning signals OUT(1) to OUT(Q) are high level shift output, and the scanning signals OUT(1) to OUT(Q) jump to high level in turn.

[0119] After the data enable signal DE jumps from low level to high level, the blanking period P2 ends and enters the display period P3. The change rule of each signal in the display period P3 is similar to that in the display period P1, and is not described herein for simplicity.

[0120] In this embodiment of the disclosure, the timing of the start signal STV1 is designed so that the start signal STV1 is set high at a specific time. This allows the virtual pixel to be scanned cyclically during the blanking period P2, so that the data signal can continuously charge the virtual pixel during the blanking period P2. This reduces the difference between the load of the display panel during the display period and the blanking period, improves the stability of the power supply voltage, reduces the ripple of the power supply voltage change caused by load changes, and improves the capacitor howling problem.

[0121] The following uses N=3, M=12, Figure 5 Taking the structure of the first driving unit shown as an example, combined with... Figure 6 The signal timing diagram shown describes the operation of the first driving unit provided in the embodiment of the present invention.

[0122] Figure 5 This is a schematic diagram of the structure of a first driving unit according to another embodiment of the present disclosure.

[0123] like Figure 5 As shown, the first driving unit 510 is electrically connected to six clock terminals CLK1 to CLK6. The first driving unit 510 includes 12 cascaded first shift registers D1 to D12.

[0124] In this embodiment of the disclosure, Figure 5 The connection relationship between the cascaded first shift registers D1 to D9 is similar to that shown in Figure 3, and will not be repeated here for simplicity. The connection relationship between the first drive unit 510 and the second drive unit is similar to that shown in Figure 3. Figure 3B The connection relationship between the first drive unit 310 and the second drive unit 320 shown is similar, and will not be repeated here for the sake of simplicity.

[0125] In this embodiment of the disclosure, the first reset terminal RST1 of the m-th stage first shift register is electrically connected to the output terminal DOUT of the m-M+N-th stage first shift register, and the second reset terminal RST2 of the m-th stage first shift register is electrically connected to the output terminal DOUT of the m-M+N+1-th stage first shift register, where M≥m≥M-N+1 and M≥4N.

[0126] For example, the first reset terminal RST1 of the m-th stage first shift register is electrically connected to the output terminal DOUT of the (m-9)-th stage first shift register, and the second reset terminal RST2 of the m-th stage first shift register is electrically connected to the output terminal DOUT of the (m-8)-th stage first shift register, where 12 ≥ m ≥ 10.

[0127] For example, the first reset terminal RST1 of the 12th stage first shift register D12 is electrically connected to the output terminal DOUT of the 3rd stage first shift register D3, and the second reset terminal RST2 of the 12th stage first shift register D12 is electrically connected to the output terminal DOUT of the 4th stage first shift register D4.

[0128] For example, the first reset terminal RST2 of the 11th stage first shift register D11 is electrically connected to the output terminal DOUT of the 2nd stage first shift register D2, and the second reset terminal RST2 of the 11th stage first shift register D11 is electrically connected to the output terminal DOUT of the 3rd stage first shift register D3.

[0129] For example, the first reset terminal RST2 of the 10th stage first shift register D10 is electrically connected to the output terminal DOUT of the 1st stage first shift register D1, and the second reset terminal RST2 of the 10th stage first shift register D10 is electrically connected to the output terminal DOUT of the 2nd stage first shift register D2.

[0130] In this embodiment, the first scan signals DOUT(1) to DOUT(3) output from the first three stages of the first shift register are used to reset the last three stages of the first shift register. This can improve the pull-down effect in the last three stages of the first shift register.

[0131] Figure 6 This is a signal timing diagram of a gate drive circuit according to another embodiment of the present disclosure. Figure 6 The timing waveforms of each signal are shown.

[0132] In this embodiment of the disclosure, Figure 6 The display period P1, the blanking period P2, and the display period P3 are shown. Figure 6 The timing variation patterns of the six clock signals CLK1 to CLK6 are shown. Figure 4 The variation pattern shown is the same, and will not be repeated for simplicity. Under the control of the six clock signals CLK1 to CLK6 from the six clock terminals CLK1 to CLK6, the cascaded twelve first shift registers D1 to D12 output twelve first scan signals DOUT(1) to DOUT(12). The cascaded Q second shift registers G1 to GQ output Q second scan signals OUT(1) to OUT(Q).

[0133] In the embodiment of the present disclosure, when M=12 and N=3, the first-stage first shift register D1 outputs the first scanning signal to the fourth-stage first shift register D4, the fourth-stage first shift register D4 outputs the first scanning signal to the seventh-stage first shift register D7, and the seventh-stage first shift register D7 outputs the first scanning signal to the tenth-stage first shift register D10. After the tenth-stage first shift register D10, the eleventh-stage first shift register D11 and the twelfth-stage first shift register D12 output the first scanning signal in turn, the first driving unit 510 realizes one-time driving of all virtual pixels in the non-display area of the display panel.

[0134] If the data enable signal DE still remains at the low level after one-time driving of all virtual pixels is completed, the start signal STV1 needs to be raised again, so that the start signal STV1 triggers the first-stage first shift register D1 to output the first scanning signal again.

[0135] The first-stage first shift register D1 and the seventh-stage first shift register D7 are electrically connected with the clock terminal CLK1, and the fourth-stage first shift register D4 and the tenth-stage first shift register D10 are electrically connected with the clock terminal CLK4.

[0136] In the first stage 1 of the blanking period P2, the clock signal CLK1 is at the high level. Under the control of the clock signal CLK1 and the start signal STV1, the first-stage first shift register D1 outputs the first scanning signal DOUT(1) with the high level. In the second stage 2 of the blanking period P2, the clock signal CLK4 is at the high level. Under the control of the clock signal CLK4 and the first scanning signal DOUT(1), the fourth-stage first shift register D4 outputs the first scanning signal DOUT(4) with the high level. In the third stage 3 of the blanking period P2, the clock signal CLK1 is at the high level. Under the control of the clock signal CLK1 and the first scanning signal DOUT(4), the seventh-stage first shift register D7 outputs the first scanning signal DOUT(7) with the high level. In the fourth stage 4 of the blanking period P2, the clock signal CLK4 is at the high level. Under the control of the clock signal CLK4 and the first scanning signal DOUT(7), the tenth-stage first shift register D10 outputs the first scanning signal DOUT(10) with the high level.

[0137] In the embodiment of the present disclosure, when it is needed to perform re-scanning driving on the virtual pixels, the timing of the start signal STV1 in the first stage 1 can be repeated in the fifth stage 5, so that the first-stage first shift register D1 outputs the first scanning signal DOUT(1) with the high level again in the fifth stage 5.

[0138] Based on this situation, to ensure that the timing of the start signal STV1 being set high for the second time is consistent with the timing of the first time it is set high, that is, to ensure that the timing change of the start signal STV1 during the period when the clock signal CLK1 is held high for the first time during the blanking period is consistent with the timing change of the start signal STV1 during the period when the clock signal CLK1 is held high for the third time during the blanking period, the start signal STV1 is set high again when the clock signal CLK1 changes from high to low for the second time during the blanking period P2.

[0139] For example, when N=3 and M=12, the number of first shift registers included in the first driving unit 510 is twice the number of clock terminals. During the blanking period P2, the first high level of the clock signal CLK1 controls the output of the first-stage first shift register D1 to produce a high-level first scan signal DOUT(1), and the second high level of the clock signal CLK1 during the blanking period P2 controls the output of the seventh-stage first shift register D7 to produce a high-level first scan signal DOUT(7). During the blanking period P2, the first high level of the clock signal CLK4 controls the output of the fourth-stage first shift register D4 to produce a high-level first scan signal DOUT(4), and the second high level of the clock signal CLK4 during the blanking period P2 controls the output of the tenth-stage first shift register D10 to produce a high-level first scan signal DOUT(10).

[0140] When cyclic scanning of virtual pixels is required, the third high-level signal of clock signal CLK1 during the blanking period P2 controls the first shift register D1 of stage 1 to output a high-level first scan signal DOUT(1). To ensure that the high level of the start signal STV1 matches the signal change pattern of clock signal CLK1, it is necessary to control the start signal STV1 to change from low to high during the blanking period P2 when clock signal CLK1 changes from high to low for the second time. At this time, the period of the start signal STV1 is twice the period of clock signal CLK1.

[0141] Figure 7 This is a schematic diagram of the structure of a first driving unit according to another embodiment of the present disclosure.

[0142] like Figure 7 As shown, the first drive unit 710 is electrically connected to six clock terminals CLK1 to CLK6. The first drive unit 710 includes 12 cascaded first shift registers D1 to D12.

[0143] In this embodiment of the disclosure, Figure 7 The connection relationship between the cascaded first shift registers D3 to D12 is shown. Figure 5The connection relationship shown is similar, and will not be described again here for the sake of brevity of the disclosure.

[0144] The connection relationship between the output terminals of the first, second and third first shift registers D1, D2 and D3 of the first driving unit 710 and the second driving unit can be referred to Figure 3B The connection relationship shown between the output terminals of the first, second and third first shift registers D1, D2 and D3 and the second driving unit 320 will not be described again here for the sake of brevity of the disclosure.

[0145] In the embodiment of the disclosure, the first input terminal INPUT1 of the mth first shift register is electrically connected to the output terminal of the m+Q-Nth second shift register, the second input terminal INPUT2 of the mth first shift register is electrically connected to the output terminal of the m+M-Nth first shift register, and the third input terminal INPUT3 of the mth first shift register is electrically connected to the start terminal STV1, N≥m≥1 and M≥4N.

[0146] For example, the second input terminal INPUT2 of the first first shift register D1 is electrically connected to the output terminal DOUT of the tenth first shift register D10, the second input terminal INPUT2 of the second first shift register D2 is electrically connected to the output terminal DOUT of the eleventh first shift register D11, and the second input terminal INPUT2 of the third first shift register D3 is electrically connected to the output terminal DOUT of the twelfth first shift register D12.

[0147] In the embodiment of the disclosure, the output terminal DOUT of the last N first shift registers is electrically connected to the second input terminal INPUT2 of the first N first shift registers, the first N first shift registers are connected in a loop, and the first scanning signals output by the last N first shift registers are used to drive the first N first shift registers, thereby realizing the loop scanning of the first driving unit 710.

[0148] For example, when the display period enters the blanking period, the Q-2th, Q-1th and Qth second shift registers of the second driving unit output second scanning signals to the first input terminals INPUT1 of the first, second and third first shift registers D1, D2 and D3, respectively. Based on the second scanning signals provided by the Q-2th, Q-1th and Qth second shift registers, the first driving unit 710 performs the first round of scanning on the virtual pixels.

[0149] If the data enable signal DE remains low after a complete driving of all the virtual pixels, the first scan signals outputted by the 10th first shift register D10, the 11th first shift register D11 and the 12th first shift register D12 can be respectively inputted to the second input terminals INPUT2 of the 1st first shift register D1, the 2nd first shift register D2 and the 3rd first shift register D3, so that the 1st first shift register D1, the 2nd first shift register D2 and the 3rd first shift register D3 start a second round of scanning of the virtual pixels based on the first scan signals outputted by the 10th first shift register D10, the 11th first shift register D11 and the 12th first shift register D12.

[0150] In the embodiments of the present disclosure, the second input terminals of the first N first shift registers are electrically connected with the output terminals of the last N first shift registers, and the structures of the first N first shift registers can be different from the structures of the N+1th to Mth first shift registers. For example, the structures of the 1st first shift register D1, the 2nd first shift register D2 and the 3rd first shift register D3 are different from the structures of the 4th to 12th first shift registers.

[0151] In the embodiments of the present disclosure, the mth first shift register comprises a shift register unit, a first transistor and a second transistor, and N≥m≥1. The mth first shift register comprises the shift register unit, and M≥m>N. The qth second shift register in the Q cascaded second shift registers comprises a shift register unit, and Q≥q≥1, q being a positive integer.

[0152] For example, the 4th to 12th first shift registers comprise shift register units, the second shift registers comprise shift register units, and the first 3 first shift registers comprise shift register units, first transistors and second transistors. The first transistors and the second transistors can be used to control the input of the start signal STV1 and the input of the signal received by the second input terminals INPUT2 respectively.

[0153] Figure 8 is a structural schematic diagram of the first shift register according to the embodiments of the present disclosure. Figure 8 shows the structure of the 1st first shift register D1 in the first driving unit, and combines Figure 9 The signal timing diagram shown in the figure describes the working process of the first shift register provided by the embodiments of the present disclosure.

[0154] As Figure 8 As shown in the figure, the first shift register D1 comprises a shift register unit 801, a first transistor M1 and a second transistor M2.

[0155] In the embodiment of the present disclosure, the shift register unit is electrically connected to the first power supply VDD1, the second power supply VDD2, the third power supply VSS, the first input terminal INPUT1, the first reset terminal RST1, the second reset terminal RST2 and the output terminal DOUT. The control electrode of the first transistor M1 is electrically connected to the third input terminal INPUT3, the first electrode of the first transistor M1 is electrically connected to the shift register unit 801, and the second electrode of the first transistor M1 is electrically connected to the third power supply VSS. The control electrode and the first electrode of the second transistor M2 are electrically connected to the second input terminal INPUT2, and the first electrode of the second transistor M2 is electrically connected to the first electrode of the first transistor M1.

[0156] In the embodiment of the present disclosure, the shift register unit 801 includes the third transistor M3 to the eighteenth transistor M18 and the capacitor C1.

[0157] The first electrode of the first transistor M1 and the first electrode of the second transistor M2 are electrically connected to the node PU.

[0158] The control electrode of the third transistor M3 is electrically connected to the node PU, the first electrode of the third transistor M3 is electrically connected to the clock terminal CLK1, and the second electrode of the third transistor M3 is electrically connected to the output terminal DOUT.

[0159] The control electrode of the fourth transistor M4 is electrically connected to the first reset terminal RST1, the first electrode of the fourth transistor M4 is electrically connected to the output terminal DOUT, and the second electrode of the fourth transistor M4 is electrically connected to the third power supply VSS.

[0160] The control electrode of the fifth transistor M5 is electrically connected to the node PD CN1, the first electrode of the fifth transistor M5 is electrically connected to the first power supply VDD1, and the second electrode of the fifth transistor M5 is electrically connected to the node PD1.

[0161] The control electrode of the sixth transistor M6 is electrically connected to the node PU, the first electrode of the sixth transistor M6 is electrically connected to the node PD1, and the second electrode of the sixth transistor M6 is electrically connected to the third power supply VSS.

[0162] The control electrode of the seventh transistor M7 is electrically connected to the second reset terminal RST2, the first electrode of the seventh transistor M7 is electrically connected to the node PU, and the second electrode of the seventh transistor M7 is electrically connected to the third power supply VSS.

[0163] The control electrode of the eighth transistor M8 is electrically connected to the node PU, the first electrode of the eighth transistor M8 is electrically connected to the node PD CN1, and the second electrode of the eighth transistor M8 is electrically connected to the third power supply VSS.

[0164] The control electrode and the first electrode of the ninth transistor M9 are electrically connected to the first power supply VDD1, and the second electrode of the ninth transistor M9 is electrically connected to the node PD CN1.

[0165] The control electrode of the tenth transistor M10 is electrically connected to the node PD1, the first electrode of the tenth transistor M10 is electrically connected to the node PU, and the second electrode of the tenth transistor M10 is electrically connected to the third power supply VSS.

[0166] The control electrode of the eleventh transistor M11 is electrically connected to the node PD1, the first electrode of the eleventh transistor M11 is electrically connected to the output terminal DOUT, and the second electrode of the eleventh transistor M11 is electrically connected to the third power supply VSS.

[0167] The control electrode and the first electrode of the twelfth transistor M12 are electrically connected to the first input terminal INPUT1, and the second electrode of the twelfth transistor M12 is electrically connected to the node PU.

[0168] The control electrode of the thirteenth transistor M13 is electrically connected to the node PD CN2, the first electrode of the thirteenth transistor M13 is electrically connected to the second power supply VDD2, and the second electrode of the thirteenth transistor M13 is electrically connected to the node PD2.

[0169] The control electrode of the fourteenth transistor M14 is electrically connected to the node PU, the first electrode of the fourteenth transistor M14 is electrically connected to the node PD CN2, and the second electrode of the fourteenth transistor M14 is electrically connected to the third power supply VSS.

[0170] The control electrode of the fifteenth transistor M15 is electrically connected to the node PU, the first electrode of the fifteenth transistor M15 is electrically connected to the node PD2, and the second electrode of the fifteenth transistor M15 is electrically connected to the third power supply VSS.

[0171] The control electrode and the first electrode of the sixteenth transistor M16 are electrically connected to the second power supply VDD2, and the second electrode of the sixteenth transistor M16 is electrically connected to the node PD CN2.

[0172] The control electrode of the seventeenth transistor M17 is electrically connected to the node PD2, the first electrode of the seventeenth transistor M17 is electrically connected to the node PU, and the second electrode of the seventeenth transistor M17 is electrically connected to the third power supply VSS.

[0173] The control electrode of the eighteenth transistor M18 is electrically connected to the node PD2, the first electrode of the eighteenth transistor M18 is electrically connected to the output terminal DOUT, and the second electrode of the eighteenth transistor M18 is electrically connected to the third power supply VSS.

[0174] The first end of the capacitor C1 is electrically connected to the node PU, and the second end of the capacitor C1 is electrically connected to the output terminal DOUT.

[0175] In combination Figure 9 To Figure 7 The first driving unit 710 and Figure 8The working process of the first shift register D1 is described.

[0176] The first input terminal INPUT1 of the first shift register D1 receives the second scanning signal OUT(Q-2) output by the second shift register at the Q-2 stage, the second input terminal INPUT2 of the first shift register D1 receives the first scanning signal DOUT(10), when the second scanning signal OUT(Q-2) and the first scanning signal DOUT(10) are high, the clock signal CLK4 is high, and the clock signal CLK1 is low.

[0177] For example, in the first stage 1 of the blanking period P2, when the first scanning signal DOUT(10) is high, the second transistor M2 or the twelfth transistor M12 is turned on, the second scanning signal OUT(Q-2) is applied to the node PU through the twelfth transistor M12 or the first scanning signal DOUT(10) is applied to the node PU through the second transistor M2, and the capacitor C1 is charged. At this time, the potential of the node PU is high.

[0178] Under the control of the high potential of the node PU, the sixth transistor M6, the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on. The third power supply voltage VSS from the third power supply VSS passes through the sixth transistor M6, the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15, respectively, to pull down the potentials of the node PD1, the node PD CN1, the node PD CN2, and the node PD2. Under the control of the low potentials of the node PD1, the node PD CN1, the node PD CN2, and the node PD2, the eleventh transistor M11, the fifth transistor M5, the thirteenth transistor M13, and the eighteenth transistor M18 are turned off.

[0179] Under the control of the high potential of the node PU, the transistor M3 is turned on. At this time, the clock signal CLK1 is output to the output terminal DOUT through the third transistor M3, and the first scanning signal DOUT(1) output by the output terminal DOUT is a low-level signal.

[0180] In the second stage 2 of the blanking period P2, the clock signal CLK1 is high, the second scanning signal OUT(Q-2) and the first scanning signal DOUT(10) are both low, and the second transistor M2 and the twelfth transistor M12 are turned off. The node PU remains high under the action of the first capacitor C1, and at this time the transistor M3 remains in the on state, the clock signal CLK1 is output to the output terminal DOUT through the third transistor M3, and the first scanning signal DOUT(1) output by the output terminal DOUT is a high-level signal.

[0181] In the third phase 3 of the blanking period P2, the clock signal CLK1 is low, the first scan signal DOUT(4) is high, and thus the signal received by the first reset terminal RST1 is high. Under the control of the high level of the first scan signal DOUT(4), the fourth transistor M4 is turned on, the third power voltage VSS is supplied to the output terminal DOUT through the fourth transistor M4, and the first scan signal DOUT(1) output by the output terminal DOUT is a low-level signal. Due to the bootstrap effect of the capacitor C1, the voltage level of the node PU is pulled low.

[0182] In the third phase 3 of the blanking period P2, when the first scan signal DOUT(5) jumps to high, the signal received by the second reset terminal RST2 is high. Under the control of the high level of the first scan signal DOUT(5), the seventh transistor M7 is turned on, the third power voltage VSS is supplied to the node PU through the seventh transistor M7, and the voltage level of the node PU is pulled low again.

[0183] Under the control of the low voltage level of the node PU, the sixth transistor M6, the eighth transistor M8, the fourteenth transistor M14, and the fifteenth transistor M15 are turned off.

[0184] Under the control of the high voltage levels of the first power voltage VDD1 and the second power voltage VDD2, the ninth transistor M9 and the sixteenth transistor M16 are turned on, the first power voltage VDD1 and the second power voltage VDD2 are supplied through the ninth transistor M9 and the sixteenth transistor M16, respectively, so that the voltage levels of the node PD CN1 and the node PD CN2 are pulled high. Under the control of the high voltage levels of the node PD CN1 and the node PD CN2, the fifth transistor M5 and the thirteenth transistor M13 are turned on, and the voltage levels of the node PD1 and the node PD2 are pulled high.

[0185] Under the control of the high voltage levels of the node PD1 and the node PD2, the eleventh transistor M11 and the eighteenth transistor M18 are turned on, the third power voltage VSS is supplied to the output terminal DOUT through the eleventh transistor M11 and the eighteenth transistor M18, and the first scan signal DOUT(1) output by the output terminal DOUT is stably maintained as a low-level signal.

[0186] The tenth transistor M10 is turned on under the control of the node PD1, the third power voltage VSS is supplied to the node PU through the tenth transistor M3, and the voltage level of the node PU is stably maintained as low.

[0187] In the fourth phase 4 of the display period P3, the start signal STV1 is high, and the clock signal CLK1 is high.

[0188] Under the control of the high level of the start signal STV1, the seventh transistor M1 is turned on, and the potential of the node PU is pulled low. Under the control of the low potential of the node PU, the third transistor M3 is turned off, and the first scan signal DOUT(1) output by the output terminal DOUT is stably kept as a low level signal.

[0189] When the level of the start signal STV1 is kept as a high level, the first scan signal DOUT(1) output by the output terminal DOUT is stably kept as a low level signal. When the first scan signal DOUT(1) output by the output terminal DOUT of the first stage first shift register D1 is continuously a low level signal, the first scan signal DOUT(4) output by the fourth stage first shift register D4 is also continuously a low level signal.

[0190] The timing changes of the first scan signals output by the second stage first shift register D2 and the third stage first shift register D3 are similar to the timing change of the first scan signal output by the first stage first shift register D1. Therefore, when the first scan signals output by the first stage first shift register D1, the second stage first shift register D2 and the third stage first shift register D3 are continuously kept as low levels, the first scan signals output by the fourth stage to the twelfth stage first shift register are also continuously kept as low levels, that is, the first driving unit 710 ends the scan driving of the virtual pixels.

[0191] In the embodiment of the present disclosure, when the display period P3 is entered from the blanking period P2, the first driving unit 710 can still be in the state of scanning the virtual pixels. In order to reduce the driving power consumption, the timing of the start signal STV1 can be designed so that the first driving unit 710 stops scanning the virtual pixels in the display period P3.

[0192] In the embodiment of the present disclosure, when the high level output by the first stage second shift register of the second driving unit is detected, the start signal STV1 is synchronized to be high, so that the first stage first shift register D1, the second stage first shift register D2 and the third stage first shift register D3 output the low level first scan signals.

[0193] For example, if the start signal STV1 is pulled high when any one of the first stage first shift register D1, the second stage first shift register D2 and the third stage first shift register D3 is outputting a high level signal, the high level of the start signal STV1 can control the first stage first shift register D1, the second stage first shift register D2 and the third stage first shift register D3 to output low level signals, so that the first driving unit 710 stops scanning the virtual pixels in the display period P3.

[0194] For example, if the start signal STV1 is pulled high, and any stage of the 4th to 12th stage of the first shift register is outputting a high level signal, the duration of the high level of the start signal STV1 can be controlled so that the high level of the start signal STV1 can control the 1st stage of the shift register to output a low level signal.

[0195] For example, if the start signal STV1 is pulled high, and the N+1th stage of the first shift register is outputting a high level signal, the duration of the high level of the start signal STV1 is the longest, so that during the duration of the high level of the start signal STV1, the first scanning signal can be sequentially shifted from the N+1th to Mth stage of the first shift register and looped to be outputted by the 1st stage of the first shift register.

[0196] For example, the clock signal CLKn is high when the clock signal CLKn+N is low, so the duration of the high level and low level of the clock signal CLKn can be N H. The level of the clock signal CLKn is set high 1 H earlier than the level of the clock signal CLKn+1, so the level of the first scanning signal DOUT(m) is set high 1 H earlier than the level of the first scanning signal DOUT(m+1). During the loop scanning process of the first driving unit 710, the 1st stage of the first shift register can be considered as the M+1th stage of the first shift register, so the level of the first scanning signal DOUT(N+1) outputted by the N+1th stage of the first shift register is set high at least (M-N) H earlier than the level of the first scanning signal DOUT(1) outputted by the 1st stage of the first shift register.

[0197] Therefore, during the display period, when the clock signal CLK1 is changed from low to high for the first time, the start signal STV1 is synchronously changed from low to high, and the duration of the high level of the start signal STV1 is at least (M-N) / N times of the duration of the high level of the clock signal CLK1 in one scanning period.

[0198] For example, N=3, M=12, the duration of the high level of the start signal STV1 is at least 3 times of the duration of the high level of the clock signal CLK1 in one scanning period, and the duration of the high level of the start signal STV1 is at least 9 H.

[0199] In Figure 8In the example, the first transistor M1 to the eighteenth transistor T18 are all M-type transistors, for example, thin film transistors with an active layer of low temperature polysilicon (LTPS). It can be understood by those skilled in the art that, according to the embodiments of the present disclosure, the first transistor M1 to the eighteenth transistor T18 can also be P-type transistors, for example, thin film transistors with an active layer of indium gallium zinc oxide (IGZO), and the levels of the gate drive signals of the respective transistors can be changed accordingly.

[0200] In addition, it can be understood by those skilled in the art that the capacitor can be implemented as a single capacitor or a plurality of capacitor units connected in parallel or in series, as long as the corresponding functions can be implemented.

[0201] It should be noted that the node PU, the node PD1, the node PD2, the node PD CN1 and the node PD CN2 do not represent actual components, but represent the convergence points of the relevant circuit connections in the circuit diagram.

[0202] Figure 10 FIG. 1 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure.

[0203] As shown in FIG. 1, the display substrate 1000 includes a timing controller 1010, a compensation circuit 1020 and a gate drive circuit 1030. Figure 10 In the embodiments of the present disclosure, the gate drive circuit 1030 can be at least one of the gate drive circuit 100, the gate drive circuit 200, the gate drive circuit 300, the gate drive circuit 500 and the gate drive circuit 700 described above.

[0204] In the embodiments of the present disclosure, the timing control circuit 1010 outputs a data enable signal DE under the control of a power supply voltage. The compensation circuit 1020 compensates the first initial voltage V1 and outputs a first drive voltage Vd1 under the control of the data enable signal DE. The gate drive circuit 1030 outputs a first scan signal and a second scan signal under the control of the first drive voltage Vd1.

[0205] In the embodiments of the present disclosure, the first initial voltage V1 can be a power supply voltage provided by a power management integrated circuit (PMIC) to the gate drive circuit 1030. The first drive voltage Vd1 is obtained by performing load compensation on the first initial voltage V1 by the compensation circuit 1020. The power supply voltage is a power supply voltage provided by the PMIC to the timing control circuit 1010.

[0206]

[0207] ​The first driving voltage Vd1 can be a first power voltage VDD1 or a second power voltage VDD2 received by the gate driving circuit 1030 in the blanking period. The first initial voltage V1 can be the first power voltage VDD1 or the second power voltage VDD2 received by the gate driving circuit 1030 in the display period.

[0208] In the embodiment of the present disclosure, the display substrate 1000 further includes a source driving circuit. The source driving circuit outputs a data signal under the control of a second driving voltage, wherein the second driving voltage is determined by the compensation circuit 1020 based on a second initial voltage. The second driving voltage can be a relatively high power voltage received by the source driving circuit in the blanking period. The second initial voltage can be a relatively high power voltage received by the source driving circuit in the display period. The power supply voltage.

[0209] In the embodiment of the present disclosure, the PMIC outputs a power supply voltage, and the timing control circuit 1010 works under the driving of the power supply voltage and outputs a data enable signal DE. The power supply voltage output by the PMIC can also be a relatively low power voltage provided to the source driving circuit.

[0210] In the embodiment of the present disclosure, since the load of the display panel in the blanking period is smaller than the load of the display panel in the display period, the load of the display panel in the blanking period is increased by using the compensation circuit 1020 to compensate the load of the display panel in the blanking period. By reducing the difference between the load of the display panel in the blanking period and the load of the display panel in the display period, the ripple of the power voltage change caused by the load change can be reduced, and the problem of capacitive howling can be improved.

[0211] Figure 11 FIG. 11 is a structural schematic diagram of a display substrate according to another embodiment of the present disclosure.

[0212] As shown in FIG. 11, the display substrate 1100 includes a timing controller 1110, a compensation circuit 1120, and a gate driving circuit 1130. Figure 11

[0213] In the embodiment of the present disclosure, the compensation circuit 1120 includes a first resistor R1, a second resistor R2, a first switch tube T1, and a second switch tube T2.

[0214] ​In the embodiment of the present disclosure, the first end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the second end of the first resistor R1 is electrically connected to the gate drive circuit 1130. The second end of the second resistor R2 is electrically connected to the control electrode of the first switch tube T1. The first electrode of the first switch tube T1 is electrically connected to the first end of the first resistor R1, and the second electrode of the first switch tube T1 is electrically connected to the second end of the first resistor R1. The control electrode of the second switch tube T2 is electrically connected to the timing control circuit 1110, the first electrode of the second switch tube T2 is electrically connected to the first end of the first resistor R1, and the second electrode of the second switch tube T2 is electrically connected to the fourth power supply GND, which can be ground.

[0215] In the embodiment of the present disclosure, the first switch tube T1 can be a PMOS tube. By controlling the on and off states of the PMOS tube, whether the first resistor R1 is connected to the circuit can be controlled.

[0216] In the embodiment of the present disclosure, the second switch tube T2 can be a triode, for example, an NPN type triode. The base of the triode is electrically connected to the timing control circuit 1110, the collector of the triode is electrically connected to the second end of the second resistor R2, and the emitter of the triode is electrically connected to the fourth power supply GND. The data enable signal DE output by the timing control circuit 1110 is provided to the base of the triode. Since the level of the data enable signal DE is low and the turn-on voltage of the triode is relatively low, the on of the triode is controlled based on the data enable signal DE, thereby controlling the potential of the control electrode of the PMOS tube.

[0217] In the embodiment of the present disclosure, the load in the display panel in the display period is denoted as LoadingA, and the load in the display panel in the blanking period is denoted as LoadingB.

[0218] In the display period, the data enable signal DE is high, the second switch tube T2 is turned on, and the voltage of the control electrode of the first switch tube T1 is 0V. Since the potential of the first electrode of the first switch tube T1 is V1, the gate-source voltage Vgs of the first switch tube T1 is -V1. Under the control of the low level, the first switch tube T1 is turned on, and thus the first resistor R1 is short-circuited. At this time, the load in the circuit is LoadingA.

[0219] During the blanking period, the data enable signal DE is low, the second switch transistor T2 is off, and the second end of the second resistor R2 is in an open circuit state. The first initial signal V1 is provided to the control electrode of the first switch transistor T1 through the second resistor R2. Since the potential of the first electrode of the first switch transistor T1 is V1, the gate-source voltage Vgs of the first switch transistor T1 is 0. Since the threshold voltage Vth of the PMOS transistor is less than 0, and the gate-source voltage Vgs is greater than the threshold voltage Vt, the first switch transistor T1 is off, and the first resistor R1 is connected to the circuit. At this time, the load in the circuit is LoadingB+R1.

[0220] Since LoadingA>LoadingB, by setting the resistance value of the first resistor R1, the difference between the load of the display device during the display period and the blanking period can be reduced. The load of the display device includes the load connected in the display panel and the load connected in the display substrate.

[0221] In the embodiment of the present disclosure, the resistance value of the second resistor R2 is greater than or equal to 10KΩ. By setting the second resistor R2 with a larger resistance value, the influence of the shunt effect of the second resistor R2 on the current in the back-end circuit can be reduced.

[0222] In the embodiment of the present disclosure, on the path of providing the first initial voltage V1 to the gate drive circuit 1130, when the first resistor R1 is connected to the circuit, the first resistor R1 divides the first initial voltage V1, and thus the voltage of the first drive voltage Vd1 is less than the first initial voltage V1.

[0223] In the embodiment of the present disclosure, the load compensation process for the source drive circuit is similar to the load compensation process for the gate drive circuit, and is not described again for simplicity.

[0224] Figure 12 FIG. 4 is a schematic diagram of a power supply voltage according to an embodiment of the present disclosure.

[0225] Figure 12 The curve of the load Loading shown represents the change of the load in the circuit during the display period and the blanking period, for example, the load in the circuit includes the load in the display panel and the load in the display substrate. The solid curve of the load Loading represents the change of the load in the circuit when the gate drive circuit and / or the display substrate provided in the present disclosure drive the display panel, and the dashed curve of the load Loading can represent the change of the load in the circuit when the existing gate drive circuit and / or the display substrate drive the display panel.

[0226] Figure 12The curve of the power supply voltage V1 represents the voltage value change of the power supply voltage provided by the power supply line in the display period and the blanking period. For example, the power supply line is used to provide the power supply voltage V1. The solid curve of the power supply voltage V1 represents the voltage value change of the power supply voltage provided by the power supply line when the gate driving circuit and / or the display substrate provided in the present disclosure is used to drive the display panel. The dotted curve of the power supply voltage V1 can represent the voltage value change of the power supply voltage provided by the power supply line when the existing gate driving circuit and / or the display substrate is used to drive the display panel.

[0227] As shown in FIG. 13, the data enable signal DE of the display period P1 is high, and the data enable signal DE of the blanking period P2 is low. The solid curve of the load Loading shows a smaller difference between the load of the display period and the load of the blanking period, compared with the dotted curve of the load Loading. The solid curve of the power supply voltage V1 shows a smaller ripple, compared with the dotted curve of the power supply voltage V1. Figure 12

[0228] In the embodiments of the present disclosure, the gate driving circuit and / or the display substrate provided in the present disclosure can reduce the difference between the load of the display panel in the display period and the load of the display panel in the blanking period, thereby improving the stability of the power supply voltage, reducing the ripple of the power supply voltage caused by the load change, and improving the problem of capacitive howling.

[0229] Figure 13A FIG. 14 is a structural schematic diagram of a display device according to another embodiment of the present disclosure.

[0230] As shown in FIG. 14, the display device 1300b includes a display panel 1310 and a display substrate 1320. The display panel 1310 includes a first pixel circuit 1311 located in a non-display area and a second pixel circuit 1312 located in a display area. The display substrate 1320 is integrated with a first driving unit 1321 and a second driving unit 1322. Figure 13A

[0231] In the embodiments of the present disclosure, the display substrate 1320 outputs the first scan signal, the second scan signal, and the data signal to the display panel 1310.

[0232] In the embodiments of the present disclosure, the display substrate 1320 can be at least one of the display substrate 1000 and the display substrate 1100 described above.

[0233] Figure 13B FIG. 14 is a structural schematic diagram of a display device according to another embodiment of the present disclosure.

[0234] As shown in FIG. 14, the display device 1300b includes a display panel 1310 and a display substrate 1320. The display panel 1310 includes a first pixel circuit 1311 located in a non-display area and a second pixel circuit 1312 located in a display area. The display substrate 1320 is integrated with a first driving unit 1321 and a second driving unit 1322. Figure 13B ​​​

[0235] In the embodiments of the present disclosure, the first pixel circuit 1311 is electrically connected with a first driving unit 1321 in the gate driving circuit included in the display substrate 1320, and the second pixel circuit 1312 is electrically connected with a second driving unit 1322 in the gate driving circuit included in the display substrate 1320.

[0236] In the embodiments of the present disclosure, the first driving unit 1321 can refer to the first driving unit 110, the first driving unit 210, the first driving unit 310, the first driving unit 510 and the first driving unit 710 described above. The second driving unit 1322 can refer to the second driving unit 120 and the second driving unit 320 described above. For the sake of brevity, no further elaboration is made here.

[0237] For example, the first pixel circuit 1311 includes M rows of virtual pixels arranged in an array form. The first driving unit 1321 includes M cascaded first shift registers outputting M first scanning signals to the M rows of virtual pixels, so as to realize scanning of the M rows of virtual scanning. The second pixel circuit 1312 includes Q rows of light-emitting pixels arranged in an array form. The second driving unit 1322 includes Q cascaded second shift registers outputting Q second scanning signals to the Q rows of light-emitting pixels, so as to realize scanning of the Q rows of light-emitting pixels.

[0238] It should be noted that, Figure 13B It is only schematically shown that the first driving unit 1321 and the second driving unit 1322 are arranged at one side of the first pixel circuit 1311 and the second pixel circuit 1312, so as to start scanning from one end of the first pixel circuit 1311 and the second pixel circuit 1312. The first driving unit 1321 and the second driving unit 1322 can also be arranged at both sides of the first pixel circuit 1311 and the second pixel circuit 1312, so as to synchronously scan from both ends of the first pixel circuit 1311 and the second pixel circuit 1312.

[0239] Figure 14 is a flowchart of a driving method according to the embodiments of the present disclosure.

[0240] As Figure 14 shown, the driving method can be applied to at least one of the gate driving circuit 100 and the gate driving circuit 300 described above.

[0241] In the embodiments of the present disclosure, the driving method can include operation S1410 to operation S1420.

[0242] In operation S1410, under the control of a clock signal and a start signal, a first scanning signal is output by the first driving unit in a blanking period.

[0243] In operation S1420, the second driving unit outputs the second scanning signal in a display period under the control of the first scanning signal and the clock signal.

[0244] In the embodiments of the present disclosure, S1410 is similar to the operation performed by the first driving unit 110 described above, and S1420 is similar to the operation performed by the second driving unit 120 described above, which will not be described here again.

[0245] In the embodiments of the present disclosure, the clock signal can include 2N clock signals, the first level of the 2N clock signals is sequentially shifted and output, the nth clock signal and the n+Nth clock signal in the 2N clock signals are not the first level at the same time, the first level is a high level, n is a positive integer, and N≥n≥1.

[0246] In the embodiments of the present disclosure, operation S1410 includes: under the control of the start signal and the first N clock signals of the 2N clock signals, outputting N first scanning signals by the first N-stage first shift register in the cascaded M first shift registers included in the first driving circuit.

[0247] The person skilled in the art can also set the first level to be a low level and the second level to be a high level according to the type of the transistor in the shift register.

[0248] In the embodiments of the present disclosure, under the control of the start signal from the start end, N first scanning signals are output by the first N-stage first shift register in the cascaded M first shift registers.

[0249] In the embodiments of the present disclosure, the first timing change of the start signal is consistent with the second timing change of the start signal, wherein the first timing change is the timing change of the start signal in the period in which the level of the first clock signal is kept as the first level for the first time in the blanking period, and the second timing change is the timing change of the start signal in the period in which the level of the first clock signal is kept as the first level for the (M / (2N))+1th time in the blanking period.

[0250] In the embodiments of the present disclosure, in the blanking period, when the first clock signal changes from the first level to the second level for the M / (2N)th time, the start signal changes from the second level to the first level.

[0251] In the embodiments of the present disclosure, in the display period, when the first clock signal changes from the second level to the first level for the first time, the start signal changes from the second level to the first level, and the duration of the first level of the start signal is (M-N) / N times the duration of the first level of the first clock signal in one scanning period.

[0252] Figure 15 is a flowchart of a driving method according to another embodiment of the present disclosure.

[0253] As shown in Figure 15 , the driving method can be applied to at least one of the display substrate 1000 and the display substrate 1100 described above.

[0254] In an embodiment of the present disclosure, the driving method can include operations S1510 to S1520.

[0255] In operation S1510, a first initial voltage is compensated to output a first driving voltage under control of a data enable signal.

[0256] In operation S1520, a first scan signal and a second scan signal are output under control of the first driving voltage.

[0257] In an embodiment of the present disclosure, operations S1510 to S1520 are similar to operations performed by the display substrate 1000 and the display substrate 1100 described above, and thus are not described again here.

[0258] In an embodiment of the present disclosure, the data enable signal has a first level in a display period, and has a second level in a blanking period; a voltage value of the first driving voltage output based on the data enable signal having the second level is less than a voltage value of the first driving voltage output based on the data enable signal having the first level.

[0259] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in a different order than that noted in the figures. For example, two blocks noted in succession can in fact be executed substantially concurrently, or at times in reverse order, depending on the functionality involved. It should also be noted that each block in the flowcharts or block diagrams and combinations of blocks in the flowcharts or block diagrams can be implemented by special-purpose hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0260] Those skilled in the art can understand that the features recited in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations, even if such combinations or integrations are not expressly recited in the present disclosure. In particular, the features recited in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0261] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be advantageously used in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A gate driving circuit, comprising: A first driving unit is electrically connected to a clock terminal. The first driving unit is configured to output a first scan signal during the blanking period under the control of a clock signal from the clock terminal and a start signal from the start terminal. as well as The second driving unit is electrically connected to the clock terminal. The second driving unit is configured to output a second scanning signal during the display period under the control of the first scanning signal and the clock signal.

2. The gate driving circuit according to claim 1, wherein, The clock terminals include 2N clock terminals, and the first driving unit is electrically connected to the 2N clock terminals; The first driving unit includes M cascaded first shift registers, the first input terminal of the m-th first shift register is electrically connected to the starting terminal, N≥m≥1, M is an integer multiple of 2N, and m, N and M are all positive integers.

3. The gate driving circuit according to claim 2, wherein, The first input terminal of the m-th stage first shift register is electrically connected to the output terminal of the mN-th stage first shift register, the first reset terminal of the m-th stage first shift register is electrically connected to the output terminal of the m+N-th stage first shift register, and the second reset terminal of the m-th stage first shift register is electrically connected to the output terminal of the m+N+1-th stage first shift register, where MN>m>N.

4. The driving circuit according to claim 2, wherein, The first reset terminal of the first shift register of the m-th stage is electrically connected to the output terminal of the first shift register of the m-M+N-th stage, and the second reset terminal of the first shift register of the m-th stage is electrically connected to the output terminal of the first shift register of the m-M+N+1-th stage, where M≥m≥M-N+1 and M≥4N.

5. The gate driving circuit according to claim 2, wherein, The second input terminal of the first shift register of the m-th stage is electrically connected to the output terminal of the first shift register of the (m+MN)-th stage, where N≥m≥1 and M≥4N.

6. The gate driving circuit according to claim 2, wherein the second driving unit is electrically connected to the 2N clock terminals; in, The second driving unit includes Q cascaded second shift registers. The output terminal of the m-th stage first shift register is electrically connected to the first reset terminal of the m+QN-th stage second shift register, and the output terminal of the m-th stage first shift register is electrically connected to the second reset terminal of the m+QN-1-th stage second shift register. N≥m≥1, Q>N, and Q is a positive integer.

7. The gate driving circuit according to claim 2, wherein, The second driving unit includes Q cascaded second shift registers; The first input terminal of the first shift register of the m-th stage is electrically connected to the output terminal of the second shift register of the (m+QN)-th stage, where N≥m≥1.

8. The gate driving circuit according to claim 7, wherein, The third input terminal of the m-th stage first shift register is electrically connected to the start terminal, where N≥m≥1.

9. The gate driving circuit according to claim 8, wherein, The q-th stage of the cascaded Q second shift registers includes shift register units, where Q ≥ q ≥ 1, and q is a positive integer; as well as The m-th stage first shift register includes the shift register unit, the first transistor, and the second transistor, where N≥m≥1; The shift register unit of the m-th stage first shift register is electrically connected to the first power supply, the second power supply, the third power supply, the first input terminal, the first reset terminal, the second reset terminal, and the output terminal. The control electrode of the first transistor is electrically connected to the third input terminal, the first electrode of the first transistor is electrically connected to the shift register unit, and the second electrode of the first transistor is electrically connected to the third power supply. The control electrode and the first electrode of the second transistor are electrically connected to the second input terminal, and the first electrode of the second transistor is electrically connected to the first electrode of the first transistor.

10. The gate driving circuit according to claim 9, wherein, The first shift register of the m-th stage includes the shift register unit, where M ≥ m > N.

11. A display substrate, comprising: The timing control circuit is configured to output a data enable signal; The compensation circuit is configured to compensate for the first initial voltage under the control of the data enable signal and output the first drive voltage. as well as The gate driving circuit according to any one of claims 1 to 10 is configured to output a first scan signal and a second scan signal under the control of the first driving voltage.

12. The display substrate according to claim 11, further comprising: The source drive circuit is configured to output a data signal under the control of a second drive voltage, wherein the second drive voltage is determined by the compensation circuit based on a second initial voltage.

13. The display substrate according to claim 11, wherein, The compensation circuit includes a first resistor, a second resistor, a first switching transistor, and a second switching transistor. Wherein, the first end of the first resistor is electrically connected to the first end of the second resistor, and the second end of the first resistor is electrically connected to the gate drive circuit. The second terminal of the second resistor is electrically connected to the control electrode of the first switching transistor; The first terminal of the first switching transistor is electrically connected to the first terminal of the first resistor, and the second terminal of the first switching transistor is electrically connected to the second terminal of the first resistor; and The control electrode of the second switch is electrically connected to the timing control circuit, the first electrode of the second switch is electrically connected to the first terminal of the first resistor, and the second electrode of the second switch is electrically connected to the fourth power supply.

14. A display device, comprising Display panel; and The display substrate as described in any one of claims 11 to 13 is configured to output a first scan signal, a second scan signal, and a data signal to the display panel.

15. The display device according to claim 14, wherein, The display panel includes a first pixel circuit located in the non-display area and a second pixel circuit located in the display area; The first pixel circuit is electrically connected to the first driving unit in the gate driving circuit included in the display substrate, and the second pixel circuit is electrically connected to the second driving unit in the gate driving circuit included in the display substrate.

16. A driving method applied to the gate driving circuit according to any one of claims 1 to 10, comprising: Under the control of the clock signal and the start signal, the first drive unit outputs a first scan signal during the blanking period; as well as Under the control of the first scan signal and the clock signal, the second drive unit outputs the second scan signal during the display period.

17. The method according to claim 16, wherein, The clock signal includes 2N clock signals; the step of outputting a first scan signal during the blanking period through the first driving unit under the control of the clock signal and the start signal includes: Under the control of the start signal and the first N clock signals of the 2N clock signals, N first scan signals are output through the first N stages of the first shift registers in the M cascaded first shift registers included in the first driving circuit; The first level of the 2N clock signals is shifted and output sequentially. The nth clock signal and the (n+Nth)th clock signal in the 2N clock signals are not simultaneously at the first level. n is a positive integer, and N≥n≥1.

18. The method according to claim 17, wherein, The first timing change of the starting signal is consistent with the second timing change of the starting signal. The first timing change is the timing change of the starting signal during the period when the level of the first clock signal among the 2N clock signals is maintained at the first level for the first time during the blanking period. The second timing change is the timing change of the starting signal during the period when the level of the first clock signal is maintained at the first level for the (M / (2N))+1th time during the blanking period.

19. The method according to claim 18, wherein, During the blanking period, when the first clock signal changes from the first level to the second level for the M / (2N)th time, the start signal changes from the second level to the first level.

20. The method of claim 17, wherein, During the display period, when the first clock signal among the 2N clock signals changes from the second level to the first level for the first time, the start signal changes from the second level to the first level, and the duration of the first level of the start signal is (MN) / N times the duration of the first level of the first clock signal in one scan cycle.

21. A driving method applied to a display substrate according to any one of claims 11 to 13, comprising: Under the control of the data enable signal, the first initial voltage is compensated and the first driving voltage is output; as well as Under the control of the first driving voltage, a first scan signal and a second scan signal are output; During the display period, the data enable signal has a first level; During the blanking period, the data enable signal has a second level; the voltage value of the first drive voltage output based on the data enable signal having the second level is less than the voltage value of the first drive voltage output based on the data enable signal having the first level.

Images