Gate drive circuit

Abstract

The invention provides a gate driving circuit. The gate drive circuit includes a pull-up circuit, a pull-down circuit, an output transistor, a control transistor, and a noise suppression circuit. The pull-up circuit pulls up a voltage value located at the operation node according to the (n-1) th level control signal. The pull-down circuit pulls down the voltage value at the operation node according to the (n + 1) th level control signal. The output transistor outputs a gate driving signal according to a first clock signal and a voltage value at an operation node. The control transistor outputs an nth-level control signal according to a first clock signal and a voltage value at an operation node. The noise suppression circuit suppresses noise at the operation node, noise at the second end of the output transistor, and noise at the second end of the control transistor according to the (n + 1) th level control signal.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly to a gate driving circuit. Background Technology

[0002] Electronic devices (such as image sensing devices or displays) include gate driving devices. These gate driving devices include multiple gate driving circuits. The gate driving circuits provide gate driving signals. Therefore, pixel rows of the display can be scanned according to the gate driving signals. However, the gate driving signals may become noisy due to temperature, pixel circuitry, or other circuitry. When the nth-stage gate driving signal of the nth-stage gate driving circuit becomes noisy, other gate driving circuits operating based on the nth-stage gate driving signal may malfunction. It should be noted that noise in the nth-stage gate driving signal may cause short circuits and damage to other gate driving circuits. Therefore, improving the stability of gate driving circuits is one of the key research focuses for those skilled in the art. Summary of the Invention

[0003] This invention provides a gate drive circuit with high stability.

[0004] In one embodiment of the present invention, the gate driving circuit includes a pull-up circuit, a pull-down circuit, an output transistor, a coupling capacitor, a control transistor, and a noise suppression circuit. The pull-up circuit is connected to the operating node. The pull-up circuit pulls up the voltage value at the operating node according to the (n-1)th level control signal. The pull-down circuit is connected to the operating node. The pull-down circuit pulls down the voltage value at the operating node according to the (n+1)th level control signal. The first terminal of the output transistor receives a first clock signal. The second terminal of the output transistor outputs a gate driving signal. The control terminal of the output transistor is connected to the operating node. The coupling capacitor is connected between the second terminal of the output transistor and the control terminal of the output transistor. The first terminal of the control transistor receives the first clock signal. The second terminal of the control transistor outputs the nth level control signal. The control terminal of the control transistor is connected to the operating node. The noise suppression circuit is connected to the operating node, the second terminal of the output transistor, and the second terminal of the control transistor. The noise suppression circuit suppresses noise at the operating node, noise at the second terminal of the output transistor, and noise at the second terminal of the control transistor according to the (n+1)th level control signal.

[0005] Based on the above, the control transistor outputs the nth-level control signal. Therefore, the gate drive circuit can use the nth-level control signal to control other gate drive circuits. The nth-level control signal is not affected by pixel circuit interference. Furthermore, the noise suppression circuit suppresses noise located at the operating node, noise at the second terminal of the output transistor, and noise at the second terminal of the control transistor. The noise suppression circuit isolates noise located at the operating node, the second terminal of the output transistor, and interference at the second terminal of the control transistor. Therefore, the risk of abnormalities in the nth-level control signal and the gate drive signal is reduced. As a result, the gate drive circuit exhibits high stability. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;

[0007] Figure 2 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;

[0008] Figure 3 This is a signal timing diagram shown according to an embodiment of the present invention;

[0009] Figure 4 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;

[0010] Figure 5 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;

[0011] Figure 6 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;

[0012] Figure 7A as well as Figure 7B These are signal timing diagrams shown according to an embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures

[0014] 110, 210, 310, 410, 510: Pull-up circuits

[0015] 120, 220, 320, 420, 520: Pull-down circuits

[0016] 130, 230, 330, 430, 530: Noise suppression circuits

[0017] 231, 331, 431, 531, 532: Setting circuit

[0018] 232, 332, 432, 533, 534: Voltage Regulator Circuits

[0019] CC: Voltage stabilizing capacitor

[0020] CK1: First clock signal

[0021] CK2: Second clock signal

[0022] CP: Coupling capacitor

[0023] G(n): Gate drive signal

[0024] GD(n): Gate drive circuit

[0025] LVGL, VGL: Reference Low Voltage

[0026] NDP: Operation Node

[0027] NDX, NDX1, NDX2: Control Nodes

[0028] SN(n-1): The (n-1)th level control signal

[0029] SN(n): The nth level control signal

[0030] SN(n+1): The (n+1)th level control signal

[0031] t1~t8: Time points

[0032] TC: Control Transistor

[0033] TD1: First Period

[0034] TD2: Second Period

[0035] TN1~TN3, TN1'~TN3': Transistors

[0036] TO: Output transistor

[0037] TP1: Pull-up transistor

[0038] TP2: Pull-down transistor

[0039] TS1~TS4, TS1'~TS3': Setting transistors

[0040] TT1, TT2: Switching transistors

[0041] VB, VB1, VB2: Bias signals Detailed Implementation

[0042] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the claims of the present invention.

[0043] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. In this embodiment, the gate driving circuit GD(n) can be the nth stage gate driving unit in a gate driving device. The gate driving circuit GD(n) includes a pull-up circuit 110, a pull-down circuit 120, an output transistor TO, a coupling capacitor CP, a control transistor TC, and a noise suppression circuit 130. The pull-up circuit 110 is connected to the operating node NDP. The pull-up circuit 110 pulls up the voltage value at the operating node NDP according to the (n-1)th stage control signal SN(n-1). The pull-down circuit 120 is connected to the operating node NDP. The pull-down circuit 120 pulls down the voltage value at the operating node NDP according to the (n+1)th stage control signal SN(n+1).

[0044] In this embodiment, the first terminal of the output transistor TO receives the first clock signal CK1. The second terminal of the output transistor TO outputs the gate drive signal G(n). The control terminal of the output transistor TO is connected to the operating node NDP. A coupling capacitor CP is connected between the second terminal of the output transistor TO and the control terminal of the output transistor TO. The first terminal of the control transistor TC receives the first clock signal CK1. The second terminal of the control transistor TC outputs the nth level control signal SN(n). The control terminal of the control transistor TC is connected to the operating node NDP.

[0045] In this embodiment, the gate driving circuit GD(n) uses the gate driving signal G(n) to drive the pixel circuit (not shown). The gate driving circuit GD(n) uses the nth-level control signal SN(n) to control other gate driving circuits.

[0046] In this embodiment, the output transistor TO and the control transistor TC are both implemented using N-type transistors. While both the output transistor TO and the control transistor TC can be N-type thin-film transistors (TFTs), this invention is not limited thereto. Therefore, the output transistor TO outputs the gate drive signal G(n) based on the first clock signal CK1 and the high voltage value at the operating node NDP. The control transistor TC outputs the nth-stage control signal SN(n) based on the first clock signal CK1 and the high voltage value at the operating node NDP. Therefore, the nth-stage control signal SN(n) can be a copy of the gate drive signal G(n).

[0047] In this embodiment, the noise suppression circuit 130 is connected to the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC. The noise suppression circuit 130 suppresses noise located at the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC according to the (n+1)th level control signal SN(n+1).

[0048] It is worth mentioning that the gate drive circuit can use the nth-level control signal SN(n) to control other gate drive circuits. The nth-level control signal SN(n) is not affected by the pixel circuit. Furthermore, the noise suppression circuit 130 suppresses noise located at the operating node NDP, noise at the second terminal of the output transistor TO, and noise at the second terminal of the control transistor TC. The noise suppression circuit 130 isolates noise located at the operating node NDP, the second terminal of the output transistor TO, and interference at the second terminal of the control transistor TC. Therefore, the risk of abnormalities in the nth-level control signal SN(n) and the gate drive signal G(n) can be reduced. As a result, the gate drive circuit GD(n) has high stability. Furthermore, even when there is no noise in the nth-level control signal SN(n), the risk of short circuits caused by abnormalities in other gate drive circuits can be reduced. Therefore, the lifespan of the gate drive device can be increased.

[0049] In this embodiment, the (n-1)th level control signal SN(n-1) and the (n+1)th level control signal SN(n+1) can be provided by other gate drive circuits. For example, the (n-1)th level control signal SN(n-1) can be provided by the gate drive circuit GD(n-1) (not shown). The (n+1)th level control signal SN(n+1) can also be provided by the gate drive circuit GD(n+1) (not shown). In this embodiment, n can be any positive integer. When n equals "1", the (n-1)th level control signal SN(n-1) can be an initial signal.

[0050] In this embodiment, the pull-up circuit 110 responds to the voltage value of the pulse of the (n-1)th level control signal SN(n-1) to pull up the voltage value located at the operating node NDP.

[0051] In this embodiment, the pull-down circuit 120 responds to the pulse of the (n+1)th level control signal SN(n+1) to pull down the voltage value located at the operating node NDP using the reference low voltage VGL.

[0052] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. In this embodiment, the gate driving circuit GD(n) includes a pull-up circuit 210, a pull-down circuit 220, an output transistor TO, a coupling capacitor CP, a control transistor TC, and a noise suppression circuit 230. The connection method of the output transistor TO, the coupling capacitor CP, and the control transistor TC has been described in [the original text]. Figure 1 The embodiments are clearly illustrated and will not be repeated here.

[0053] Pull-up circuit 210 includes pull-up transistor TP1. The first terminal and control terminal of pull-up transistor TP1 receive the (n-1)th level control signal SN(n-1). The second terminal of pull-up transistor TP1 is connected to the operating node NDP. In this embodiment, pull-up transistor TP1 is implemented using an N-type transistor. Pull-up transistor TP1 can be an N-type TFT (however, the invention is not limited thereto). Pull-up transistor TP1 is connected between the (n-1)th level control signal SN(n-1) and the operating node NDP in a diode configuration. Therefore, pull-up transistor TP1 can be turned on according to the positive pulse of the (n-1)th level control signal SN(n-1), and the voltage value at the operating node NDP is pulled up to a first voltage value using the positive pulse of the (n-1)th level control signal SN(n-1). Therefore, control transistor TC and output transistor TO are turned on. Furthermore, pull-up transistor TP1 can float the operating node NDP according to a low voltage value (e.g., equal to or below 0 volts).

[0054] Pull-down circuit 220 includes pull-down transistor TP2. The first terminal of pull-down transistor TP2 receives a reference low voltage VGL. The second terminal of pull-down transistor TP2 is connected to the operating node NDP. The control terminal of pull-down transistor TP2 receives a (n+1)th stage control signal SN(n+1). Pull-down transistor TP2 is implemented using an N-type transistor. Pull-down transistor TP2 can be an N-type TFT (however, the invention is not limited thereto). Therefore, pull-down transistor TP2 is turned on by the positive pulse of the (n+1)th stage control signal SN(n+1) and uses the reference low voltage VGL to pull down the voltage value at the operating node NDP. Therefore, control transistor TC and output transistor TO are turned off.

[0055] In this embodiment, the noise suppression circuit 230 includes a setting circuit 231 and a voltage regulator circuit 232. The setting circuit 231 is connected to the control node NDX. The setting circuit 231 pulls up the voltage value at the control node NDX to a high voltage value according to the (n+1)th level control signal SN(n+1). The voltage regulator circuit 232 is connected to the control node NDX, the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC. The voltage regulator circuit 232 responds to the high voltage value at the control node NDX to suppress noise at the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC. Furthermore, the voltage regulator circuit 232 stabilizes the low voltage values ​​at the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC. Therefore, the noise at the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC can be suppressed.

[0056] In this embodiment, the setting circuit 231 includes setting transistors TS1 to TS3. The first terminal of setting transistor TS1 receives a bias signal. The second terminal of setting transistor TS1 is connected to the control node NDX. The control terminal of setting transistor TS1 receives the (n+1)th level control signal SN(n+1). The first terminal of setting transistor TS2 receives a bias signal VB. The second terminal of setting transistor TS2 is connected to the control node NDX. The control terminal of setting transistor TS2 receives the bias signal VB. In some embodiments, the control terminal of setting transistor TS2 may receive a second clock signal different from the first clock signal CK1. In this embodiment, the first terminal of setting transistor TS3 is connected to the control node NDX. The second terminal of setting transistor TS3 is connected to the reference low voltage LVGL. The control terminal of setting transistor TS3 is connected to the operating node NDP.

[0057] In this embodiment, the voltage regulator circuit 232 includes transistors TN1 to TN3. The first terminal of transistor TN1 is connected to the operating node NDP. The second terminal of transistor TN1 is connected to the reference low voltage LVGL. The control terminal of transistor TN1 is connected to the control node NDX. The first terminal of transistor TN2 is connected to the second terminal of the control transistor TC. The second terminal of transistor TN2 is connected to the reference low voltage VGL. The control terminal of transistor TN2 is connected to the control node NDX. The first terminal of transistor TN3 is connected to the second terminal of the output transistor TO. The second terminal of transistor TN3 is connected to the reference low voltage VGL. The control terminal of transistor TN3 is connected to the control node NDX.

[0058] In this embodiment, transistors TS1-TS3 and TN1-TN3 are configured as N-type transistors. Transistors TS1-TS3 and TN1-TN3 can each be N-type TFTs (however, this invention is not limited thereto). The control terminals of transistors TN1-TN3 are connected to the control node NDX. Therefore, transistors TN1-TN3 are turned on based on a high voltage value at the control node NDX and turned off based on a low voltage value at the control node NDX.

[0059] In this embodiment, the voltage value of the reference low voltage VGL may be the same as or different from the voltage value of the reference low voltage LVGL.

[0060] Please refer to Figure 2 as well as Figure 3 , Figure 3 This is a signal timing diagram according to an embodiment of the present invention. In this embodiment, during the setting period between time point t1 and time point t2, the (n-1)th level control signal SN(n-1) has a positive pulse. The pull-up transistor TP1 can be turned on according to the positive pulse of the (n-1)th level control signal SN(n-1), and the voltage value at the operating node NDP is pulled up to a first voltage value using the positive pulse of the (n-1)th level control signal SN(n-1). Therefore, the control transistor TC and the output transistor TO are turned on. In addition, the setting transistor TS3 is also turned on. Therefore, the voltage value at the control node NDX is pulled down to a low voltage value. During the setting period, the first clock signal CK1 has a low voltage value. Therefore, the nth level control signal SN(n) has a low voltage value. The gate drive signal G(n) also has a low voltage value.

[0061] During the boost phase between time points t2 and t3, the (n-1)th stage control signal SN(n-1) has a low voltage value. Pull-up transistor TP1 is disconnected to allow the operating node NDP to float. Control transistor TC and output transistor TO remain on. The first clock signal CK1 has a positive pulse. A high voltage value is present at the second terminal of output transistor TO. Therefore, based on the capacitive coupling of coupling capacitor CP, the gate drive circuit GD(n) uses the high voltage value at the second terminal of output transistor TO to further boost the voltage value of operating node NDP to a second voltage value, thereby ensuring the conduction of control transistor TC and output transistor TO. During the boost phase between time points t2 and t3, the nth stage control signal SN(n) has a positive pulse. The gate drive signal G(n) also has a positive pulse.

[0062] During the reset period between time points t3 and t4, the first clock signal CK1 has a low voltage value. Therefore, the nth stage control signal SN(n) has a low voltage value. The gate drive signal G(n) also has a low voltage value. During the reset period, the (n+1)th stage control signal SN(n+1) has a positive pulse. Therefore, the pull-down transistor TP2 is turned on to pull down the voltage value at the operating node NDP to a low voltage value. The control transistor TC, the output transistor TO, and the setting transistor TS3 are turned off. During the reset period, the setting transistor TS1 is turned on to pull up the voltage value at the control node NDX to a high voltage value. Transistors TN1 to TN3 are turned on according to the high voltage value at the control node NDX. Therefore, the voltage regulator circuit 232 pulls down the voltage value at the operating node NDP, the voltage value at the second terminal of the output transistor TO, and the voltage value at the second terminal of the control transistor TC according to the high voltage value at the control node NDX. Therefore, during the reset period, the voltage values ​​at the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC are maintained at low voltage levels. Noise at the operating node NDP, the second terminal of the output transistor TO, and the second terminal of the control transistor TC are suppressed.

[0063] During the stabilization period after time point t4, the setting transistor TS2 remains on to maintain the voltage value at the control node NDX at a high voltage value. Therefore, the voltage regulator circuit 232 can continuously pull down the voltage value at the operating node NDP, the voltage value at the second terminal of the output transistor TO, and the voltage value at the second terminal of the control transistor TC.

[0064] In this embodiment, the aspect ratio of the channel of the setting transistor TS2 is smaller than that of the channel of the setting transistor TS3. Therefore, when the setting transistor TS3 is turned on, the setting transistor TS2 does not significantly hinder the decrease of the voltage value at the control node NDX.

[0065] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. In this embodiment, the gate driving circuit GD(n) includes a pull-up circuit 310, a pull-down circuit 320, an output transistor TO, a coupling capacitor CP, a control transistor TC, and a noise suppression circuit 330. The connection method of the output transistor TO, the coupling capacitor CP, and the control transistor TC has been described in detail. Figure 1 The embodiments are clearly illustrated and will not be repeated here. The implementations of pull-up circuit 310 and pull-down circuit 320 are the same as those described above. Figure 2 The implementation methods of the pull-up circuit 210 and pull-down circuit 220 shown are not repeated here.

[0066] In this embodiment, the noise suppression circuit 330 includes a setting circuit 331 and a voltage regulator circuit 332. The setting circuit 331 includes setting transistors TS1 to TS4. The voltage regulator circuit 332 includes transistors TN1 to TN3. The setting transistors TS1 to TS3 and transistors TN1 to TN3 are connected in the same way as... Figure 2 The connection methods of the setting transistors TS1-TS3 and TN1-TN3 shown are not repeated here. In this embodiment, the first terminal of the setting transistor TS4 is connected to the control node NDX. The second terminal of the setting transistor TS4 is connected to the first reference low voltage LVGL. The control terminal of the setting transistor TS4 receives the (n-1)th level control signal SN(n-1). The setting transistor TS4 can pull down the voltage value at the control node NDX according to the positive pulse of the (n-1)th level control signal SN(n-1). Therefore, the setting transistor TS4 can accelerate the speed at which the voltage value at the control node NDX is pulled down.

[0067] The gate drive circuit GD(n) in this embodiment is also applicable to Figure 3 The timing diagram.

[0068] In this embodiment, the setting transistor TS4 is implemented by an N-type transistor. The setting transistor TS4 can be an N-type TFT (however, the present invention is not limited thereto).

[0069] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. In this embodiment, the gate driving circuit GD(n) includes a pull-up circuit 410, a pull-down circuit 420, an output transistor TO, a coupling capacitor CP, a control transistor TC, and a noise suppression circuit 430. The connection method of the output transistor TO, the coupling capacitor CP, and the control transistor TC has been described in [the original text]. Figure 1 The embodiments are clearly illustrated and will not be repeated here. The implementations of pull-up circuit 410 and pull-down circuit 420 are the same as those described above. Figure 2 The implementation methods of the pull-up circuit 210 and pull-down circuit 220 shown are not repeated here.

[0070] The noise suppression circuit 430 includes a setting circuit 431 and a voltage regulator circuit 432. The setting circuit 431 includes setting transistors TS1 to TS4 and a voltage regulator capacitor CC. The voltage regulator circuit 432 includes transistors TN1 to TN3. The setting transistors TS1 to TS4 are connected in the same way as... Figure 4 The connection methods for transistors TS1 to TS4 are shown below, and will not be repeated here. The connection methods for transistors TN1 to TN3 are the same as... Figure 2 The connection method of transistors TN1 to TN3 shown is not repeated here.

[0071] In this embodiment, the voltage regulator capacitor CC is connected between the control node NDX and the reference low voltage VGL. The voltage regulator capacitor CC is used to extend the duration of the high voltage value maintained at the control node NDX. In this embodiment, the voltage regulator capacitor CC is connected between the control node NDX and the reference low voltage LVGL.

[0072] The gate drive circuit GD(n) in this embodiment is also applicable to Figure 3 The timing diagram.

[0073] In some embodiments, the setting transistor TS4 may be omitted.

[0074] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. In this embodiment, the gate driving circuit GD(n) includes a pull-up circuit 510, a pull-down circuit 520, an output transistor TO, a coupling capacitor CP, a control transistor TC, and a noise suppression circuit 530. The connection method of the output transistor TO, the coupling capacitor CP, and the control transistor TC has been described in [the original text]. Figure 1 The embodiments are clearly illustrated and will not be repeated here. The implementation of pull-up circuit 510 and pull-down circuit 520 is the same as that in the previous embodiments. Figure 2 The implementation methods of the pull-up circuit 210 and pull-down circuit 220 shown are not repeated here.

[0075] In this embodiment, the noise suppression circuit 530 includes setting circuits 531 and 532, and voltage regulation circuits 533 and 534. Setting circuit 531 is connected to control node NDX1. Setting circuit 531 pulls the voltage value at control node NDX1 to a high voltage value based on the (n+1)th level control signal SN(n+1) and the bias signal VB1. Setting circuit 532 is connected to control node NDX2. Setting circuit 532 pulls the voltage value at control node NDX2 to a high voltage value based on the (n+1)th level control signal SN(n+1) and the bias signal VB2.

[0076] In this embodiment, the bias signals VB1 and VB2 are complementary to each other. Specifically, bias signal VB1 has a high voltage value, while bias signal VB2 has a low voltage value. For example, the voltage values ​​of bias signals VB1 and VB2 are inverted after at least one frame.

[0077] Voltage regulator circuit 533 is connected to control node NDX1, operating node NDP, the second terminal of output transistor TO, and the second terminal of control transistor TC. Voltage regulator circuit 533 responds to the high voltage value at control node NDX1 to suppress noise at operating node NDP, the second terminal of output transistor TO, and the second terminal of control transistor TC. Voltage regulator circuit 534 is connected to control node NDX2, operating node NDP, the second terminal of output transistor TO, and the second terminal of control transistor TC. Voltage regulator circuit 534 responds to the high voltage value at control node NDX2 to suppress noise at operating node NDP, the second terminal of output transistor TO, and the second terminal of control transistor TC.

[0078] In this embodiment, the noise suppression circuit 530 switches the voltage value of control node NDX2 to a low voltage value based on the high voltage value at control node NDX1, and switches the voltage value of control node NDX1 to a low voltage value based on the high voltage value at control node NDX2. Therefore, the voltage regulator circuits 533 and 534 can take turns resting. This extends the lifespan of the voltage regulator circuits 533 and 534.

[0079] In this embodiment, the setting circuit 531 includes setting transistors TS1 to TS3. The first terminal of setting transistor TS1 receives a bias signal VB1. The second terminal of setting transistor TS1 is connected to control node NDX1. The control terminal of setting transistor TS1 receives the (n+1)th level control signal SN(n+1). The first terminal of setting transistor TS2 receives the bias signal VB1. The second terminal of setting transistor TS2 is connected to control node NDX1. The control terminal of setting transistor TS2 receives a second clock signal CK2. The first terminal of setting transistor TS3 is connected to control node NDX1. The second terminal of setting transistor TS3 is connected to the reference low voltage LVGL. The control terminal of setting transistor TS3 is connected to operation node NDP.

[0080] The setting circuit 532 includes setting transistors TS1' to TS3'. The first terminal of setting transistor TS1' receives the bias signal VB2. The second terminal of setting transistor TS1' is connected to control node NDX2. The control terminal of setting transistor TS1' receives the (n+1)th level control signal SN(n+1). The first terminal of setting transistor TS2' receives the bias signal VB2. The second terminal of setting transistor TS2' is connected to control node NDX2. The control terminal of setting transistor TS2' receives the second clock signal CK2. The first terminal of setting transistor TS3' is connected to control node NDX2. The second terminal of setting transistor TS3' is connected to the reference low voltage LVGL. The control terminal of setting transistor TS3' is connected to operation node NDP.

[0081] The voltage regulator circuit 533 includes transistors TN1 to TN3. The first terminal of transistor TN1 is connected to the operating node NDP. The second terminal of transistor TN1 is connected to the reference low voltage LVGL. The control terminal of transistor TN1 is connected to the control node NDX1. The first terminal of transistor TN2 is connected to the second terminal of the control transistor TC. The second terminal of transistor TN2 is connected to the reference low voltage VGL. The control terminal of transistor TN2 is connected to the control node NDX1. The first terminal of transistor TN3 is connected to the second terminal of the output transistor TO. The second terminal of transistor TN3 is connected to the reference low voltage VGL. The control terminal of transistor TN3 is connected to the control node NDX1.

[0082] The voltage regulator circuit 534 includes transistors TN1' to TN3'. The first terminal of transistor TN1' is connected to the operating node NDP. The second terminal of transistor TN1' is connected to the reference low voltage LVGL. The control terminal of transistor TN1' is connected to the control node NDX2. The first terminal of transistor TN2' is connected to the second terminal of the control transistor TC. The second terminal of transistor TN2' is connected to the reference low voltage VGL. The control terminal of transistor TN2' is connected to the control node NDX2. The first terminal of transistor TN3' is connected to the second terminal of the output transistor TO. The second terminal of transistor TN3' is connected to the reference low voltage VGL. The control terminal of transistor TN3' is connected to the control node NDX2.

[0083] In this embodiment, the noise suppression circuit 530 further includes switching transistors TT1 and TT2. A first terminal of switching transistor TT1 is connected to control node NDX1. A second terminal of switching transistor TT1 is connected to a reference low voltage LVGL. A control terminal of switching transistor TT1 is connected to control node NDX2. A first terminal of switching transistor TT2 is connected to control node NDX2. A second terminal of switching transistor TT2 is connected to the reference low voltage LVGL. A control terminal of switching transistor TT2 is connected to control node NDX1.

[0084] In this embodiment, the switching transistors TT1 and TT2, the setting transistors TS1-TS3, TS1'-TS3', and the transistors TN1-TN3, TN1'-TN3' are all implemented by N-type transistors. The switching transistors TT1 and TT2, the setting transistors TS1-TS3, TS1'-TS3', and the transistors TN1-TN3, TN1'-TN3' can all be N-type TFTs (however, the present invention is not limited thereto).

[0085] Please refer to Figure 6 , Figure 7A as well as Figure 7B , Figure 7A as well as Figure 7BThese are signal timing diagrams shown according to an embodiment of the present invention. In this embodiment, Figure 7A The signal timing diagram for TD1 during the first period is shown. Figure 7B The signal timing diagram for the second period TD2 is shown. The first period TD1 and the second period TD2 alternate with each other. For example, the duration of the first period TD1 is equal to at least one frame. The duration of the second period TD2 is equal to at least one frame. Depending on design requirements, the duration of the first period TD1 may be the same as or different from the duration of the second period TD2. In this embodiment, the voltage values ​​of the bias signals VB1 and VB2 can be inverted based on the first period TD1 and the second period TD2.

[0086] During the first period TD1, bias signal VB1 has a high voltage value. Bias signal VB2 has a low voltage value. During the setting period between time point t1 and time point t2, the (n-1)th stage control signal SN(n-1) has a positive pulse. Pull-up transistor TP1 can be turned on according to the positive pulse of the (n-1)th stage control signal SN(n-1), pulling up the voltage value at the operating node NDP to the first voltage value. Therefore, control transistor TC and output transistor TO are turned on. In addition, setting transistors TS3 and TS3' are also turned on. Therefore, the voltage values ​​at control nodes NDX1 and NDX2 are pulled down to low voltage values. During the setting period, the first clock signal CK1 has a low voltage value. Therefore, the nth stage control signal SN(n) has a low voltage value. The gate drive signal G(n) also has a low voltage value.

[0087] During the boost phase between time points t2 and t3, the (n-1)th stage control signal SN(n-1) has a low voltage value. Pull-up transistor TP1 is disconnected to allow the operating node NDP to float. Control transistor TC and output transistor TO remain on. The first clock signal CK1 has a positive pulse. A high voltage value is present at the second terminal of output transistor TO. Therefore, based on the capacitive coupling of coupling capacitor CP, the gate drive circuit GD(n) uses the high voltage value at the second terminal of output transistor TO to further boost the voltage value of operating node NDP to a second voltage value, thereby ensuring the conduction of control transistor TC and output transistor TO. During the boost phase, the nth stage control signal SN(n) has a positive pulse. The gate drive signal G(n) also has a positive pulse.

[0088] During the reset period between time points t3 and t4, the first clock signal CK1 has a low voltage value. Therefore, the nth-level control signal SN(n) has a low voltage value. The gate drive signal G(n) also has a low voltage value. During the reset period, the (n+1)th-level control signal SN(n+1) has a positive pulse. Therefore, the pull-down transistor TP2 is turned on to pull down the voltage value at the operating node NDP to a low voltage value. The control transistor TC, the output transistor TO, and the setting transistors TS3 and TS3' are turned off. During the reset period, the second clock signal CK2 has a positive pulse. Therefore, the setting transistors TS1 and TS2 are turned on to pull up the voltage value at the control node NDX1 to a high voltage value. Transistors TN1 to TN3 and the switching transistor TT2 are turned on according to the high voltage value at the control node NDX1. Therefore, the noise at the operating node NDP, the noise at the second terminal of the output transistor TO, and the noise at the second terminal of the control transistor TC are suppressed.

[0089] During the reset period between time points t3 and t4, setting transistors TS1' and TS2' are turned on to pull down the voltage at control node NDX2 to a low value. Transistors TN1' to TN3' are turned off based on the low voltage at control node NDX2. Therefore, transistors TN1' to TN3' are idle. Furthermore, switching transistor TT2 is turned off based on the low voltage at control node NDX2. Switching transistor TT2 also pulls down the voltage at control node NDX2 based on the high voltage at control node NDX1, thereby ensuring that the voltage at control node NDX2 remains at a low value.

[0090] After time point t4, the setting transistor TS2 is configured to respond to the positive pulse of the second clock signal CK2 to maintain the voltage value at the control node NDX1 at a high voltage value.

[0091] During the second period TD2, bias signal VB2 has a high voltage value. Bias signal VB1 has a low voltage value. During the setting period between time point t5 and time point t6, the (n-1)th stage control signal SN(n-1) has a positive pulse. Pull-up transistor TP1 can be turned on according to the positive pulse of the (n-1)th stage control signal SN(n-1), pulling up the voltage value at the operating node NDP to the first voltage value. Therefore, control transistor TC and output transistor TO are turned on. In addition, setting transistors TS3 and TS3' are also turned on. Therefore, the voltage values ​​at control nodes NDX1 and NDX2 are pulled down to low voltage values. During the setting period, the first clock signal CK1 has a low voltage value. Therefore, the nth stage control signal SN(n) has a low voltage value. The gate drive signal G(n) also has a low voltage value.

[0092] During the boost phase between time points t6 and t7, the (n-1)th stage control signal SN(n-1) has a low voltage value. Pull-up transistor TP1 is disconnected to allow the operating node NDP to float. Control transistor TC and output transistor TO remain on. The first clock signal CK1 has a positive pulse. A high voltage value is present at the second terminal of output transistor TO. Therefore, based on the capacitive coupling of coupling capacitor CP, the gate drive circuit GD(n) uses the high voltage value at the second terminal of output transistor TO to further boost the voltage value of operating node NDP to a second voltage value, thereby ensuring the conduction of control transistor TC and output transistor TO. During the boost phase, the nth stage control signal SN(n) has a positive pulse. The gate drive signal G(n) also has a positive pulse.

[0093] During the reset period between time points t7 and t8, the first clock signal CK1 has a low voltage value. Therefore, the nth stage control signal SN(n) has a low voltage value. The gate drive signal G(n) also has a low voltage value. During the reset period, the (n+1)th stage control signal SN(n+1) has a positive pulse. Therefore, the pull-down transistor TP2 is turned on to pull down the voltage value at the operating node NDP to a low voltage value. The control transistor TC, the output transistor TO, and the setting transistors TS3 and TS3' are turned off. During the reset period, the second clock signal CK2 has a positive pulse. Therefore, the setting transistors TS1' and TS2' are turned on to pull up the voltage value at the control node NDX2 to a high voltage value. Transistors TN1' to TN3' and the switching transistor TT1 are turned on according to the high voltage value at the control node NDX2. Therefore, the noise at the operating node NDP, the noise at the second terminal of the output transistor TO, and the noise at the second terminal of the control transistor TC are suppressed.

[0094] During the reset period between time points t7 and t8, setting transistors TS1 and TS2 are turned on to pull down the voltage value at control node NDX1 to a low value. Transistors TN1 to TN3 are turned off based on the low voltage value at control node NDX2. Therefore, transistors TN1 to TN3 are idle. Furthermore, switching transistor TT2 is turned off based on the low voltage value at control node NDX2. Switching transistor TT1 also pulls down the voltage value at control node NDX1 based on the high voltage value at control node NDX2, thereby ensuring that the voltage value at control node NDX1 remains at a low value.

[0095] After time point t8, the transistor TS2' is configured to respond to the positive pulse of the second clock signal CK2 to maintain the voltage value at the control node NDX2 at a high voltage value.

[0096] In some embodiments, Figure 4The voltage regulator capacitor CC shown can be positioned between the control node NDX1 and the reference low voltage VGL. In some embodiments, Figure 4 The voltage regulator capacitor CC shown can be positioned between the control node NDX2 and the reference low voltage VGL.

[0097] In summary, the gate drive circuit can use the nth-level control signal to control other gate drive circuits. The nth-level control signal is not affected by pixel circuit interference. Furthermore, the noise suppression circuit suppresses noise located at the operating node, the second terminal of the output transistor, and the second terminal of the control transistor. The noise suppression circuit isolates noise located at the operating node, the second terminal of the output transistor, and interference from the second terminal of the control transistor. Therefore, the risk of noise in the nth-level control signal and the gate drive signal can be reduced. This results in high stability for the gate drive circuit. Moreover, even when the nth-level control signal is free of noise, the risk of short circuits caused by malfunctions in other gate drive circuits can be reduced. Therefore, the lifespan of the gate drive device can be increased.

[0098] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: A pull-up circuit, connected to the operating node, is configured to pull up the voltage value located at the operating node according to the (n-1)th level control signal; A pull-down circuit, connected to the operating node, is configured to pull down the voltage value located at the operating node according to the (n+1)th level control signal; An output transistor, wherein a first terminal of the output transistor receives a first clock signal, a second terminal of the output transistor outputs a gate drive signal, and a control terminal of the output transistor is connected to the operating node; A coupling capacitor is connected between the second terminal of the output transistor and the control terminal of the output transistor; A control transistor, wherein a first terminal of the control transistor receives the first clock signal, a second terminal of the control transistor outputs an nth-level control signal, and the control terminal of the control transistor is connected to the operating node; and A noise suppression circuit, connected to the operating node, the second terminal of the output transistor, and the second terminal of the control transistor, is configured to suppress noise located at the operating node, the second terminal of the output transistor, and the second terminal of the control transistor according to the (n+1)th level control signal.

2. The gate driving circuit according to claim 1, characterized in that, The pull-up circuit includes: A pull-up transistor, wherein the first terminal of the pull-up transistor and the control terminal of the pull-up transistor receive the (n-1)th level control signal, and the second terminal of the pull-up transistor is connected to the operating node.

3. The gate driving circuit according to claim 1, characterized in that, The pull-down circuit includes: A pull-down transistor, wherein the first terminal of the pull-down transistor receives a reference low voltage, the second terminal of the pull-down transistor is connected to the operating node, and the control terminal of the pull-down transistor receives the (n+1)th stage control signal.

4. The gate driving circuit according to claim 1, characterized in that, The noise suppression circuit includes: A circuit is configured, connected to the control node, to pull up the voltage value at the control node to a high voltage value according to the (n+1)th level control signal; and A voltage regulator circuit, connected to the control node, the operating node, the second terminal of the output transistor, and the second terminal of the control transistor, is configured to suppress noise at the operating node, the second terminal of the output transistor, and the second terminal of the control transistor in response to a high voltage value at the control node.

5. The gate driving circuit according to claim 4, characterized in that, The setting circuit includes: A first setting transistor, the first terminal of the first setting transistor receives a bias signal, the second terminal of the first setting transistor is connected to the control node, and the control terminal of the first setting transistor receives the (n+1)th level control signal; A second setting transistor, wherein a first terminal of the second setting transistor receives the bias signal, a second terminal of the second setting transistor is connected to the control node, and a control terminal of the second setting transistor receives one of the bias signal and a second clock signal; and A third setting transistor, wherein the first terminal of the third setting transistor is connected to the control node, the second terminal of the third setting transistor is connected to the first reference low voltage, and the control terminal of the third setting transistor is connected to the operation node.

6. The gate driving circuit according to claim 5, characterized in that, The setting circuit also includes: A fourth setting transistor, wherein the first terminal of the fourth setting transistor is connected to the control node, the second terminal of the fourth setting transistor is connected to the first reference low voltage, and the control terminal of the fourth setting transistor receives the (n-1)th level control signal.

7. The gate driving circuit according to claim 5, characterized in that, The setting circuit also includes: A voltage-stabilizing capacitor is connected between the control node and the second reference low voltage.

8. The gate driving circuit according to claim 4, characterized in that, The voltage regulator circuit includes: A first transistor, wherein a first terminal of the first transistor is connected to the operating node, a second terminal of the first transistor is connected to a first reference low voltage, and a control terminal of the first transistor is connected to the control node; A second transistor, the first terminal of which is connected to the second terminal of the control transistor, the second terminal of which is connected to a second reference low voltage, and the control terminal of which is connected to the control node; and The third transistor has a first terminal connected to the second terminal of the output transistor, a second terminal connected to a second reference low voltage, and a control terminal connected to the control node.

9. The gate driving circuit according to claim 8, characterized in that, The first transistor, the second transistor, and the third transistor are turned on according to a high voltage value at the control node and turned off according to a low voltage value at the control node.

10. The gate driving circuit according to claim 1, characterized in that, The noise suppression circuit includes: A first setting circuit, connected to a first control node, is configured to pull up the voltage value at the first control node to a high voltage value based on the (n+1)th level control signal and the first bias signal. A second setting circuit, connected to the second control node, is configured to pull up the voltage value at the second control node to a high voltage value according to the (n+1)th level control signal and the second bias signal, wherein the first bias signal and the second bias signal are complementary to each other. A first voltage regulator circuit, connected to the first control node, the operating node, the second terminal of the output transistor, and the second terminal of the control transistor, is configured to suppress noise at the operating node, the second terminal of the output transistor, and the second terminal of the control transistor in response to a high voltage value at the first control node; and A second voltage regulator circuit, connected to the second control node, the operating node, the second terminal of the output transistor, and the second terminal of the control transistor, is configured to suppress noise at the operating node, the second terminal of the output transistor, and the second terminal of the control transistor in response to a high voltage value at the second control node.

11. The gate driving circuit according to claim 10, characterized in that, The noise suppression circuit switches the voltage value of the second control node to a low voltage value based on the high voltage value of the first control node, and switches the voltage value of the first control node to a low voltage value based on the high voltage value of the second control node.

12. The gate driving circuit according to claim 10, characterized in that, The first setting circuit includes: A first setting transistor, the first terminal of the first setting transistor receives a first bias signal, the second terminal of the first setting transistor is connected to the first control node, and the control terminal of the first setting transistor receives the (n+1)th level control signal. A second setting transistor, wherein a first terminal of the second setting transistor receives the first bias signal, a second terminal of the second setting transistor is connected to the first control node, and a control terminal of the second setting transistor receives a second clock signal; and A third setting transistor, wherein the first terminal of the third setting transistor is connected to the first control node, the second terminal of the third setting transistor is connected to the first reference low voltage, and the control terminal of the third setting transistor is connected to the operation node.

13. The gate driving circuit according to claim 12, characterized in that, The second setting circuit includes: The fourth setting transistor has a first terminal that receives a second bias signal, a second terminal that is connected to the second control node, and a control terminal that receives the (n+1)th level control signal. A fifth setting transistor, wherein a first terminal of the fifth setting transistor receives the second bias signal, a second terminal of the fifth setting transistor is connected to the second control node, and a control terminal of the fifth setting transistor receives a second clock signal; and A sixth setting transistor, the first terminal of which is connected to the second control node, the second terminal of which is connected to the first reference low voltage, and the control terminal of which is connected to the operation node.

14. The gate driving circuit according to claim 10, characterized in that, The first voltage regulator circuit includes: A first transistor, wherein a first terminal of the first transistor is connected to the operating node, a second terminal of the first transistor is connected to a first reference low voltage, and a control terminal of the first transistor is connected to the first control node; A second transistor, the first terminal of which is connected to the second terminal of the control transistor, the second terminal of which is connected to a second reference low voltage, and the control terminal of which is connected to the first control node; and The third transistor has a first terminal connected to the second terminal of the output transistor, a second terminal connected to the second reference low voltage, and a control terminal connected to the first control node.

15. The gate driving circuit according to claim 14, characterized in that, The second voltage regulator circuit includes: A fourth transistor, wherein a first terminal of the fourth transistor is connected to the operating node, a second terminal of the fourth transistor is connected to a first reference low voltage, and a control terminal of the fourth transistor is connected to the second control node; A fifth transistor, wherein a first terminal of the fifth transistor is connected to a second terminal of the control transistor, the second terminal of the fifth transistor is connected to a second reference low voltage, and a control terminal of the fifth transistor is connected to the second control node; and A sixth transistor, wherein the first terminal of the sixth transistor is connected to the second terminal of the output transistor, the second terminal of the sixth transistor is connected to the second reference low voltage, and the control terminal of the sixth transistor is connected to the second control node.

16. The gate driving circuit according to claim 10, characterized in that, The noise suppression circuit further includes: A first switching transistor, wherein a first terminal of the first switching transistor is connected to the first control node, a second terminal of the first switching transistor is connected to a first reference low voltage, and a control terminal of the first switching transistor is connected to the second control node; and The second switching transistor has a first terminal connected to the second control node, a second terminal connected to the first reference low voltage, and a control terminal connected to the first control node.

Images