Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving assembly, a multiplexing circuit, a connecting line and a plurality of pixel units, the driving assembly is arranged in the binding area and comprises a first output unit; the multiplexing circuit is arranged in the circuit area and comprises a first circuit unit; the connecting line is connected between the driving assembly and the multiplexing circuit, and comprises a first connecting line connected between the first circuit unit and the first output unit; the plurality of pixel units are arranged in the display area and are connected with the multiplexing circuit; the first connecting line comprises a winding section distributed in the display area. The resolution ratio of the display panel can be improved, the wiring space outside the display area is reduced, the frame width of the display panel is reduced, and the narrow-frame display panel is achieved.

Description

[0001] This divisional application is based on a Chinese Patent Application No. 202311070048.5 filed on August 23, 2023, entitled “Display Panel and Display Device”. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] An organic light emitting diode (OLED) display panel has many advantages such as self-emission, low driving voltage, high emission efficiency, short response time, high clarity and contrast, and the realization of flexible display and large-area full-color display, and is considered as the most potential display panel in the industry.

[0004] At present, in the related art, the technology of fanout line layout in the display area (FIAA) is to wind the fanout line from the AA area and connect it to the data line, thereby reducing the area of the lower frame occupied by the fanout line. However, in the case of a large number of data lines, the number of fanout lines corresponding to the data lines is also large, which leads to the need for more space in the AA area for winding the fanout line, making it difficult to meet the demand for high resolution. SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device, which can reduce the wiring space of the first connection line outside the display area and reduce the frame width of the display panel.

[0006] Embodiments of the present application provide a display panel, which comprises a display area, a binding area, and a circuit area between the display area and the binding area.

[0007] The display panel further comprises:

[0008] A driving component is arranged in the binding area and comprises a first output unit.

[0009] A multiplexing circuit is arranged in the circuit area and comprises a first circuit unit.

[0010] A connection line is connected between the driving component and the multiplexing circuit and comprises a first connection line connected between the first circuit unit and the first output unit.

[0011] A plurality of pixel units are arranged in the display area and connected to the multiplexing circuit.

[0012] The first connection line comprises a winding segment distributed in the display area.

[0013] In one embodiment of the present application, the first connection line further comprises a first line segment extending from the binding area to the circuit area and connected to the first output unit, and a second line segment extending from the boundary of the display area to the circuit area and connected to the first circuit unit, and the winding segment is connected between the first line segment and the second line segment.

[0014] In one embodiment of the present application, the first line segment and the second line segment both extend along a first direction, and the first direction is a direction in which the binding area points to the display area, the first line segment and the second line segment are arranged staggered along the first direction, and the winding segment is distributed in the display area in a meandering shape.

[0015] In one embodiment of the present application, the first output unit and the first circuit unit are arranged staggered along the first direction.

[0016] In one embodiment of the present application, the multiplexing circuit comprises a plurality of second circuit units, the plurality of first circuit units and the plurality of second circuit units are arranged along a second direction, the second direction intersects the first direction, the driving assembly comprises a plurality of second output units, the plurality of first output units and the plurality of second output units are arranged along the second direction, and the connection line further comprises a plurality of second connection lines.

[0017] The second connection line extends along the first direction and is connected between the second circuit unit and the second output unit.

[0018] In one embodiment of the present application, the connection line comprises a plurality of the first connection lines, and the plurality of winding segments of the plurality of first connection lines do not intersect.

[0019] In one embodiment of the present application, the connection line comprises at least one winding group, one winding group comprises a plurality of winding segments, and in one winding group, the plurality of winding segments are arranged nested one by one.

[0020] In one embodiment of the present application, the length of the binding area along the second direction is less than the length of the circuit area along the second direction, and the circuit area comprises a first sub-area and a second sub-area, the second sub-area is arranged in alignment with the binding area along the first direction, and the first sub-area is connected to the second sub-area along the second direction.

[0021] The plurality of first circuit units are distributed in the first sub-area, and the second circuit unit is distributed in the second sub-area.

[0022] In an embodiment of the present application, the plurality of second output units comprises edge second output units located at the end of the driving component, and the first output units connected to the first circuit units away from the second sub-area are located at the side of the first output units connected to the first circuit units close to the second sub-area away from the edge second output units.

[0023] In an embodiment of the present application, in the driving component, among the plurality of second output units close to the edge second output units, one first output unit is arranged between two adjacent second output units, and among the plurality of second output units away from the edge second output units, the plurality of second output units are arranged adjacently.

[0024] In an embodiment of the present application, the length of the winding section of the first connecting line connected to the first circuit units away from the second sub-area is greater than the length of the winding section of the first connecting line connected to the first circuit units close to the second sub-area.

[0025] In an embodiment of the present application, the second circuit units and the second output units are arranged in alignment along the first direction.

[0026] In an embodiment of the present application, the plurality of pixel units comprises a plurality of pixel unit groups arranged along the second direction, and each pixel unit group comprises a plurality of pixel units arranged along the first direction.

[0027] In an embodiment of the present application, one pixel unit group is arranged in alignment with one first circuit unit or one second circuit unit along the first direction.

[0028] In an embodiment of the present application, the display panel further comprises a plurality of data line groups, one data line group is connected to one pixel unit group, and each data line group comprises at least two data lines extending along the first direction, and the data lines are connected to the pixel units in the corresponding pixel unit group.

[0029] In an embodiment of the present application, one data line group is connected to one first circuit unit or one second circuit unit along the first direction.

[0030] In an embodiment of the present application, the display panel comprises a substrate, a thin film transistor layer arranged on the substrate, the first circuit units comprise a plurality of first multiplexing thin film transistors in the thin film transistor layer, and the second circuit units comprise a plurality of second multiplexing thin film transistors in the thin film transistor layer.

[0031] One of the first connection lines is connected to the source of the plurality of first multiplex thin film transistors, one of the data lines is connected to the drain of one of the first multiplex thin film transistors, one of the second connection lines is connected to the source of the plurality of second multiplex thin film transistors, and one of the data lines is connected to the drain of one of the second multiplex thin film transistors.

[0032] In an embodiment of the present application, the display panel further comprises a conductive layer disposed on a side of the thin film transistor layer away from the substrate, and a light emitting device layer disposed on a side of the conductive layer away from the thin film transistor layer.

[0033] The conductive layer comprises the first line segment, the second line segment, and the winding segment.

[0034] In an embodiment of the present application, the first line segment partially overlaps the second circuit unit, and the second line segment extends to the first circuit unit from the boundary of the display area and is connected to the source of the first multiplex thin film transistor.

[0035] According to the above-mentioned purposes of the present application, an embodiment of the present application further provides a display device, which comprises the display panel.

[0036] The present application has the following beneficial effects: in the present application, the first connection line is arranged between the first circuit unit and the first output unit, so that the signal in the driving assembly is transmitted to the display area through the multiplexing circuit, and then the number of the first connection line relative to the number of the data line in the related art can be reduced, and the winding segment in the first connection line is arranged, so that the first circuit unit can be arranged according to the actual demand at the preset position, and then the winding of the fanout in the related art can be replaced by the winding segment of the first connection line between the multiplexing circuit and the driving assembly, the number of the winding can be reduced, the available space in the display area is increased, and the resolution of the display panel is improved; further, the winding segment in the first connection line is located in the display area, so that the winding segment does not occupy the space of the circuit area, and then the wiring space outside the display area is reduced, and the frame width of the display panel is reduced, and a narrow frame display panel can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0037] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application, combined with the accompanying drawings.

[0038] Figure 1 A partial planar distribution structure schematic diagram of the display panel provided by an embodiment of the present application is shown in the following figure.

[0039] Figure 2 Another partial planar distribution structure schematic diagram of the display panel provided by an embodiment of the present application is shown in the following figure.

[0040] Figure 3 A circuit structure schematic diagram of the first circuit unit and the second circuit unit provided for the embodiment of the present application is shown in FIG. 1;

[0041] Figure 4 A circuit structure schematic diagram of the second circuit unit provided for the embodiment of the present application is shown in FIG. 2;

[0042] Figure 5 Another partial plane distribution structure schematic diagram of the display panel provided for the embodiment of the present application is shown in FIG. 3;

[0043] Figure 6 A plane distribution structure schematic diagram of the display panel provided for the embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0045] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplifying the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to the same reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0046] The embodiment of the present application provides a display panel, please combine Figure 1 and Figure 2 The display panel includes a display area 101, a binding area 1022, and a circuit area 1021 located between the display area 101 and the binding area 1022.

[0047] Further, the display panel further comprises a driving component 10, a multiplexing circuit 20, a connection line and a plurality of pixel units 40; the driving component 10 is arranged in the binding area 1022 and comprises a first output unit 11; the multiplexing circuit 20 is arranged in the circuit area 1021 and comprises a first circuit unit 21; the connection line is connected between the driving component 10 and the multiplexing circuit 20 and comprises a first connection line 31 connected between the first circuit unit 21 and the first output unit 11; the plurality of pixel units 40 are arranged in the display area 101 and connected with the plurality of multiplexing circuits 20.

[0048] The first connection line 31 comprises a winding segment 313 distributed in the display area 101.

[0049] In the implementation process, the first connection line 31 is arranged between the first circuit unit 21 and the first output unit 11 in the embodiment of the present application, so that the signal in the driving component 10 is transmitted to the display area 101 through the multiplexing circuit 20, and then the number of the first connection line 31 relative to the number of the data line in the related art can be reduced, and the winding segment 313 is arranged in the first connection line 31, so that the first circuit unit 21 can be arranged according to the preset position, and then the winding of the fanout line in the related art can be replaced by the winding segment 313 of the first connection line 31 between the multiplexing circuit 20 and the driving component 10 in the embodiment of the present application, the number of the winding can be reduced, the available space in the display area 101 is increased, and the resolution of the display panel is improved; further, the winding segment 313 in the first connection line 31 is located in the display area 101, which avoids occupying the space of the circuit area 1021 by the winding segment 313, and then the wiring space outside the display area 101 is reduced, and then the frame width of the display panel is reduced, and the narrow-frame display panel can be realized.

[0050] Specifically, please continue to combine Figure 1 and Figure 2 The display panel provided by the embodiment of the present application comprises a display area 101 and a non-display area 102 adjacent to the display area 101, and the non-display area 102 can be arranged around the display area 101; and the non-display area 102 can comprise a binding area 1022 located at least one side of the display area 101 and a circuit area 1021 located between the binding area 1022 and the display area 101.

[0051] Further, the display panel further comprises a plurality of pixel units 40 arranged in the display area 101, a driving component 10 arranged in the binding area 1022, a multiplexing circuit 20 arranged in the circuit area 1021, and a plurality of connection lines.

[0052] The plurality of pixel units 40 are arranged in an array along a first direction M and a second direction N, the first direction M is a direction in which the binding area 1022 points to the display area 101, and the second direction N intersects the first direction M.

[0053] In an embodiment, the first direction M is perpendicular to the second direction N.

[0054] The plurality of pixel units 40 can be divided into a plurality of pixel unit groups arranged along the second direction N, and each pixel unit group includes a plurality of pixel units 40 arranged along the first direction M, that is, each pixel unit group includes a column of pixel units 40 arranged along the first direction M.

[0055] The driving assembly 10 includes a plurality of first output units 11 and a plurality of second output units 12; in an embodiment, the plurality of first output units 11 and the plurality of second output units 12 can be arranged on a side of the driving assembly 10 close to the display area 101.

[0056] The multiplexing circuit 20 includes a plurality of first circuit units 21 and a plurality of second circuit units 22, and the connection lines include a plurality of first connection lines 31 and a plurality of second connection lines 32, wherein the first output units 11 are connected to the first circuit units 21 through the first connection lines 31, and the second output units 12 are connected to the second circuit units 22 through the second connection lines 32.

[0057] The first connection line 31 includes a first line segment 311 connected to the first output unit 11 and extending into the circuit area 1021 from the binding area 1022, a second line segment 312 extending into the circuit area 1021 and connected to the first circuit unit 21, and a winding segment 313 connected between the first line segment 311 and the second line segment 312 and located in the display area 101; one end of the second connection line 32 is connected to the second output unit 12, and the other end is connected to the second circuit unit 22.

[0058] In an embodiment of the present application, one pixel unit group is arranged in alignment with one first circuit unit 21 along the first direction M or in alignment with one second circuit unit 22, and the display panel further includes a plurality of data line groups arranged in the display area 101 along the first direction M, one data line group is connected to one first circuit unit 21 or one second circuit unit 22 along the first direction M, one data line group is connected to one pixel unit group, each data line group includes at least two data lines 50, and the at least two data lines 50 are connected to the pixel units 40 in the corresponding pixel unit group.

[0059] In an embodiment, the number of data lines 50 in the data line group is four.

[0060] It can be understood that the first circuit unit 21 is connected by the first connection line 31, and then the signal is transmitted to the at least two data lines 50 by the first circuit unit 21, or the second circuit unit 22 is connected by the second connection line 32, and then the signal is transmitted to the at least two data lines 50 by the second circuit unit 22, so as to realize the multiplexing function of the multiplexing circuit 20.

[0061] The length of the binding area 1022 along the second direction N is less than the length of the circuit area 1021 along the second direction N, so that part of the driving components 10 and part of the multiplexing circuit 20 cannot be aligned; in an embodiment, the circuit area 1021 includes a second sub-area 1032 aligned with the binding area 1022, and a first sub-area 1031 connected to the second sub-area 1032 along the second direction N.

[0062] In the embodiment of the present application, the first circuit unit 21 is arranged in the first sub-area 1031, and the second circuit unit 22 is arranged in the second sub-area 1032, so that the first circuit unit 21 and the second circuit unit 22 can be aligned with the corresponding pixel unit group along the first direction M, so as to avoid the need for additional fan-out lines in the display area 101 corresponding to each data line, thereby saving wiring space and reducing signal interference.

[0063] It should be noted that in the embodiment of the present application, the display panel can include a substrate, a thin film transistor layer arranged on the substrate, a conductive layer arranged on the side of the thin film transistor layer away from the substrate, and a light emitting device layer arranged on the side of the conductive layer away from the thin film transistor layer, further, the light emitting device layer includes an anode layer arranged on the side of the conductive layer away from the thin film transistor layer, a light emitting layer arranged on the side of the anode layer away from the conductive layer, and a cathode layer arranged on the side of the light emitting layer away from the anode layer; wherein the winding segment 313 of the first connection line 31 can be located in the conductive layer, so that the winding segment 313 can overlap with each pixel unit 40 without affecting the normal light emission of the pixel unit 40; in addition, the thin film transistor layer includes a display thin film transistor arranged in each pixel unit 40, the display thin film transistor includes a source-drain electrode, the conductive layer further includes a transfer part connected between the source-drain electrode and the anode layer, and the winding segment 313 is arranged apart from the transfer part.

[0064] In an embodiment, the first output unit 11 and the first circuit unit 21 are arranged staggered along the first direction M, the second output unit 12 and the second circuit unit 22 are aligned along the first direction M, one first connection line 31 connects one first circuit unit 21, and one second connection line 32 connects one second circuit unit 22.

[0065] Please refer to Figure 1 , Figure 3 andFigure 4 The first circuit unit 21 includes a first multiplex thin film transistor T1 in the thin film transistor layer, and the first multiplex thin film transistor T1 includes an active layer, a gate, a source and a drain. The second circuit unit 22 includes a second multiplex thin film transistor T2 in the thin film transistor layer, and the second multiplex thin film transistor T2 includes an active layer, a gate, a source and a drain.

[0066] In the multiplex circuit 20, for the first circuit unit 21, one first connecting line 31 is connected to the sources of the plurality of first multiplex thin film transistors T1, one data line 50 is connected to the drain of one first multiplex thin film transistor T1, and one first control line 61 is connected to the gate of one first multiplex thin film transistor T1. Thus, in the first circuit unit 21, the plurality of first multiplex thin film transistors T1 can be selected to be turned on or turned off by the plurality of first control lines 61, so that the one first connecting line 31 and the plurality of first multiplex thin film transistors T1 transmit signals to the plurality of data lines 50, and Figure 3 In the multiplex circuit 20, for the first circuit unit 21, one first connecting line 31 is connected to the sources of the plurality of first multiplex thin film transistors T1, one data line 50 is connected to the drain of one first multiplex thin film transistor T1, and one first control line 61 is connected to the gate of one first multiplex thin film transistor T1. Thus, in the first circuit unit 21, the plurality of first multiplex thin film transistors T1 can be selected to be turned on or turned off by the plurality of first control lines 61, so that the one first connecting line 31 and the plurality of first multiplex thin film transistors T1 transmit signals to the plurality of data lines 50, and Figure 4 In the multiplex circuit 20, for the first circuit unit 21, one first connecting line 31 is connected to the sources of the plurality of first multiplex thin film transistors T1, one data line 50 is connected to the drain of one first multiplex thin film transistor T1, and one first control line 61 is connected to the gate of one first multiplex thin film transistor T1. Thus, in the first circuit unit 21, the plurality of first multiplex thin film transistors T1 can be selected to be turned on or turned off by the plurality of first control lines 61, so that the one first connecting line 31 and the plurality of first multiplex thin film transistors T1 transmit signals to the plurality of data lines 50, and Figure 1 Figure 3 As the first connecting line 31 is connected to the first circuit unit 21 through the first line segment 311, the winding segment 313 and the second line segment 312 in sequence, and the second line segment 312 is arranged to be staggered with the corresponding first circuit unit 21 along the first direction M, the winding segment 313 is bent and wound back to the second line segment 312 in the display area 101, so that the second line segment 312 can be arranged to be aligned with the corresponding first circuit unit 21 along the first direction M. Thus, the second line segment 312 extends from the boundary of the display area 101 into the first circuit unit 21 and is connected to the source of the first multiplex thin film transistor T1, and extends into the first circuit unit 21 along the data line 50, as shown in Figure 3

[0067] It can be understood that, Figure 3 and Figure 4 ​​The first circuit unit 21 and the second circuit unit 22 and the distribution of the lines provided in the embodiment of the present application are only a schematic diagram, and can be adjusted according to actual needs, and are not limited herein.

[0068] Further, the first output unit 11 and the second circuit unit 22 can be arranged in alignment along the first direction M; it should be noted that the first line segment 311 and the second line segment 312 are both located in the conductive layer, and thus when the first line segment 311 extends from the binding area 1022 to the circuit area 1021, the first line segment 311 can be arranged to pass through the second circuit unit 22, that is, the second line segment 312 can partially overlap the second circuit unit 22, and can also partially overlap the second multiplex thin film transistor T2.

[0069] It should be noted that in the embodiment of the present application, the first circuit unit 21 and the second circuit unit 22 are arranged in the area aligned with the corresponding pixel unit group, and then the connection between the first circuit unit 21 and the first output unit 11 and the connection between the second circuit unit 22 and the second output unit 12 are realized through the first connecting line 31 and the second connecting line 32; since the first output unit 11 and the first circuit unit 21 are arranged in misalignment along the first direction M, there will be a line segment intersecting the first direction M in the first connecting line 31, for example, the winding line segment 313.

[0070] As described above, the first line segment 311 and the second line segment 312 extend along the first direction M, and the first line segment 311 and the second line segment 312 are arranged staggered along the first direction M and are distributed in the display area 101 in a bent shape around the winding segment 313; that is, in the embodiment of the present application, the first line segment 311 and the second line segment 312 of the first connecting line 31 located outside the display area 101 are arranged as straight line segments, and the winding segment 313 in a curve or broken line is arranged in the display area 101, thereby effectively reducing the wiring space outside the display area 101 to reduce the width of the frame; in addition, in the embodiment of the present application, the winding is arranged in the first connecting line 31 between the first output unit 11 and the first circuit unit 21 to realize signal transmission, so that the first circuit unit 21 can be arranged in alignment with the corresponding pixel unit group along the first direction M, and the data lines 50 in the data line group corresponding to the pixel unit group can be connected to the corresponding first circuit unit 21 along the first direction M. Since there are at least two data lines 50 in each data line group, for example, there can be four data lines 50, compared with the related art, in the related art, a plurality of fanout wires corresponding to the plurality of data lines 50 are required to be arranged for winding, and in the embodiment of the present application, the winding of the fanout wire is replaced by the winding segment 313 in the first connecting line 31 between the first circuit unit 21 and the first output unit 11, and the number of the first connecting line 31 is less than the number of the data line 50, that is, less than the number of the fanout wire in the related art, thereby avoiding the winding of a large number of fanout wires in the display area 101, and the winding of a small number of first connecting lines 31, thereby reducing the space for winding in the display area 101, and simplifying the wiring difficulty and reducing the signal interference.

[0071] In addition, since the second output unit 12 and the second circuit unit 22 are arranged in alignment along the first direction M, the second connecting line 32 is connected between the second output unit 12 and the second circuit unit 22 along the first direction M.

[0072] Further, the plurality of winding segments 313 in the plurality of first connecting lines 31 do not intersect, so as to reduce the wiring difficulty.

[0073] In an embodiment, the plurality of connection lines comprises at least one winding group, and each winding group comprises a plurality of winding segments 313, and in each winding group, the plurality of winding segments 313 are arranged in a nested manner. The plurality of winding segments 313 in the plurality of first connection lines 31 are arranged in a nested manner, i.e., the plurality of winding segments 313 are arranged in a coil. The winding segment 313 in the first connection line 31 connected to the first circuit unit 21 near the side of the second sub-area 1032 is located at the inner side of the coil, and the winding segment 313 in the first connection line 31 connected to the first circuit unit 21 far from the side of the second sub-area 1032 is located at the outer side of the coil. Further, the length of the winding segment 313 in the first connection line 31 connected to the first circuit unit 21 far from the side of the second sub-area 1032 is greater than the length of the winding segment 313 in the first connection line 31 connected to the first circuit unit 21 near the side of the second sub-area 1032.

[0074] In an embodiment, please refer to Figure 1 In the driving assembly 10, at least one second output unit 12 is arranged between two first output units 11, for example, one second output unit 12 is arranged between two first output units 11. In addition, the plurality of second output units 12 comprises edge second output units 121 located at the ends of the driving assembly 10, and the first output unit 11 connected to the first circuit unit 21 far from the side of the second sub-area 1032 is located at the side of the first output unit 11 connected to the first circuit unit 21 near the side of the second sub-area 1032 far from the edge second output unit 121. Further, in the plurality of second output units 12 near the edge second output unit 121, one first output unit 11 is arranged between two adjacent second output units 12, and in the plurality of second output units 12 far from the edge second output unit 121, the plurality of second output units 12 are arranged in a nested manner.

[0075] As described above, in an embodiment of the present application, please refer to Figure 2 and Figure 5P1 to P610 are a plurality of circuit units in the multiplexing circuit 20, and S1 to S610 are a plurality of output units in the driving assembly 10; wherein P1 to P200 are first circuit units 21, P201 to P610 are second circuit units 22, S1 to S200 are first output units 11, and S201 to S610 are second output units 12. In the embodiment of the present application, the plurality of circuit units P1 to P610 can be arranged in position according to the respective data line groups or pixel unit groups, so that the plurality of circuit units P1 to P610 are arranged in order; further, the edge second output unit 121 at the end of the driving assembly 10 is S201, and the second output units arranged in order from right to left starting from S201 are S201, S202, S199, …, S399, S2, S400, S1, S401, S402, …, S609, and S610, wherein the plurality of second output units 12 include S201 to S610 and are arranged in order; the plurality of first output units 11 include S1 to S200 and are arranged in reverse order.

[0076] Since P1 connected by S1 is located at the position of the first sub-area 1031 farthest from the second sub-area 1032, the length of the winding segment 313 corresponding to S1 is the largest, so that S1 is located at the position farthest from S201 among S1 to S200, and P200 connected by S200 is located at the position of the first sub-area 1031 closest to the second sub-area 1032, so that the length of the winding segment 313 corresponding to S2 is the smallest, so that S200 is adjacent to S201, and by analogy, the remaining first output units 11 are arranged according to the positions of the first circuit units 21 connected by them, so that S1 to S200 are arranged in reverse order from left to right, and the end of the driving assembly 10 is the edge second output unit 121 (S210), wherein S201 and S202 are separated by S200, S202 and S203 (not shown in the figure) are separated by S199, S399 and S400 are separated by S2, S400 and S401 are separated by S1, and in the above, the embodiment of the present application arranges the first output units 11 in reverse order and the second output units 12 in order in the driving assembly 10, and the first output units 11 and the second output units 12 are arranged in disorder alternately, and cooperates with the plurality of winding segments 313 arranged in nesting in the first connection line 31, so that the plurality of circuit units P1 to P610 can be arranged in order, that is, the circuit units can be arranged in position with the corresponding data line groups or pixel unit groups.

[0077] Further, please refer to Figure 6 , wherein Figure 6The first connection line 31, the second connection line 32, the driving component 10 and the multiplexing circuit 20 are symmetrically arranged on the left and right sides of the display area 101. Figure 6 The plurality of winding segments 313 on the left side of the display area 101 form a winding group. Figure 6 The plurality of winding segments 313 on the right side of the display area 101 form a winding group.

[0078] In summary, in the embodiment of the present application, the first line segment 311 and the second line segment 312 of the first connection line 31 located outside the display area 101 are set as straight line segments, and the winding segment 313 in a curve or a broken line is set in the display area 101, thereby effectively reducing the wiring space outside the display area 101 to reduce the frame width. In addition, in the embodiment of the present application, the winding is arranged in the first connection line 31 between the first output unit 11 and the first circuit unit 21 to realize signal transmission, so that the first circuit unit 21 can be aligned with the corresponding pixel unit group along the first direction M, and the data line 50 in the data line group corresponding to the pixel unit group can be connected to the corresponding first circuit unit 21 along the first direction M. Since there are at least two data lines 50 in each data line group, for example, there can be four data lines, the embodiment of the present application avoids winding a large number of data lines 50 in the display area 101, and makes a small number of first connection lines 31 wind, thereby reducing the arrangement space of the winding in the display area 101, simplifying the wiring difficulty, and reducing signal interference.

[0079] In addition, the embodiment of the present application also provides a display device, which comprises the display panel provided in the above-mentioned embodiments.

[0080] Since the display device is provided with the display panel provided in the above-mentioned embodiments of the present application, the display device has the same beneficial effects as the above-mentioned display panel.

[0081] In an embodiment, the display device can include a television, a computer, a mobile phone, a tablet and other display devices.

[0082] In the above-mentioned embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0083] The above describes in detail the display panel and the display device provided by the embodiment of the present application, and the principle and the implementation mode of the present application are described by using specific examples. The above embodiment is only used to help understand the technical solution of the present application and the core idea thereof. Those skilled in the art should understand that the technical solution recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The display panel includes a display area, a bonding area, and a circuit area located between the display area and the bonding area; The display panel also includes: A driving component, disposed within the binding area, includes a first output unit; A multiplexing circuit is disposed within the circuit area and includes a first circuit unit; A connecting line is connected between the driving component and the multiplexing circuit, and includes a first connecting line connecting the first circuit unit and the first output unit; Multiple pixel units are disposed in the display area and connected to the multiplexing circuit. The multiple pixel units include multiple pixel unit groups arranged along a second direction. The pixel unit group includes multiple pixel units arranged along a first direction. The first direction is the direction from the binding area to the display area. The second direction intersects with the first direction. One pixel unit group is aligned with one of the first circuit units along the first direction. The first connecting line includes winding segments distributed within the display area.

2. The display panel according to claim 1, characterized in that, The first connecting line further includes a first line segment extending from the bonding area to the circuit area and connected to the first output unit, and a second line segment extending from the boundary of the display area to the circuit area and connected to the first circuit unit, wherein the winding segment is connected between the first line segment and the second line segment.

3. The display panel according to claim 2, characterized in that, Both the first line segment and the second line segment extend along the first direction, and the first line segment and the second line segment are staggered along the first direction. The winding line segment is distributed in a bent shape within the display area.

4. The display panel according to claim 2, characterized in that, The first output unit and the first circuit unit are staggered along the first direction.

5. The display panel according to claim 1, characterized in that, The connecting line includes multiple first connecting lines, and the multiple winding segments of the multiple first connecting lines do not intersect.

6. The display panel according to claim 5, characterized in that, The connecting line includes at least one winding group, and a winding group includes multiple winding segments, wherein the multiple winding segments are nested one by one within the winding group.

7. The display panel according to any one of claims 2 to 6, characterized in that, The multiplexing circuit includes multiple second circuit units, and the multiple first circuit units and multiple second circuit units are arranged along the second direction. The driving component includes multiple second output units, and the multiple first output units and multiple second output units are arranged along the second direction. The connecting line also includes multiple second connecting lines. The second connecting line extends along the first direction and connects the second circuit unit and the second output unit.

8. The display panel according to claim 7, characterized in that, The length of the binding area along the second direction is less than the length of the circuit area along the second direction, and the circuit area includes a first sub-area and a second sub-area. The second sub-area is aligned with the binding area along the first direction, and the first sub-area is connected to the second sub-area along the second direction. The plurality of the first circuit units are distributed in the first sub-region, and the plurality of the second circuit units are distributed in the second sub-region.

9. The display panel according to claim 8, characterized in that, The plurality of second output units include an edge second output unit located at the end of the drive assembly, and a first output unit connected to the first circuit unit on the side away from the second sub-region is located on the side of the first output unit connected to the first circuit unit on the side close to the second sub-region away from the edge second output unit.

10. The display panel according to claim 9, characterized in that, Within the drive assembly, among the plurality of second output units near the edge second output unit, there is a first output unit spaced apart between two adjacent second output units, and among the plurality of second output units away from the edge second output unit, the plurality of second output units are arranged adjacent to each other.

11. The display panel according to claim 8, characterized in that, The length of the winding segment of the first connecting line connected to the first circuit unit on the side away from the second sub-region is greater than the length of the winding segment of the first connecting line connected to the first circuit unit on the side closer to the second sub-region.

12. The display panel according to claim 7, characterized in that, The connecting line includes multiple first connecting lines, and multiple winding segments of the multiple first connecting lines are arranged in a loop. The winding segment of the first connecting line connected to the first circuit unit near the second sub-region is located inside the loop, and the winding segment of the first connecting line connected to the first circuit unit away from the second sub-region is located outside the loop.

13. The display panel according to claim 7, characterized in that, The second circuit unit and the second output unit are aligned along the first direction.

14. The display panel according to claim 7, characterized in that, One of the pixel unit groups is aligned with one of the second circuit units along the first direction.

15. The display panel according to claim 7, characterized in that, The display panel further includes multiple data line groups, one of the data line groups being connected to one of the pixel unit groups. Each data line group includes at least two data lines extending along the first direction, and the data lines are connected to the pixel units in the corresponding pixel unit group. In this configuration, one of the data line groups is connected along the first direction to a corresponding first circuit unit or a second circuit unit.

16. The display panel according to claim 15, characterized in that, The display panel includes a substrate and a thin-film transistor layer disposed on the substrate. The first circuit unit includes a plurality of first multiplexed thin-film transistors located in the thin-film transistor layer, and the second circuit unit includes a plurality of second multiplexed thin-film transistors located in the thin-film transistor layer. In this configuration, one first connection line is connected to the source of one of the first multiplexed thin-film transistors, one data line is connected to the drain of one of the first multiplexed thin-film transistors, one second connection line is connected to the source of one of the second multiplexed thin-film transistors, and one data line is connected to the drain of one of the second multiplexed thin-film transistors.

17. The display panel according to claim 16, characterized in that, The display panel further includes a conductive layer disposed on the side of the thin film transistor layer away from the substrate, and a light-emitting device layer disposed on the side of the conductive layer away from the thin film transistor layer; The conductive layer includes the first line segment, the second line segment, and the winding segment.

18. The display panel according to claim 17, characterized in that, The winding segment overlaps with the pixel unit.

19. The display panel according to claim 16, characterized in that, The first line segment partially overlaps with the second circuit unit, and the second line segment extends from the boundary of the display area to the first circuit unit and is connected to the source of the first multiplexed thin-film transistor.

20. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 19.

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