Display panel driving circuit, array substrate row driving circuit and liquid crystal display panel

Abstract

The invention discloses a display panel driving circuit, an array substrate row driving circuit and a liquid crystal display panel, and belongs to the technical field of display. The display panel driving circuit provided by the invention comprises a liquid crystal capacitor, wherein a first end of the liquid crystal capacitor is grounded; the scanning driving module is connected with a scanning driving voltage and a data writing voltage, and the scanning driving module is used for outputting the data writing voltage based on the driving of the scanning driving voltage; the input end of the partial pressure compensation module is connected with the output end of the scanning driving module, the output end of the partial pressure compensation module is connected with the second end of the liquid crystal capacitor, and the partial pressure compensation module is used for compensating the liquid crystal capacitor based on the data write-in voltage under the condition that the scanning driving voltage stops driving. And the control efficiency of the display panel driving circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel driving circuit, an array substrate row driving circuit and a liquid crystal display panel. BACKGROUND

[0002] With the application of display technology more and more frequently, users have higher requirements for the driving circuit on the display panel of VRR (Variable Refresh Rate).

[0003] The traditional display panel driving circuit adopts an algorithm compensation method, detects the time of Vblank (vertical blank area), compensates the Gamma voltage or Vcom voltage, and improves the flicker phenomenon caused by liquid crystal capacitor leakage before and after the refresh rate changes. This display panel driving circuit has great defects, and can only compensate for the low refresh rate that may be cut by the node (i.e. the length of Vblank) prediction. That is, this display panel driving circuit can only compensate for the low refresh rate that may be cut by the node prediction (i.e. the number of nodes needs to be determined first to realize compensation), thereby causing the control efficiency of the display panel driving circuit to be not high.

[0004] The above content is only used to assist in understanding the technical solutions of the present application, and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide a display panel driving circuit, an array substrate row driving circuit and a liquid crystal display panel, which aims to solve the technical problem of low control efficiency of the display panel driving circuit.

[0006] To achieve the above purpose, the present application provides a display panel driving circuit, which comprises:

[0007] A liquid crystal capacitor, a first end of the liquid crystal capacitor being grounded;

[0008] A scan driving module, the scan driving module being connected with a scan driving voltage and a data writing voltage, the scan driving module being configured to output the data writing voltage under the driving of the scan driving voltage;

[0009] A voltage division compensation module, an input end of the voltage division compensation module being connected with an output end of the scan driving module, an output end of the voltage division compensation module being connected with a second end of the liquid crystal capacitor, the voltage division compensation module being configured to compensate the liquid crystal capacitor based on the data writing voltage when the scan driving voltage stops driving.

[0010] In an embodiment, the scan driving module comprises:

[0011] a first thin film transistor, a control terminal of the first thin film transistor being connected to the scan driving voltage, a first terminal of the first thin film transistor being connected to the data writing voltage, and a second terminal of the first thin film transistor being connected to an input terminal of the voltage division compensation module.

[0012] In an embodiment, the voltage division compensation module comprises:

[0013] a third thin film transistor, a control terminal of the third thin film transistor being connected to the second terminal of the first thin film transistor, a first terminal of the third thin film transistor being connected to a power supply, and a second terminal of the third thin film transistor being connected to a second terminal of the liquid crystal capacitor;

[0014] a fourth thin film transistor, a control terminal of the fourth thin film transistor being connected to the second terminal of the first thin film transistor, a second terminal of the fourth thin film transistor being connected to the second terminal of the liquid crystal capacitor, and a first terminal of the fourth thin film transistor being connected to a ground;

[0015] a first gate capacitor, a first terminal of the first gate capacitor being connected to the second terminal of the first thin film transistor, and a second terminal of the first gate capacitor being connected to the first terminal of the third thin film transistor, or a first terminal of the first gate capacitor being connected to the second terminal of the first thin film transistor, and a second terminal of the first gate capacitor being connected to the first terminal of the fourth thin film transistor.

[0016] In an embodiment, the data writing voltage comprises a first data writing voltage and a second data writing voltage, and the scan driving module comprises:

[0017] a first thin film transistor, a control terminal of the first thin film transistor being connected to the scan driving voltage, a first terminal of the first thin film transistor being connected to the first data writing voltage, and a second terminal of the first thin film transistor being connected to an input terminal of the voltage division compensation module;

[0018] a second thin film transistor, a control terminal of the second thin film transistor being connected to the scan driving voltage, a first terminal of the second thin film transistor being connected to the second data writing voltage, and a second terminal of the second thin film transistor being connected to an input terminal of the voltage division compensation module.

[0019] In an embodiment, the voltage division compensation module comprises:

[0020] a third thin film transistor, a control terminal of the third thin film transistor being connected to the second terminal of the first thin film transistor, a first terminal of the third thin film transistor being connected to a power supply, and a second terminal of the third thin film transistor being connected to a second terminal of the liquid crystal capacitor;

[0021] a first gate capacitor, a first end of the first gate capacitor being connected with the second end of the first thin film transistor, and a second end of the first gate capacitor being connected with the first end of the third thin film transistor;

[0022] a fourth thin film transistor, a control end of the fourth thin film transistor being connected with the second end of the second thin film transistor, a second end of the fourth thin film transistor being connected with the second end of the liquid crystal capacitor, and a first end of the fourth thin film transistor being grounded;

[0023] a second gate capacitor, a first end of the second gate capacitor being connected with the second end of the second thin film transistor, and a second end of the second gate capacitor being connected with the first end of the fourth thin film transistor.

[0024] In an embodiment, when the liquid crystal capacitor is in a data writing stage, the first thin film transistor and the second thin film transistor are both turned on, the first data writing voltage is output to the first gate capacitor, and the second data writing voltage is output to the second gate capacitor.

[0025] In an embodiment, when the liquid crystal capacitor is in a writing completion stage, the first thin film transistor and the second thin film transistor are both turned off, the first data writing voltage controls the third thin film transistor to be in a first turned-on state, and the second data writing voltage controls the fourth thin film transistor to be in a second turned-on state, wherein in the first turned-on state and the second turned-on state, a first end-point voltage value of the second end of the liquid crystal capacitor is unchanged.

[0026] In an embodiment, when the liquid crystal capacitor is in a white balance adjustment stage, the first thin film transistor is turned off, the second thin film transistor is turned on, and the fourth thin film transistor is in a third turned-on state, wherein in the first turned-on state and the third turned-on state, a second end-point voltage value of the second end of the liquid crystal capacitor is not equal to the first end-point voltage value.

[0027] In addition, to achieve the above object, the present application further provides an array substrate row driving circuit, which comprises the display panel driving circuit.

[0028] In addition, to achieve the above object, the present application further provides a liquid crystal display panel, which comprises a color film substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being arranged between the array substrate and the color film substrate, and the array substrate comprising the array substrate row driving circuit.

[0029] The application provides a display panel driving circuit, an array substrate row driving circuit and a liquid crystal display panel. The display panel driving circuit is optimized, and the display panel driving circuit comprises a voltage division compensation module and a scanning driving module connected with a liquid crystal capacitor in sequence. The display panel driving circuit of the liquid crystal display panel can only compensate the Gamma voltage or the Vcom voltage by predicting the low refresh rate that can be cut through the node (the length of Vblank) according to the flicker phenomenon caused by the leakage of the liquid crystal capacitor. The node quantity needs to be determined in priority, and the control steps are relatively complicated. The voltage division compensation module stores the data write-in voltage under the driving of the scanning driving module (the scanning driving voltage drives the data write-in voltage of the scanning driving module), so that the liquid crystal capacitor can be compensated based on the data write-in voltage in the case that the scanning driving voltage stops driving (at this time, the leakage of the liquid crystal capacitor exists), and the compensation of the leakage of the liquid crystal capacitor can be directly realized without determining the node quantity, so that the control efficiency of the display panel driving circuit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained according to the structures shown in the drawings without creative labor for those skilled in the art.

[0031] Figure 1 The figure is a functional module schematic diagram of an embodiment of the display panel driving circuit of the application.

[0032] Figure 2 The figure is a circuit connection schematic diagram of an existing display panel driving circuit.

[0033] Figure 3 The figure is a circuit connection schematic diagram of the first embodiment of the display panel driving circuit of the application.

[0034] Figure 4 The figure is a characteristic curve schematic diagram of a thin film transistor in the display panel driving circuit of the application.

[0035] Figure 5 The figure is a circuit connection schematic diagram of the second embodiment of the display panel driving circuit of the application.

[0036] Figure 6 The figure is a circuit connection schematic diagram of the third embodiment of the display panel driving circuit of the application.

[0037] Figure 7 The figure is a structure schematic diagram of the liquid crystal display panel related to the embodiment of the application.

[0038] Explanation of the drawings:

[0039] Scan, scan driving voltage; 10, scan driving module; 20, voltage division compensation module; Data, data writing voltage; ClC, liquid crystal capacitor; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; C1, first gate capacitor; C2, second gate capacitor; VAA, power supply; Data1, first data writing voltage; Data2, second data writing voltage; iD, drain current; uDS, source-drain voltage; uGS, source-gate voltage.

[0040] Scan, scan driving voltage; 10, scan driving module; 20, voltage division compensation module; Data, data writing voltage; ClC, liquid crystal capacitor; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; C1, first gate capacitor; C2, second gate capacitor; VAA, power supply; Data1, first data writing voltage; Data2, second data writing voltage; iD, drain current; uDS, source-drain voltage; uGS, source-gate voltage.

[0041] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0042] It should be understood that the specific embodiments described herein are merely exemplary and are not intended to limit the present application.

[0043] The present application provides a display panel driving circuit, which will be described with reference to Figure 1 , Figure 1 The present application provides a display panel driving circuit, which will be described with reference to

[0044] In the present embodiment, the display panel driving circuit comprises:

[0045] A liquid crystal capacitor ClC, a first end of the liquid crystal capacitor ClC being connected to ground;

[0046] A scan driving module 10, the scan driving module 10 being connected to a scan driving voltage Scan and a data writing voltage Data, the scan driving module 10 being configured to output the data writing voltage Data under the driving of the scan driving voltage Scan;

[0047] A voltage division compensation module 20, an input end of the voltage division compensation module 20 being connected to an output end of the scan driving module 10, an output end of the voltage division compensation module 20 being connected to a second end of the liquid crystal capacitor ClC, the voltage division compensation module 20 being configured to compensate the liquid crystal capacitor ClC based on the data writing voltage Data when the scan driving voltage Scan stops driving.

[0048] It should be noted that the implementation of VRR display is generally achieved by changing Vblank on the panel. On the display panel, in addition to the actual display Active area, there are other areas, which are collectively referred to as blank area, the vertical direction is Vblank, and the horizontal direction is Hblank. VRR is to change the total time of a frame by changing the length of Vblank, and then change the refresh rate. Therefore, when the panel is turned on VRR, there will be a long Vblank time for low refresh rate and a short Vblank for high refresh rate. Because the Vblank interval does not charge the liquid crystal capacitor, the liquid crystal capacitor will leak, and the longer the Vblank time, the more the leakage. That is, when VRR is turned on, the liquid crystal capacitor leaks more at low refresh rate, and the brightness is low. The liquid crystal capacitor leaks less at high refresh rate, and the brightness is high at high refresh rate. When the refresh rate changes greatly (such as switching from high refresh rate to low refresh rate, or switching from low refresh rate to high refresh rate), flicker can be seen due to the leakage of the liquid crystal capacitor in the Vblank time interval. Further, in order to improve the flicker phenomenon caused by the switching of the refresh rate, the charging voltage is compensated, which can be referred to as Figure 2 , Figure 2 The present application provides a circuit connection diagram of a display panel driving circuit. When charging the liquid crystal capacitor Clc, the first thin film transistor T1 is turned on by the scan driving voltage Scan to directly send the data write voltage Data to the liquid crystal capacitor Clc to charge the liquid crystal capacitor Clc. However, after charging (i.e. the first thin film transistor T1 is turned off by the scan driving voltage Scan), the liquid crystal capacitor Clc leaks because it is not charged. The amount of leakage increases with the increase of Vblank. Finally, when displaying at other refresh rates next time, there is a flicker phenomenon due to the large difference in the amount of charge of the liquid crystal capacitor Clc before and after charging, which affects the user's viewing experience. Therefore, in order to avoid this phenomenon, the prior art uses an algorithm compensation method to compensate the Gamma voltage or Vcom voltage by detecting the time of Vblank. However, the compensation can only be made by predicting the low refresh rate that the node may cut to. Therefore, the number of nodes (i.e. the length of Vblank) determines the compensation accuracy, i.e. the number of nodes needs to be determined to achieve compensation (and the number of nodes at each refresh rate is different). In addition, during debugging, each node needs to be adjusted, which is tedious and affects the control efficiency of the display panel driving circuit, specifically the control efficiency of the display panel driving circuit to improve the flicker phenomenon caused by VRR.

[0049] In the embodiment, by adding the voltage division compensation module 20 in the original display panel driving circuit, and connecting the voltage division compensation module 20 between the scan driving module 10 and the liquid crystal capacitor ClC, at this time the scan driving module 10 is still scanned and driven by the scan driving voltage Scan, and the required voltage is written to the liquid crystal capacitor ClC under the scan driving of the scan driving voltage Scan. Further, the data write voltage Data can be output under the driving of the scan driving voltage Scan, but because the input end of the voltage division compensation module 20 is connected with the output end of the scan driving module 10, the data write voltage Data can be stored in the voltage division compensation module 20 (i.e. a storage device such as a capacitor is arranged in the voltage division compensation module 20). Of course, in order not to affect the voltage writing to the liquid crystal capacitor ClC, the voltage division compensation module 20 can be controlled by the data write voltage Data, and then the voltage is written to the liquid crystal capacitor ClC, and on the other hand, the data write voltage Data can be stored for subsequent use. When the entire scan driving by the scan driving voltage Scan is completed (i.e. the scan driving voltage Scan stops driving, that is, there is no continuous charging to the liquid crystal capacitor ClC), if there is no subsequent continuous charging to the liquid crystal capacitor ClC, the liquid crystal capacitor ClC will leak, and then cause the flicker phenomenon when the refresh rate is switched under VRR. Therefore, the voltage division compensation module 20 will compensate the liquid crystal capacitor ClC based on the previously stored data write voltage Data during the time when there is no continuous charging to the liquid crystal capacitor ClC, so as to ensure that the liquid crystal capacitor ClC will not flicker due to leakage. At this time, the previously stored data write voltage Data can be used to compensate the liquid crystal capacitor ClC during the time when there is no continuous charging to the liquid crystal capacitor ClC, without the algorithm calculation of predicting the low refresh rate to be cut to compensate the Gamma voltage or Vcom voltage, thereby improving the control efficiency of the display panel driving circuit.

[0050] Further, with reference to Figure 3 , Figure 3 is a circuit connection schematic diagram of the first embodiment of the display panel driving circuit of the present application.

[0051] As shown in Figure 3 , in some possible embodiments, the scan driving module 10 includes:

[0052] The first thin film transistor T1 has a control end connected with the scan driving voltage Scan, a first end connected with the data write voltage Data, and a second end connected with the input end of the voltage division compensation module 20.

[0053] Further, in some possible embodiments, the voltage division compensation module 20 comprises:

[0054] a third thin film transistor T3, a control terminal of the third thin film transistor T3 is connected with the second terminal of the first thin film transistor T1, a first terminal of the third thin film transistor T3 is connected with the power supply VAA, and a second terminal of the third thin film transistor T3 is connected with the second terminal of the liquid crystal capacitor ClC;

[0055] a fourth thin film transistor T4, a control terminal of the fourth thin film transistor T4 is connected with the second terminal of the second thin film transistor T2, a second terminal of the fourth thin film transistor T4 is connected with the second terminal of the liquid crystal capacitor ClC, and a first terminal of the fourth thin film transistor T4 is grounded;

[0056] a first gate capacitor C1, a first terminal of the first gate capacitor C1 is connected with the second terminal of the first thin film transistor T1, and a second terminal of the first gate capacitor C1 is connected with the first terminal of the third thin film transistor T3, or a first terminal of the first gate capacitor C1 is connected with the second terminal of the first thin film transistor T1, and a second terminal of the first gate capacitor C1 is connected with the first terminal of the fourth thin film transistor T4.

[0057] In the embodiment, the scan driving module 10 can use the first thin film transistor T1 to perform scan driving, that is, under the control of the scan driving voltage Scan, the data write-in voltage Data can be output to the voltage division compensation module 20, and the voltage division compensation module 20 stores the data write-in voltage Data, so that when the scan driving voltage Scan does not continue to control the first thin film transistor T1, the data write-in voltage Data is used to compensate the electric quantity of the liquid crystal capacitor ClC, so as to avoid the display flicker phenomenon caused by the leakage. For example, refer to Figure 3 The voltage division compensation module 20 is composed of the third thin film transistor T3, the fourth thin film transistor T4 and the first gate capacitor C1, at this time, the liquid crystal capacitor ClC is connected on the connection line between the third thin film transistor T3 and the fourth thin film transistor T4, and the first gate capacitor C1 is used to store the data write-in voltage Data in the time when the data write-in voltage Data is received, so as to compensate the electric quantity of the liquid crystal capacitor ClC subsequently. For example, refer to Figure 4 , Figure 4This is a schematic diagram of the characteristic curve of a thin-film transistor in the display panel driving circuit of this application. The iD-uGS on the left is the transfer characteristic curve of the thin-film transistor, and the iD-uDS on the right is the output characteristic curve of the thin-film transistor. In the output characteristic curve of the thin-film transistor, the state of the thin-film transistor is divided into three working regions: the variable resistance region (non-saturation region) to the left of the thick line, the constant current region (saturation region) to the right of the red line, and the cutoff region below the uGS=1V curve (the output characteristic curve is not shown, but it can be seen from the transfer characteristic curve that when uGS>1V, current flows through ID. This voltage is usually called the threshold voltage Uth of the thin-film transistor). The thick line is the connection that satisfies the relationship uDS=uGS-Uth. Further, it is derived that the drain-source current of the thin-film transistor in the constant current region satisfies formula (1):

[0058] iDS = k*(uGS - |uth|) 2 (1)

[0059] Where k is a constant designed for the thin-film transistor, and k = 1 / 2 * μ * (W / L) * CO, where μ is the carrier mobility (determined by the semiconductor material), W / L is the channel width-to-length ratio, and C0 is the gate capacitance of the thin-film transistor. If the designed and manufactured third thin-film transistor T3 and fourth thin-film transistor T4 have the same channel width-to-length ratio and the same gate capacitance, then the turn-on degree of the third thin-film transistor T3 and the fourth thin-film transistor T4 is controlled by the size of uGS, i.e., the voltage difference between Data and VCOM or Data and VAA in the circuit. Based on the above output characteristic curves, the third thin-film transistor T3 and the fourth thin-film transistor T4 can be considered as resistors that vary with Data; the larger the voltage difference, the greater the conduction degree and the smaller the resistance. Therefore, the conduction degree of the third thin-film transistor T3 and the fourth thin-film transistor T4 can be controlled by Data. In this case, the third thin-film transistor T3 and the fourth thin-film transistor T4 form a push-pull output circuit. According to the principle of push-pull output, the output voltage will be equal to the input voltage. When the scan drive voltage Scan stops controlling the first thin-film transistor T1 to output the data write voltage Data, the data write voltage Data stored on the first gate capacitor C1 is used to maintain the conduction level of the third thin-film transistor T3 and the fourth thin-film transistor T4, so as to ensure that the voltage value between the third thin-film transistor T3 and the fourth thin-film transistor T4 is fixed, thereby ensuring that the second terminal of the liquid crystal capacitor ClC has a stable voltage value. The actual effect is that the liquid crystal capacitor ClC is continuously charged by the data write voltage Data to offset the leakage energy of the liquid crystal capacitor ClC, thereby suppressing or even eliminating the influence of leakage, and thus improving the control efficiency of the display panel driving circuit.

[0060] For example, refer to Figure 5 , Figure 5As shown in FIG. 6, the circuit connection diagram of the second embodiment of the display panel driving circuit of the present application is shown, and the first gate capacitor C1 can also be arranged between the gate and the source of the fourth thin film transistor T4. After scanning of the current row is completed, the Scan signal is turned off the first thin film transistor T1, and thereafter the on-off degree of the third thin film transistor T3 and the fourth thin film transistor T4 is maintained by the first gate capacitor C1, until the next frame scans to the current row, and the data is updated. Through this circuit, the liquid crystal capacitor ClC can be continuously powered, and the leakage charge of the liquid crystal capacitor ClC will be continuously replenished, and when the VRR is turned on, the brightness change caused by the change of the refresh rate will not occur.

[0061] It should be noted that the transistors used in all embodiments of the present application can be TFTs (Thin Film Transistors), field effect transistors or other devices with the same characteristics. Since the second end and the drain of the transistor used herein are symmetrical, the source and the drain can be interchangeable. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one pole is called the source and the other pole is called the drain. In the embodiments of the present application, the source and the drain of the transistor can be interchangeable. Figure 4 In the first thin film transistor T1, the characteristics of each port can be determined according to the G, D and S labels in the figure, wherein G is the control end of T1, S is the first end of T1, and D is the second end of T1. The characteristics of the remaining transistors can be determined according to the shapes in the figure: the middle end of each transistor is the gate, the signal input end is the source, and the signal output end is the drain. Figure 4 In addition, the transistors used in the embodiments of the present application can include P-type transistors and / or N-type transistors, wherein the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. The first gate driving voltage Vgate and the second gate driving voltage Share_Vgate of the corresponding N-type and P-type transistors have different on-off modes, and the corresponding control modes also have differences. The actual transistor is controlled, which is not limited herein.

[0062] Further, in some possible embodiments, the first thin film transistor T1 to the fourth thin film transistor T4 can be low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon thin film transistors. The transistors in the driving circuit provided by the embodiments of the present application are transistors of the same material, thereby avoiding the influence of the differences between transistors of different materials on the driving circuit.

[0063] Further, in some possible embodiments, the first thin film transistor T1 to the fourth thin film transistor T4 can be low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon thin film transistors. The transistors in the driving circuit provided by the embodiments of the present application are transistors of the same material, thereby avoiding the influence of the differences between transistors of different materials on the driving circuit. Figure 6 , Figure 6Fig. 3 is a circuit connection diagram of a third embodiment of a display panel driving circuit according to the present application. The data write voltage Data includes a first data write voltage Data1 and a second data write voltage Data2. The scan driving module 10 includes:

[0064] A first thin film transistor T1, a control terminal of the first thin film transistor T1 being connected to the scan driving voltage Scan, a first terminal of the first thin film transistor T1 being connected to the first data write voltage Data1, and a second terminal of the first thin film transistor T1 being connected to an input terminal of the voltage division compensation module 20.

[0065] A second thin film transistor T2, a control terminal of the second thin film transistor T2 being connected to the scan driving voltage Scan, a first terminal of the second thin film transistor T2 being connected to the second data write voltage Data2, and a second terminal of the second thin film transistor T2 being connected to the input terminal of the voltage division compensation module 20.

[0066] Further, in some possible embodiments, the voltage division compensation module 20 includes:

[0067] A third thin film transistor T3, a control terminal of the third thin film transistor T3 being connected to the second terminal of the first thin film transistor T1, a first terminal of the third thin film transistor T3 being connected to the power supply VAA, and a second terminal of the third thin film transistor T3 being connected to a second terminal of the liquid crystal capacitor ClC.

[0068] A first gate capacitor C1, a first terminal of the first gate capacitor C1 being connected to the second terminal of the first thin film transistor T1, and a second terminal of the first gate capacitor C1 being connected to the first terminal of the third thin film transistor T3.

[0069] A fourth thin film transistor T4, a control terminal of the fourth thin film transistor T4 being connected to the second terminal of the second thin film transistor T2, a second terminal of the fourth thin film transistor T4 being connected to the second terminal of the liquid crystal capacitor ClC, and a first terminal of the fourth thin film transistor T4 being connected to the ground.

[0070] A second gate capacitor C2, a first terminal of the second gate capacitor C2 being connected to the second terminal of the second thin film transistor T2, and a second terminal of the second gate capacitor C2 being connected to the first terminal of the fourth thin film transistor T4.

[0071] In this embodiment, the scan driving module 10 can use the first thin film transistor T1 and the second thin film transistor T2 to simultaneously perform scan driving, and at this time, the data writing voltage Data includes the first data writing voltage Data1 and the second data writing voltage Data2, so as to separately write the voltage compensation module 20 through the first thin film transistor T1 and the second thin film transistor T2. The voltage compensation module 20 is composed of two thin film transistors and a capacitor, so as to respectively use the first gate capacitor C1 and the second gate capacitor C2 to store the first data writing voltage Data1 and the second data writing voltage Data2, and use the first data writing voltage Data1 and the second data writing voltage Data2 to charge and compensate the liquid crystal capacitor ClC at the time when the liquid crystal capacitor ClC needs to be compensated (the charging time of each pair of liquid crystal capacitor ClC), so as to avoid the influence caused by the leakage of the liquid crystal capacitor ClC. It is worth noting that the working principle at this time is that the third thin film transistor T3 and the fourth thin film transistor T4 designed and manufactured have the same channel width-length ratio and the same gate capacitor, and the opening degree of the third thin film transistor T3 and the fourth thin film transistor T4 is controlled by the size of uGS, that is, the voltage difference between Data and VCOM or Data and VAA in the circuit. Then according to the above output characteristic curve, the third thin film transistor T3 and the fourth thin film transistor T4 can be regarded as a resistance varying with Data, the greater the voltage difference, the greater the conduction degree, and the smaller the resistance. Therefore, based on the control of the conduction degree of the third thin film transistor T3 and the fourth thin film transistor T4, the voltage of the liquid crystal capacitor ClC can be fixed at a constant value, that is, at this time, the equivalent is to continuously charge the liquid crystal capacitor ClC, thereby eliminating the influence of leakage, and improving the control efficiency of the display panel driving circuit.

[0072] For example, to ensure the consistency of the panel display, all the sub-pixels Data2 in the panel can be set to the same voltage value, i.e., the equivalent resistance of the fourth thin film transistor T4 of each sub-pixel is the same. Then, only the Data1 voltage needs to be controlled to control the voltage division ratio of the third thin film transistor T3 and the fourth thin film transistor T4. Further, the first gate capacitor C1 and the second gate capacitor C2 are used to maintain the conduction degree of the third thin film transistor T3 and the fourth thin film transistor T4 (i.e., the voltage is constant). Since the two capacitors are only used to maintain the gate voltage of the third thin film transistor T3 and the fourth thin film transistor T4, at this time, the area of the two poles of the first gate capacitor C1 and the second gate capacitor C2 is much smaller than that of the liquid crystal capacitor ClC, and the leakage current is also much smaller than that of the liquid crystal capacitor ClC. At the same time, the simultaneous change of the first gate capacitor C1 and the second gate capacitor C2 can offset each other to cause the conduction degree of the third thin film transistor T3 and the fourth thin film transistor T4 to be the same, thereby forming the final result that the voltage division ratio of the third thin film transistor T3 and the fourth thin film transistor T4 is unchanged. This can make the voltage value between the third thin film transistor T3 and the fourth thin film transistor T4 a constant value, and then it will be equivalent to the high point voltage of the liquid crystal capacitor ClC when the leakage current is a constant value, that is, the liquid crystal capacitor ClC is not affected by the leakage current. Further, the flicker phenomenon caused by the leakage of the liquid crystal capacitor ClC can be eliminated based on the control of the above circuit to improve the control efficiency of the display panel driving circuit.

[0073] Further, in some possible embodiments, when the liquid crystal capacitor ClC is in the data writing stage, the first thin film transistor T1 and the second thin film transistor T2 are both turned on, the first data writing voltage Data1 is output to the first gate capacitor C1, and the second data writing voltage Data2 is output to the second gate capacitor C2.

[0074] Further, in some possible embodiments, when the liquid crystal capacitor ClC is in the writing completion stage, the first thin film transistor T1 and the second thin film transistor T2 are both turned off, the first data writing voltage Data1 controls the third thin film transistor T3 to be in the first conduction state, and the second data writing voltage Data2 controls the fourth thin film transistor T4 to be in the second conduction state. In the first conduction state and the second conduction state, the first end point voltage value of the second end of the liquid crystal capacitor ClC is unchanged.

[0075] In the embodiment, when the liquid crystal capacitor ClC of a certain row is charged, a thin film transistor T1 and a second thin film transistor T2 are turned on, and then a first data write-in voltage Data1 is output to the first gate capacitor C1, and a second data write-in voltage Data2 is output to the second gate capacitor C2, so that the two gate capacitors store the voltage for maintaining the on state of the third thin film transistor T3 and the fourth thin film transistor T4. At the same time, the data is written into the liquid crystal capacitor ClC due to the on state of the third thin film transistor T3 and the fourth thin film transistor T4. After the scanning of the current row is completed, the first thin film transistor T1 and the second thin film transistor T2 are turned off, and then the on state of the third thin film transistor T3 and the fourth thin film transistor T4 is maintained by the first gate capacitor C1 and the second gate capacitor C2, that is, maintained by the first data write-in voltage Data1 and the second data write-in voltage Data2. According to the output characteristics of the thin film transistor described in the above embodiment, the resistance of the thin film transistor is controlled by the size of uGS (that is, the size of the first data write-in voltage Data1 and the second data write-in voltage Data2), so that the first data write-in voltage Data1 and the second data write-in voltage Data2 can be used to control the third thin film transistor T3 to be in a first on state and the fourth thin film transistor T4 to be in a second on state, so that the first end point voltage value of the second end of the liquid crystal capacitor ClC is unchanged in the first on state and the second on state. Assuming that the resistance ratio of the third thin film transistor T3 and the fourth thin film transistor T4 is 1:1, and the power supply VAA is A, the first end point voltage value will always be A / 2. If the first gate capacitor C1 and the second gate capacitor C2 leak, the resistance of the third thin film transistor T3 and the fourth thin film transistor T4 will change, but the resistance ratio of the third thin film transistor T3 and the fourth thin film transistor T4 will not change, thereby ensuring the accuracy of the compensation of the liquid crystal capacitor ClC. Therefore, the display panel driving circuit can continuously supply power to the liquid crystal capacitor ClC, and the leakage charge of the liquid crystal capacitor ClC will be continuously replenished. When the VRR is turned on, the brightness will not change due to the change of the refresh rate, thereby improving the control efficiency of the display panel driving circuit.

[0076] Further, in some possible embodiments, when the liquid crystal capacitor ClC is in the white balance adjustment stage, the first thin film transistor T1 is turned off, the second thin film transistor T2 is turned on, and the fourth thin film transistor T4 is in a third on state. In the first on state and the third on state, the second end point voltage value of the second end of the liquid crystal capacitor ClC is not equal to the first end point voltage value.

[0077] In the embodiment, based on the above principle, the voltage value of the second end of the liquid crystal capacitor ClC can be adjusted to achieve white balance adjustment by inputting different voltages to the liquid crystal capacitor ClC. As shown in voltage A, the display is pure white, and as shown in voltage A1, the display is light white. If Data2 is controlled alone, the conduction degree of the fourth thin film transistor T4 can also be fine-tuned, which can be used to fine-tune the display gray scale of the sub-pixel, and thus the color depth of the panel is improved. That is, the power used or leaked by the fourth thin film transistor T4 continues to be compensated under the original compensation control, thereby controlling the fourth thin film transistor T4 to be in the third conduction state, and the second end point voltage value of the second end of the liquid crystal capacitor ClC is not equal to the first end point voltage value in the first conduction state and the third conduction state, that is, the voltage value of the second end of the liquid crystal capacitor ClC changes, thereby greatly expanding the functionality of the display panel driving circuit.

[0078] It is worth noting that the first data write voltage Data1 and the second data write voltage Data2 can be exchanged or the voltage value can be changed according to actual conditions. Of course, to achieve white balance adjustment, the first data write voltage Data1 or the second data write voltage Data2 can be directly adjusted to achieve the same effect, thereby greatly expanding the functionality of the display panel driving circuit.

[0079] The embodiment provides a display panel driving circuit, an array substrate row driving circuit and a liquid crystal display panel. The display panel driving circuit is optimized, and a display panel driving circuit is obtained. The display panel driving circuit comprises a voltage division compensation module and a scan driving module connected with a liquid crystal capacitor in sequence. Since the display panel driving circuit in the liquid crystal display panel can only compensate the Gamma voltage or the Vcom voltage by predicting the low refresh rate that can be cut through the node (i.e. the length of Vblank) according to the flicker phenomenon caused by the leakage of the liquid crystal capacitor, the number of nodes needs to be determined in priority, and the control steps are relatively complicated. In combination with the above modules, the voltage division compensation module stores the data write voltage under the driving of the scan driving module (i.e. the scan driving voltage drives the output data write voltage of the scan driving module), so as to compensate the liquid crystal capacitor based on the data write voltage in the case that the scan driving voltage stops driving (at this time, the leakage of the liquid crystal capacitor exists), thereby realizing the compensation of the leakage of the liquid crystal capacitor without determining the number of nodes, and improving the control efficiency of the display panel driving circuit.

[0080] In addition, the embodiment of the application further provides an array substrate row driving circuit. The array substrate row driving circuit comprises the display panel driving circuit.

[0081] In addition, the embodiment of the present application also provides a liquid crystal display panel, which comprises at least a color film substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color film substrate, and the array substrate comprises a display panel driving circuit. The liquid crystal display panel can also comprise the display panel driving circuit as above, and the display panel driving circuit is controlled by referring to Figure 7 , Figure 7 The structure of the liquid crystal display panel related to the embodiment of the present application is shown in the figure.

[0082] As shown in the figure, Figure 7 the liquid crystal display panel can comprise a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004 and a memory 1005. The communication bus 1002 is used to realize the connection and communication among the components. The user interface 1003 can comprise a display and an input unit such as a keyboard. The optional user interface 1003 can also comprise a standard wired interface and a wireless interface. The network interface 1004 can optionally comprise a standard wired interface and a wireless interface (such as a wireless fidelity (WIreless-FIdelity, WI-FI) interface). The memory 1005 can be a high-speed random access memory (RAM) memory or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk memory. The memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0083] Those skilled in the art can understand that Figure 7 the structure shown in the figure does not constitute a limitation on the liquid crystal display panel, and can comprise more or fewer components than the figure, or combine certain components, or different component arrangements.

[0084] As shown in the figure, Figure 7 the memory 1005 as a storage medium can comprise an operating system, a data storage module, a network communication module, a user interface module and a computer program.

[0085] In the liquid crystal display panel shown in the figure, Figure 7 the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the embodiment can be arranged in the liquid crystal display panel, and the liquid crystal display panel controls the display panel driving circuit by calling the computer program stored in the memory 1005 through the processor 1001.

[0086] The liquid crystal display panel of each embodiment of the present application can refer to each embodiment of the display panel driving circuit of the present application, and details are not repeated here.

[0087] It should be noted that in this document, the terms "comprise", "comprising", or any other variant thereof are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or systems that comprise a list of elements do not include only those elements recited, but also other elements not expressly listed or inherent to such processes, methods, articles, or systems. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or system that includes the element.

[0088] The above-mentioned sequence numbers of embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0089] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and necessary general hardware platforms, and of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk) and includes a number of instructions for making a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device) execute the methods of various embodiments of the present application.

[0090] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields based on the content of the present application specification and drawings, are also included in the patent protection scope of the present application.

Claims

1. A display panel driving circuit, characterized in that, The display panel driving circuit includes: A liquid crystal capacitor, wherein the first terminal of the liquid crystal capacitor is grounded; A scan driving module is connected to a scan driving voltage and a data writing voltage, and the scan driving module is used to output the data writing voltage under the drive of the scan driving voltage; A voltage divider compensation module is configured such that its input terminal is connected to the output terminal of the scan drive module, and its output terminal is connected to the second terminal of the liquid crystal capacitor. The voltage divider compensation module is used to compensate the liquid crystal capacitor based on the data writing voltage when the scan drive voltage stops driving.

2. The display panel driving circuit as described in claim 1, characterized in that, The scanning drive module includes: A first thin-film transistor (TFT) is connected to the scan drive voltage at its control terminal, the data write voltage at its first terminal, and the input terminal of the voltage divider compensation module at its second terminal.

3. The display panel driving circuit as described in claim 2, characterized in that, The voltage divider compensation module includes: A third thin-film transistor, wherein the control terminal of the third thin-film transistor is connected to the second terminal of the first thin-film transistor, the first terminal of the third thin-film transistor is connected to a power supply, and the second terminal of the third thin-film transistor is connected to the second terminal of the liquid crystal capacitor; A fourth thin-film transistor, wherein the control terminal of the fourth thin-film transistor is connected to the second terminal of the first thin-film transistor, the second terminal of the fourth thin-film transistor is connected to the second terminal of the liquid crystal capacitor, and the first terminal of the fourth thin-film transistor is grounded; A first gate capacitor, wherein a first terminal of the first gate capacitor is connected to a second terminal of the first thin-film transistor, and a second terminal of the first gate capacitor is connected to a first terminal of the third thin-film transistor; or, a first terminal of the first gate capacitor is connected to a second terminal of the first thin-film transistor, and a second terminal of the first gate capacitor is connected to a first terminal of the fourth thin-film transistor.

4. The display panel driving circuit as described in claim 1, characterized in that, The data writing voltage includes a first data writing voltage and a second data writing voltage, and the scan driving module includes: A first thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the scan driving voltage, the first terminal of the first thin-film transistor is connected to the first data writing voltage, and the second terminal of the first thin-film transistor is connected to the input terminal of the voltage divider compensation module; The second thin-film transistor has its control terminal connected to the scan drive voltage, its first terminal connected to the second data write voltage, and its second terminal connected to the input terminal of the voltage divider compensation module.

5. The display panel driving circuit as described in claim 4, characterized in that, The voltage divider compensation module includes: A third thin-film transistor, wherein the control terminal of the third thin-film transistor is connected to the second terminal of the first thin-film transistor, the first terminal of the third thin-film transistor is connected to a power supply, and the second terminal of the third thin-film transistor is connected to the second terminal of the liquid crystal capacitor; A first gate capacitor, the first end of which is connected to the second end of the first thin-film transistor, and the second end of which is connected to the first end of the third thin-film transistor; A fourth thin-film transistor, wherein the control terminal of the fourth thin-film transistor is connected to the second terminal of the second thin-film transistor, the second terminal of the fourth thin-film transistor is connected to the second terminal of the liquid crystal capacitor, and the first terminal of the fourth thin-film transistor is grounded; The second gate capacitor has its first terminal connected to the second terminal of the second thin-film transistor, and its second terminal connected to the first terminal of the fourth thin-film transistor.

6. The display panel driving circuit as described in claim 5, characterized in that, When the liquid crystal capacitor is in the data writing stage, both the first thin-film transistor and the second thin-film transistor are turned on, the first data writing voltage is output to the first gate capacitor, and the second data writing voltage is output to the second gate capacitor.

7. The display panel driving circuit as described in claim 6, characterized in that, When the liquid crystal capacitor is in the writing completion stage, both the first thin film transistor and the second thin film transistor are turned off. The first data writing voltage controls the third thin film transistor to be in a first conducting state, and the second data writing voltage controls the fourth thin film transistor to be in a second conducting state. In the first conducting state and the second conducting state, the voltage value of the first terminal of the second end of the liquid crystal capacitor remains unchanged.

8. The display panel driving circuit as described in claim 7, characterized in that, When the liquid crystal capacitor is in the white balance adjustment stage, the first thin film transistor is turned off, the second thin film transistor is turned on, and the fourth thin film transistor is in the third on state. In the first on state and the third on state, the voltage value of the second terminal of the second end of the liquid crystal capacitor is not equal to the voltage value of the first terminal.

9. A row driving circuit for an array substrate, characterized in that, The array substrate row driving circuit includes the display panel driving circuit as described in any one of claims 1 to 8.

10. A liquid crystal display panel, characterized in that, The liquid crystal display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes the array substrate row driving circuit as described in claim 9.

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