Write equalization system and storage device
By performing frequency division processing and data control on the clock signal and data strobe signal, a data signal indicating the rising edge of the data strobe signal is generated, which solves the problem of delay difference caused by processing, voltage and temperature changes in double data rate synchronous dynamic random access memory, and improves the accuracy of data writing operations.
Patent Information
- Application Number
- CN202410601110.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-15
- Publication Date
- 2025-11-18
AI Technical Summary
In double data rate synchronous dynamic random access memory, the delay difference between the clock signal and the data strobe signal caused by changes in processing, voltage and temperature can cause errors in data write operations.
The clock signal and data strobe signal are processed by a frequency divider and signal processing circuit to generate multiple frequency-divided signals. The data control circuit then generates a data signal based on these signals to indicate that the rising edge of the data strobe signal is at a specific level of the clock signal, thereby achieving write equalization.
It effectively avoids signal delay issues caused by processing, voltage, and temperature changes, thus improving the accuracy of data writing operations.
Smart Images
Figure CN120977345A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to double data rate (DDR) synchronous dynamic random access memory (SDRAM), and more particularly to a write leveling system and related storage device capable of performing write leveling operations through data control and frequency division operations within the DDR synchronous dynamic random access memory. Background Technology
[0002] With the development of Double Data Rate (DDR) synchronous dynamic random access memory (DRAM), multiple frequency division operations are typically performed on the high-speed clock signal and the data strobe (DQS) signal to generate multiple divided clock signals and multiple divided data strobe signals for data write operations. For LPDDR4, during write equalization, the DRAM receives the clock signal and data strobe signal from the memory controller, and generates and sends back a data (DQ) signal to the memory controller based on the clock signal and data strobe signal, indicating whether the rising edge of the data strobe signal is at a high or low level of the clock signal. The memory controller then determines whether to delay the data strobe signal based on the data signal to successfully perform the data write operation. For existing memory devices that include a memory controller and DRAM, write equalization can be performed using the clock signal and data strobe signal by using multiple delay circuits (e.g., multiple inverters) that mimic the delay of the normal data write path. However, certain problems may arise. For example, when process, voltage, and temperature (PVT) vary and the LPDDR4 standard only allows tDQSS to have 1 ± 0.25tck (clock cycle time; that is, at the fastest current clock speed, the clock cycle time tck is 0.46 nanoseconds (ns),) the delay of these multiple delay circuits may differ from the delay of the normal data write path, causing errors in subsequent data write operations. Therefore, there is a great need for a write equalization system and related storage device capable of write equalization through data control and frequency division operations within the double data rate synchronous dynamic random access memory. Summary of the Invention
[0003] Therefore, one of the objectives of this invention is to provide a write equalization system and related storage device capable of performing write equalization operations by means of data control and frequency division operations within a double data rate synchronous dynamic random access memory, in order to solve the above-mentioned problems.
[0004] According to an embodiment of the present invention, a write equalization system is provided. The write equalization system includes a frequency divider, a signal processing circuit, and a data control circuit. The frequency divider is used to divide a clock signal to generate multiple divided clock signals. The signal processing circuit is used to process a data strobe signal to generate multiple processed data strobe signals. The data control circuit is used to generate a data signal based on the multiple divided clock signals and the multiple processed data strobe signals, for indicating that a rising edge of the data strobe signal is at a first level or a second level of the clock signal, wherein the first level is higher than the second level.
[0005] According to an embodiment of the present invention, a storage device is provided. The storage device includes a memory controller and a write equalization system. The write equalization system includes a frequency divider, a signal processing circuit, a data control circuit, and a data pin. The frequency divider is used to receive a clock signal from the memory controller and perform a frequency division operation on the clock signal to generate a plurality of frequency-divided clock signals. The signal processing circuit is used to receive a data strobe signal from the memory controller and perform data processing on the data strobe signal to generate a plurality of processed data strobe signals. The data control circuit is used to generate a data signal based on the plurality of frequency-divided clock signals and the plurality of processed data strobe signals, so as to indicate that a rising edge of the data strobe signal is at a first level or a second level of the clock signal, wherein the first level is higher than the second level. The data pin is used to receive the data signal from the data control circuit and transmit the data signal to the memory controller.
[0006] One of the objectives of this invention is to provide a write equalization system that, compared to cases where clock signals and data strobe signals are transmitted from the memory controller to the double data rate synchronous dynamic random access memory (DRAM) via multiple delay circuits (e.g., multiple inverters) for write equalization, performs write equalization by frequency division and data control within the DRAM. This avoids signal delay problems caused by delay circuit processing, voltage and temperature variations (e.g., the reduction of skew margin between the data strobe signal and the clock signal during data write operations), thereby significantly improving the accuracy of data write operations. Attached Figure Description
[0007] Figure 1 This is a schematic diagram of a storage device according to an embodiment of the present invention.
[0008] Figure 2 This is a schematic diagram of a write equalization system according to an embodiment of the present invention.
[0009] Figure 3 According to an embodiment of the present invention Figure 2 The timing diagram shown is of the relevant signals written to the equalization system.
[0010] Figure 4 This is a schematic diagram of the first part of a data control circuit according to an embodiment of the present invention.
[0011] Figure 5 This is a schematic diagram of the second part of a data control circuit according to an embodiment of the present invention.
[0012] [Symbol Explanation]
[0013] 100: Storage device
[0014] 102: Memory controller
[0015] 104: Memory
[0016] 106, 200: Write to the equalization system
[0017] XCLK: Clock signal
[0018] XDQS: Data strobe signal
[0019] DQ: Data signal
[0020] 202: Frequency divider
[0021] 204: Signal Processing Circuit
[0022] 206: Data Control Circuit
[0023] 208: Data Pin
[0024] CK[0]~CK[3]: Clock signals after frequency division
[0025] DQS[0], DQS[2]: Processed data strobe signals
[0026] FS_R: First gating result
[0027] SS_R: Second gating result
[0028] F_RE: First rising edge
[0029] S_RE: Second rising edge
[0030] t0, t1: Time points
[0031] T: Period
[0032] 402, 404, 406, 408, 410, 412, 414, 416: D-type triggers
[0033] 418, 420, 422, 424, 504, 506, 508: Inverters
[0034] 426, 428, 430, 432, 434, 436: NAND gate circuits
[0035] IR_1, IR_2, IR_3, IR_4: inverted results
[0036] WRL_R0, WRL_R1: Write the equalization result
[0037] 500, 502: Transmission gate circuits Detailed Implementation
[0038] Figure 1 This is a schematic diagram of a storage device 100 according to an embodiment of the present invention. Figure 1 As shown, the storage device 100 may include a memory controller 102 and a memory (e.g., double data rate (DDR) synchronous dynamic random access memory (SDRAM)) 104, wherein the memory 104 may include a write leveling system 106. In response to the memory 104 being in write leveling mode, the memory controller 102 may transmit a clock signal XCLK and a data strobe (DQS) signal XDQS to the memory 104 (especially the write leveling system 106 of the memory 104). The write equalization system 106 can be used to divide the clock signal XCLK by one to generate multiple divided clock signals, process the data strobe signal XDQS to generate multiple processed data strobe signals, and generate and transmit a data (DQ) signal DQ to the memory controller 102 based on the multiple divided clock signals and the multiple processed data strobe signals, so as to indicate that a rising edge of the data strobe signal XDQS is at a high level (e.g., logic "1") or a low level (e.g., logic "0") of the clock signal XCLK. The memory controller 102 can determine whether to delay the data strobe signal XDQS based on the data signal DQ to ensure a successful data write operation.
[0039] For details, please refer to the following: Figure 2 and Figure 3 . Figure 2 This is a schematic diagram of a write equalization system 200 according to an embodiment of the present invention, wherein... Figure 1 The write equalization system 106 shown can be implemented by the write equalization system 200. Figure 3 According to an embodiment of the present invention Figure 2 The timing diagram shown is for the relevant signals written to the equalization system 200. (See diagram for example.) Figure 2 As shown, the write equalization system 200 may include a frequency divider 202, a signal processing circuit 204, a data control circuit 206, and a data pin 208. The frequency divider 202 can be used to divide the clock signal XCLK to generate multiple divided clock signals CK[0] to CK[M]. In this embodiment, the frequency divider 202 can divide the clock signal XCLK by a divisor of "2" to generate four divided clock signals CK[0] to CK[3] (i.e., M = 3) with different phases, wherein the frequency of each of the divided clock signals CK[0] to CK[3] is half the frequency of the clock signal XCLK, but the present invention is not limited thereto. In some embodiments, the frequency divider 202 can divide the clock signal XCLK by other divisors (e.g., "4") to generate divided clock signals.
[0040] exist Figure 3 In the above, the clock signal XCLK is a square wave signal with a period of "T", and each of the frequency-divided clock signals CK[0] to CK[3] is a square wave signal with a period of "2T". The frequency-divided clock signal CK[0] is generated based on the first rising edge of the clock signal XCLK (for example, the first rising edge of the frequency-divided clock signal CK[0] is aligned with the first rising edge of the clock signal XCLK). The frequency-divided clock signal CK[1] is generated based on the first falling edge of the clock signal XCLK (for example, the first rising edge of the frequency-divided clock signal CK[1] is aligned with the first falling edge of the clock signal XCLK), the frequency-divided clock signal CK[2] is generated based on the second rising edge of the clock signal XCLK (for example, the first rising edge of the frequency-divided clock signal CK[2] is aligned with the second rising edge of the clock signal XCLK), and the frequency-divided clock signal CK[3] is generated based on the second falling edge of the clock signal XCLK (for example, the first rising edge of the frequency-divided clock signal CK[3] is aligned with the second falling edge of the clock signal XCLK).
[0041] Signal processing circuit 204 can be used to process the data strobe signal XDQS to generate two processed data strobe signals DQS[0] and DQS[2]. According to the standard of Double Data Rate Synchronous Dynamic Random Access Memory, the data strobe signal XDQS has two rising edges (e.g., a first rising edge F_RE and a second rising edge S_RE). Signal processing circuit 204 can generate one of the processed data strobe signals DQS[0] and DQS[2] in response to the first rising edge F_RE of the data strobe signal XDQS, and generate the other of the processed data strobe signals DQS[0] and DQS[2] in response to the second rising edge S_RE of the data strobe signal XDQS.
[0042] like Figure 3 As shown, the data strobe signal XDQS has a first rising edge F_RE and a second rising edge S_RE at time points t0 and t1, respectively. The signal processing circuit 204 can generate the processed data strobe signal DQS[0] at time point t0 in response to the first rising edge F_RE (for example, a rising edge of the processed data strobe signal DQS[0] is aligned with the first rising edge F_RE of the data strobe signal XDQS at time point t0), and can generate the processed data strobe signal DQS[2] at time point t1 in response to the second rising edge S_RE (for example, a rising edge of the processed data strobe signal DQS[2] is aligned with the second rising edge S_RE of the data strobe signal XDQS at time point t1), wherein the processed data strobe signal DQS[0] is an inverted signal of the processed data strobe signal DQS[2]. For example, the processed data strobe signal DQS[0] is a signal that is initially at a low level (e.g., logic value "0") and is converted to a high level (e.g., logic value "1") when toggled, while the processed data strobe signal DQS[2] is a signal that is initially at a high level (e.g., logic value "1") and is converted to a low level (e.g., logic value "0") when toggled.
[0043] For example, the signal processing circuit 204 may include a frequency divider and a signal extraction circuit. The frequency divider can be used to perform a division operation of the data gating signal XDQS by a divisor of "2" to generate four frequency-divided data gating signals F_DQS[0]~F_DQS[3] with different phases. The frequency of each frequency-divided data gating signal F_DQS[0]~F_DQS[3] is half the frequency of the data gating signal XDQS. The frequency-divided data gating signal F_DQS[0] is generated based on the first rising edge of the data gating signal XDQS (for example, the rising edge of the frequency-divided data gating signal F_DQS[0] is aligned with the first rising edge of the data gating signal XDQS). The frequency-divided data strobe signal F_DQS[1] is generated based on the first falling edge of the data strobe signal XDQS (for example, the rising edge of the frequency-divided data strobe signal F_DQS[1] is aligned with the first falling edge of the data strobe signal XDQS), the frequency-divided data strobe signal F_DQS[2] is generated based on the second rising edge of the data strobe signal XDQS (for example, the rising edge of the frequency-divided data strobe signal F_DQS[2] is aligned with the second rising edge of the data strobe signal XDQS), and the frequency-divided data strobe signal F_DQS[3] is generated based on the second falling edge of the data strobe signal XDQS (for example, the rising edge of the frequency-divided data strobe signal F_DQS[3] is aligned with the second falling edge of the data strobe signal XDQS). The signal extraction circuit can be used to extract the frequency-divided data strobe signals F_DQS[0] and F_DQS[2] as the processed data strobe signals DQS[0] and DQS[2], respectively.
[0044] This is for illustrative purposes only, and the invention is not limited thereto. In some embodiments, the signal processing circuit 204 may generate a processed data strobe signal DQS[0] at time t1 in response to the second rising edge S_RE (e.g., the rising edge of the processed data strobe signal DQS[0] is aligned with the second rising edge S_RE of the data strobe signal XDQS at time t1), and may generate a processed data strobe signal DQS[2] at time t0 in response to the first rising edge F_RE (e.g., the rising edge of the processed data strobe signal DQS[2] is aligned with the first rising edge F_RE of the data strobe signal XDQS at time t0).
[0045] The data control circuit 206 can be used to receive the frequency-divided clock signals CK[0]~CK[3] and the processed data strobe signals DQS[0] and DQS[2] from the frequency divider 202 and the signal processing circuit 204 respectively, and generate the data signal DQ based on the frequency-divided clock signals CK[0]~CK[3] and the processed data strobe signals DQS[0] and DQS[2]. Specifically, the data control circuit 206 can use one of the processed data strobe signals DQS[0] and DQS[2] to strobe the frequency-divided clock signals CK[0] and CK[1] to generate a first strobe result FS_R, and use the other of the processed data strobe signals DQS[0] and DQS[2] to strobe the frequency-divided clock signals CK[2] and CK[3] to generate a second strobe result SS_R. The first strobe result FS_R indicates that the frequency-divided clock signal CK[0] is at a high level (e.g., logic value "1") and the frequency-divided clock signal CK[1] is at a low level (e.g., logic value "0"); and the second strobe result SS_R indicates that the frequency-divided clock signal CK[2] is at a high level (e.g., logic value "1") and the frequency-divided clock signal CK[3] is at a low level (e.g., logic value "0").
[0046] exist Figure 2 and Figure 3 In the embodiment shown, when the processed data strobe signal DQS[0] is generated at time point t0 in response to the first rising edge F_RE and the processed data strobe signal DQS[2] is generated at time point t1 in response to the second rising edge S_RE, the frequency-divided clock signals CK[0] and CK[1] are both selected by the processed data strobe signal DQS[0] to generate the first strobe result FS_R, while the frequency-divided clock signals CK[2] and CK[3] are both selected by the processed data strobe signal DQS[2] to generate the second strobe result SS_R. In fact, the processed data strobe signal DQS[0] can also be generated at time point t1 in response to the second rising edge S_RE, and the processed data strobe signal DQS[2] can also be generated at time point t0 in response to the first rising edge F_RE. In this case, the frequency-divided clock signals CK[0] and CK[1] are both selected by the processed data strobe signal DQS[2] to generate the first strobe result FS_R, while the frequency-divided clock signals CK[2] and CK[3] are both selected by the processed data strobe signal DQS[0] to generate the second strobe result SS_R.
[0047] The data control circuit 206 can generate a data signal DQ based on the first gating result FS_R and the second gating result SS_R. For details, please refer to the configuration. Figure 4 and Figure 5 . Figure 4 This is a schematic diagram of the first part of a data control circuit 400 according to an embodiment of the present invention, wherein... Figure 2 The data control circuit 206 shown can be implemented by the data control circuit 400. Figure 5 This is a schematic diagram of the second part of a data control circuit 400 according to an embodiment of the present invention. Figure 4 As shown, the data control circuit 400 may include multiple D flip-flops (DFFs) 402, 404, 406, 408, 410, 412, 414 and 416, multiple inverters 418, 420, 422 and 424, and multiple NAND gate circuits 426, 428, 430, 432, 434 and 436.
[0048] For each of the D-type flip-flops 402, 404, 406 and 408, the clock port is used to receive the processed data strobe signal DQS[0] (for example, each of the D-type flip-flops 402, 404, 406 and 408 is triggered by the rising edge of the processed data strobe signal DQS[0]), wherein the input port of D-type flip-flop 402 is used to receive the divided clock signal CK[0], the input port of D-type flip-flop 404 is used to receive the divided clock signal CK[1], the input port of D-type flip-flop 406 is used to receive the divided clock signal CK[2], and the input port of D-type flip-flop 408 is used to receive the divided clock signal CK[3]. That is, D-type flip-flop 402 is used to output the current value (e.g., logic value "0" or "1") of the divided clock signal CK[0] at the output port in response to the rising edge of the processed data strobe signal DQS[0], D-type flip-flop 404 is used to output the current value of the divided clock signal CK[1] at the output port in response to the rising edge of the processed data strobe signal DQS[0], D-type flip-flop 406 is used to output the current value of the divided clock signal CK[2] at the output port in response to the rising edge of the processed data strobe signal DQS[0], and D-type flip-flop 408 is used to output the current value of the divided clock signal CK[3] at the output port in response to the rising edge of the processed data strobe signal DQS[0].
[0049] Inverter 418 has an input port and an output port coupled to the output port of D-type flip-flop 404, and is used to invert the output result of D-type flip-flop 404 to generate an inverted result IR_1 at the output port. Inverter 420 has an input port and an output port coupled to the output port of D-type flip-flop 408, and is used to invert the output result of D-type flip-flop 408 to generate an inverted result IR_2 at the output port. NAND gate 426 has a first input port coupled to the output port of D-type flip-flop 402, a second input port coupled to the output port of inverter 418, and an output port. NAND gate 428 has a first input port coupled to the output port of D-type flip-flop 406, a second input port coupled to the output port of inverter 420, and an output port. NAND gate 430 has a first input port coupled to the output port of NAND gate 426, a second input port coupled to the output port of NAND gate 428, and an output port, wherein the write equalization result WRL_R0 is output from the output port of NAND gate 430, and the write equalization result WRL_R0 can represent one of the first gating result FS_R and the second gating result SS_R.
[0050] Similarly, for each of the D-type flip-flops 410, 412, 414 and 416, the clock port is used to receive the processed data strobe signal DQS[2] (for example, each of the D-type flip-flops 410, 412, 414 and 416 is triggered by the rising edge of the processed data strobe signal DQS[2]), wherein the input port of the D-type flip-flop 410 is used to receive the divided clock signal CK[0], the input port of the D-type flip-flop 412 is used to receive the divided clock signal CK[1], the input port of the D-type flip-flop 414 is used to receive the divided clock signal CK[2], and the input port of the D-type flip-flop 416 is used to receive the divided clock signal CK[3]. That is, D-type flip-flop 410 is used to output the current value (e.g., logic value "0" or "1") of the divided clock signal CK[0] at the output port in response to the rising edge of the processed data strobe signal DQS[2], D-type flip-flop 412 is used to output the current value of the divided clock signal CK[1] at the output port in response to the rising edge of the processed data strobe signal DQS[2], D-type flip-flop 414 is used to output the current value of the divided clock signal CK[2] at the output port in response to the rising edge of the processed data strobe signal DQS[2], and D-type flip-flop 416 is used to output the current value of the divided clock signal CK[3] at the output port in response to the rising edge of the processed data strobe signal DQS[2].
[0051] Inverter 422 has an input port and an output port coupled to the output port of D-type flip-flop 412, and is used to invert the output result of D-type flip-flop 412 to generate an inverted result IR_3 at the output port. Inverter 424 has an input port and an output port coupled to the output port of D-type flip-flop 416, and is used to invert the output result of D-type flip-flop 416 to generate an inverted result IR_4 at the output port. NAND gate 432 has a first input port coupled to the output port of D-type flip-flop 410, a second input port coupled to the output port of inverter 422, and an output port. NAND gate 434 has a first input port coupled to the output port of D-type flip-flop 414, a second input port coupled to the output port of inverter 424, and an output port. NAND gate 436 has a first input port coupled to the output port of NAND gate 432, a second input port coupled to the output port of NAND gate 434, and an output port, wherein the write equalization result WRL_R1 is output from the output port of NAND gate 436, and the write equalization result WRL_R1 can represent another gating result between the first gating result FS_R and the second gating result SS_R.
[0052] For example, when the processed data strobe signal DQS[0] is generated in response to the first rising edge F_RE of the data strobe signal XDQS and the processed data strobe signal DQS[2] is generated in response to the second rising edge S_RE of the data strobe signal XDQS, the written equalization result WRL_R0 represents the first strobe result FS_R, and the written equalization result WRL_R1 represents the second strobe result SS_R. As another example, when the processed data strobe signal DQS[0] is generated in response to the second rising edge S_RE of the data strobe signal XDQS and the processed data strobe signal DQS[2] is generated in response to the first rising edge F_RE of the data strobe signal XDQS, the written equalization result WRL_R0 represents the second strobe result SS_R, and the written equalization result WRL_R1 represents the first strobe result FS_R.
[0053] like Figure 5As shown, the data control circuit 400 may further include multiple transmission gate circuits 500 and 502 and multiple inverters 504, 506 and 508. Each of the transmission gate circuits 500 and 502 may be a complementary metal-oxide-semiconductor (CMOS) circuit containing an n-type metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as an n-type transistor) and a p-type metal-oxide-semiconductor field-effect transistor (hereinafter referred to as a p-type transistor). The transmission gate circuit 500 has an input port for receiving the written equalization result WRL_R0 and a control port for receiving the processed data strobe signal DQS[0] (for example, the gate of the n-type transistor is used to receive the processed data strobe signal DQS[0], and the gate of the p-type transistor is used to receive an inverted signal of the processed data strobe signal DQS[0]). Figure 5 The middle mark is The transmission gate circuit 502 has an input port for receiving the written equalization result WRL_R1, a control port for receiving the processed data strobe signal DQS[2] (for example, the gate of an n-type transistor is used to receive the processed data strobe signal DQS[2], while the gate of a p-type transistor is used to receive an inverted signal of the processed data strobe signal DQS[2] (in Figure 5 The middle mark is Inverter 504 has an input port and an output port coupled to the output port of transmission gate 500. Inverter 506 has an input port coupled to the output port of inverter 504 and an output port coupled to the input port of inverter 504. Inverter 508 has an input port coupled to the output port of inverter 504 and an output port, wherein the data signal DQ is generated at the output port of inverter 508. After the data signal DQ is generated, data pin 208 can be used to receive the data signal DQ from data control circuit 206 / 400 and transmit the data signal DQ to memory controller 102, wherein memory controller 102 can determine whether to delay the data strobe signal XDQS based on the data signal DQ in order to successfully perform the data write operation.
[0054] In summary, compared to cases where clock and data strobe signals are transmitted from the memory controller to the double data rate synchronous dynamic random access memory (DRAM) via multiple delay circuits (e.g., multiple inverters) for write equalization, the write equalization system of this invention performs write equalization through frequency division and data control within the DRAM. This avoids signal delay problems caused by processing, voltage, and temperature (PVT) variations in the delay circuits (e.g., the reduction of skew margin between the data strobe signal and the clock signal during data write operations), thereby significantly improving the accuracy of data write operations.
[0055] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.
Claims
1. A write equalization system, comprising: A frequency divider is used to divide a clock signal to generate multiple divided clock signals. Signal processing circuit, used to process data strobe signals to generate multiple processed data strobe signals; as well as A data control circuit is used to generate a data signal based on the plurality of frequency-divided clock signals and the plurality of processed data strobe signals, so as to indicate that the rising edge of the data strobe signal is at a first level or a second level of the clock signal, wherein the first level is higher than the second level.
2. The write equalization system of claim 1, wherein the plurality of processed data strobe signals include a first processed data strobe signal and a second processed data strobe signal, the data strobe signal having a first rising edge and a second rising edge, one of the first processed data strobe signal and the second processed data strobe signal being generated in response to the first rising edge of the data strobe signal, and the other of the first processed data strobe signal and the second processed data strobe signal being generated in response to the second rising edge of the data strobe signal.
3. The write equalization system as claimed in claim 1, wherein the plurality of processed data gating signals include a first processed data gating signal and a second processed data gating signal, and the first processed data gating signal is the inverted signal of the second processed data gating signal.
4. The write equalization system as described in claim 1, wherein the plurality of frequency-divided clock signals include a first frequency-divided clock signal, a second frequency-divided clock signal, a third frequency-divided clock signal, and a fourth frequency-divided clock signal.
5. The write equalization system as claimed in claim 4, wherein the first frequency-divided clock signal is generated based on the first rising edge of the clock signal, the second frequency-divided clock signal is generated based on the first falling edge of the clock signal, the third frequency-divided clock signal is generated based on the second rising edge of the clock signal, and the fourth frequency-divided clock signal is generated based on the second falling edge of the clock signal.
6. The write equalization system of claim 5, wherein the plurality of processed data gating signals include a first processed data gating signal and a second processed data gating signal; the first frequency-divided clock signal and the second frequency-divided clock signal are both gated by one of the processed data gating signals of the first and the second processed data gating signals to generate a first gating result; and the third frequency-divided clock signal and the fourth frequency-divided clock signal are both gated by the other of the processed data gating signals of the first and the second processed data gating signals to generate a second gating result.
7. The write equalization system of claim 6, wherein the first strobe result indicates that the first frequency-divided clock signal is at a third level and the second frequency-divided clock signal is at a fourth level; the second strobe result indicates that the third frequency-divided clock signal is at the third level and the fourth frequency-divided clock signal is at the fourth level; and the third level is higher than the fourth level.
8. The write equalization system of claim 6, wherein the data signal is generated based on the first gating result and the second gating result.
9. The write equalization system of claim 4, wherein the plurality of processed data strobe signals include a first processed data strobe signal and a second processed data strobe signal; and the data control circuit includes: The first D-type flip-flop has a first clock port, a first input port and a first output port, wherein the first clock port is used to receive the processed data strobe signal from the first processed data strobe signal and the second processed data strobe signal, and the first input port is used to receive the first frequency-divided clock signal. The second D-type flip-flop has a second clock port, a second input port and a second output port, wherein the second clock port is used to receive the processed data strobe signal from the first processed data strobe signal and the second processed data strobe signal, and the second input port is used to receive the second frequency-divided clock signal. The third D-type flip-flop has a third clock port, a third input port and a third output port, wherein the third clock port is used to receive the processed data strobe signal from the first processed data strobe signal and the second processed data strobe signal, and the third input port is used to receive the third frequency-divided clock signal. as well as The fourth D-type flip-flop has a fourth clock port, a fourth input port, and a fourth output port, wherein the fourth clock port is used to receive the processed data strobe signal from the first processed data strobe signal and the second processed data strobe signal, and the fourth input port is used to receive the fourth frequency-divided clock signal.
10. The write equalization system of claim 9, wherein the data control circuit further comprises: The first inverter has an input port and an output port coupled to the second output port of the second D-type flip-flop; The second inverter has an input port and an output port coupled to the fourth output port of the fourth D-type flip-flop; The first NAND gate circuit has a first input port coupled to the output port of the first inverter, a second input port coupled to the first output port of the first D flip-flop, and an output port; The second NAND gate circuit has a first input port coupled to the output port of the second inverter, a second input port coupled to the third output port of the third D-type flip-flop, and an output port. as well as The third NAND gate circuit has a first input port coupled to the output port of the first NAND gate circuit, a second input port coupled to the output port of the second NAND gate circuit, and an output port.
11. The write equalization system of claim 10, wherein, since the processed data strobe signal is the first processed data strobe signal among the first processed data strobe signal and the second processed data strobe signal, a first write equalization result is output from the output port of the third NAND gate; since the processed data strobe signal is the second processed data strobe signal among the first processed data strobe signal and the second processed data strobe signal, a second write equalization result is output from the output port of the third NAND gate; and the data signal is generated based on the first write equalization result and the second write equalization result.
12. The write equalization system of claim 11, wherein the data control circuit further comprises: The first transmission gate circuit has an input port for receiving the first write equalization result, a control port for receiving the first processed data strobe signal, and an output port. The second transmission gate circuit has an input port for receiving the second write equalization result, a control port for receiving the second processed data strobe signal, and an output port. The third inverter has an input port and an output port coupled to the output port of the first transmission gate circuit and the output port of the second transmission gate circuit. The fourth inverter has an input port coupled to the output port of the third inverter and an output port coupled to the input port of the third inverter; as well as The fifth inverter has an input port and an output port coupled to the output port of the third inverter, wherein the data signal is generated at the output port of the fifth inverter.
13. A storage device comprising: Memory controller; Write to the equalizer system, which includes: A frequency divider is used to receive a clock signal from the memory controller and divide the clock signal to generate multiple divided clock signals. A signal processing circuit is used to receive a data strobe signal from the memory controller and process the data strobe signal to generate multiple processed data strobe signals. A data control circuit is used to generate a data signal based on the plurality of frequency-divided clock signals and the plurality of processed data strobe signals, so as to indicate that the rising edge of the data strobe signal is at a first level or a second level of the clock signal, wherein the first level is higher than the second level; as well as The data pin is used to receive the data signal from the data control circuit and transmit the data signal to the memory controller.